RTEMS 6.1-rc2
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alt_gpio.h
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1
7/*******************************************************************************
8* *
9* Copyright 2013 Altera Corporation. All Rights Reserved. *
10* *
11* Redistribution and use in source and binary forms, with or without *
12* modification, are permitted provided that the following conditions are met: *
13* *
14* 1. Redistributions of source code must retain the above copyright notice, *
15* this list of conditions and the following disclaimer. *
16* *
17* 2. Redistributions in binary form must reproduce the above copyright notice, *
18* this list of conditions and the following disclaimer in the documentation *
19* and/or other materials provided with the distribution. *
20* *
21* 3. The name of the author may not be used to endorse or promote products *
22* derived from this software without specific prior written permission. *
23* *
24* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
25* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
26* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
27* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
28* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
29* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
30* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
31* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
32* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
33* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
34* *
35*******************************************************************************/
36
37/* Altera - ALT_GPIO */
38
39#ifndef __ALTERA_ALT_GPIO_H__
40#define __ALTERA_ALT_GPIO_H__
41
42#ifdef __cplusplus
43extern "C"
44{
45#endif /* __cplusplus */
46
47/*
48 * Component : GPIO Module - ALT_GPIO
49 * GPIO Module
50 *
51 * Registers in the GPIO module
52 *
53 */
54/*
55 * Register : Port A Data Register - gpio_swporta_dr
56 *
57 * This GPIO Data register is used to input or output data
58 *
59 * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
60 *
61 * Register Layout
62 *
63 * Bits | Access | Reset | Description
64 * :--------|:-------|:------|:------------
65 * [28:0] | RW | 0x0 | Port A Data
66 * [31:29] | ??? | 0x0 | *UNDEFINED*
67 *
68 */
69/*
70 * Field : Port A Data - gpio_swporta_dr
71 *
72 * Values written to this register are output on the I/O signals of the GPIO Data
73 * Register, if the corresponding data direction bits for GPIO Data Direction Field
74 * are set to Output mode. The value read back is equal to the last value written
75 * to this register.
76 *
77 * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
78 *
79 * Field Access Macros:
80 *
81 */
82/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
83#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_LSB 0
84/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
85#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_MSB 28
86/* The width in bits of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
87#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_WIDTH 29
88/* The mask used to set the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
89#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET_MSK 0x1fffffff
90/* The mask used to clear the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value. */
91#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_CLR_MSK 0xe0000000
92/* The reset value of the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field. */
93#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_RESET 0x0
94/* Extracts the ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR field value from a register. */
95#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_GET(value) (((value) & 0x1fffffff) >> 0)
96/* Produces a ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR register field value suitable for setting the register. */
97#define ALT_GPIO_SWPORTA_DR_GPIO_SWPORTA_DR_SET(value) (((value) << 0) & 0x1fffffff)
98
99#ifndef __ASSEMBLY__
100/*
101 * WARNING: The C register and register group struct declarations are provided for
102 * convenience and illustrative purposes. They should, however, be used with
103 * caution as the C language standard provides no guarantees about the alignment or
104 * atomicity of device memory accesses. The recommended practice for writing
105 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
106 * alt_write_word() functions.
107 *
108 * The struct declaration for register ALT_GPIO_SWPORTA_DR.
109 */
110struct ALT_GPIO_SWPORTA_DR_s
111{
112 uint32_t gpio_swporta_dr : 29; /* Port A Data */
113 uint32_t : 3; /* *UNDEFINED* */
114};
115
116/* The typedef declaration for register ALT_GPIO_SWPORTA_DR. */
117typedef volatile struct ALT_GPIO_SWPORTA_DR_s ALT_GPIO_SWPORTA_DR_t;
118#endif /* __ASSEMBLY__ */
119
120/* The byte offset of the ALT_GPIO_SWPORTA_DR register from the beginning of the component. */
121#define ALT_GPIO_SWPORTA_DR_OFST 0x0
122/* The address of the ALT_GPIO_SWPORTA_DR register. */
123#define ALT_GPIO_SWPORTA_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DR_OFST))
124
125/*
126 * Register : Port A Data Direction Register - gpio_swporta_ddr
127 *
128 * This register establishes the direction of each corresponding GPIO Data Field
129 * Bit.
130 *
131 * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
132 *
133 * Register Layout
134 *
135 * Bits | Access | Reset | Description
136 * :--------|:-------|:------|:----------------------------
137 * [28:0] | RW | 0x0 | Port A Data Direction Field
138 * [31:29] | ??? | 0x0 | *UNDEFINED*
139 *
140 */
141/*
142 * Field : Port A Data Direction Field - gpio_swporta_ddr
143 *
144 * Values written to this register independently control the direction of the
145 * corresponding data bit in the Port A Data Register.
146 *
147 * Check the GPIO chapter in the handbook for details on how GPIO2 is implemented.
148 *
149 * Field Enumeration Values:
150 *
151 * Enum | Value | Description
152 * :--------------------------------------------|:------|:-----------------
153 * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN | 0x0 | Input Direction
154 * ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT | 0x1 | Output Direction
155 *
156 * Field Access Macros:
157 *
158 */
159/*
160 * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
161 *
162 * Input Direction
163 */
164#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_IN 0x0
165/*
166 * Enumerated value for register field ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR
167 *
168 * Output Direction
169 */
170#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_E_OUT 0x1
171
172/* The Least Significant Bit (LSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
173#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_LSB 0
174/* The Most Significant Bit (MSB) position of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
175#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_MSB 28
176/* The width in bits of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
177#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_WIDTH 29
178/* The mask used to set the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
179#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET_MSK 0x1fffffff
180/* The mask used to clear the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value. */
181#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_CLR_MSK 0xe0000000
182/* The reset value of the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field. */
183#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_RESET 0x0
184/* Extracts the ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR field value from a register. */
185#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_GET(value) (((value) & 0x1fffffff) >> 0)
186/* Produces a ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR register field value suitable for setting the register. */
187#define ALT_GPIO_SWPORTA_DDR_GPIO_SWPORTA_DDR_SET(value) (((value) << 0) & 0x1fffffff)
188
189#ifndef __ASSEMBLY__
190/*
191 * WARNING: The C register and register group struct declarations are provided for
192 * convenience and illustrative purposes. They should, however, be used with
193 * caution as the C language standard provides no guarantees about the alignment or
194 * atomicity of device memory accesses. The recommended practice for writing
195 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
196 * alt_write_word() functions.
197 *
198 * The struct declaration for register ALT_GPIO_SWPORTA_DDR.
199 */
200struct ALT_GPIO_SWPORTA_DDR_s
201{
202 uint32_t gpio_swporta_ddr : 29; /* Port A Data Direction Field */
203 uint32_t : 3; /* *UNDEFINED* */
204};
205
206/* The typedef declaration for register ALT_GPIO_SWPORTA_DDR. */
207typedef volatile struct ALT_GPIO_SWPORTA_DDR_s ALT_GPIO_SWPORTA_DDR_t;
208#endif /* __ASSEMBLY__ */
209
210/* The byte offset of the ALT_GPIO_SWPORTA_DDR register from the beginning of the component. */
211#define ALT_GPIO_SWPORTA_DDR_OFST 0x4
212/* The address of the ALT_GPIO_SWPORTA_DDR register. */
213#define ALT_GPIO_SWPORTA_DDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_SWPORTA_DDR_OFST))
214
215/*
216 * Register : Interrupt Enable Register - gpio_inten
217 *
218 * The Interrupt enable register allows interrupts for each bit of the Port A data
219 * register.
220 *
221 * Register Layout
222 *
223 * Bits | Access | Reset | Description
224 * :--------|:-------|:------|:-----------------------
225 * [28:0] | RW | 0x0 | Interrupt Enable Field
226 * [31:29] | ??? | 0x0 | *UNDEFINED*
227 *
228 */
229/*
230 * Field : Interrupt Enable Field - gpio_inten
231 *
232 * Allows each bit of Port A Data Register to be configured for interrupt
233 * capability. Interrupts are disabled on the corresponding bits of Port A Data
234 * Register if the corresponding data direction register is set to Output.
235 *
236 * Field Enumeration Values:
237 *
238 * Enum | Value | Description
239 * :--------------------------------|:------|:----------------------------
240 * ALT_GPIO_INTEN_GPIO_INTEN_E_DIS | 0x0 | Disable Interrupt on Port A
241 * ALT_GPIO_INTEN_GPIO_INTEN_E_EN | 0x1 | Enable Interrupt on Port A
242 *
243 * Field Access Macros:
244 *
245 */
246/*
247 * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
248 *
249 * Disable Interrupt on Port A
250 */
251#define ALT_GPIO_INTEN_GPIO_INTEN_E_DIS 0x0
252/*
253 * Enumerated value for register field ALT_GPIO_INTEN_GPIO_INTEN
254 *
255 * Enable Interrupt on Port A
256 */
257#define ALT_GPIO_INTEN_GPIO_INTEN_E_EN 0x1
258
259/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
260#define ALT_GPIO_INTEN_GPIO_INTEN_LSB 0
261/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
262#define ALT_GPIO_INTEN_GPIO_INTEN_MSB 28
263/* The width in bits of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
264#define ALT_GPIO_INTEN_GPIO_INTEN_WIDTH 29
265/* The mask used to set the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
266#define ALT_GPIO_INTEN_GPIO_INTEN_SET_MSK 0x1fffffff
267/* The mask used to clear the ALT_GPIO_INTEN_GPIO_INTEN register field value. */
268#define ALT_GPIO_INTEN_GPIO_INTEN_CLR_MSK 0xe0000000
269/* The reset value of the ALT_GPIO_INTEN_GPIO_INTEN register field. */
270#define ALT_GPIO_INTEN_GPIO_INTEN_RESET 0x0
271/* Extracts the ALT_GPIO_INTEN_GPIO_INTEN field value from a register. */
272#define ALT_GPIO_INTEN_GPIO_INTEN_GET(value) (((value) & 0x1fffffff) >> 0)
273/* Produces a ALT_GPIO_INTEN_GPIO_INTEN register field value suitable for setting the register. */
274#define ALT_GPIO_INTEN_GPIO_INTEN_SET(value) (((value) << 0) & 0x1fffffff)
275
276#ifndef __ASSEMBLY__
277/*
278 * WARNING: The C register and register group struct declarations are provided for
279 * convenience and illustrative purposes. They should, however, be used with
280 * caution as the C language standard provides no guarantees about the alignment or
281 * atomicity of device memory accesses. The recommended practice for writing
282 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
283 * alt_write_word() functions.
284 *
285 * The struct declaration for register ALT_GPIO_INTEN.
286 */
287struct ALT_GPIO_INTEN_s
288{
289 uint32_t gpio_inten : 29; /* Interrupt Enable Field */
290 uint32_t : 3; /* *UNDEFINED* */
291};
292
293/* The typedef declaration for register ALT_GPIO_INTEN. */
294typedef volatile struct ALT_GPIO_INTEN_s ALT_GPIO_INTEN_t;
295#endif /* __ASSEMBLY__ */
296
297/* The byte offset of the ALT_GPIO_INTEN register from the beginning of the component. */
298#define ALT_GPIO_INTEN_OFST 0x30
299/* The address of the ALT_GPIO_INTEN register. */
300#define ALT_GPIO_INTEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTEN_OFST))
301
302/*
303 * Register : Interrupt Mask Register - gpio_intmask
304 *
305 * Controls which pins cause interrupts on Port A Data Register inputs.
306 *
307 * Register Layout
308 *
309 * Bits | Access | Reset | Description
310 * :--------|:-------|:------|:---------------------
311 * [28:0] | RW | 0x0 | Interrupt Mask Field
312 * [31:29] | ??? | 0x0 | *UNDEFINED*
313 *
314 */
315/*
316 * Field : Interrupt Mask Field - gpio_intmask
317 *
318 * Controls whether an interrupt on Port A Data Register can generate an interrupt
319 * to the interrupt controller by not masking it. The unmasked status can be read
320 * as well as the resultant status after masking.
321 *
322 * Field Enumeration Values:
323 *
324 * Enum | Value | Description
325 * :----------------------------------|:------|:----------------------------
326 * ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS | 0x0 | Interrupt bits are unmasked
327 * ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN | 0x1 | Mask Interrupt
328 *
329 * Field Access Macros:
330 *
331 */
332/*
333 * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
334 *
335 * Interrupt bits are unmasked
336 */
337#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_DIS 0x0
338/*
339 * Enumerated value for register field ALT_GPIO_INTMSK_GPIO_INTMSK
340 *
341 * Mask Interrupt
342 */
343#define ALT_GPIO_INTMSK_GPIO_INTMSK_E_EN 0x1
344
345/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
346#define ALT_GPIO_INTMSK_GPIO_INTMSK_LSB 0
347/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
348#define ALT_GPIO_INTMSK_GPIO_INTMSK_MSB 28
349/* The width in bits of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
350#define ALT_GPIO_INTMSK_GPIO_INTMSK_WIDTH 29
351/* The mask used to set the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
352#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET_MSK 0x1fffffff
353/* The mask used to clear the ALT_GPIO_INTMSK_GPIO_INTMSK register field value. */
354#define ALT_GPIO_INTMSK_GPIO_INTMSK_CLR_MSK 0xe0000000
355/* The reset value of the ALT_GPIO_INTMSK_GPIO_INTMSK register field. */
356#define ALT_GPIO_INTMSK_GPIO_INTMSK_RESET 0x0
357/* Extracts the ALT_GPIO_INTMSK_GPIO_INTMSK field value from a register. */
358#define ALT_GPIO_INTMSK_GPIO_INTMSK_GET(value) (((value) & 0x1fffffff) >> 0)
359/* Produces a ALT_GPIO_INTMSK_GPIO_INTMSK register field value suitable for setting the register. */
360#define ALT_GPIO_INTMSK_GPIO_INTMSK_SET(value) (((value) << 0) & 0x1fffffff)
361
362#ifndef __ASSEMBLY__
363/*
364 * WARNING: The C register and register group struct declarations are provided for
365 * convenience and illustrative purposes. They should, however, be used with
366 * caution as the C language standard provides no guarantees about the alignment or
367 * atomicity of device memory accesses. The recommended practice for writing
368 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
369 * alt_write_word() functions.
370 *
371 * The struct declaration for register ALT_GPIO_INTMSK.
372 */
373struct ALT_GPIO_INTMSK_s
374{
375 uint32_t gpio_intmask : 29; /* Interrupt Mask Field */
376 uint32_t : 3; /* *UNDEFINED* */
377};
378
379/* The typedef declaration for register ALT_GPIO_INTMSK. */
380typedef volatile struct ALT_GPIO_INTMSK_s ALT_GPIO_INTMSK_t;
381#endif /* __ASSEMBLY__ */
382
383/* The byte offset of the ALT_GPIO_INTMSK register from the beginning of the component. */
384#define ALT_GPIO_INTMSK_OFST 0x34
385/* The address of the ALT_GPIO_INTMSK register. */
386#define ALT_GPIO_INTMSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTMSK_OFST))
387
388/*
389 * Register : Interrupt Level Register - gpio_inttype_level
390 *
391 * The interrupt level register defines the type of interrupt (edge or level).
392 *
393 * Register Layout
394 *
395 * Bits | Access | Reset | Description
396 * :--------|:-------|:------|:----------------------
397 * [28:0] | RW | 0x0 | Interrupt Level Field
398 * [31:29] | ??? | 0x0 | *UNDEFINED*
399 *
400 */
401/*
402 * Field : Interrupt Level Field - gpio_inttype_level
403 *
404 * This field controls the type of interrupt that can occur on the Port A Data
405 * Register.
406 *
407 * Field Enumeration Values:
408 *
409 * Enum | Value | Description
410 * :--------------------------------------------------|:------|:----------------
411 * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL | 0x0 | Level-sensitive
412 * ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE | 0x1 | Edge-sensitive
413 *
414 * Field Access Macros:
415 *
416 */
417/*
418 * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
419 *
420 * Level-sensitive
421 */
422#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_LEVEL 0x0
423/*
424 * Enumerated value for register field ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL
425 *
426 * Edge-sensitive
427 */
428#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_E_EDGE 0x1
429
430/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
431#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_LSB 0
432/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
433#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_MSB 28
434/* The width in bits of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
435#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_WIDTH 29
436/* The mask used to set the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
437#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET_MSK 0x1fffffff
438/* The mask used to clear the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value. */
439#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_CLR_MSK 0xe0000000
440/* The reset value of the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field. */
441#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_RESET 0x0
442/* Extracts the ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL field value from a register. */
443#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_GET(value) (((value) & 0x1fffffff) >> 0)
444/* Produces a ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL register field value suitable for setting the register. */
445#define ALT_GPIO_INTTYPE_LEVEL_GPIO_INTTYPE_LEVEL_SET(value) (((value) << 0) & 0x1fffffff)
446
447#ifndef __ASSEMBLY__
448/*
449 * WARNING: The C register and register group struct declarations are provided for
450 * convenience and illustrative purposes. They should, however, be used with
451 * caution as the C language standard provides no guarantees about the alignment or
452 * atomicity of device memory accesses. The recommended practice for writing
453 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
454 * alt_write_word() functions.
455 *
456 * The struct declaration for register ALT_GPIO_INTTYPE_LEVEL.
457 */
458struct ALT_GPIO_INTTYPE_LEVEL_s
459{
460 uint32_t gpio_inttype_level : 29; /* Interrupt Level Field */
461 uint32_t : 3; /* *UNDEFINED* */
462};
463
464/* The typedef declaration for register ALT_GPIO_INTTYPE_LEVEL. */
465typedef volatile struct ALT_GPIO_INTTYPE_LEVEL_s ALT_GPIO_INTTYPE_LEVEL_t;
466#endif /* __ASSEMBLY__ */
467
468/* The byte offset of the ALT_GPIO_INTTYPE_LEVEL register from the beginning of the component. */
469#define ALT_GPIO_INTTYPE_LEVEL_OFST 0x38
470/* The address of the ALT_GPIO_INTTYPE_LEVEL register. */
471#define ALT_GPIO_INTTYPE_LEVEL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTTYPE_LEVEL_OFST))
472
473/*
474 * Register : Interrupt Polarity Register - gpio_int_polarity
475 *
476 * Controls the Polarity of Interrupts that can occur on inputs of Port A Data
477 * Register
478 *
479 * Register Layout
480 *
481 * Bits | Access | Reset | Description
482 * :--------|:-------|:------|:-----------------------
483 * [28:0] | RW | 0x0 | Polarity Control Field
484 * [31:29] | ??? | 0x0 | *UNDEFINED*
485 *
486 */
487/*
488 * Field : Polarity Control Field - gpio_int_polarity
489 *
490 * Controls the polarity of edge or level sensitivity that can occur on input of
491 * Port A Data Register.
492 *
493 * Field Enumeration Values:
494 *
495 * Enum | Value | Description
496 * :----------------------------------------|:------|:------------
497 * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW | 0x0 | Active low
498 * ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH | 0x1 | Active high
499 *
500 * Field Access Macros:
501 *
502 */
503/*
504 * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
505 *
506 * Active low
507 */
508#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTLOW 0x0
509/*
510 * Enumerated value for register field ALT_GPIO_INT_POL_GPIO_INT_POL
511 *
512 * Active high
513 */
514#define ALT_GPIO_INT_POL_GPIO_INT_POL_E_ACTHIGH 0x1
515
516/* The Least Significant Bit (LSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
517#define ALT_GPIO_INT_POL_GPIO_INT_POL_LSB 0
518/* The Most Significant Bit (MSB) position of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
519#define ALT_GPIO_INT_POL_GPIO_INT_POL_MSB 28
520/* The width in bits of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
521#define ALT_GPIO_INT_POL_GPIO_INT_POL_WIDTH 29
522/* The mask used to set the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
523#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET_MSK 0x1fffffff
524/* The mask used to clear the ALT_GPIO_INT_POL_GPIO_INT_POL register field value. */
525#define ALT_GPIO_INT_POL_GPIO_INT_POL_CLR_MSK 0xe0000000
526/* The reset value of the ALT_GPIO_INT_POL_GPIO_INT_POL register field. */
527#define ALT_GPIO_INT_POL_GPIO_INT_POL_RESET 0x0
528/* Extracts the ALT_GPIO_INT_POL_GPIO_INT_POL field value from a register. */
529#define ALT_GPIO_INT_POL_GPIO_INT_POL_GET(value) (((value) & 0x1fffffff) >> 0)
530/* Produces a ALT_GPIO_INT_POL_GPIO_INT_POL register field value suitable for setting the register. */
531#define ALT_GPIO_INT_POL_GPIO_INT_POL_SET(value) (((value) << 0) & 0x1fffffff)
532
533#ifndef __ASSEMBLY__
534/*
535 * WARNING: The C register and register group struct declarations are provided for
536 * convenience and illustrative purposes. They should, however, be used with
537 * caution as the C language standard provides no guarantees about the alignment or
538 * atomicity of device memory accesses. The recommended practice for writing
539 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
540 * alt_write_word() functions.
541 *
542 * The struct declaration for register ALT_GPIO_INT_POL.
543 */
544struct ALT_GPIO_INT_POL_s
545{
546 uint32_t gpio_int_polarity : 29; /* Polarity Control Field */
547 uint32_t : 3; /* *UNDEFINED* */
548};
549
550/* The typedef declaration for register ALT_GPIO_INT_POL. */
551typedef volatile struct ALT_GPIO_INT_POL_s ALT_GPIO_INT_POL_t;
552#endif /* __ASSEMBLY__ */
553
554/* The byte offset of the ALT_GPIO_INT_POL register from the beginning of the component. */
555#define ALT_GPIO_INT_POL_OFST 0x3c
556/* The address of the ALT_GPIO_INT_POL register. */
557#define ALT_GPIO_INT_POL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INT_POL_OFST))
558
559/*
560 * Register : Interrupt Status Register - gpio_intstatus
561 *
562 * The Interrupt status is reported for all Port A Data Register Bits.
563 *
564 * Register Layout
565 *
566 * Bits | Access | Reset | Description
567 * :--------|:-------|:------|:-----------------------
568 * [28:0] | RW | 0x0 | Interrupt Status Field
569 * [31:29] | ??? | 0x0 | *UNDEFINED*
570 *
571 */
572/*
573 * Field : Interrupt Status Field - gpio_intstatus
574 *
575 * Interrupt status of Port A Data Register.
576 *
577 * Field Enumeration Values:
578 *
579 * Enum | Value | Description
580 * :--------------------------------------|:------|:------------
581 * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT | 0x0 | Inactive
582 * ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT | 0x1 | Active
583 *
584 * Field Access Macros:
585 *
586 */
587/*
588 * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
589 *
590 * Inactive
591 */
592#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_INACT 0x0
593/*
594 * Enumerated value for register field ALT_GPIO_INTSTAT_GPIO_INTSTAT
595 *
596 * Active
597 */
598#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_E_ACT 0x1
599
600/* The Least Significant Bit (LSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
601#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_LSB 0
602/* The Most Significant Bit (MSB) position of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
603#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_MSB 28
604/* The width in bits of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
605#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_WIDTH 29
606/* The mask used to set the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
607#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET_MSK 0x1fffffff
608/* The mask used to clear the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value. */
609#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_CLR_MSK 0xe0000000
610/* The reset value of the ALT_GPIO_INTSTAT_GPIO_INTSTAT register field. */
611#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_RESET 0x0
612/* Extracts the ALT_GPIO_INTSTAT_GPIO_INTSTAT field value from a register. */
613#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
614/* Produces a ALT_GPIO_INTSTAT_GPIO_INTSTAT register field value suitable for setting the register. */
615#define ALT_GPIO_INTSTAT_GPIO_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
616
617#ifndef __ASSEMBLY__
618/*
619 * WARNING: The C register and register group struct declarations are provided for
620 * convenience and illustrative purposes. They should, however, be used with
621 * caution as the C language standard provides no guarantees about the alignment or
622 * atomicity of device memory accesses. The recommended practice for writing
623 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
624 * alt_write_word() functions.
625 *
626 * The struct declaration for register ALT_GPIO_INTSTAT.
627 */
628struct ALT_GPIO_INTSTAT_s
629{
630 uint32_t gpio_intstatus : 29; /* Interrupt Status Field */
631 uint32_t : 3; /* *UNDEFINED* */
632};
633
634/* The typedef declaration for register ALT_GPIO_INTSTAT. */
635typedef volatile struct ALT_GPIO_INTSTAT_s ALT_GPIO_INTSTAT_t;
636#endif /* __ASSEMBLY__ */
637
638/* The byte offset of the ALT_GPIO_INTSTAT register from the beginning of the component. */
639#define ALT_GPIO_INTSTAT_OFST 0x40
640/* The address of the ALT_GPIO_INTSTAT register. */
641#define ALT_GPIO_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_INTSTAT_OFST))
642
643/*
644 * Register : Raw Interrupt Status Register - gpio_raw_intstatus
645 *
646 * This is the Raw Interrupt Status Register for Port A Data Register. It is used
647 * with the Interrupt Mask Register to allow interrupts from the Port A Data
648 * Register.
649 *
650 * Register Layout
651 *
652 * Bits | Access | Reset | Description
653 * :--------|:-------|:------|:---------------------------
654 * [28:0] | RW | 0x0 | Raw Interrupt Status Field
655 * [31:29] | ??? | 0x0 | *UNDEFINED*
656 *
657 */
658/*
659 * Field : Raw Interrupt Status Field - gpio_raw_intstatus
660 *
661 * Raw interrupt of status of Port A Data Register (premasking bits)
662 *
663 * Field Enumeration Values:
664 *
665 * Enum | Value | Description
666 * :----------------------------------------------|:------|:------------
667 * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT | 0x0 | Inactive
668 * ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT | 0x1 | Active
669 *
670 * Field Access Macros:
671 *
672 */
673/*
674 * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
675 *
676 * Inactive
677 */
678#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_INACT 0x0
679/*
680 * Enumerated value for register field ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT
681 *
682 * Active
683 */
684#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_E_ACT 0x1
685
686/* The Least Significant Bit (LSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
687#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_LSB 0
688/* The Most Significant Bit (MSB) position of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
689#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_MSB 28
690/* The width in bits of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
691#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_WIDTH 29
692/* The mask used to set the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
693#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET_MSK 0x1fffffff
694/* The mask used to clear the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value. */
695#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_CLR_MSK 0xe0000000
696/* The reset value of the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field. */
697#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_RESET 0x0
698/* Extracts the ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT field value from a register. */
699#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_GET(value) (((value) & 0x1fffffff) >> 0)
700/* Produces a ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT register field value suitable for setting the register. */
701#define ALT_GPIO_RAW_INTSTAT_GPIO_RAW_INTSTAT_SET(value) (((value) << 0) & 0x1fffffff)
702
703#ifndef __ASSEMBLY__
704/*
705 * WARNING: The C register and register group struct declarations are provided for
706 * convenience and illustrative purposes. They should, however, be used with
707 * caution as the C language standard provides no guarantees about the alignment or
708 * atomicity of device memory accesses. The recommended practice for writing
709 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
710 * alt_write_word() functions.
711 *
712 * The struct declaration for register ALT_GPIO_RAW_INTSTAT.
713 */
714struct ALT_GPIO_RAW_INTSTAT_s
715{
716 uint32_t gpio_raw_intstatus : 29; /* Raw Interrupt Status Field */
717 uint32_t : 3; /* *UNDEFINED* */
718};
719
720/* The typedef declaration for register ALT_GPIO_RAW_INTSTAT. */
721typedef volatile struct ALT_GPIO_RAW_INTSTAT_s ALT_GPIO_RAW_INTSTAT_t;
722#endif /* __ASSEMBLY__ */
723
724/* The byte offset of the ALT_GPIO_RAW_INTSTAT register from the beginning of the component. */
725#define ALT_GPIO_RAW_INTSTAT_OFST 0x44
726/* The address of the ALT_GPIO_RAW_INTSTAT register. */
727#define ALT_GPIO_RAW_INTSTAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_RAW_INTSTAT_OFST))
728
729/*
730 * Register : Debounce Enable Register - gpio_debounce
731 *
732 * Debounces each IO Pin
733 *
734 * Register Layout
735 *
736 * Bits | Access | Reset | Description
737 * :--------|:-------|:------|:--------------------------------
738 * [28:0] | RW | 0x0 | ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
739 * [31:29] | ??? | 0x0 | *UNDEFINED*
740 *
741 */
742/*
743 * Field : gpio_debounce
744 *
745 * Controls whether an external signal that is the source of an interrupt needs to
746 * be debounced to remove any spurious glitches. A signal must be valid for two
747 * periods of an external clock (gpio_db_clk) before it is internally processed.
748 *
749 * Field Enumeration Values:
750 *
751 * Enum | Value | Description
752 * :--------------------------------------|:------|:----------------
753 * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS | 0x0 | No debounce
754 * ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN | 0x1 | Enable debounce
755 *
756 * Field Access Macros:
757 *
758 */
759/*
760 * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
761 *
762 * No debounce
763 */
764#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_DIS 0x0
765/*
766 * Enumerated value for register field ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE
767 *
768 * Enable debounce
769 */
770#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_E_EN 0x1
771
772/* The Least Significant Bit (LSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
773#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_LSB 0
774/* The Most Significant Bit (MSB) position of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
775#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_MSB 28
776/* The width in bits of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
777#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_WIDTH 29
778/* The mask used to set the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
779#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET_MSK 0x1fffffff
780/* The mask used to clear the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value. */
781#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_CLR_MSK 0xe0000000
782/* The reset value of the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field. */
783#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_RESET 0x0
784/* Extracts the ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE field value from a register. */
785#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_GET(value) (((value) & 0x1fffffff) >> 0)
786/* Produces a ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE register field value suitable for setting the register. */
787#define ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE_SET(value) (((value) << 0) & 0x1fffffff)
788
789#ifndef __ASSEMBLY__
790/*
791 * WARNING: The C register and register group struct declarations are provided for
792 * convenience and illustrative purposes. They should, however, be used with
793 * caution as the C language standard provides no guarantees about the alignment or
794 * atomicity of device memory accesses. The recommended practice for writing
795 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
796 * alt_write_word() functions.
797 *
798 * The struct declaration for register ALT_GPIO_DEBOUNCE.
799 */
800struct ALT_GPIO_DEBOUNCE_s
801{
802 uint32_t gpio_debounce : 29; /* ALT_GPIO_DEBOUNCE_GPIO_DEBOUNCE */
803 uint32_t : 3; /* *UNDEFINED* */
804};
805
806/* The typedef declaration for register ALT_GPIO_DEBOUNCE. */
807typedef volatile struct ALT_GPIO_DEBOUNCE_s ALT_GPIO_DEBOUNCE_t;
808#endif /* __ASSEMBLY__ */
809
810/* The byte offset of the ALT_GPIO_DEBOUNCE register from the beginning of the component. */
811#define ALT_GPIO_DEBOUNCE_OFST 0x48
812/* The address of the ALT_GPIO_DEBOUNCE register. */
813#define ALT_GPIO_DEBOUNCE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_DEBOUNCE_OFST))
814
815/*
816 * Register : Clear Interrupt Register - gpio_porta_eoi
817 *
818 * Port A Data Register interrupt handling.
819 *
820 * Register Layout
821 *
822 * Bits | Access | Reset | Description
823 * :--------|:-------|:------|:-----------------------------
824 * [28:0] | W | 0x0 | Clears Edge Interrupts Field
825 * [31:29] | ??? | 0x0 | *UNDEFINED*
826 *
827 */
828/*
829 * Field : Clears Edge Interrupts Field - gpio_porta_eoi
830 *
831 * Controls the clearing of edge type interrupts from the Port A Data Register.
832 *
833 * Field Enumeration Values:
834 *
835 * Enum | Value | Description
836 * :------------------------------------------|:------|:-------------------
837 * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR | 0x0 | No interrupt clear
838 * ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR | 0x1 | Clear interrupt
839 *
840 * Field Access Macros:
841 *
842 */
843/*
844 * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
845 *
846 * No interrupt clear
847 */
848#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_NOCLR 0x0
849/*
850 * Enumerated value for register field ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI
851 *
852 * Clear interrupt
853 */
854#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_E_CLR 0x1
855
856/* The Least Significant Bit (LSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
857#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_LSB 0
858/* The Most Significant Bit (MSB) position of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
859#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_MSB 28
860/* The width in bits of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
861#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_WIDTH 29
862/* The mask used to set the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
863#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET_MSK 0x1fffffff
864/* The mask used to clear the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value. */
865#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_CLR_MSK 0xe0000000
866/* The reset value of the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field. */
867#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_RESET 0x0
868/* Extracts the ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI field value from a register. */
869#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_GET(value) (((value) & 0x1fffffff) >> 0)
870/* Produces a ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI register field value suitable for setting the register. */
871#define ALT_GPIO_PORTA_EOI_GPIO_PORTA_EOI_SET(value) (((value) << 0) & 0x1fffffff)
872
873#ifndef __ASSEMBLY__
874/*
875 * WARNING: The C register and register group struct declarations are provided for
876 * convenience and illustrative purposes. They should, however, be used with
877 * caution as the C language standard provides no guarantees about the alignment or
878 * atomicity of device memory accesses. The recommended practice for writing
879 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
880 * alt_write_word() functions.
881 *
882 * The struct declaration for register ALT_GPIO_PORTA_EOI.
883 */
884struct ALT_GPIO_PORTA_EOI_s
885{
886 uint32_t gpio_porta_eoi : 29; /* Clears Edge Interrupts Field */
887 uint32_t : 3; /* *UNDEFINED* */
888};
889
890/* The typedef declaration for register ALT_GPIO_PORTA_EOI. */
891typedef volatile struct ALT_GPIO_PORTA_EOI_s ALT_GPIO_PORTA_EOI_t;
892#endif /* __ASSEMBLY__ */
893
894/* The byte offset of the ALT_GPIO_PORTA_EOI register from the beginning of the component. */
895#define ALT_GPIO_PORTA_EOI_OFST 0x4c
896/* The address of the ALT_GPIO_PORTA_EOI register. */
897#define ALT_GPIO_PORTA_EOI_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_PORTA_EOI_OFST))
898
899/*
900 * Register : External Port A Register - gpio_ext_porta
901 *
902 * The external port register is used to input data to the metastability flops.
903 *
904 * Register Layout
905 *
906 * Bits | Access | Reset | Description
907 * :--------|:-------|:------|:--------------------
908 * [28:0] | R | 0x0 | External Port Field
909 * [31:29] | ??? | 0x0 | *UNDEFINED*
910 *
911 */
912/*
913 * Field : External Port Field - gpio_ext_porta
914 *
915 * When Port A Data Register is configured as Input, then reading this location
916 * reads the values on the signals. When the data direction of Port A Data Register
917 * is set as Output, reading this location reads Port A Data Register
918 *
919 * Field Access Macros:
920 *
921 */
922/* The Least Significant Bit (LSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
923#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_LSB 0
924/* The Most Significant Bit (MSB) position of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
925#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_MSB 28
926/* The width in bits of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
927#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_WIDTH 29
928/* The mask used to set the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
929#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET_MSK 0x1fffffff
930/* The mask used to clear the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value. */
931#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_CLR_MSK 0xe0000000
932/* The reset value of the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field. */
933#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_RESET 0x0
934/* Extracts the ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA field value from a register. */
935#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_GET(value) (((value) & 0x1fffffff) >> 0)
936/* Produces a ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA register field value suitable for setting the register. */
937#define ALT_GPIO_EXT_PORTA_GPIO_EXT_PORTA_SET(value) (((value) << 0) & 0x1fffffff)
938
939#ifndef __ASSEMBLY__
940/*
941 * WARNING: The C register and register group struct declarations are provided for
942 * convenience and illustrative purposes. They should, however, be used with
943 * caution as the C language standard provides no guarantees about the alignment or
944 * atomicity of device memory accesses. The recommended practice for writing
945 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
946 * alt_write_word() functions.
947 *
948 * The struct declaration for register ALT_GPIO_EXT_PORTA.
949 */
950struct ALT_GPIO_EXT_PORTA_s
951{
952 const uint32_t gpio_ext_porta : 29; /* External Port Field */
953 uint32_t : 3; /* *UNDEFINED* */
954};
955
956/* The typedef declaration for register ALT_GPIO_EXT_PORTA. */
957typedef volatile struct ALT_GPIO_EXT_PORTA_s ALT_GPIO_EXT_PORTA_t;
958#endif /* __ASSEMBLY__ */
959
960/* The byte offset of the ALT_GPIO_EXT_PORTA register from the beginning of the component. */
961#define ALT_GPIO_EXT_PORTA_OFST 0x50
962/* The address of the ALT_GPIO_EXT_PORTA register. */
963#define ALT_GPIO_EXT_PORTA_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_EXT_PORTA_OFST))
964
965/*
966 * Register : Synchronization Level Register - gpio_ls_sync
967 *
968 * The Synchronization level register is used to synchronize input with l4_mp_clk
969 *
970 * Register Layout
971 *
972 * Bits | Access | Reset | Description
973 * :-------|:-------|:------|:----------------------------
974 * [0] | RW | 0x0 | Synchronization Level Field
975 * [31:1] | ??? | 0x0 | *UNDEFINED*
976 *
977 */
978/*
979 * Field : Synchronization Level Field - gpio_ls_sync
980 *
981 * The level-sensitive interrupts is synchronized to l4_mp_clk.
982 *
983 * Field Enumeration Values:
984 *
985 * Enum | Value | Description
986 * :---------------------------------------|:------|:--------------------------------
987 * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC | 0x0 | No synchronization to l4_mp_clk
988 * ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC | 0x1 | Synchronize to l4_mp_clk
989 *
990 * Field Access Macros:
991 *
992 */
993/*
994 * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
995 *
996 * No synchronization to l4_mp_clk
997 */
998#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_NOSYNC 0x0
999/*
1000 * Enumerated value for register field ALT_GPIO_LS_SYNC_GPIO_LS_SYNC
1001 *
1002 * Synchronize to l4_mp_clk
1003 */
1004#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_E_SYNC 0x1
1005
1006/* The Least Significant Bit (LSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1007#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_LSB 0
1008/* The Most Significant Bit (MSB) position of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1009#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_MSB 0
1010/* The width in bits of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1011#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_WIDTH 1
1012/* The mask used to set the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1013#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET_MSK 0x00000001
1014/* The mask used to clear the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value. */
1015#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_CLR_MSK 0xfffffffe
1016/* The reset value of the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field. */
1017#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_RESET 0x0
1018/* Extracts the ALT_GPIO_LS_SYNC_GPIO_LS_SYNC field value from a register. */
1019#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_GET(value) (((value) & 0x00000001) >> 0)
1020/* Produces a ALT_GPIO_LS_SYNC_GPIO_LS_SYNC register field value suitable for setting the register. */
1021#define ALT_GPIO_LS_SYNC_GPIO_LS_SYNC_SET(value) (((value) << 0) & 0x00000001)
1022
1023#ifndef __ASSEMBLY__
1024/*
1025 * WARNING: The C register and register group struct declarations are provided for
1026 * convenience and illustrative purposes. They should, however, be used with
1027 * caution as the C language standard provides no guarantees about the alignment or
1028 * atomicity of device memory accesses. The recommended practice for writing
1029 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1030 * alt_write_word() functions.
1031 *
1032 * The struct declaration for register ALT_GPIO_LS_SYNC.
1033 */
1034struct ALT_GPIO_LS_SYNC_s
1035{
1036 uint32_t gpio_ls_sync : 1; /* Synchronization Level Field */
1037 uint32_t : 31; /* *UNDEFINED* */
1038};
1039
1040/* The typedef declaration for register ALT_GPIO_LS_SYNC. */
1041typedef volatile struct ALT_GPIO_LS_SYNC_s ALT_GPIO_LS_SYNC_t;
1042#endif /* __ASSEMBLY__ */
1043
1044/* The byte offset of the ALT_GPIO_LS_SYNC register from the beginning of the component. */
1045#define ALT_GPIO_LS_SYNC_OFST 0x60
1046/* The address of the ALT_GPIO_LS_SYNC register. */
1047#define ALT_GPIO_LS_SYNC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_LS_SYNC_OFST))
1048
1049/*
1050 * Register : ID Code Register - gpio_id_code
1051 *
1052 * GPIO ID code.
1053 *
1054 * Register Layout
1055 *
1056 * Bits | Access | Reset | Description
1057 * :-------|:-------|:------|:--------------
1058 * [31:0] | R | 0x0 | ID Code Field
1059 *
1060 */
1061/*
1062 * Field : ID Code Field - gpio_id_code
1063 *
1064 * Chip identification
1065 *
1066 * Field Access Macros:
1067 *
1068 */
1069/* The Least Significant Bit (LSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1070#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_LSB 0
1071/* The Most Significant Bit (MSB) position of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1072#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_MSB 31
1073/* The width in bits of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1074#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_WIDTH 32
1075/* The mask used to set the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1076#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET_MSK 0xffffffff
1077/* The mask used to clear the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value. */
1078#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_CLR_MSK 0x00000000
1079/* The reset value of the ALT_GPIO_ID_CODE_GPIO_ID_CODE register field. */
1080#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_RESET 0x0
1081/* Extracts the ALT_GPIO_ID_CODE_GPIO_ID_CODE field value from a register. */
1082#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1083/* Produces a ALT_GPIO_ID_CODE_GPIO_ID_CODE register field value suitable for setting the register. */
1084#define ALT_GPIO_ID_CODE_GPIO_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1085
1086#ifndef __ASSEMBLY__
1087/*
1088 * WARNING: The C register and register group struct declarations are provided for
1089 * convenience and illustrative purposes. They should, however, be used with
1090 * caution as the C language standard provides no guarantees about the alignment or
1091 * atomicity of device memory accesses. The recommended practice for writing
1092 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1093 * alt_write_word() functions.
1094 *
1095 * The struct declaration for register ALT_GPIO_ID_CODE.
1096 */
1097struct ALT_GPIO_ID_CODE_s
1098{
1099 const uint32_t gpio_id_code : 32; /* ID Code Field */
1100};
1101
1102/* The typedef declaration for register ALT_GPIO_ID_CODE. */
1103typedef volatile struct ALT_GPIO_ID_CODE_s ALT_GPIO_ID_CODE_t;
1104#endif /* __ASSEMBLY__ */
1105
1106/* The byte offset of the ALT_GPIO_ID_CODE register from the beginning of the component. */
1107#define ALT_GPIO_ID_CODE_OFST 0x64
1108/* The address of the ALT_GPIO_ID_CODE register. */
1109#define ALT_GPIO_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_ID_CODE_OFST))
1110
1111/*
1112 * Register : GPIO Version Register - gpio_ver_id_code
1113 *
1114 * GPIO Component Version
1115 *
1116 * Register Layout
1117 *
1118 * Bits | Access | Reset | Description
1119 * :-------|:-------|:-----------|:------------------------------
1120 * [31:0] | R | 0x3230382a | ASCII Component Version Field
1121 *
1122 */
1123/*
1124 * Field : ASCII Component Version Field - gpio_ver_id_code
1125 *
1126 * ASCII value for each number in the version, followed by *. For example.
1127 * 32_30_31_2A represents the version 2.01
1128 *
1129 * Field Access Macros:
1130 *
1131 */
1132/* The Least Significant Bit (LSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1133#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_LSB 0
1134/* The Most Significant Bit (MSB) position of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1135#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_MSB 31
1136/* The width in bits of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1137#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_WIDTH 32
1138/* The mask used to set the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1139#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET_MSK 0xffffffff
1140/* The mask used to clear the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value. */
1141#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_CLR_MSK 0x00000000
1142/* The reset value of the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field. */
1143#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_RESET 0x3230382a
1144/* Extracts the ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE field value from a register. */
1145#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_GET(value) (((value) & 0xffffffff) >> 0)
1146/* Produces a ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE register field value suitable for setting the register. */
1147#define ALT_GPIO_VER_ID_CODE_GPIO_VER_ID_CODE_SET(value) (((value) << 0) & 0xffffffff)
1148
1149#ifndef __ASSEMBLY__
1150/*
1151 * WARNING: The C register and register group struct declarations are provided for
1152 * convenience and illustrative purposes. They should, however, be used with
1153 * caution as the C language standard provides no guarantees about the alignment or
1154 * atomicity of device memory accesses. The recommended practice for writing
1155 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1156 * alt_write_word() functions.
1157 *
1158 * The struct declaration for register ALT_GPIO_VER_ID_CODE.
1159 */
1160struct ALT_GPIO_VER_ID_CODE_s
1161{
1162 const uint32_t gpio_ver_id_code : 32; /* ASCII Component Version Field */
1163};
1164
1165/* The typedef declaration for register ALT_GPIO_VER_ID_CODE. */
1166typedef volatile struct ALT_GPIO_VER_ID_CODE_s ALT_GPIO_VER_ID_CODE_t;
1167#endif /* __ASSEMBLY__ */
1168
1169/* The byte offset of the ALT_GPIO_VER_ID_CODE register from the beginning of the component. */
1170#define ALT_GPIO_VER_ID_CODE_OFST 0x6c
1171/* The address of the ALT_GPIO_VER_ID_CODE register. */
1172#define ALT_GPIO_VER_ID_CODE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_VER_ID_CODE_OFST))
1173
1174/*
1175 * Register : Configuration Register 2 - gpio_config_reg2
1176 *
1177 * Specifies the bit width of port A.
1178 *
1179 * Register Layout
1180 *
1181 * Bits | Access | Reset | Description
1182 * :--------|:-------|:------|:----------------------
1183 * [4:0] | R | 0x1c | Port A Width (less 1)
1184 * [9:5] | R | 0x7 | Port B Width (less 1)
1185 * [14:10] | R | 0x7 | Port C Width (less 1)
1186 * [19:15] | R | 0x7 | Port D Width (less 1)
1187 * [31:20] | ??? | 0x0 | *UNDEFINED*
1188 *
1189 */
1190/*
1191 * Field : Port A Width (less 1) - encoded_id_pwidth_a
1192 *
1193 * Specifies the width of GPIO Port A. The value 28 represents the 29-bit width
1194 * less one.
1195 *
1196 * Field Enumeration Values:
1197 *
1198 * Enum | Value | Description
1199 * :-------------------------------------------------------|:------|:--------------------------
1200 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1201 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1202 *
1203 * Field Access Macros:
1204 *
1205 */
1206/*
1207 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1208 *
1209 * Width (less 1) of 8 bits
1210 */
1211#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7
1212/*
1213 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
1214 *
1215 * Width (less 1) of 29 bits
1216 */
1217#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE29BITS 0x1c
1218
1219/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1220#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB 0
1221/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1222#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB 4
1223/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1224#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH 5
1225/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1226#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK 0x0000001f
1227/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value. */
1228#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK 0xffffffe0
1229/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field. */
1230#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET 0x1c
1231/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register. */
1232#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value) (((value) & 0x0000001f) >> 0)
1233/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register. */
1234#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value) (((value) << 0) & 0x0000001f)
1235
1236/*
1237 * Field : Port B Width (less 1) - encoded_id_pwidth_b
1238 *
1239 * Specifies the width of GPIO Port B. Ignored because there is no Port B in the
1240 * GPIO.
1241 *
1242 * Field Enumeration Values:
1243 *
1244 * Enum | Value | Description
1245 * :-------------------------------------------------------|:------|:--------------------------
1246 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1247 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1248 *
1249 * Field Access Macros:
1250 *
1251 */
1252/*
1253 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1254 *
1255 * Width (less 1) of 8 bits
1256 */
1257#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7
1258/*
1259 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
1260 *
1261 * Width (less 1) of 29 bits
1262 */
1263#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE29BITS 0x1c
1264
1265/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1266#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB 5
1267/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1268#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB 9
1269/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1270#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH 5
1271/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1272#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK 0x000003e0
1273/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value. */
1274#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK 0xfffffc1f
1275/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field. */
1276#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET 0x7
1277/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register. */
1278#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value) (((value) & 0x000003e0) >> 5)
1279/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register. */
1280#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value) (((value) << 5) & 0x000003e0)
1281
1282/*
1283 * Field : Port C Width (less 1) - encoded_id_pwidth_c
1284 *
1285 * Specifies the width of GPIO Port C. Ignored because there is no Port C in the
1286 * GPIO.
1287 *
1288 * Field Enumeration Values:
1289 *
1290 * Enum | Value | Description
1291 * :-------------------------------------------------------|:------|:--------------------------
1292 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1293 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1294 *
1295 * Field Access Macros:
1296 *
1297 */
1298/*
1299 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1300 *
1301 * Width (less 1) of 8 bits
1302 */
1303#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7
1304/*
1305 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
1306 *
1307 * Width (less 1) of 29 bits
1308 */
1309#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE29BITS 0x1c
1310
1311/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1312#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB 10
1313/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1314#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB 14
1315/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1316#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH 5
1317/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1318#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK 0x00007c00
1319/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value. */
1320#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK 0xffff83ff
1321/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field. */
1322#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET 0x7
1323/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register. */
1324#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value) (((value) & 0x00007c00) >> 10)
1325/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register. */
1326#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value) (((value) << 10) & 0x00007c00)
1327
1328/*
1329 * Field : Port D Width (less 1) - encoded_id_pwidth_d
1330 *
1331 * Specifies the width of GPIO Port D. Ignored because there is no Port D in the
1332 * GPIO.
1333 *
1334 * Field Enumeration Values:
1335 *
1336 * Enum | Value | Description
1337 * :-------------------------------------------------------|:------|:--------------------------
1338 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS | 0x7 | Width (less 1) of 8 bits
1339 * ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS | 0x1c | Width (less 1) of 29 bits
1340 *
1341 * Field Access Macros:
1342 *
1343 */
1344/*
1345 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1346 *
1347 * Width (less 1) of 8 bits
1348 */
1349#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7
1350/*
1351 * Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
1352 *
1353 * Width (less 1) of 29 bits
1354 */
1355#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE29BITS 0x1c
1356
1357/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1358#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB 15
1359/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1360#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB 19
1361/* The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1362#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH 5
1363/* The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1364#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK 0x000f8000
1365/* The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value. */
1366#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK 0xfff07fff
1367/* The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field. */
1368#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET 0x7
1369/* Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register. */
1370#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value) (((value) & 0x000f8000) >> 15)
1371/* Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register. */
1372#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value) (((value) << 15) & 0x000f8000)
1373
1374#ifndef __ASSEMBLY__
1375/*
1376 * WARNING: The C register and register group struct declarations are provided for
1377 * convenience and illustrative purposes. They should, however, be used with
1378 * caution as the C language standard provides no guarantees about the alignment or
1379 * atomicity of device memory accesses. The recommended practice for writing
1380 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1381 * alt_write_word() functions.
1382 *
1383 * The struct declaration for register ALT_GPIO_CFG_REG2.
1384 */
1385struct ALT_GPIO_CFG_REG2_s
1386{
1387 const uint32_t encoded_id_pwidth_a : 5; /* Port A Width (less 1) */
1388 const uint32_t encoded_id_pwidth_b : 5; /* Port B Width (less 1) */
1389 const uint32_t encoded_id_pwidth_c : 5; /* Port C Width (less 1) */
1390 const uint32_t encoded_id_pwidth_d : 5; /* Port D Width (less 1) */
1391 uint32_t : 12; /* *UNDEFINED* */
1392};
1393
1394/* The typedef declaration for register ALT_GPIO_CFG_REG2. */
1395typedef volatile struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t;
1396#endif /* __ASSEMBLY__ */
1397
1398/* The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component. */
1399#define ALT_GPIO_CFG_REG2_OFST 0x70
1400/* The address of the ALT_GPIO_CFG_REG2 register. */
1401#define ALT_GPIO_CFG_REG2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST))
1402
1403/*
1404 * Register : Configuration Register 1 - gpio_config_reg1
1405 *
1406 * Reports settings of various GPIO configuration parameters
1407 *
1408 * Register Layout
1409 *
1410 * Bits | Access | Reset | Description
1411 * :--------|:-------|:------|:----------------------------------
1412 * [1:0] | R | 0x2 | APB DATA WIDTH
1413 * [3:2] | R | 0x0 | NUM PORTS
1414 * [4] | R | 0x1 | PORT A SINGLE CTL
1415 * [5] | R | 0x1 | PORT B SINGLE CTL
1416 * [6] | R | 0x1 | PORT C SINGLE CTL
1417 * [7] | R | 0x1 | PORT D SINGLE CTL
1418 * [8] | R | 0x0 | HW PORTA
1419 * [11:9] | ??? | 0x0 | *UNDEFINED*
1420 * [12] | R | 0x1 | Port A Interrupt Field
1421 * [13] | R | 0x1 | Debounce Field
1422 * [14] | R | 0x1 | Encoded GPIO Parameters Available
1423 * [15] | R | 0x1 | ID Field
1424 * [20:16] | R | 0x1f | Encoded ID Width Field
1425 * [31:21] | ??? | 0x0 | *UNDEFINED*
1426 *
1427 */
1428/*
1429 * Field : APB DATA WIDTH - apb_data_width
1430 *
1431 * Fixed to support an ABP data bus width of 32-bits.
1432 *
1433 * Field Enumeration Values:
1434 *
1435 * Enum | Value | Description
1436 * :-----------------------------------------------|:------|:-------------------------
1437 * ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS | 0x2 | APB Data Width = 32-bits
1438 *
1439 * Field Access Macros:
1440 *
1441 */
1442/*
1443 * Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
1444 *
1445 * APB Data Width = 32-bits
1446 */
1447#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
1448
1449/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1450#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0
1451/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1452#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1
1453/* The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1454#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2
1455/* The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1456#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003
1457/* The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value. */
1458#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
1459/* The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field. */
1460#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2
1461/* Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register. */
1462#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
1463/* Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register. */
1464#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
1465
1466/*
1467 * Field : NUM PORTS - num_ports
1468 *
1469 * The value of this register is fixed at one port (Port A).
1470 *
1471 * Field Enumeration Values:
1472 *
1473 * Enum | Value | Description
1474 * :---------------------------------------|:------|:-------------------------
1475 * ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA | 0x0 | Number of GPIO Ports = 1
1476 *
1477 * Field Access Macros:
1478 *
1479 */
1480/*
1481 * Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS
1482 *
1483 * Number of GPIO Ports = 1
1484 */
1485#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0
1486
1487/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1488#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2
1489/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1490#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3
1491/* The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1492#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2
1493/* The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1494#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c
1495/* The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value. */
1496#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3
1497/* The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field. */
1498#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0
1499/* Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register. */
1500#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2)
1501/* Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register. */
1502#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c)
1503
1504/*
1505 * Field : PORT A SINGLE CTL - porta_single_ctl
1506 *
1507 * Indicates the mode of operation of Port A to be software controlled only.
1508 *
1509 * Field Enumeration Values:
1510 *
1511 * Enum | Value | Description
1512 * :-------------------------------------------------|:------|:-----------------------------------------
1513 * ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1514 *
1515 * Field Access Macros:
1516 *
1517 */
1518/*
1519 * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
1520 *
1521 * Software Enabled Individual Port Control
1522 */
1523#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1
1524
1525/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1526#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4
1527/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1528#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4
1529/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1530#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1
1531/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1532#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010
1533/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value. */
1534#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef
1535/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field. */
1536#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1
1537/* Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register. */
1538#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4)
1539/* Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register. */
1540#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010)
1541
1542/*
1543 * Field : PORT B SINGLE CTL - portb_single_ctl
1544 *
1545 * Indicates the mode of operation of Port B to be software controlled only.
1546 * Ignored because there is no Port B in the GPIO.
1547 *
1548 * Field Enumeration Values:
1549 *
1550 * Enum | Value | Description
1551 * :-------------------------------------------------|:------|:-----------------------------------------
1552 * ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1553 *
1554 * Field Access Macros:
1555 *
1556 */
1557/*
1558 * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
1559 *
1560 * Software Enabled Individual Port Control
1561 */
1562#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1
1563
1564/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1565#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5
1566/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1567#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5
1568/* The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1569#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1
1570/* The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1571#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020
1572/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value. */
1573#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf
1574/* The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field. */
1575#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1
1576/* Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register. */
1577#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5)
1578/* Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register. */
1579#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020)
1580
1581/*
1582 * Field : PORT C SINGLE CTL - portc_single_ctl
1583 *
1584 * Indicates the mode of operation of Port C to be software controlled only.
1585 * Ignored because there is no Port C in the GPIO.
1586 *
1587 * Field Enumeration Values:
1588 *
1589 * Enum | Value | Description
1590 * :-------------------------------------------------|:------|:-----------------------------------------
1591 * ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1592 *
1593 * Field Access Macros:
1594 *
1595 */
1596/*
1597 * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
1598 *
1599 * Software Enabled Individual Port Control
1600 */
1601#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1
1602
1603/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1604#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6
1605/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1606#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6
1607/* The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1608#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1
1609/* The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1610#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040
1611/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value. */
1612#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf
1613/* The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field. */
1614#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1
1615/* Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register. */
1616#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6)
1617/* Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register. */
1618#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040)
1619
1620/*
1621 * Field : PORT D SINGLE CTL - portd_single_ctl
1622 *
1623 * Indicates the mode of operation of Port D to be software controlled only.
1624 * Ignored because there is no Port D in the GPIO.
1625 *
1626 * Field Enumeration Values:
1627 *
1628 * Enum | Value | Description
1629 * :-------------------------------------------------|:------|:-----------------------------------------
1630 * ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY | 0x1 | Software Enabled Individual Port Control
1631 *
1632 * Field Access Macros:
1633 *
1634 */
1635/*
1636 * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
1637 *
1638 * Software Enabled Individual Port Control
1639 */
1640#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1
1641
1642/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1643#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7
1644/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1645#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7
1646/* The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1647#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1
1648/* The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1649#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080
1650/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value. */
1651#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f
1652/* The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field. */
1653#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1
1654/* Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register. */
1655#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7)
1656/* Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register. */
1657#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080)
1658
1659/*
1660 * Field : HW PORTA - hw_porta
1661 *
1662 * The value is fixed to enable Port A configuration to be controlled by software
1663 * only.
1664 *
1665 * Field Enumeration Values:
1666 *
1667 * Enum | Value | Description
1668 * :-----------------------------------------|:------|:---------------------------------------
1669 * ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD | 0x0 | Software Configuration Control Enabled
1670 *
1671 * Field Access Macros:
1672 *
1673 */
1674/*
1675 * Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA
1676 *
1677 * Software Configuration Control Enabled
1678 */
1679#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0
1680
1681/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1682#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8
1683/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1684#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8
1685/* The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1686#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1
1687/* The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1688#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100
1689/* The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value. */
1690#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff
1691/* The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field. */
1692#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0
1693/* Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register. */
1694#define ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8)
1695/* Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register. */
1696#define ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100)
1697
1698/*
1699 * Field : Port A Interrupt Field - porta_intr
1700 *
1701 * The value of this field is fixed to allow interrupts on Port A.
1702 *
1703 * Field Enumeration Values:
1704 *
1705 * Enum | Value | Description
1706 * :-------------------------------------------|:------|:--------------------------
1707 * ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR | 0x1 | Port A Interrupts Enabled
1708 *
1709 * Field Access Macros:
1710 *
1711 */
1712/*
1713 * Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR
1714 *
1715 * Port A Interrupts Enabled
1716 */
1717#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1
1718
1719/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1720#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12
1721/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1722#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12
1723/* The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1724#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1
1725/* The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
1726#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000
1727/* The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value. */
1728#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff
1729/* The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field. */
1730#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1
1731/* Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register. */
1732#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12)
1733/* Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register. */
1734#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000)
1735
1736/*
1737 * Field : Debounce Field - debounce
1738 *
1739 * The value of this field is fixed to allow debouncing of the Port A signals.
1740 *
1741 * Field Enumeration Values:
1742 *
1743 * Enum | Value | Description
1744 * :---------------------------------------|:------|:--------------------
1745 * ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA | 0x1 | Debounce is Enabled
1746 *
1747 * Field Access Macros:
1748 *
1749 */
1750/*
1751 * Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE
1752 *
1753 * Debounce is Enabled
1754 */
1755#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1
1756
1757/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1758#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13
1759/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1760#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13
1761/* The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1762#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1
1763/* The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
1764#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000
1765/* The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value. */
1766#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff
1767/* The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field. */
1768#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1
1769/* Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register. */
1770#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13)
1771/* Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register. */
1772#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000)
1773
1774/*
1775 * Field : Encoded GPIO Parameters Available - add_encoded_params
1776 *
1777 * Fixed to allow the indentification of the Designware IP component.
1778 *
1779 * Field Enumeration Values:
1780 *
1781 * Enum | Value | Description
1782 * :------------------------------------------------|:------|:--------------------------
1783 * ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS | 0x1 | Enable IP indentification
1784 *
1785 * Field Access Macros:
1786 *
1787 */
1788/*
1789 * Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
1790 *
1791 * Enable IP indentification
1792 */
1793#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
1794
1795/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1796#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14
1797/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1798#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14
1799/* The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1800#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1
1801/* The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
1802#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000
1803/* The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value. */
1804#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff
1805/* The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field. */
1806#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1
1807/* Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register. */
1808#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14)
1809/* Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register. */
1810#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000)
1811
1812/*
1813 * Field : ID Field - gpio_id
1814 *
1815 * Provides an ID code value
1816 *
1817 * Field Enumeration Values:
1818 *
1819 * Enum | Value | Description
1820 * :-----------------------------------|:------|:-------------
1821 * ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE | 0x1 | GPIO ID Code
1822 *
1823 * Field Access Macros:
1824 *
1825 */
1826/*
1827 * Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID
1828 *
1829 * GPIO ID Code
1830 */
1831#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1
1832
1833/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1834#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15
1835/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1836#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15
1837/* The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1838#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1
1839/* The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
1840#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000
1841/* The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value. */
1842#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff
1843/* The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field. */
1844#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1
1845/* Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register. */
1846#define ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15)
1847/* Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register. */
1848#define ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000)
1849
1850/*
1851 * Field : Encoded ID Width Field - encoded_id_width
1852 *
1853 * This value is fixed at 32 bits.
1854 *
1855 * Field Enumeration Values:
1856 *
1857 * Enum | Value | Description
1858 * :--------------------------------------------|:------|:------------------
1859 * ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH | 0x1f | Width of ID Field
1860 *
1861 * Field Access Macros:
1862 *
1863 */
1864/*
1865 * Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
1866 *
1867 * Width of ID Field
1868 */
1869#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f
1870
1871/* The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1872#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16
1873/* The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1874#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20
1875/* The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1876#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5
1877/* The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
1878#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000
1879/* The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value. */
1880#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff
1881/* The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field. */
1882#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f
1883/* Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register. */
1884#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16)
1885/* Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register. */
1886#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000)
1887
1888#ifndef __ASSEMBLY__
1889/*
1890 * WARNING: The C register and register group struct declarations are provided for
1891 * convenience and illustrative purposes. They should, however, be used with
1892 * caution as the C language standard provides no guarantees about the alignment or
1893 * atomicity of device memory accesses. The recommended practice for writing
1894 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1895 * alt_write_word() functions.
1896 *
1897 * The struct declaration for register ALT_GPIO_CFG_REG1.
1898 */
1899struct ALT_GPIO_CFG_REG1_s
1900{
1901 const uint32_t apb_data_width : 2; /* APB DATA WIDTH */
1902 const uint32_t num_ports : 2; /* NUM PORTS */
1903 const uint32_t porta_single_ctl : 1; /* PORT A SINGLE CTL */
1904 const uint32_t portb_single_ctl : 1; /* PORT B SINGLE CTL */
1905 const uint32_t portc_single_ctl : 1; /* PORT C SINGLE CTL */
1906 const uint32_t portd_single_ctl : 1; /* PORT D SINGLE CTL */
1907 const uint32_t hw_porta : 1; /* HW PORTA */
1908 uint32_t : 3; /* *UNDEFINED* */
1909 const uint32_t porta_intr : 1; /* Port A Interrupt Field */
1910 const uint32_t debounce : 1; /* Debounce Field */
1911 const uint32_t add_encoded_params : 1; /* Encoded GPIO Parameters Available */
1912 const uint32_t gpio_id : 1; /* ID Field */
1913 const uint32_t encoded_id_width : 5; /* Encoded ID Width Field */
1914 uint32_t : 11; /* *UNDEFINED* */
1915};
1916
1917/* The typedef declaration for register ALT_GPIO_CFG_REG1. */
1918typedef volatile struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t;
1919#endif /* __ASSEMBLY__ */
1920
1921/* The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component. */
1922#define ALT_GPIO_CFG_REG1_OFST 0x74
1923/* The address of the ALT_GPIO_CFG_REG1 register. */
1924#define ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST))
1925
1926#ifndef __ASSEMBLY__
1927/*
1928 * WARNING: The C register and register group struct declarations are provided for
1929 * convenience and illustrative purposes. They should, however, be used with
1930 * caution as the C language standard provides no guarantees about the alignment or
1931 * atomicity of device memory accesses. The recommended practice for writing
1932 * hardware drivers is to use the SoCAL access macros and alt_read_word() and
1933 * alt_write_word() functions.
1934 *
1935 * The struct declaration for register group ALT_GPIO.
1936 */
1937struct ALT_GPIO_s
1938{
1939 volatile ALT_GPIO_SWPORTA_DR_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
1940 volatile ALT_GPIO_SWPORTA_DDR_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
1941 volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
1942 volatile ALT_GPIO_INTEN_t gpio_inten; /* ALT_GPIO_INTEN */
1943 volatile ALT_GPIO_INTMSK_t gpio_intmask; /* ALT_GPIO_INTMSK */
1944 volatile ALT_GPIO_INTTYPE_LEVEL_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
1945 volatile ALT_GPIO_INT_POL_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
1946 volatile ALT_GPIO_INTSTAT_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
1947 volatile ALT_GPIO_RAW_INTSTAT_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
1948 volatile ALT_GPIO_DEBOUNCE_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
1949 volatile ALT_GPIO_PORTA_EOI_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
1950 volatile ALT_GPIO_EXT_PORTA_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
1951 volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
1952 volatile ALT_GPIO_LS_SYNC_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
1953 volatile ALT_GPIO_ID_CODE_t gpio_id_code; /* ALT_GPIO_ID_CODE */
1954 volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
1955 volatile ALT_GPIO_VER_ID_CODE_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
1956 volatile ALT_GPIO_CFG_REG2_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
1957 volatile ALT_GPIO_CFG_REG1_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
1958 volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
1959};
1960
1961/* The typedef declaration for register group ALT_GPIO. */
1962typedef volatile struct ALT_GPIO_s ALT_GPIO_t;
1963/* The struct declaration for the raw register contents of register group ALT_GPIO. */
1964struct ALT_GPIO_raw_s
1965{
1966 volatile uint32_t gpio_swporta_dr; /* ALT_GPIO_SWPORTA_DR */
1967 volatile uint32_t gpio_swporta_ddr; /* ALT_GPIO_SWPORTA_DDR */
1968 volatile uint32_t _pad_0x8_0x2f[10]; /* *UNDEFINED* */
1969 volatile uint32_t gpio_inten; /* ALT_GPIO_INTEN */
1970 volatile uint32_t gpio_intmask; /* ALT_GPIO_INTMSK */
1971 volatile uint32_t gpio_inttype_level; /* ALT_GPIO_INTTYPE_LEVEL */
1972 volatile uint32_t gpio_int_polarity; /* ALT_GPIO_INT_POL */
1973 volatile uint32_t gpio_intstatus; /* ALT_GPIO_INTSTAT */
1974 volatile uint32_t gpio_raw_intstatus; /* ALT_GPIO_RAW_INTSTAT */
1975 volatile uint32_t gpio_debounce; /* ALT_GPIO_DEBOUNCE */
1976 volatile uint32_t gpio_porta_eoi; /* ALT_GPIO_PORTA_EOI */
1977 volatile uint32_t gpio_ext_porta; /* ALT_GPIO_EXT_PORTA */
1978 volatile uint32_t _pad_0x54_0x5f[3]; /* *UNDEFINED* */
1979 volatile uint32_t gpio_ls_sync; /* ALT_GPIO_LS_SYNC */
1980 volatile uint32_t gpio_id_code; /* ALT_GPIO_ID_CODE */
1981 volatile uint32_t _pad_0x68_0x6b; /* *UNDEFINED* */
1982 volatile uint32_t gpio_ver_id_code; /* ALT_GPIO_VER_ID_CODE */
1983 volatile uint32_t gpio_config_reg2; /* ALT_GPIO_CFG_REG2 */
1984 volatile uint32_t gpio_config_reg1; /* ALT_GPIO_CFG_REG1 */
1985 volatile uint32_t _pad_0x78_0x80[2]; /* *UNDEFINED* */
1986};
1987
1988/* The typedef declaration for the raw register contents of register group ALT_GPIO. */
1989typedef volatile struct ALT_GPIO_raw_s ALT_GPIO_raw_t;
1990#endif /* __ASSEMBLY__ */
1991
1992
1993#ifdef __cplusplus
1994}
1995#endif /* __cplusplus */
1996#endif /* __ALTERA_ALT_GPIO_H__ */
1997
ALT_GPIO_CFG_REG1_s
Definition: alt_gpio.h:1900
ALT_GPIO_CFG_REG2_s
Definition: alt_gpio.h:1386
ALT_GPIO_DEBOUNCE_s
Definition: alt_gpio.h:801
ALT_GPIO_EXT_PORTA_s
Definition: alt_gpio.h:951
ALT_GPIO_ID_CODE_s
Definition: alt_gpio.h:1098
ALT_GPIO_INTEN_s
Definition: alt_gpio.h:288
ALT_GPIO_INTMSK_s
Definition: alt_gpio.h:374
ALT_GPIO_INTSTAT_s
Definition: alt_gpio.h:629
ALT_GPIO_INTTYPE_LEVEL_s
Definition: alt_gpio.h:459
ALT_GPIO_INT_POL_s
Definition: alt_gpio.h:545
ALT_GPIO_LS_SYNC_s
Definition: alt_gpio.h:1035
ALT_GPIO_PORTA_EOI_s
Definition: alt_gpio.h:885
ALT_GPIO_RAW_INTSTAT_s
Definition: alt_gpio.h:715
ALT_GPIO_SWPORTA_DDR_s
Definition: alt_gpio.h:201
ALT_GPIO_SWPORTA_DR_s
Definition: alt_gpio.h:111
ALT_GPIO_VER_ID_CODE_s
Definition: alt_gpio.h:1161
ALT_GPIO_raw_s
Definition: alt_gpio.h:1965
ALT_GPIO_s
Definition: alt_gpio.h:1938
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