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RTEMS 6.1-rc1
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Implementations for interrupt mechanisms for Time Test 27. More...
Go to the source code of this file.
Macros | |
| #define | SIS_USE_SYNCHRONOUS_TRAP 0 |
| #define | TEST_INTERRUPT_SOURCE 5 |
| #define | TEST_INTERRUPT_SOURCE2 6 |
| #define | MUST_WAIT_FOR_INTERRUPT 1 |
| #define | Lower_tm27_intr() /* empty */ |
Variables | |
| uint32_t | Interrupt_nest |
Implementations for interrupt mechanisms for Time Test 27.