RTEMS 6.1-rc1
stm32h7xx_hal_flash_ex.h
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1
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef STM32H7xx_HAL_FLASH_EX_H
20#define STM32H7xx_HAL_FLASH_EX_H
21
22#ifdef __cplusplus
23 extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32h7xx_hal_def.h"
28
37/* Exported types ------------------------------------------------------------*/
46typedef struct
47{
48 uint32_t TypeErase;
51 uint32_t Banks;
54 uint32_t Sector;
57 uint32_t NbSectors;
60 uint32_t VoltageRange;
64
65
69typedef struct
70{
71 uint32_t OptionType;
74 uint32_t WRPState;
77 uint32_t WRPSector;
80 uint32_t RDPLevel;
83 uint32_t BORLevel;
86 uint32_t USERType;
89 uint32_t USERConfig;
92 uint32_t Banks;
95 uint32_t PCROPConfig;
99 uint32_t PCROPStartAddr;
102 uint32_t PCROPEndAddr;
105 uint32_t BootConfig;
108 uint32_t BootAddr0;
111 uint32_t BootAddr1;
113#if defined(DUAL_CORE)
114 uint32_t CM4BootConfig;
118 uint32_t CM4BootAddr0;
121 uint32_t CM4BootAddr1;
123#endif /*DUAL_CORE*/
124
135#if defined (FLASH_OTPBL_LOCKBL)
136 uint32_t OTPBlockLock;
138#endif /* FLASH_OTPBL_LOCKBL */
139
140#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
141 uint32_t SharedRamConfig;
143#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
144
145#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
146 uint32_t FreqBoostState;
148#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
149
151
155typedef struct
156{
157 uint32_t TypeCRC;
160 uint32_t BurstSize;
163 uint32_t Bank;
166 uint32_t Sector;
169 uint32_t NbSectors;
172 uint32_t CRCStartAddr;
175 uint32_t CRCEndAddr;
179
183/* Exported constants --------------------------------------------------------*/
184
194#define FLASH_TYPEERASE_SECTORS 0x00U
195#define FLASH_TYPEERASE_MASSERASE 0x01U
200#if defined (FLASH_CR_PSIZE)
205#define FLASH_VOLTAGE_RANGE_1 0x00000000U
206#define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0
207#define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1
208#define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE
212#endif /* FLASH_CR_PSIZE */
213
218#define OB_WRPSTATE_DISABLE 0x00000000U
219#define OB_WRPSTATE_ENABLE 0x00000001U
228#define OPTIONBYTE_WRP 0x01U
229#define OPTIONBYTE_RDP 0x02U
230#define OPTIONBYTE_USER 0x04U
231#define OPTIONBYTE_PCROP 0x08U
232#define OPTIONBYTE_BOR 0x10U
233#define OPTIONBYTE_SECURE_AREA 0x20U
234#if defined (DUAL_CORE)
235#define OPTIONBYTE_CM7_BOOTADD 0x40U
236#define OPTIONBYTE_CM4_BOOTADD 0x80U
237#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD
238#else /* Single core */
239#define OPTIONBYTE_BOOTADD 0x40U
240#endif /*DUAL_CORE*/
241#if defined (FLASH_OTPBL_LOCKBL)
242#define OPTIONBYTE_OTP_LOCK 0x80U
243#endif /* FLASH_OTPBL_LOCKBL */
244#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
245#define OPTIONBYTE_SHARED_RAM 0x100U
246#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
247#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
248#define OPTIONBYTE_FREQ_BOOST 0x200U
249#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
250
251#if defined (DUAL_CORE)
252#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
253 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
254 OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD)
255#elif defined (FLASH_OTPBL_LOCKBL)
256#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
257 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
258 OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK)
259#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
260#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
261 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
262 OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST)
263#else
264#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
265 OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
266 OPTIONBYTE_BOOTADD)
267#endif /* DUAL_CORE */
276#define OB_RDP_LEVEL_0 0xAA00U
277#define OB_RDP_LEVEL_1 0x5500U
278#define OB_RDP_LEVEL_2 0xCC00U
288#define OB_IWDG_SW OB_IWDG1_SW
289#define OB_IWDG_HW OB_IWDG1_HW
298#define OB_STOP_NO_RST 0x40U
299#define OB_STOP_RST 0x00U
308#define OB_STDBY_NO_RST 0x80U
309#define OB_STDBY_RST 0x00U
318#define OB_IWDG_STOP_FREEZE 0x00000000U
319#define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP
328#define OB_IWDG_STDBY_FREEZE 0x00000000U
329#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY
338#define OB_BOR_LEVEL0 0x00000000U
339#define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
340#define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
341#define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)
352#define OB_BOOTADDR_ITCM_RAM 0x0000U
353#define OB_BOOTADDR_SYSTEM 0x0040U
354#define OB_BOOTADDR_ITCM_FLASH 0x0080U
355#define OB_BOOTADDR_AXIM_FLASH 0x2000U
356#define OB_BOOTADDR_DTCM_RAM 0x8000U
357#define OB_BOOTADDR_SRAM1 0x8004U
358#define OB_BOOTADDR_SRAM2 0x8013U
367#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
368#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
369#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
370#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
371#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
372#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
373#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
374#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
376/* Unused FLASH Latency defines */
377#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
378#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
379#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
380#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
381#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
382#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
383#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
384#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
393#define FLASH_BANK_1 0x01U
394#if defined (DUAL_BANK)
395#define FLASH_BANK_2 0x02U
396#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)
397#endif /* DUAL_BANK */
406#define OB_PCROP_RDP_NOT_ERASE 0x00000000U
408#define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP
419#if (FLASH_SECTOR_TOTAL == 128)
420#define OB_WRP_SECTOR_0TO3 0x00000001U
421#define OB_WRP_SECTOR_4TO7 0x00000002U
422#define OB_WRP_SECTOR_8TO11 0x00000004U
423#define OB_WRP_SECTOR_12TO15 0x00000008U
424#define OB_WRP_SECTOR_16TO19 0x00000010U
425#define OB_WRP_SECTOR_20TO23 0x00000020U
426#define OB_WRP_SECTOR_24TO27 0x00000040U
427#define OB_WRP_SECTOR_28TO31 0x00000080U
428#define OB_WRP_SECTOR_32TO35 0x00000100U
429#define OB_WRP_SECTOR_36TO39 0x00000200U
430#define OB_WRP_SECTOR_40TO43 0x00000400U
431#define OB_WRP_SECTOR_44TO47 0x00000800U
432#define OB_WRP_SECTOR_48TO51 0x00001000U
433#define OB_WRP_SECTOR_52TO55 0x00002000U
434#define OB_WRP_SECTOR_56TO59 0x00004000U
435#define OB_WRP_SECTOR_60TO63 0x00008000U
436#define OB_WRP_SECTOR_64TO67 0x00010000U
437#define OB_WRP_SECTOR_68TO71 0x00020000U
438#define OB_WRP_SECTOR_72TO75 0x00040000U
439#define OB_WRP_SECTOR_76TO79 0x00080000U
440#define OB_WRP_SECTOR_80TO83 0x00100000U
441#define OB_WRP_SECTOR_84TO87 0x00200000U
442#define OB_WRP_SECTOR_88TO91 0x00400000U
443#define OB_WRP_SECTOR_92TO95 0x00800000U
444#define OB_WRP_SECTOR_96TO99 0x01000000U
445#define OB_WRP_SECTOR_100TO103 0x02000000U
446#define OB_WRP_SECTOR_104TO107 0x04000000U
447#define OB_WRP_SECTOR_108TO111 0x08000000U
448#define OB_WRP_SECTOR_112TO115 0x10000000U
449#define OB_WRP_SECTOR_116TO119 0x20000000U
450#define OB_WRP_SECTOR_120TO123 0x40000000U
451#define OB_WRP_SECTOR_124TO127 0x80000000U
452#define OB_WRP_SECTOR_ALL 0xFFFFFFFFU
453#else
454#define OB_WRP_SECTOR_0 0x00000001U
455#define OB_WRP_SECTOR_1 0x00000002U
456#define OB_WRP_SECTOR_2 0x00000004U
457#define OB_WRP_SECTOR_3 0x00000008U
458#define OB_WRP_SECTOR_4 0x00000010U
459#define OB_WRP_SECTOR_5 0x00000020U
460#define OB_WRP_SECTOR_6 0x00000040U
461#define OB_WRP_SECTOR_7 0x00000080U
462#define OB_WRP_SECTOR_ALL 0x000000FFU
463#endif /* FLASH_SECTOR_TOTAL == 128 */
472#define OB_SECURITY_DISABLE 0x00000000U
473#define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY
482#define OB_ST_RAM_SIZE_2KB 0x00000000U
483#define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
484#define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
485#define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE
490#if defined(DUAL_CORE)
495#define OB_BCM7_DISABLE 0x00000000U
496#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7
506#define OB_BCM4_DISABLE 0x00000000U
507#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4
511#endif /* DUAL_CORE */
512
517#define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
518#define OB_IWDG1_HW 0x00000000U
523#if defined(DUAL_CORE)
528#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW
529#define OB_IWDG2_HW 0x00000000U
533#endif
534
539#define OB_STOP_RST_D1 0x00000000U
540#define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1
549#define OB_STDBY_RST_D1 0x00000000U
550#define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1
555#if defined (FLASH_OPTSR_NRST_STOP_D2)
560#define OB_STOP_RST_D2 0x00000000U
561#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2
570#define OB_STDBY_RST_D2 0x00000000U
571#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2
575#endif /* FLASH_OPTSR_NRST_STOP_D2 */
576
577#if defined (DUAL_BANK)
582#define OB_SWAP_BANK_DISABLE 0x00000000U
583#define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT
587#endif /* DUAL_BANK */
588
593#define OB_IOHSLV_DISABLE 0x00000000U
594#define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV
599#if defined (FLASH_OPTSR_VDDMMC_HSLV)
604#define OB_VDDMMC_HSLV_DISABLE 0x00000000U
605#define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV
609#endif /* FLASH_OPTSR_VDDMMC_HSLV */
610
611#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
616#define OB_CPUFREQ_BOOST_DISABLE 0x00000000U
617#define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST
621#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
622
623#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
628#define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U
629#define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0
630#define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1
631#define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED
635#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
636
641#define OB_USER_IWDG1_SW 0x0001U
642#define OB_USER_NRST_STOP_D1 0x0002U
643#define OB_USER_NRST_STDBY_D1 0x0004U
644#define OB_USER_IWDG_STOP 0x0008U
645#define OB_USER_IWDG_STDBY 0x0010U
646#define OB_USER_ST_RAM_SIZE 0x0020U
647#define OB_USER_SECURITY 0x0040U
648#define OB_USER_IOHSLV 0x0080U
649#if defined (DUAL_BANK)
650#define OB_USER_SWAP_BANK 0x0100U
651#endif /* DUAL_BANK */
652#if defined (FLASH_OPTSR_VDDMMC_HSLV)
653#define OB_USER_VDDMMC_HSLV 0x0200U
654#endif /* FLASH_OPTSR_VDDMMC_HSLV */
655#if defined (DUAL_CORE)
656#define OB_USER_IWDG2_SW 0x0200U
657#define OB_USER_BCM4 0x0400U
658#define OB_USER_BCM7 0x0800U
659#endif /*DUAL_CORE*/
660#if defined (FLASH_OPTSR_NRST_STOP_D2)
661#define OB_USER_NRST_STOP_D2 0x1000U
662#define OB_USER_NRST_STDBY_D2 0x2000U
663#endif /* FLASH_OPTSR_NRST_STOP_D2 */
664
665#if defined (DUAL_CORE)
666#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
667 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
668 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
669 OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
670 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
671#elif defined (FLASH_OPTSR_VDDMMC_HSLV)
672#if defined (DUAL_BANK)
673#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
674 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
675 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
676 OB_USER_VDDMMC_HSLV)
677#else
678#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
679 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
680 OB_USER_SECURITY | OB_USER_IOHSLV |\
681 OB_USER_VDDMMC_HSLV)
682#endif /* DUAL_BANK */
683#elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
684#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
685 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
686 OB_USER_SECURITY | OB_USER_IOHSLV |\
687 OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
688#else /* Single core */
689#if defined (DUAL_BANK)
690#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
691 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
692 OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
693#else
694#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
695 OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
696 OB_USER_SECURITY | OB_USER_IOHSLV )
697#endif /* DUAL_BANK */
698#endif /* DUAL_CORE */
707#define OB_BOOT_ADD0 0x01U
708#define OB_BOOT_ADD1 0x02U
709#define OB_BOOT_ADD_BOTH 0x03U
718#define OB_SECURE_RDP_NOT_ERASE 0x00000000U
720#define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES
730#define FLASH_CRC_ADDR 0x00000000U
731#define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
732#define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)
741#define FLASH_CRC_BURST_SIZE_4 0x00000000U
742#define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
743#define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
744#define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST
753#define FLASH_PROGRAMMING_DELAY_0 0x00000000U
754#define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
755#define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
756#define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ
761#if defined (FLASH_OTPBL_LOCKBL)
766#define FLASH_OTP_BLOCK_0 0x00000001U
767#define FLASH_OTP_BLOCK_1 0x00000002U
768#define FLASH_OTP_BLOCK_2 0x00000004U
769#define FLASH_OTP_BLOCK_3 0x00000008U
770#define FLASH_OTP_BLOCK_4 0x00000010U
771#define FLASH_OTP_BLOCK_5 0x00000020U
772#define FLASH_OTP_BLOCK_6 0x00000040U
773#define FLASH_OTP_BLOCK_7 0x00000080U
774#define FLASH_OTP_BLOCK_8 0x00000100U
775#define FLASH_OTP_BLOCK_9 0x00000200U
776#define FLASH_OTP_BLOCK_10 0x00000400U
777#define FLASH_OTP_BLOCK_11 0x00000800U
778#define FLASH_OTP_BLOCK_12 0x00001000U
779#define FLASH_OTP_BLOCK_13 0x00002000U
780#define FLASH_OTP_BLOCK_14 0x00004000U
781#define FLASH_OTP_BLOCK_15 0x00008000U
782#define FLASH_OTP_BLOCK_ALL 0x0000FFFFU
786#endif /* FLASH_OTPBL_LOCKBL */
791/* Exported macro ------------------------------------------------------------*/
802#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
803
804#if defined (FLASH_CR_PSIZE)
812#if defined (DUAL_BANK)
813#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
814 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
815 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
816#else
817#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
818#endif /* DUAL_BANK */
819
826#if defined (DUAL_BANK)
827#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
828 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
829 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
830#else
831#define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
832#endif /* DUAL_BANK */
833
834#endif /* FLASH_CR_PSIZE */
835
842#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
843
849#define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
854/* Exported functions --------------------------------------------------------*/
862/* Extension Program operation functions *************************************/
863HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
864HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
865HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
866void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
867
868HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
869HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
870#if defined (DUAL_BANK)
871HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
872HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
873#endif /* DUAL_BANK */
874
875HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
876
884/* Private types -------------------------------------------------------------*/
885/* Private variables ---------------------------------------------------------*/
886/* Private constants ---------------------------------------------------------*/
887/* Private macros ------------------------------------------------------------*/
898#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
899 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
900
901#if defined (FLASH_CR_PSIZE)
902#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
903 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
904 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
905 ((RANGE) == FLASH_VOLTAGE_RANGE_4))
906#endif /* FLASH_CR_PSIZE */
907
908#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
909 ((VALUE) == OB_WRPSTATE_ENABLE))
910
911#define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
912 (((VALUE) & ~OPTIONBYTE_ALL) == 0U))
913
914#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
915
916#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
917 ((LEVEL) == OB_RDP_LEVEL_1) ||\
918 ((LEVEL) == OB_RDP_LEVEL_2))
919
920#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
921
922#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
923
924#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
925
926#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
927
928#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
929
930#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
931 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
932
933#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
934 ((LATENCY) == FLASH_LATENCY_1) || \
935 ((LATENCY) == FLASH_LATENCY_2) || \
936 ((LATENCY) == FLASH_LATENCY_3) || \
937 ((LATENCY) == FLASH_LATENCY_4) || \
938 ((LATENCY) == FLASH_LATENCY_5) || \
939 ((LATENCY) == FLASH_LATENCY_6) || \
940 ((LATENCY) == FLASH_LATENCY_7) || \
941 ((LATENCY) == FLASH_LATENCY_8) || \
942 ((LATENCY) == FLASH_LATENCY_9) || \
943 ((LATENCY) == FLASH_LATENCY_10) || \
944 ((LATENCY) == FLASH_LATENCY_11) || \
945 ((LATENCY) == FLASH_LATENCY_12) || \
946 ((LATENCY) == FLASH_LATENCY_13) || \
947 ((LATENCY) == FLASH_LATENCY_14) || \
948 ((LATENCY) == FLASH_LATENCY_15))
949
950#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
951
952#if (FLASH_SECTOR_TOTAL == 8U)
953#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
954#else
955#define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
956#endif /* FLASH_SECTOR_TOTAL == 8U */
957
958#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
959 ((CONFIG) == OB_PCROP_RDP_ERASE))
960
961#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
962 ((CONFIG) == OB_SECURE_RDP_ERASE))
963
964#if defined (DUAL_BANK)
965#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
966#endif /* DUAL_BANK */
967
968#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
969
970#if defined (FLASH_OPTSR_VDDMMC_HSLV)
971#define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
972#endif /* FLASH_OPTSR_VDDMMC_HSLV */
973
974#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
975#if defined (DUAL_CORE)
976#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
977#endif /* DUAL_CORE */
978#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
979
980#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
981
982#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
983
984#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
985
986#define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
987 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
988
989#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
990
991#if defined (DUAL_CORE)
992#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
993
994#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
995#endif /* DUAL_CORE */
996
997#if defined (FLASH_OPTSR_NRST_STOP_D2)
998#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
999
1000#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
1001#endif /* FLASH_OPTSR_NRST_STOP_D2 */
1002
1003#if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
1004#define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
1005 ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
1006#endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
1007
1008#if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
1009#define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
1010#endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
1011
1012#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
1013 (((TYPE) & ~OB_USER_ALL) == 0U))
1014
1015#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
1016 ((VALUE) == OB_BOOT_ADD1) || \
1017 ((VALUE) == OB_BOOT_ADD_BOTH))
1018
1019#define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
1020 ((VALUE) == FLASH_CRC_SECTORS) || \
1021 ((VALUE) == FLASH_CRC_BANK))
1022
1023#if defined (FLASH_OTPBL_LOCKBL)
1024#define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
1025#endif /* FLASH_OTPBL_LOCKBL */
1034/* Private functions ---------------------------------------------------------*/
1039void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
1052#ifdef __cplusplus
1053}
1054#endif
1055
1056#endif /* STM32H7xx_HAL_FLASH_EX_H */
1057
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
FLASH Erase structure definition.
Definition: stm32h7xx_hal_flash_ex.h:156
uint32_t TypeCRC
Definition: stm32h7xx_hal_flash_ex.h:157
uint32_t BurstSize
Definition: stm32h7xx_hal_flash_ex.h:160
uint32_t CRCStartAddr
Definition: stm32h7xx_hal_flash_ex.h:172
uint32_t Sector
Definition: stm32h7xx_hal_flash_ex.h:166
uint32_t NbSectors
Definition: stm32h7xx_hal_flash_ex.h:169
uint32_t Bank
Definition: stm32h7xx_hal_flash_ex.h:163
uint32_t CRCEndAddr
Definition: stm32h7xx_hal_flash_ex.h:175
FLASH Erase structure definition.
Definition: stm32h7xx_hal_flash_ex.h:47
uint32_t Sector
Definition: stm32h7xx_hal_flash_ex.h:54
uint32_t VoltageRange
Definition: stm32h7xx_hal_flash_ex.h:60
uint32_t TypeErase
Definition: stm32h7xx_hal_flash_ex.h:48
uint32_t Banks
Definition: stm32h7xx_hal_flash_ex.h:51
uint32_t NbSectors
Definition: stm32h7xx_hal_flash_ex.h:57
FLASH Option Bytes Program structure definition.
Definition: stm32h7xx_hal_flash_ex.h:70
uint32_t BootAddr0
Definition: stm32h7xx_hal_flash_ex.h:108
uint32_t RDPLevel
Definition: stm32h7xx_hal_flash_ex.h:80
uint32_t WRPState
Definition: stm32h7xx_hal_flash_ex.h:74
uint32_t BootAddr1
Definition: stm32h7xx_hal_flash_ex.h:111
uint32_t PCROPConfig
Definition: stm32h7xx_hal_flash_ex.h:95
uint32_t SecureAreaConfig
Definition: stm32h7xx_hal_flash_ex.h:125
uint32_t OptionType
Definition: stm32h7xx_hal_flash_ex.h:71
uint32_t BORLevel
Definition: stm32h7xx_hal_flash_ex.h:83
uint32_t Banks
Definition: stm32h7xx_hal_flash_ex.h:92
uint32_t SecureAreaStartAddr
Definition: stm32h7xx_hal_flash_ex.h:129
uint32_t USERType
Definition: stm32h7xx_hal_flash_ex.h:86
uint32_t WRPSector
Definition: stm32h7xx_hal_flash_ex.h:77
uint32_t SecureAreaEndAddr
Definition: stm32h7xx_hal_flash_ex.h:132
uint32_t BootConfig
Definition: stm32h7xx_hal_flash_ex.h:105
uint32_t PCROPStartAddr
Definition: stm32h7xx_hal_flash_ex.h:99
uint32_t PCROPEndAddr
Definition: stm32h7xx_hal_flash_ex.h:102
uint32_t USERConfig
Definition: stm32h7xx_hal_flash_ex.h:89