37#ifndef _RTEMS_SCORE_CPU_H
38#define _RTEMS_SCORE_CPU_H
41#if defined(RTEMS_PARAVIRT)
42#include <rtems/score/paravirt.h>
45#include <libcpu/vectors.h>
59#define AARCH64_PSTATE_N (1LL << 31)
60#define AARCH64_PSTATE_Z (1LL << 30)
61#define AARCH64_PSTATE_C (1LL << 29)
62#define AARCH64_PSTATE_V (1LL << 28)
63#define AARCH64_PSTATE_D (1LL << 9)
64#define AARCH64_PSTATE_A (1LL << 8)
65#define AARCH64_PSTATE_I (1LL << 7)
66#define AARCH64_PSTATE_F (1LL << 6)
73#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
75#define CPU_ISR_PASSES_FRAME_POINTER FALSE
77#define CPU_HARDWARE_FP FALSE
79#define CPU_SOFTWARE_FP FALSE
81#define CPU_ALL_TASKS_ARE_FP FALSE
83#define CPU_IDLE_TASK_IS_FP FALSE
85#define CPU_USE_DEFERRED_FP_SWITCH FALSE
87#define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
89#define CPU_STACK_GROWS_UP FALSE
91#if defined(AARCH64_MULTILIB_CACHE_LINE_MAX_64)
92 #define CPU_CACHE_LINE_BYTES 64
94 #define CPU_CACHE_LINE_BYTES 32
97#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
99#define CPU_MODES_INTERRUPT_MASK 0x1
101#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
103#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
105#define CPU_STACK_MINIMUM_SIZE (1024 * 8)
110#define CPU_SIZEOF_POINTER __SIZEOF_POINTER__
113#define CPU_ALIGNMENT 16
115#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
118#define CPU_STACK_ALIGNMENT 16
120#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
122#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
124#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE
126#define CPU_MAXIMUM_PROCESSORS 32
128#define AARCH64_CONTEXT_CONTROL_THREAD_ID_OFFSET 0x70
130#ifdef AARCH64_MULTILIB_VFP
131 #define AARCH64_CONTEXT_CONTROL_D8_OFFSET 0x78
134#define AARCH64_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 0x68
137 #if defined(AARCH64_MULTILIB_VFP)
138 #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0xb8
140 #define AARCH64_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x78
144#define AARCH64_EXCEPTION_FRAME_SIZE 0x350
146#define AARCH64_EXCEPTION_FRAME_REGISTER_SP_OFFSET 0xF8
147#define AARCH64_EXCEPTION_FRAME_REGISTER_LR_OFFSET 0xF0
148#define AARCH64_EXCEPTION_FRAME_REGISTER_DAIF_OFFSET 0x108
149#define AARCH64_EXCEPTION_FRAME_REGISTER_SYNDROME_OFFSET 0x118
150#define AARCH64_EXCEPTION_FRAME_REGISTER_VECTOR_OFFSET 0x128
151#define AARCH64_EXCEPTION_FRAME_REGISTER_FPSR_OFFSET 0x138
152#define AARCH64_EXCEPTION_FRAME_REGISTER_Q0_OFFSET 0x150
164#pragma GCC diagnostic push
165#pragma GCC diagnostic ignored "-Wpedantic"
166typedef unsigned __int128 uint128_t;
167#pragma GCC diagnostic pop
170 uint64_t register_x19;
171 uint64_t register_x20;
172 uint64_t register_x21;
173 uint64_t register_x22;
174 uint64_t register_x23;
175 uint64_t register_x24;
176 uint64_t register_x25;
177 uint64_t register_x26;
178 uint64_t register_x27;
179 uint64_t register_x28;
180 uint64_t register_fp;
181 uint64_t register_lr;
182 uint64_t register_sp;
185#ifdef AARCH64_MULTILIB_VFP
186 uint64_t register_d8;
187 uint64_t register_d9;
188 uint64_t register_d10;
189 uint64_t register_d11;
190 uint64_t register_d12;
191 uint64_t register_d13;
192 uint64_t register_d14;
193 uint64_t register_d15;
196 volatile bool is_executing;
200static inline void _AARCH64_Data_memory_barrier(
void )
202 __asm__ volatile (
"dmb SY" : : :
"memory" );
205static inline void _AARCH64_Data_synchronization_barrier(
void )
207 __asm__ volatile (
"dsb SY" : : :
"memory" );
210static inline void _AARCH64_Instruction_synchronization_barrier(
void )
212 __asm__ volatile (
"isb" : : :
"memory" );
219#if defined(AARCH64_DISABLE_INLINE_ISR_DISABLE_ENABLE)
220uint64_t AArch64_interrupt_disable(
void );
221void AArch64_interrupt_enable( uint64_t isr_cookie );
222void AArch64_interrupt_flash( uint64_t isr_cookie );
224static inline uint64_t AArch64_interrupt_disable(
void )
229 "mrs %[isr_cookie], DAIF\n"
230 "msr DAIFSet, #0x2\n"
231 : [isr_cookie]
"=&r" (isr_cookie)
237static inline void AArch64_interrupt_enable( uint64_t isr_cookie )
240 "msr DAIF, %[isr_cookie]\n"
241 : : [isr_cookie]
"r" (isr_cookie)
245static inline void AArch64_interrupt_flash( uint64_t isr_cookie )
247 AArch64_interrupt_enable(isr_cookie);
248 AArch64_interrupt_disable();
252#define _CPU_ISR_Disable( _isr_cookie ) \
254 _isr_cookie = AArch64_interrupt_disable(); \
257#define _CPU_ISR_Enable( _isr_cookie ) \
258 AArch64_interrupt_enable( _isr_cookie )
260#define _CPU_ISR_Flash( _isr_cookie ) \
261 AArch64_interrupt_flash( _isr_cookie )
263static inline bool _CPU_ISR_Is_enabled( uint64_t isr_cookie )
265 return ( isr_cookie & AARCH64_PSTATE_I ) == 0;
270 void *stack_area_begin,
271 size_t stack_area_size,
273 void (*entry_point)(
void ),
278#define _CPU_Context_Get_SP( _context ) \
279 (_context)->register_sp
282 static inline bool _CPU_Context_Get_is_executing(
289 static inline void _CPU_Context_Set_is_executing(
294 context->is_executing = is_executing;
299 #define _CPU_Start_multitasking( _heir ) _AArch64_Start_multitasking( _heir )
302#define _CPU_Context_Restart_self( _the_context ) \
303 _CPU_Context_restore( (_the_context) );
305#define _CPU_Context_Initialize_fp( _destination ) \
307 *(*(_destination)) = _CPU_Null_fp_context; \
315typedef void ( *CPU_ISR_handler )( void );
330 uint32_t _CPU_SMP_Initialize(
void );
332 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
334 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
336 void _CPU_SMP_Prepare_start_multitasking(
void );
338 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
343 "mrs %[mpidr], mpidr_el1\n"
344 : [mpidr]
"=&r" (mpidr)
347 return mpidr & 0xffU;
350 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
352 static inline void _AARCH64_Send_event(
void )
354 __asm__ volatile (
"sev" : : :
"memory" );
357 static inline void _AARCH64_Wait_for_event(
void )
359 __asm__ volatile (
"wfe" : : :
"memory" );
364static inline uint32_t CPU_swap_u32( uint32_t value )
366 uint32_t tmp = value;
367 __asm__ volatile (
"EOR %1, %0, %0, ROR #16\n"
368 "BIC %1, %1, #0xff0000\n"
369 "MOV %0, %0, ROR #8\n"
370 "EOR %0, %0, %1, LSR #8\n"
371 :
"=r" (value),
"=r" (tmp)
372 :
"0" (value),
"1" (tmp));
378 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
390 AARCH64_EXCEPTION_SP0_SYNCHRONOUS = 0,
391 AARCH64_EXCEPTION_SP0_IRQ = 1,
392 AARCH64_EXCEPTION_SP0_FIQ = 2,
393 AARCH64_EXCEPTION_SP0_SERROR = 3,
394 AARCH64_EXCEPTION_SPx_SYNCHRONOUS = 4,
395 AARCH64_EXCEPTION_SPx_IRQ = 5,
396 AARCH64_EXCEPTION_SPx_FIQ = 6,
397 AARCH64_EXCEPTION_SPx_SERROR = 7,
398 AARCH64_EXCEPTION_LEL64_SYNCHRONOUS = 8,
399 AARCH64_EXCEPTION_LEL64_IRQ = 9,
400 AARCH64_EXCEPTION_LEL64_FIQ = 10,
401 AARCH64_EXCEPTION_LEL64_SERROR = 11,
402 AARCH64_EXCEPTION_LEL32_SYNCHRONOUS = 12,
403 AARCH64_EXCEPTION_LEL32_IRQ = 13,
404 AARCH64_EXCEPTION_LEL32_FIQ = 14,
405 AARCH64_EXCEPTION_LEL32_SERROR = 15,
407 AARCH64_EXCEPTION_MAKE_ENUM_64_BIT = INT_MAX
408} AArch64_symbolic_exception_name;
410#define VECTOR_POINTER_OFFSET 0x78
411#define VECTOR_ENTRY_SIZE 0x80
412void _AArch64_Exception_interrupt_no_nest(
void );
413void _AArch64_Exception_interrupt_nest(
void );
414static inline void* AArch64_set_exception_handler(
415 AArch64_symbolic_exception_name exception,
416 void (*handler)(
void)
420 char *vbar = (
char*)AArch64_get_vector_base_address();
423 char *cvector_address = vbar + VECTOR_ENTRY_SIZE * exception
424 + VECTOR_POINTER_OFFSET;
427 void (**vector_address)(void) = (
void(**)(void))cvector_address;
428 void (*current_vector_pointer)(void);
429 current_vector_pointer = *vector_address;
432 *vector_address = handler;
440#pragma GCC diagnostic push
441#pragma GCC diagnostic ignored "-Wpedantic"
442 return (
void*)current_vector_pointer;
443#pragma GCC diagnostic pop
447 uint64_t register_x0;
448 uint64_t register_x1;
449 uint64_t register_x2;
450 uint64_t register_x3;
451 uint64_t register_x4;
452 uint64_t register_x5;
453 uint64_t register_x6;
454 uint64_t register_x7;
455 uint64_t register_x8;
456 uint64_t register_x9;
457 uint64_t register_x10;
458 uint64_t register_x11;
459 uint64_t register_x12;
460 uint64_t register_x13;
461 uint64_t register_x14;
462 uint64_t register_x15;
463 uint64_t register_x16;
464 uint64_t register_x17;
465 uint64_t register_x18;
466 uint64_t register_x19;
467 uint64_t register_x20;
468 uint64_t register_x21;
469 uint64_t register_x22;
470 uint64_t register_x23;
471 uint64_t register_x24;
472 uint64_t register_x25;
473 uint64_t register_x26;
474 uint64_t register_x27;
475 uint64_t register_x28;
476 uint64_t register_fp;
478#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
479 uint32_t _register_lr_top;
481 uintptr_t register_sp;
482#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
483 uint32_t _register_sp_top;
486#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
487 uint32_t _register_pc_top;
489 uint64_t register_daif;
490 uint64_t register_cpsr;
491 uint64_t register_syndrome;
492 uint64_t register_fault_address;
493 AArch64_symbolic_exception_name vector;
494 uint64_t reserved_for_stack_alignment;
495 uint64_t register_fpsr;
496 uint64_t register_fpcr;
497 uint128_t register_q0;
498 uint128_t register_q1;
499 uint128_t register_q2;
500 uint128_t register_q3;
501 uint128_t register_q4;
502 uint128_t register_q5;
503 uint128_t register_q6;
504 uint128_t register_q7;
505 uint128_t register_q8;
506 uint128_t register_q9;
507 uint128_t register_q10;
508 uint128_t register_q11;
509 uint128_t register_q12;
510 uint128_t register_q13;
511 uint128_t register_q14;
512 uint128_t register_q15;
513 uint128_t register_q16;
514 uint128_t register_q17;
515 uint128_t register_q18;
516 uint128_t register_q19;
517 uint128_t register_q20;
518 uint128_t register_q21;
519 uint128_t register_q22;
520 uint128_t register_q23;
521 uint128_t register_q24;
522 uint128_t register_q25;
523 uint128_t register_q26;
524 uint128_t register_q27;
525 uint128_t register_q28;
526 uint128_t register_q29;
527 uint128_t register_q30;
528 uint128_t register_q31;
538void _CPU_Exception_disable_thread_dispatch(
void );
545void _CPU_Exception_frame_make_resume_next_instruction(
549void _AArch64_Exception_frame_copy(
ARM AArch64 Assembler Support API.
This header file provides basic definitions used by the API and the implementation.
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:149
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:39
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Definition: vectorexceptions.c:64
uint32_t _CPU_Counter_frequency(void)
Gets the current CPU counter frequency in Hz.
Definition: system-clocks.c:125
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:110
CPU_Counter_ticks _CPU_Counter_read(void)
Gets the current CPU counter value.
Definition: system-clocks.c:130
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: cpu.c:167
RTEMS_NO_RETURN void _CPU_Context_restore(Context_Control *new_context)
Definition: cpu_asm.c:130
#define CPU_swap_u16(value)
Definition: cpu.h:597
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:165
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1294
rtems_termios_device_context * context
Definition: console-config.c:62
The set of registers that specifies the complete processor state.
Definition: cpu.h:446
Thread register context.
Definition: cpu.h:169
uint64_t isr_dispatch_disable
This member is used for the external interrupt controller (EIC) support.
Definition: cpu.h:183