RTEMS 6.1-rc1
cpuimpl.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
13 * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _RTEMS_SCORE_CPUIMPL_H
38#define _RTEMS_SCORE_CPUIMPL_H
39
40#include <rtems/score/cpu.h>
41
52#define CPU_PER_CPU_CONTROL_SIZE 0
53
54#define CPU_INTERRUPT_FRAME_SIZE 0x2E0
55
56#define CPU_THREAD_LOCAL_STORAGE_VARIANT 11
57
58#ifndef ASM
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
65
66typedef struct {
67 uint64_t x0;
68 uint64_t register_lr_original;
69 uint64_t register_lr;
70 uint64_t x1;
71 uint64_t x2;
72 uint64_t x3;
73 uint64_t x4;
74 uint64_t x5;
75 uint64_t x6;
76 uint64_t x7;
77 uint64_t x8;
78 uint64_t x9;
79 uint64_t x10;
80 uint64_t x11;
81 uint64_t x12;
82 uint64_t x13;
83 uint64_t x14;
84 uint64_t x15;
85 uint64_t x16;
86 uint64_t x17;
87 uint64_t x18;
88 uint64_t x19;
89 uint64_t x20;
90 uint64_t x21;
91#ifdef AARCH64_MULTILIB_VFP
92 uint128_t q0;
93 uint128_t q1;
94 uint128_t q2;
95 uint128_t q3;
96 uint128_t q4;
97 uint128_t q5;
98 uint128_t q6;
99 uint128_t q7;
100 uint128_t q8;
101 uint128_t q9;
102 uint128_t q10;
103 uint128_t q11;
104 uint128_t q12;
105 uint128_t q13;
106 uint128_t q14;
107 uint128_t q15;
108 uint128_t q16;
109 uint128_t q17;
110 uint128_t q18;
111 uint128_t q19;
112 uint128_t q20;
113 uint128_t q21;
114 uint128_t q22;
115 uint128_t q23;
116 uint128_t q24;
117 uint128_t q25;
118 uint128_t q26;
119 uint128_t q27;
120 uint128_t q28;
121 uint128_t q29;
122 uint128_t q30;
123 uint128_t q31;
124#endif /* AARCH64_MULTILIB_VFP */
125 uint64_t register_elr;
126 uint64_t register_spsr;
127 uint64_t register_fpsr;
128 uint64_t register_fpcr;
130
131#ifdef RTEMS_SMP
132
133static inline
134struct Per_CPU_Control *_AARCH64_Get_current_per_CPU_control( void )
135{
136 struct Per_CPU_Control *cpu_self;
137 uint64_t value;
138
139 __asm__ volatile (
140 "mrs %0, TPIDR_EL1" : "=&r" ( value ) : : "memory"
141 );
142
143 /* Use EL1 Thread ID Register (TPIDR_EL1) */
144 cpu_self = (struct Per_CPU_Control *)(uintptr_t)value;
145
146 return cpu_self;
147}
148
149#define _CPU_Get_current_per_CPU_control() \
150 _AARCH64_Get_current_per_CPU_control()
151
152#endif /* RTEMS_SMP */
153
154void _CPU_Context_volatile_clobber( uintptr_t pattern );
155
156void _CPU_Context_validate( uintptr_t pattern );
157
158static inline void _CPU_Instruction_illegal( void )
159{
160 __asm__ volatile ( ".inst 0x0" );
161}
162
163static inline void _CPU_Instruction_no_operation( void )
164{
165 __asm__ volatile ( "nop" );
166}
167
168static inline void _CPU_Use_thread_local_storage(
170)
171{
172 __asm__ volatile (
173 "msr TPIDR_EL0, %0" : : "r" ( context->thread_id ) : "memory"
174 );
175}
176
177static inline void *_CPU_Get_TLS_thread_pointer(
179)
180{
181 return (void *)(uintptr_t) context->thread_id;
182}
183
184#ifdef __cplusplus
185}
186#endif
187
188#endif /* ASM */
189
192#endif /* _RTEMS_SCORE_CPUIMPL_H */
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
RTEMS_NO_RETURN void _CPU_Fatal_halt(uint32_t source, CPU_Uint32ptr error)
Definition: bsp_fatal_halt.c:31
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
rtems_termios_device_context * context
Definition: console-config.c:62
Interrupt stack frame (ISF).
Definition: cpuimpl.h:66
Thread register context.
Definition: cpu.h:169
Per CPU Core Structure.
Definition: percpu.h:384