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RTEMS 6.1-rc1
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26#ifndef XREG_CORTEXA53_H
27#define XREG_CORTEXA53_H
72#define XREG_CPSR_MODE_BITS 0x1FU
73#define XREG_CPSR_EL3h_MODE 0xDU
74#define XREG_CPSR_EL3t_MODE 0xCU
75#define XREG_CPSR_EL2h_MODE 0x9U
76#define XREG_CPSR_EL2t_MODE 0x8U
77#define XREG_CPSR_EL1h_MODE 0x5U
78#define XREG_CPSR_EL1t_MODE 0x4U
79#define XREG_CPSR_EL0t_MODE 0x0U
81#define XREG_CPSR_IRQ_ENABLE 0x80U
82#define XREG_CPSR_FIQ_ENABLE 0x40U
84#define XREG_CPSR_N_BIT 0x80000000U
85#define XREG_CPSR_Z_BIT 0x40000000U
86#define XREG_CPSR_C_BIT 0x20000000U
87#define XREG_CPSR_V_BIT 0x10000000U
90#define XREG_FPSID_IMPLEMENTER_BIT (24U)
91#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT)
92#define XREG_FPSID_SOFTWARE (0X00000001U<<23U)
93#define XREG_FPSID_ARCH_BIT (16U)
94#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT)
95#define XREG_FPSID_PART_BIT (8U)
96#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT)
97#define XREG_FPSID_VARIANT_BIT (4U)
98#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT)
99#define XREG_FPSID_REV_BIT (0U)
100#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT)
103#define XREG_FPSCR_N_BIT (0X00000001U << 31U)
104#define XREG_FPSCR_Z_BIT (0X00000001U << 30U)
105#define XREG_FPSCR_C_BIT (0X00000001U << 29U)
106#define XREG_FPSCR_V_BIT (0X00000001U << 28U)
107#define XREG_FPSCR_QC (0X00000001U << 27U)
108#define XREG_FPSCR_AHP (0X00000001U << 26U)
109#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U)
110#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U)
111#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U)
112#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U)
113#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U)
114#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U)
115#define XREG_FPSCR_RMODE_BIT (22U)
116#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT)
117#define XREG_FPSCR_STRIDE_BIT (20U)
118#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT)
119#define XREG_FPSCR_LENGTH_BIT (16U)
120#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT)
121#define XREG_FPSCR_IDC (0X00000001U << 7U)
122#define XREG_FPSCR_IXC (0X00000001U << 4U)
123#define XREG_FPSCR_UFC (0X00000001U << 3U)
124#define XREG_FPSCR_OFC (0X00000001U << 2U)
125#define XREG_FPSCR_DZC (0X00000001U << 1U)
126#define XREG_FPSCR_IOC (0X00000001U << 0U)
129#define XREG_MVFR0_RMODE_BIT (28U)
130#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT)
131#define XREG_MVFR0_SHORT_VEC_BIT (24U)
132#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
133#define XREG_MVFR0_SQRT_BIT (20U)
134#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT)
135#define XREG_MVFR0_DIVIDE_BIT (16U)
136#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
137#define XREG_MVFR0_EXEC_TRAP_BIT (0X00000012U)
138#define XREG_MVFR0_EXEC_TRAP_MASK (0X0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
139#define XREG_MVFR0_DP_BIT (8U)
140#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT)
141#define XREG_MVFR0_SP_BIT (4U)
142#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT)
143#define XREG_MVFR0_A_SIMD_BIT (0U)
144#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT)
147#define XREG_FPEXC_EX (0X00000001U << 31U)
148#define XREG_FPEXC_EN (0X00000001U << 30U)
149#define XREG_FPEXC_DEX (0X00000001U << 29U)
152#define XREG_CONTROL_DCACHE_BIT (0X00000001U<<2U)
153#define XREG_CONTROL_ICACHE_BIT (0X00000001U<<12U)