RTEMS 6.1-rc1
cpuimpl.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
9/*
10 * Copyright (C) 2013, 2016 embedded brains GmbH & Co. KG
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef _RTEMS_SCORE_CPUIMPL_H
35#define _RTEMS_SCORE_CPUIMPL_H
36
37#include <rtems/score/cpu.h>
38
55#define CPU_PER_CPU_CONTROL_SIZE 0
56
73#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10
74
75#ifndef ASM
76
77#ifdef __cplusplus
78extern "C" {
79#endif
80
91typedef struct {
92 /* CPU specific per-CPU state */
94
102register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" );
103
111#define _CPU_Get_current_per_CPU_control() ( _CPU_Per_CPU_current )
112
121#define _CPU_Get_thread_executing() ( _CPU_Per_CPU_current->executing )
122
132RTEMS_NO_RETURN void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error );
133
134/* end of Fatal Error manager macros */
135
148void _CPU_Context_volatile_clobber( uintptr_t pattern );
149
165void _CPU_Context_validate( uintptr_t pattern );
166
172static inline void _CPU_Instruction_illegal( void )
173{
174 __asm__ volatile ( ".word 0" );
175}
176
182static inline void _CPU_Instruction_no_operation( void )
183{
184 __asm__ volatile ( "nop" );
185}
186
197static inline void _CPU_Use_thread_local_storage(
199)
200{
201 (void) context;
202}
203
212static inline void *_CPU_Get_TLS_thread_pointer(
214)
215{
216 (void) context;
217 return NULL;
218}
219
220#ifdef __cplusplus
221}
222#endif
223
224#endif /* ASM */
225
228#endif /* _RTEMS_SCORE_CPUIMPL_H */
#define RTEMS_NO_RETURN
Tells the compiler in a function declaration that this function does not return.
Definition: basedefs.h:386
RTEMS_NO_RETURN void _CPU_Fatal_halt(uint32_t source, CPU_Uint32ptr error)
Definition: bsp_fatal_halt.c:31
uintptr_t CPU_Uint32ptr
Definition: cpu.h:557
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
#define NULL
Requests a GPIO pin group configuration.
Definition: xil_types.h:54
rtems_termios_device_context * context
Definition: console-config.c:62
The CPU specific per-CPU control.
Definition: cpuimpl.h:91
Thread register context.
Definition: cpu.h:169
Per CPU Core Structure.
Definition: percpu.h:384