43#define L1_DATA_PREFETCH_CONTROL_MASK 0xE000
44#define L1_DATA_PREFETCH_CONTROL_SHIFT 13
51#define Xil_DCacheFlushRange Xil_DCacheInvalidateRange
void Xil_ICacheInvalidate(void)
Invalidate the entire instruction cache.
Definition: xil_cache.c:627
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len)
Invalidate the instruction cache for the given address range. If the instructions specified by the ad...
Definition: xil_cache.c:681
void Xil_DCacheEnable(void)
Enable the Data cache.
Definition: xil_cache.c:90
void Xil_ICacheInvalidateLine(INTPTR adr)
Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by ...
Definition: xil_cache.c:654
void Xil_ICacheDisable(void)
Disable the instruction cache.
Definition: xil_cache.c:594
void Xil_DCacheDisable(void)
Disable the Data cache.
Definition: xil_cache.c:127
void Xil_DCacheInvalidate(void)
Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.
Definition: xil_cache.c:257
void Xil_ConfigureL1Prefetch(u8 num)
Configure the maximum number of outstanding data prefetches allowed in L1 cache.
Definition: xil_cache.c:723
void Xil_ICacheEnable(void)
Enable the instruction cache.
Definition: xil_cache.c:558
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
Invalidate the Data cache for the given address range. The cachelines present in the adderss range ar...
Definition: xil_cache.c:404
void Xil_DCacheFlush(void)
Flush the Data cache.
Definition: xil_cache.c:429
void Xil_DCacheFlushLine(INTPTR adr)
Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache,...
Definition: xil_cache.c:533
void Xil_DCacheInvalidateLine(INTPTR adr)
Invalidate a Data cache line. The cacheline is cleaned and invalidated.
Definition: xil_cache.c:364