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#define | CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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#define | CPU_ISR_PASSES_FRAME_POINTER FALSE |
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#define | CPU_HARDWARE_FP FALSE |
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#define | CPU_SOFTWARE_FP FALSE |
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#define | CPU_ALL_TASKS_ARE_FP FALSE |
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#define | CPU_IDLE_TASK_IS_FP FALSE |
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#define | CPU_USE_DEFERRED_FP_SWITCH FALSE |
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#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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#define | CPU_STACK_GROWS_UP FALSE |
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#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64) |
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#define | CPU_CACHE_LINE_BYTES 64 |
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#define | CPU_MODES_INTERRUPT_MASK 0x00000001 |
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#define | CPU_MAXIMUM_PROCESSORS 32 |
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#define | CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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#define | CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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#define | _CPU_Context_Get_SP(_context) (_context)->rsp |
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#define | CPU_INTERRUPT_FRAME_SIZE 72 |
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#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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#define | CPU_STACK_MINIMUM_SIZE (1024*4) |
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#define | CPU_SIZEOF_POINTER 8 |
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#define | CPU_ALIGNMENT 16 |
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#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_STACK_ALIGNMENT 16 |
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#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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#define | _CPU_ISR_Enable(_level) |
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#define | _CPU_ISR_Disable(_level) |
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#define | _CPU_ISR_Flash(_level) |
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#define | _CPU_Context_Destroy(_the_thread, _the_context) |
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#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
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#define | _CPU_Context_Initialize_fp(_destination) |
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#define | CPU_USE_LIBC_INIT_FINI_ARRAY FALSE |
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#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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#define | _CPU_Bitfield_Find_first_bit(_value, _output) |
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#define | _CPU_Priority_Mask(_bit_number) ( 1 << (_bit_number) ) |
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#define | _CPU_Priority_bits_index(_priority) (_priority) |
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#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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x86_64 Dependent Source
This include file contains information pertaining to the x86_64 processor.