RTEMS 6.1-rc1
xil_cache.h
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1/******************************************************************************
2* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
37#ifndef XIL_CACHE_H
38#define XIL_CACHE_H
39
40#include "xil_types.h"
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46#ifdef __GNUC__
47
48#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
49 XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
50
51#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
52 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
53
54#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
55 XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
56
57#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
58 XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
59
60#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
61 XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
62
63#elif defined (__ICCARM__)
64
65#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
66 XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
67
68#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
69 XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
70
71#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
72 XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
73
74#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
75 XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
76
77#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
78 XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
79
80#endif
81
86void Xil_DCacheEnable(void);
87void Xil_DCacheDisable(void);
88void Xil_DCacheInvalidate(void);
89void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
90void Xil_DCacheFlush(void);
91void Xil_DCacheFlushRange(INTPTR adr, u32 len);
92
93void Xil_ICacheEnable(void);
94void Xil_ICacheDisable(void);
95void Xil_ICacheInvalidate(void);
96void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
97
98#ifdef __cplusplus
99}
100#endif
101
102#endif
void Xil_ICacheInvalidate(void)
Invalidate the entire instruction cache.
Definition: xil_cache.c:627
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len)
Invalidate the instruction cache for the given address range. If the instructions specified by the ad...
Definition: xil_cache.c:681
void Xil_DCacheEnable(void)
Enable the Data cache.
Definition: xil_cache.c:90
void Xil_ICacheDisable(void)
Disable the instruction cache.
Definition: xil_cache.c:594
void Xil_DCacheDisable(void)
Disable the Data cache.
Definition: xil_cache.c:127
void Xil_DCacheInvalidate(void)
Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.
Definition: xil_cache.c:257
void Xil_ICacheEnable(void)
Enable the instruction cache.
Definition: xil_cache.c:558
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
Invalidate the Data cache for the given address range. The cachelines present in the adderss range ar...
Definition: xil_cache.c:404
void Xil_DCacheFlush(void)
Flush the Data cache.
Definition: xil_cache.c:429
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
Flush the Data cache for the given address range. If the bytes specified by the address (adr) are cac...
Definition: xil_cache.c:348