RTEMS 6.1-rc1
cache.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2016 Pavel Pisa
13 * Copyright (C) 2014, 2021 embedded brains GmbH & Co. KG
14 * Copyright (C) 2000, 2008 On-Line Applications Research Corporation (OAR)
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
18 * are met:
19 * 1. Redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
29 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * This file is part of the RTEMS quality process and was automatically
40 * generated. If you find something that needs to be fixed or
41 * worded better please post a report or patch to an RTEMS mailing list
42 * or raise a bug report:
43 *
44 * https://www.rtems.org/bugs.html
45 *
46 * For information on updating and regenerating please refer to the How-To
47 * section in the Software Requirements Engineering chapter of the
48 * RTEMS Software Engineering manual. The manual is provided as a part of
49 * a release. For development sources please refer to the online
50 * documentation at:
51 *
52 * https://docs.rtems.org
53 */
54
55/* Generated from spec:/rtems/cache/if/header */
56
57#ifndef _RTEMS_RTEMS_CACHE_H
58#define _RTEMS_RTEMS_CACHE_H
59
60#include <stddef.h>
61#include <stdint.h>
62
63#ifdef __cplusplus
64extern "C" {
65#endif
66
67/* Generated from spec:/rtems/cache/if/group */
68
83/* Generated from spec:/rtems/cache/if/coherent-add-area */
84
105void rtems_cache_coherent_add_area( void *begin, uintptr_t size );
106
107/* Generated from spec:/rtems/cache/if/coherent-allocate */
108
158 size_t size,
159 uintptr_t alignment,
160 uintptr_t boundary
161);
162
163/* Generated from spec:/rtems/cache/if/coherent-free */
164
183void rtems_cache_coherent_free( void *ptr );
184
185/* Generated from spec:/rtems/cache/if/freeze-data */
186
199void rtems_cache_freeze_data( void );
200
201/* Generated from spec:/rtems/cache/if/freeze-instruction */
202
216
217/* Generated from spec:/rtems/cache/if/unfreeze-data */
218
231void rtems_cache_unfreeze_data( void );
232
233/* Generated from spec:/rtems/cache/if/unfreeze-instruction */
234
248
249/* Generated from spec:/rtems/cache/if/flush-multiple-data-lines */
250
272void rtems_cache_flush_multiple_data_lines( const void *begin, size_t size );
273
274/* Generated from spec:/rtems/cache/if/invalidate-multiple-data-lines */
275
306 const void *begin,
307 size_t size
308);
309
310/* Generated from spec:/rtems/cache/if/invalidate-multiple-instruction-lines */
311
339 const void *begin,
340 size_t size
341);
342
343/* Generated from spec:/rtems/cache/if/instruction-sync-after-code-change */
344
371 const void *begin,
372 size_t size
373);
374
375/* Generated from spec:/rtems/cache/if/get-maximal-line-size */
376
398
399/* Generated from spec:/rtems/cache/if/get-data-line-size */
400
420size_t rtems_cache_get_data_line_size( void );
421
422/* Generated from spec:/rtems/cache/if/get-instruction-line-size */
423
444
445/* Generated from spec:/rtems/cache/if/get-data-size */
446
468size_t rtems_cache_get_data_cache_size( uint32_t level );
469
470/* Generated from spec:/rtems/cache/if/get-instruction-size */
471
495size_t rtems_cache_get_instruction_cache_size( uint32_t level );
496
497/* Generated from spec:/rtems/cache/if/flush-entire-data */
498
514
515/* Generated from spec:/rtems/cache/if/invalidate-entire-data */
516
532
533/* Generated from spec:/rtems/cache/if/invalidate-entire-instruction */
534
550
551/* Generated from spec:/rtems/cache/if/enable-data */
552
567void rtems_cache_enable_data( void );
568
569/* Generated from spec:/rtems/cache/if/disable-data */
570
585void rtems_cache_disable_data( void );
586
587/* Generated from spec:/rtems/cache/if/enable-instruction */
588
604
605/* Generated from spec:/rtems/cache/if/disable-instruction */
606
622
623/* Generated from spec:/rtems/cache/if/aligned-malloc */
624
652void *rtems_cache_aligned_malloc( size_t size );
653
654#ifdef __cplusplus
655}
656#endif
657
658#endif /* _RTEMS_RTEMS_CACHE_H */
void rtems_cache_unfreeze_instruction(void)
Unfreezes the instruction cache.
Definition: cacheimpl.h:450
void * rtems_cache_coherent_allocate(size_t size, uintptr_t alignment, uintptr_t boundary)
Allocates a memory area from cache coherent memory.
Definition: cachecoherentalloc.c:48
void rtems_cache_unfreeze_data(void)
Unfreezes the data cache.
Definition: cacheimpl.h:274
void rtems_cache_coherent_add_area(void *begin, uintptr_t size)
Adds a cache coherent memory area to the cache coherent allocator.
Definition: cachecoherentalloc.c:121
void rtems_cache_freeze_instruction(void)
Freezes the instruction caches.
Definition: cacheimpl.h:443
void rtems_cache_coherent_free(void *ptr)
Frees memory allocated by rtems_cache_coherent_allocate().
Definition: cachecoherentalloc.c:76
void rtems_cache_freeze_data(void)
Freezes the data caches.
Definition: cacheimpl.h:267
void rtems_cache_instruction_sync_after_code_change(const void *begin, size_t size)
Ensures necessary synchronization required after code changes.
Definition: cacheimpl.h:501
size_t rtems_cache_get_maximal_line_size(void)
Gets the maximal cache line size in bytes of all caches (data, instruction, or unified).
Definition: cacheimpl.h:474
void rtems_cache_invalidate_entire_instruction(void)
Invalidates the entire instruction cache.
Definition: cacheimpl.h:404
void rtems_cache_invalidate_entire_data(void)
Invalidates the entire data cache.
Definition: cacheimpl.h:228
void rtems_cache_invalidate_multiple_instruction_lines(const void *begin, size_t size)
Invalidates the instruction cache lines covering the memory area.
Definition: cacheimpl.h:383
size_t rtems_cache_get_data_cache_size(uint32_t level)
Gets the data cache size in bytes for the cache level.
Definition: cacheimpl.h:253
void rtems_cache_enable_data(void)
Enables the data cache.
Definition: cacheimpl.h:282
void rtems_cache_disable_instruction(void)
Disables the instruction cache.
Definition: cacheimpl.h:466
void rtems_cache_disable_data(void)
Disables the data cache.
Definition: cacheimpl.h:291
size_t rtems_cache_get_instruction_cache_size(uint32_t level)
Gets the instruction cache size in bytes for the cache level.
Definition: cacheimpl.h:429
void * rtems_cache_aligned_malloc(size_t size)
Allocates memory from the C Program Heap which begins at a cache line boundary.
Definition: cachealignedalloc.c:37
void rtems_cache_invalidate_multiple_data_lines(const void *begin, size_t size)
Invalidates the data cache lines covering the memory area.
Definition: cacheimpl.h:180
void rtems_cache_flush_entire_data(void)
Flushes the entire data cache.
Definition: cacheimpl.h:213
void rtems_cache_flush_multiple_data_lines(const void *begin, size_t size)
Flushes the data cache lines covering the memory area.
Definition: cacheimpl.h:146
size_t rtems_cache_get_instruction_line_size(void)
Gets the instruction cache line size in bytes.
Definition: cacheimpl.h:419
size_t rtems_cache_get_data_line_size(void)
Gets the data cache line size in bytes.
Definition: cacheimpl.h:243
void rtems_cache_enable_instruction(void)
Enables the instruction cache.
Definition: cacheimpl.h:458
unsigned size
Definition: tte.h:1