RTEMS 6.1-rc1
arm-a9mpcore-start.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
37#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
38
39#include <rtems/score/smpimpl.h>
40
41#include <libcpu/arm-cp15.h>
42
43#include <bsp.h>
44#include <bsp/start.h>
46#include <bsp/arm-cp15-start.h>
47#include <bsp/arm-errata.h>
48#include <dev/irq/arm-gic-irq.h>
49
50#ifdef __cplusplus
51extern "C" {
52#endif /* __cplusplus */
53
60BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate(
61 volatile a9mpcore_scu *scu,
62 uint32_t cpu_id,
63 uint32_t ways
64)
65{
66 scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
67}
68
69BSP_START_TEXT_SECTION static inline void
70arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
71{
72 if (arm_errata_is_applicable_processor_errata_764369()) {
73 scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
74 }
75}
76
77BSP_START_TEXT_SECTION static inline void
78arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
79{
80 scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
81 arm_a9mpcore_start_errata_764369_handler(scu);
82}
83
84#ifdef RTEMS_SMP
85BSP_START_TEXT_SECTION static inline void
86arm_a9mpcore_start_on_secondary_processor(void)
87{
88 uint32_t ctrl;
89
90 arm_gic_irq_initialize_secondary_cpu();
91
92 /* Change the VBAR from the start to the normal vector table */
93 arm_cp15_set_vector_base_address(bsp_vector_table_begin);
94
95 ctrl = arm_cp15_start_setup_mmu_and_cache(
96 0,
97 ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
98 );
99
100 arm_cp15_set_domain_access_control(
101 ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
102 );
103
104 /* FIXME: Sharing the translation table between processors is brittle */
105 arm_cp15_set_translation_table_base(
106 (uint32_t *) bsp_translation_table_base
107 );
108
109 ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
110 arm_cp15_set_control(ctrl);
111
112 _SMP_Start_multitasking_on_secondary_processor(_Per_CPU_Get());
113}
114
115BSP_START_TEXT_SECTION static inline void
116arm_a9mpcore_start_enable_smp_in_auxiliary_control(void)
117{
118 /*
119 * Enable cache coherency support and cache/MMU maintenance broadcasts for
120 * this processor.
121 */
122 uint32_t actlr = arm_cp15_get_auxiliary_control();
123 actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
124 arm_cp15_set_auxiliary_control(actlr);
125}
126
127BSP_START_TEXT_SECTION static inline void
128arm_a9mpcore_start_errata_794072_handler(void)
129{
130 uint32_t diag;
131
132 /*
133 * Workaround for Errata 794072: A short loop including a DMB instruction
134 * might cause a denial of service on another which executes a CP15 broadcast
135 * operation.
136 */
137 diag = arm_cp15_get_diagnostic_control();
138 diag |= 1U << 4;
139 arm_cp15_set_diagnostic_control(diag);
140}
141
142BSP_START_TEXT_SECTION static inline void
143arm_a9mpcore_start_errata_845369_handler(void)
144{
145 uint32_t diag;
146
147 /*
148 * Workaround for Errata 845369: Under Very Rare Timing Circumstances
149 * Transition into Streaming Mode Might Create Data Corruption.
150 */
151 diag = arm_cp15_get_diagnostic_control();
152 diag |= 1U << 22;
153 arm_cp15_set_diagnostic_control(diag);
154}
155#endif
156
157BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
158{
159 volatile a9mpcore_scu *scu =
160 (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
161 uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
162
163 if (cpu_id == 0) {
164 arm_a9mpcore_start_scu_enable(scu);
165 }
166
167#ifdef RTEMS_SMP
168 arm_a9mpcore_start_errata_794072_handler();
169 arm_a9mpcore_start_errata_845369_handler();
170 arm_a9mpcore_start_enable_smp_in_auxiliary_control();
171#endif
172
173 arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
174
175#ifdef RTEMS_SMP
176 if (cpu_id != 0) {
177 arm_a9mpcore_start_on_secondary_processor();
178 }
179#endif
180}
181
182BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void)
183{
184 volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE;
185
186 gt->ctrl = 0;
187 gt->cntrlower = 0;
188 gt->cntrupper = 0;
189 gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
190}
191
192BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void)
193{
194 arm_a9mpcore_start_global_timer();
195}
196
199#ifdef __cplusplus
200}
201#endif /* __cplusplus */
202
203#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */
This header file provides the interfaces of the Cortex-A9 MPCore Support.
Arm CP15 start.
ARM co-processor 15 (CP15) API.
Create #defines which state which erratas shall get applied.
ARM GIC IRQ.
This header file provides interfaces of the SMP Support which are only used by the implementation.
Definition: arm-a9mpcore-regs.h:98
Definition: arm-a9mpcore-regs.h:51