RTEMS 6.1-rc1
xreg_cortexa9.h
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1/******************************************************************************
2* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
26#ifndef XREG_CORTEXA9_H
27#define XREG_CORTEXA9_H
28
29#ifdef __cplusplus
30extern "C" {
31#endif /* __cplusplus */
32
37/* GPRs */
38#define XREG_GPR0 r0
39#define XREG_GPR1 r1
40#define XREG_GPR2 r2
41#define XREG_GPR3 r3
42#define XREG_GPR4 r4
43#define XREG_GPR5 r5
44#define XREG_GPR6 r6
45#define XREG_GPR7 r7
46#define XREG_GPR8 r8
47#define XREG_GPR9 r9
48#define XREG_GPR10 r10
49#define XREG_GPR11 r11
50#define XREG_GPR12 r12
51#define XREG_GPR13 r13
52#define XREG_GPR14 r14
53#define XREG_GPR15 r15
54#define XREG_CPSR cpsr
55
56/* Coprocessor number defines */
57#define XREG_CP0 0
58#define XREG_CP1 1
59#define XREG_CP2 2
60#define XREG_CP3 3
61#define XREG_CP4 4
62#define XREG_CP5 5
63#define XREG_CP6 6
64#define XREG_CP7 7
65#define XREG_CP8 8
66#define XREG_CP9 9
67#define XREG_CP10 10
68#define XREG_CP11 11
69#define XREG_CP12 12
70#define XREG_CP13 13
71#define XREG_CP14 14
72#define XREG_CP15 15
73
74/* Coprocessor control register defines */
75#define XREG_CR0 cr0
76#define XREG_CR1 cr1
77#define XREG_CR2 cr2
78#define XREG_CR3 cr3
79#define XREG_CR4 cr4
80#define XREG_CR5 cr5
81#define XREG_CR6 cr6
82#define XREG_CR7 cr7
83#define XREG_CR8 cr8
84#define XREG_CR9 cr9
85#define XREG_CR10 cr10
86#define XREG_CR11 cr11
87#define XREG_CR12 cr12
88#define XREG_CR13 cr13
89#define XREG_CR14 cr14
90#define XREG_CR15 cr15
91
92/* Current Processor Status Register (CPSR) Bits */
93#define XREG_CPSR_THUMB_MODE 0x20
94#define XREG_CPSR_MODE_BITS 0x1F
95#define XREG_CPSR_SYSTEM_MODE 0x1F
96#define XREG_CPSR_UNDEFINED_MODE 0x1B
97#define XREG_CPSR_DATA_ABORT_MODE 0x17
98#define XREG_CPSR_SVC_MODE 0x13
99#define XREG_CPSR_IRQ_MODE 0x12
100#define XREG_CPSR_FIQ_MODE 0x11
101#define XREG_CPSR_USER_MODE 0x10
102
103#define XREG_CPSR_IRQ_ENABLE 0x80
104#define XREG_CPSR_FIQ_ENABLE 0x40
105
106#define XREG_CPSR_N_BIT 0x80000000
107#define XREG_CPSR_Z_BIT 0x40000000
108#define XREG_CPSR_C_BIT 0x20000000
109#define XREG_CPSR_V_BIT 0x10000000
110
111
112/* CP15 defines */
113#if defined (__GNUC__) || defined (__ICCARM__)
114/* C0 Register defines */
115#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
116#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
117#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
118#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
119#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
120
121#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
122#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
123#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
124#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
125#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
126#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
127#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
128
129#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
130#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
131#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
132#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
133#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
134
135#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
136#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
137#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
138
139#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
140
141/* C1 Register Defines */
142#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
143#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
144#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
145
146#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
147#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
148#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
149#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
150
151#else /* RVCT */
152/* C0 Register defines */
153#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
154#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
155#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
156#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
157#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
158
159#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
160#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
161#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
162#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
163#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
164#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
165#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
166
167#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
168#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
169#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
170#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
171#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
172
173#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
174#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
175#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
176
177#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
178
179/* C1 Register Defines */
180#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
181#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
182#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
183
184#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
185#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
186#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
187#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
188#endif
189
190/* XREG_CP15_CONTROL bit defines */
191#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
192#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
193#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
194#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
195#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
196#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
197#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
198#define XREG_CP15_CONTROL_V_BIT 0x00002000U
199#define XREG_CP15_CONTROL_I_BIT 0x00001000U
200#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
201#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
202#define XREG_CP15_CONTROL_B_BIT 0x00000080U
203#define XREG_CP15_CONTROL_C_BIT 0x00000004U
204#define XREG_CP15_CONTROL_A_BIT 0x00000002U
205#define XREG_CP15_CONTROL_M_BIT 0x00000001U
206
207#if defined (__GNUC__) || defined (__ICCARM__)
208/* C2 Register Defines */
209#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
210#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
211#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
212
213/* C3 Register Defines */
214#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
215
216/* C4 Register Defines */
217/* Not Used */
218
219/* C5 Register Defines */
220#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
221#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
222
223#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
224#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
225
226/* C6 Register Defines */
227#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
228#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
229
230/* C7 Register Defines */
231#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
232
233#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
234#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
235
236#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
237
238#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
239#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
240
241/* The CP15 register access below has been deprecated in favor of the new
242 * isb instruction in Cortex A9.
243 */
244#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
245#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
246
247#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
248#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
249
250#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
251#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
252#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
253#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
254
255#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
256#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
257#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
258#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
259
260#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
261#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
262
263/* The next two CP15 register accesses below have been deprecated in favor
264 * of the new dsb and dmb instructions in Cortex A9.
265 */
266#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
267#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
268
269#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
270
271#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
272
273#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
274#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
275
276/* C8 Register Defines */
277#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
278#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
279#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
280#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
281
282#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
283#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
284#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
285
286#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
287#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
288#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
289
290#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
291#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
292#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
293#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
294
295/* C9 Register Defines */
296#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
297#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
298#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
299#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
300#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
301#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
302
303#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
304#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
305#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
306
307#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
308#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
309#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
310
311/* C10 Register Defines */
312#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
313
314#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
315#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
316
317/* C11 Register Defines */
318/* Not used */
319
320/* C12 Register Defines */
321#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
322#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
323
324#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
325#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
326
327/* C13 Register Defines */
328#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
329#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
330#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
331#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
332
333/* C14 Register Defines */
334/* not used */
335
336/* C15 Register Defines */
337#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
338#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
339
340#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
341#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
342
343#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
344
345#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
346
347#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
348
349#else
350/* C2 Register Defines */
351#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
352#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
353#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
354
355/* C3 Register Defines */
356#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
357
358/* C4 Register Defines */
359/* Not Used */
360
361/* C5 Register Defines */
362#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
363#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
364
365#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
366#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
367
368/* C6 Register Defines */
369#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
370#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
371
372/* C7 Register Defines */
373#define XREG_CP15_NOP "cp15:0:c7:c0:4"
374
375#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
376#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
377
378#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
379
380#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
381#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
382
383/* The CP15 register access below has been deprecated in favor of the new
384 * isb instruction in Cortex A9.
385 */
386#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
387#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
388
389#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
390#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
391
392#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
393#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
394#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
395#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
396
397#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
398#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
399#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
400#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
401
402#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
403#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
404
405/* The next two CP15 register accesses below have been deprecated in favor
406 * of the new dsb and dmb instructions in Cortex A9.
407 */
408#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
409#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
410
411#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
412
413#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
414
415#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
416#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
417
418/* C8 Register Defines */
419#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
420#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
421#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
422#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
423
424#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
425#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
426#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
427
428#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
429#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
430#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
431
432#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
433#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
434#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
435#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
436
437/* C9 Register Defines */
438#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
439#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
440#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
441#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
442#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
443#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
444
445#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
446#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
447#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
448
449#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
450#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
451#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
452
453/* C10 Register Defines */
454#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
455
456#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
457#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
458
459/* C11 Register Defines */
460/* Not used */
461
462/* C12 Register Defines */
463#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
464#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
465
466#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
467#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
468
469/* C13 Register Defines */
470#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
471#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
472#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
473#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
474
475/* C14 Register Defines */
476/* not used */
477
478/* C15 Register Defines */
479#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
480#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
481
482#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
483#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
484
485#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
486
487#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
488
489#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
490#endif
491
492
493/* MPE register definitions */
494#define XREG_FPSID c0
495#define XREG_FPSCR c1
496#define XREG_MVFR1 c6
497#define XREG_MVFR0 c7
498#define XREG_FPEXC c8
499#define XREG_FPINST c9
500#define XREG_FPINST2 c10
501
502/* FPSID bits */
503#define XREG_FPSID_IMPLEMENTER_BIT (24)
504#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
505#define XREG_FPSID_SOFTWARE (1<<23)
506#define XREG_FPSID_ARCH_BIT (16)
507#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
508#define XREG_FPSID_PART_BIT (8)
509#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
510#define XREG_FPSID_VARIANT_BIT (4)
511#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
512#define XREG_FPSID_REV_BIT (0)
513#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
514
515/* FPSCR bits */
516#define XREG_FPSCR_N_BIT (1 << 31)
517#define XREG_FPSCR_Z_BIT (1 << 30)
518#define XREG_FPSCR_C_BIT (1 << 29)
519#define XREG_FPSCR_V_BIT (1 << 28)
520#define XREG_FPSCR_QC (1 << 27)
521#define XREG_FPSCR_AHP (1 << 26)
522#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
523#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
524#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
525#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
526#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
527#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
528#define XREG_FPSCR_RMODE_BIT (22)
529#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
530#define XREG_FPSCR_STRIDE_BIT (20)
531#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
532#define XREG_FPSCR_LENGTH_BIT (16)
533#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
534#define XREG_FPSCR_IDC (1 << 7)
535#define XREG_FPSCR_IXC (1 << 4)
536#define XREG_FPSCR_UFC (1 << 3)
537#define XREG_FPSCR_OFC (1 << 2)
538#define XREG_FPSCR_DZC (1 << 1)
539#define XREG_FPSCR_IOC (1 << 0)
540
541/* MVFR0 bits */
542#define XREG_MVFR0_RMODE_BIT (28)
543#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
544#define XREG_MVFR0_SHORT_VEC_BIT (24)
545#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
546#define XREG_MVFR0_SQRT_BIT (20)
547#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
548#define XREG_MVFR0_DIVIDE_BIT (16)
549#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
550#define XREG_MVFR0_EXEC_TRAP_BIT (12)
551#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
552#define XREG_MVFR0_DP_BIT (8)
553#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
554#define XREG_MVFR0_SP_BIT (4)
555#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
556#define XREG_MVFR0_A_SIMD_BIT (0)
557#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
558
559/* FPEXC bits */
560#define XREG_FPEXC_EX (1 << 31)
561#define XREG_FPEXC_EN (1 << 30)
562#define XREG_FPEXC_DEX (1 << 29)
563
564
569#ifdef __cplusplus
570}
571#endif /* __cplusplus */
572
573#endif /* XREG_CORTEXA9_H */