RTEMS 6.1-rc1
xnandpsu.h
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1/******************************************************************************
2* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
162#ifndef XNANDPSU_H /* prevent circular inclusions */
163#define XNANDPSU_H /* by using protection macros */
164
165#ifdef __cplusplus
166extern "C" {
167#endif
168
169/***************************** Include Files *********************************/
170#include "xil_types.h"
171#include <string.h>
172#include "xstatus.h"
173#include "xil_assert.h"
174#include "xnandpsu_hw.h"
175#include "xnandpsu_onfi.h"
176#include "xil_cache.h"
177#if defined (XCLOCKING)
178#include "xil_clocking.h"
179#endif
180/************************** Constant Definitions *****************************/
181
182#define XNANDPSU_DEBUG
183
184#ifdef __rtems__
185#define XNANDPSU_MAX_TARGETS 2U
186#else
187#define XNANDPSU_MAX_TARGETS 1U
188#endif
189#define XNANDPSU_MAX_PKT_SIZE 0x7FFU
190#define XNANDPSU_MAX_PKT_COUNT 0xFFFU
192#define XNANDPSU_PAGE_SIZE_512 512U
193#define XNANDPSU_PAGE_SIZE_2K 2048U
194#define XNANDPSU_PAGE_SIZE_4K 4096U
195#define XNANDPSU_PAGE_SIZE_8K 8192U
196#define XNANDPSU_PAGE_SIZE_16K 16384U
197#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U
198#define XNANDPSU_MAX_PAGE_SIZE 16384U
200#define XNANDPSU_HAMMING 0x1U
201#define XNANDPSU_BCH 0x2U
203#define XNANDPSU_MAX_BLOCKS 16384U
204#define XNANDPSU_MAX_SPARE_SIZE 0x800U
206#define XNANDPSU_MAX_LUNS 8U
207#define XNANDPSU_MAX_PAGES_PER_BLOCK 512U
209#define XNANDPSU_INTR_POLL_TIMEOUT 0xF000000U
210
211#define XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
212#define XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)
213#define XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)
214#define XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)
215#define XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)
216#define XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)
217#define XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
218
219#define XNANDPSU_MAX_TIMING_MODE 5
224typedef struct {
228#if defined (XCLOCKING)
229 u32 RefClk;
230#endif
232
236typedef enum {
240
244typedef enum {
245 XNANDPSU_SDR0 = 0U,
246 XNANDPSU_SDR1,
247 XNANDPSU_SDR2,
248 XNANDPSU_SDR3,
249 XNANDPSU_SDR4,
250 XNANDPSU_SDR5,
251 XNANDPSU_NVDDR0,
252 XNANDPSU_NVDDR1,
253 XNANDPSU_NVDDR2,
254 XNANDPSU_NVDDR3,
255 XNANDPSU_NVDDR4,
256 XNANDPSU_NVDDR5
258
262typedef enum {
266
270typedef enum {
275
279typedef enum {
280 XNANDPSU_NONE = 0,
281 XNANDPSU_HWECC,
282 XNANDPSU_EZNAND,
283 XNANDPSU_ONDIE
285
289typedef struct {
290 u32 PageOffset[XNANDPSU_MAX_TARGETS];
296 char Signature[5];
299 u32 Valid;
301
305typedef struct {
307 u32 Offset;
308 u32 Length;
309 u8 Pattern[2];
311
315typedef struct {
316 /* Parameter page information */
327 /* Driver specific information */
337
341typedef struct {
342 u32 NvDdr;
343 u32 EzNand;
344 u32 OnDie;
345 u32 ExtPrmPage;
347
351typedef struct {
352 u16 PageSize;
353 u16 CodeWordSize;
354 u8 NumEccBits;
355 u8 IsBCH;
356 u16 EccAddr;
357 u16 EccSize;
359
363typedef struct {
364 u16 EccAddr;
365 u16 EccSize;
366 u16 CodeWordSize;
367 u8 NumEccBits;
368 u8 IsBCH;
370
377#ifdef __ICCARM__
378#pragma pack(push, 1)
379#endif
380typedef struct {
382 XNandPsu_Config Config;
385 XNandPsu_DataInterface DataInterface;
386 XNandPsu_TimingMode TimingMode;
393#ifdef __ICCARM__
394 u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE];
395#pragma pack(pop)
396#else
397 u8 PartialDataBuf[XNANDPSU_MAX_PAGE_SIZE] __attribute__ ((aligned(64)));
398#endif
399 /* Bad block table definitions */
404 u8 Bbt[XNANDPSU_MAX_BLOCKS >> 2];
405} XNandPsu;
406
407/******************* Macro Definitions (Inline Functions) *******************/
408
409/*****************************************************************************/
423#define XNandPsu_SetBits(InstancePtr, RegOffset, BitMask) \
424 XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
425 (RegOffset), \
426 ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
427 (RegOffset)) | (BitMask))))
428
429/*****************************************************************************/
443#define XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask) \
444 XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
445 (RegOffset), \
446 ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
447 (RegOffset)) & ~(BitMask))))
448
449/*****************************************************************************/
464#define XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value) \
465 XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
466 (RegOffset), \
467 ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
468 (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))
469
470/*****************************************************************************/
482#define XNandPsu_IntrSigEnable(InstancePtr, Mask) \
483 XNandPsu_SetBits((InstancePtr), \
484 XNANDPSU_INTR_SIG_EN_OFFSET, \
485 (Mask))
486
487/*****************************************************************************/
499#define XNandPsu_IntrSigClear(InstancePtr, Mask) \
500 XNandPsu_ClrBits((InstancePtr), \
501 XNANDPSU_INTR_SIG_EN_OFFSET, \
502 (Mask))
503
504/*****************************************************************************/
516#define XNandPsu_IntrStsEnable(InstancePtr, Mask) \
517 XNandPsu_SetBits((InstancePtr), \
518 XNANDPSU_INTR_STS_EN_OFFSET, \
519 (Mask))
520
521/*****************************************************************************/
530#define IS_ONFI(Buff) \
531 ((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \
532 ((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I')
533
534/************************** Function Prototypes *****************************/
535
536s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
537 u32 EffectiveAddr);
538
539s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length);
540
541s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length,
542 u8 *SrcBuf);
543
544s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length,
545 u8 *DestBuf);
546
547s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block);
548
549s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
550
551s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf);
552
553s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr,
555 XNandPsu_TimingMode NewMode);
556
557s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
558 u8 *Buf);
559
560s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature,
561 u8 *Buf);
562
563s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr);
564
565s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block);
566
567void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr);
568
569void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr);
570
571void XNandPsu_EnableEccMode(XNandPsu *InstancePtr);
572
573void XNandPsu_DisableEccMode(XNandPsu *InstancePtr);
574
575void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
576 u8 DmaMode, u8 AddrCycles);
577
578/* XNandPsu_LookupConfig in xnandpsu_sinit.c */
579XNandPsu_Config *XNandPsu_LookupConfig(u16 DevID);
580
581
582#ifdef __cplusplus
583}
584#endif
585
586#endif /* XNANDPSU_H end of protection macro */
void XNandPsu_DisableEccMode(XNandPsu *InstancePtr)
Definition: xnandpsu.c:808
void XNandPsu_EnableEccMode(XNandPsu *InstancePtr)
Definition: xnandpsu.c:786
s32 XNandPsu_ReadSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
Definition: xnandpsu.c:2115
XNandPsu_SWMode
Definition: xnandpsu.h:262
#define XNANDPSU_MAX_TARGETS
Definition: xnandpsu.h:187
s32 XNandPsu_ChangeTimingMode(XNandPsu *InstancePtr, XNandPsu_DataInterface NewIntf, XNandPsu_TimingMode NewMode)
Definition: xnandpsu.c:2389
void XNandPsu_EnableDmaMode(XNandPsu *InstancePtr)
Definition: xnandpsu.c:742
XNandPsu_DmaMode
Definition: xnandpsu.h:270
#define XNANDPSU_MAX_BLOCKS
Definition: xnandpsu.h:203
s32 XNandPsu_EraseBlock(XNandPsu *InstancePtr, u32 Target, u32 Block)
Definition: xnandpsu.c:2190
#define XNANDPSU_MAX_PAGE_SIZE
Definition: xnandpsu.h:198
s32 XNandPsu_SetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, u8 *Buf)
Definition: xnandpsu.c:2307
s32 XNandPsu_WriteSpareBytes(XNandPsu *InstancePtr, u32 Page, u8 *Buf)
Definition: xnandpsu.c:1842
s32 XNandPsu_Erase(XNandPsu *InstancePtr, u64 Offset, u64 Length)
Definition: xnandpsu.c:1665
s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr, u32 EffectiveAddr)
Definition: xnandpsu.c:225
s32 XNandPsu_ScanBbt(XNandPsu *InstancePtr)
Definition: xnandpsu_bbm.c:253
s32 XNandPsu_MarkBlockBad(XNandPsu *InstancePtr, u32 Block)
Definition: xnandpsu_bbm.c:873
XNandPsu_EccMode
Definition: xnandpsu.h:279
XNandPsu_TimingMode
Definition: xnandpsu.h:244
void XNandPsu_DisableDmaMode(XNandPsu *InstancePtr)
Definition: xnandpsu.c:764
s32 XNandPsu_GetFeature(XNandPsu *InstancePtr, u32 Target, u8 Feature, u8 *Buf)
Definition: xnandpsu.c:2248
void XNandPsu_Prepare_Cmd(XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState, u8 DmaMode, u8 AddrCycles)
Definition: xnandpsu.c:2717
XNandPsu_DataInterface
Definition: xnandpsu.h:236
s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf)
Definition: xnandpsu.c:1544
s32 XNandPsu_Write(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *SrcBuf)
Definition: xnandpsu.c:1425
@ XNANDPSU_POLLING
Definition: xnandpsu.h:263
@ XNANDPSU_INTERRUPT
Definition: xnandpsu.h:264
@ XNANDPSU_MDMA
Definition: xnandpsu.h:273
@ XNANDPSU_PIO
Definition: xnandpsu.h:271
@ XNANDPSU_SDMA
Definition: xnandpsu.h:272
@ XNANDPSU_SDR
Definition: xnandpsu.h:237
@ XNANDPSU_NVDDR
Definition: xnandpsu.h:238
unsigned short int uint16 __attribute__((__may_alias__))
Perform a 32-bit endian conversion.
Definition: mcf5282.h:37
Definition: xnandpsu.h:305
u32 Options
Definition: xnandpsu.h:306
u32 Length
Definition: xnandpsu.h:308
u32 Offset
Definition: xnandpsu.h:307
Definition: xnandpsu.h:289
u32 MaxBlocks
Definition: xnandpsu.h:295
u32 VerOffset
Definition: xnandpsu.h:293
u32 SigOffset
Definition: xnandpsu.h:292
u32 SigLength
Definition: xnandpsu.h:294
u32 Valid
Definition: xnandpsu.h:299
Definition: xnandpsu.h:224
u16 DeviceId
Definition: xnandpsu.h:225
u8 IsCacheCoherent
Definition: xnandpsu.h:227
u32 BaseAddress
Definition: xnandpsu.h:226
Definition: xnandpsu.h:363
Definition: xnandpsu.h:351
Definition: xnandpsu.h:341
Definition: xnandpsu.h:315
u8 NumBitsPerCell
Definition: xnandpsu.h:324
u32 NumTargetPages
Definition: xnandpsu.h:329
u8 NumLuns
Definition: xnandpsu.h:321
u32 BlocksPerLun
Definition: xnandpsu.h:320
u8 NumBitsECC
Definition: xnandpsu.h:325
u32 PagesPerBlock
Definition: xnandpsu.h:319
u32 EccCodeWordSize
Definition: xnandpsu.h:326
u64 DeviceSize
Definition: xnandpsu.h:335
u32 BlockSize
Definition: xnandpsu.h:328
u8 ColAddrCycles
Definition: xnandpsu.h:323
u64 TargetSize
Definition: xnandpsu.h:331
u32 NumBlocks
Definition: xnandpsu.h:334
u8 NumTargets
Definition: xnandpsu.h:332
u32 NumPages
Definition: xnandpsu.h:333
u32 NumTargetBlocks
Definition: xnandpsu.h:330
u16 SpareBytesPerPage
Definition: xnandpsu.h:318
u32 BytesPerPage
Definition: xnandpsu.h:317
u8 RowAddrCycles
Definition: xnandpsu.h:322
Definition: xnandpsu.h:380
XNandPsu_EccMode EccMode
Definition: xnandpsu.h:389
XNandPsu_Features Features
Definition: xnandpsu.h:392
XNandPsu_BadBlockPattern BbPattern
Definition: xnandpsu.h:402
XNandPsu_SWMode Mode
Definition: xnandpsu.h:387
XNandPsu_EccCfg EccCfg
Definition: xnandpsu.h:390
u32 Ecc_Stats_total_flips
Definition: xnandpsu.h:384
XNandPsu_BbtDesc BbtMirrorDesc
Definition: xnandpsu.h:401
XNandPsu_BbtDesc BbtDesc
Definition: xnandpsu.h:400
XNandPsu_Geometry Geometry
Definition: xnandpsu.h:391
XNandPsu_DmaMode DmaMode
Definition: xnandpsu.h:388
u32 IsReady
Definition: xnandpsu.h:381
u32 Ecc_Stat_PerPage_flips
Definition: xnandpsu.h:383