RTEMS 6.1-rc1
tms570_selftest.h
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1
8/*
9 * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
10 *
11 * Czech Technical University in Prague
12 * Zikova 1903/4
13 * 166 36 Praha 6
14 * Czech Republic
15 *
16 * The license and distribution terms for this file may be
17 * found in the file LICENSE in this distribution or at
18 * http://www.rtems.org/license/LICENSE.
19 *
20 * Algorithms are based on Ti manuals and Ti HalCoGen generated
21 * code available under following copyright.
22 */
23/*
24 * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
25 *
26 *
27 * Redistribution and use in source and binary forms, with or without
28 * modification, are permitted provided that the following conditions
29 * are met:
30 *
31 * Redistributions of source code must retain the above copyright
32 * notice, this list of conditions and the following disclaimer.
33 *
34 * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the
37 * distribution.
38 *
39 * Neither the name of Texas Instruments Incorporated nor the names of
40 * its contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 */
56
57#ifndef LIBBSP_ARM_TMS570_SELFTEST_H
58#define LIBBSP_ARM_TMS570_SELFTEST_H
59
60#include <stdint.h>
61#include <stdbool.h>
62
63#define CCMSELFCHECK_FAIL1 1U
64#define CCMSELFCHECK_FAIL2 2U
65#define CCMSELFCHECK_FAIL3 3U
66#define CCMSELFCHECK_FAIL4 4U
67#define PBISTSELFCHECK_FAIL1 5U
68#define EFCCHECK_FAIL1 6U
69#define EFCCHECK_FAIL2 7U
70#define FMCECCCHECK_FAIL1 8U
71#define CHECKB0RAMECC_FAIL1 9U
72#define CHECKB1RAMECC_FAIL1 10U
73#define CHECKFLASHECC_FAIL1 11U
74#define VIMPARITYCHECK_FAIL1 12U
75#define DMAPARITYCHECK_FAIL1 13U
76#define HET1PARITYCHECK_FAIL1 14U
77#define HTU1PARITYCHECK_FAIL1 15U
78#define HET2PARITYCHECK_FAIL1 16U
79#define HTU2PARITYCHECK_FAIL1 17U
80#define ADC1PARITYCHECK_FAIL1 18U
81#define ADC2PARITYCHECK_FAIL1 19U
82#define CAN1PARITYCHECK_FAIL1 20U
83#define CAN2PARITYCHECK_FAIL1 21U
84#define CAN3PARITYCHECK_FAIL1 22U
85#define MIBSPI1PARITYCHECK_FAIL1 23U
86#define MIBSPI3PARITYCHECK_FAIL1 24U
87#define MIBSPI5PARITYCHECK_FAIL1 25U
88#define CHECKRAMECC_FAIL1 26U
89#define CHECKRAMECC_FAIL2 27U
90#define CHECKCLOCKMONITOR_FAIL1 28U
91#define CHECKFLASHEEPROMECC_FAIL1 29U
92#define CHECKFLASHEEPROMECC_FAIL2 31U
93#define CHECKFLASHEEPROMECC_FAIL3 32U
94#define CHECKFLASHEEPROMECC_FAIL4 33U
95#define CHECKPLL1SLIP_FAIL1 34U
96#define CHECKRAMADDRPARITY_FAIL1 35U
97#define CHECKRAMADDRPARITY_FAIL2 36U
98#define CHECKRAMUERRTEST_FAIL1 37U
99#define CHECKRAMUERRTEST_FAIL2 38U
100#define FMCBUS1PARITYCHECK_FAIL1 39U
101#define FMCBUS1PARITYCHECK_FAIL2 40U
102#define PBISTSELFCHECK_FAIL2 41U
103#define PBISTSELFCHECK_FAIL3 42U
104
105/* PBIST and STC ROM - PBIST RAM GROUPING */
106#define PBIST_ROM_PBIST_RAM_GROUP 1U
107#define STC_ROM_PBIST_RAM_GROUP 2U
108
109#define VIMRAMLOC (*(volatile uint32_t *)0xFFF82000U)
110#define VIMRAMPARLOC (*(volatile uint32_t *)0xFFF82400U)
111
112#define NHET1RAMPARLOC (*(volatile uint32_t *)0xFF462000U)
113#define NHET2RAMPARLOC (*(volatile uint32_t *)0xFF442000U)
114#define adcPARRAM1 (*(volatile uint32_t *)(0xFF3E0000U + 0x1000U))
115#define adcPARRAM2 (*(volatile uint32_t *)(0xFF3A0000U + 0x1000U))
116#define canPARRAM1 (*(volatile uint32_t *)(0xFF1E0000U + 0x10U))
117#define canPARRAM2 (*(volatile uint32_t *)(0xFF1C0000U + 0x10U))
118#define canPARRAM3 (*(volatile uint32_t *)(0xFF1A0000U + 0x10U))
119#define HTU1PARLOC (*(volatile uint32_t *)0xFF4E0200U)
120#define HTU2PARLOC (*(volatile uint32_t *)0xFF4C0200U)
121
122#define NHET1RAMLOC (*(volatile uint32_t *)0xFF460000U)
123#define NHET2RAMLOC (*(volatile uint32_t *)0xFF440000U)
124#define HTU1RAMLOC (*(volatile uint32_t *)0xFF4E0000U)
125#define HTU2RAMLOC (*(volatile uint32_t *)0xFF4C0000U)
126
127#define adcRAM1 (*(volatile uint32_t *)0xFF3E0000U)
128#define adcRAM2 (*(volatile uint32_t *)0xFF3A0000U)
129#define canRAM1 (*(volatile uint32_t *)0xFF1E0000U)
130#define canRAM2 (*(volatile uint32_t *)0xFF1C0000U)
131#define canRAM3 (*(volatile uint32_t *)0xFF1A0000U)
132
133#define DMARAMPARLOC (*(volatile uint32_t *)(0xFFF80A00U))
134#define DMARAMLOC (*(volatile uint32_t *)(0xFFF80000U))
135
136#define MIBSPI1RAMLOC (*(volatile uint32_t *)(0xFF0E0000U))
137#define MIBSPI3RAMLOC (*(volatile uint32_t *)(0xFF0C0000U))
138#define MIBSPI5RAMLOC (*(volatile uint32_t *)(0xFF0A0000U))
139
140#define mibspiPARRAM1 (*(volatile uint32_t *)(0xFF0E0000U + 0x00000400U))
141#define mibspiPARRAM3 (*(volatile uint32_t *)(0xFF0C0000U + 0x00000400U))
142#define mibspiPARRAM5 (*(volatile uint32_t *)(0xFF0A0000U + 0x00000400U))
143
155 PBIST_PORT1 = 1U
157
158enum {
159 PBIST_TripleReadSlow = 0x00000001U,
160 PBIST_TripleReadFast = 0x00000002U,
161 PBIST_March13N_DP = 0x00000004U,
162};
163
164uint32_t tms570_efc_check( void );
165
166bool tms570_efc_check_self_test( void );
167
168void bsp_selftest_fail_notification( uint32_t flag );
169
170void tms570_memory_port0_fail_notification(
171 uint32_t groupSelect,
172 uint32_t dataSelect,
173 uint32_t address,
174 uint32_t data
175);
176
178 unsigned grp,
179 unsigned chan
180);
181
183 unsigned grp,
184 unsigned chan
185);
186
187void tms570_pbist_self_check( void );
188
190 uint32_t raminfoL,
191 uint32_t algomask
192);
193
195
196bool tms570_pbist_is_test_passed( void );
197
198void tms570_pbist_fail( void );
199
200void tms570_pbist_stop( void );
201
202void tms570_enable_parity( void );
203
204void tms570_disable_parity( void );
205
206bool tms570_efc_stuck_zero( void );
207
208void tms570_efc_self_test( void );
209
210bool tms570_pbist_port_test_status( uint32_t port );
211
212void tms570_check_tcram_ecc( void );
213
214#endif /*LIBBSP_ARM_TMS570_SELFTEST_H*/
int tms570_esm_channel_sr_get(unsigned grp, unsigned chan)
Routine to test is specified error channel is signalling error.
Definition: tms570_selftest.c:541
void tms570_pbist_self_check(void)
PBIST self test Driver (HCG:pbistSelfCheck)
Definition: tms570_selftest.c:230
void tms570_pbist_run(uint32_t raminfoL, uint32_t algomask)
CPU self test Driver (HCG:pbistRun)
Definition: tms570_selftest.c:326
@ PBIST_March13N_DP
Definition: tms570_selftest.h:161
@ PBIST_TripleReadFast
Definition: tms570_selftest.h:160
@ PBIST_TripleReadSlow
Definition: tms570_selftest.h:159
void tms570_check_tcram_ecc(void)
Check TCRAM ECC error detection logic (HCG:checkRAMECC)
Definition: tms570_tcram_tests.c:85
void tms570_pbist_fail(void)
Reaction to PBIST failure (HCG:pbistFail)
Definition: tms570_selftest.c:458
bool tms570_pbist_is_test_passed(void)
Checks to see if the PBIST test is completed successfully (HCG:pbistIsTestPassed)
Definition: tms570_selftest.c:413
bool tms570_pbist_port_test_status(uint32_t port)
Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus)
Definition: tms570_selftest.c:436
bool tms570_efc_stuck_zero(void)
Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest)....
Definition: tms570_selftest.c:59
void tms570_efc_self_test(void)
EFUSE module self check Driver (HCG:efcSelfTest)
Definition: tms570_selftest.c:118
void tms570_esm_channel_sr_clear(unsigned grp, unsigned chan)
Routine to clear specified error channel signalling bit.
Definition: tms570_selftest.c:523
void tms570_enable_parity(void)
Enable peripheral RAM parity (HCG:enableParity)
Definition: tms570_selftest.c:563
void tms570_pbist_stop(void)
Routine to stop PBIST test enabled (HCG:pbistStop)
Definition: tms570_selftest.c:382
void tms570_disable_parity(void)
Disable peripheral RAM parity (HCG:disableParity)
Definition: tms570_selftest.c:585
bool tms570_efc_check_self_test(void)
EFUSE module self check Driver (HCG:checkefcSelfTest)
Definition: tms570_selftest.c:142
pbistPort
Alias names for pbist Port number.
Definition: tms570_selftest.h:153
@ PBIST_PORT0
Definition: tms570_selftest.h:154
@ PBIST_PORT1
Definition: tms570_selftest.h:155
bool tms570_pbist_is_test_completed(void)
Checks to see if the PBIST test is completed (HCG:pbistIsTestCompleted)
Definition: tms570_selftest.c:399
uint32_t tms570_efc_check(void)
EFUSE module self check Driver (HCG:efcCheck)
Definition: tms570_selftest.c:185