RTEMS 6.1-rc1
stm32h7xx_ll_rng.h
Go to the documentation of this file.
1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_RNG_H
21#define STM32H7xx_LL_RNG_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined (RNG)
35
41/* Private types -------------------------------------------------------------*/
42/* Private defines -----------------------------------------------------------*/
47/* Health test control register information to use in CCM algorithm */
48#define LL_RNG_HTCFG 0x17590ABCU
52/* Private variables ---------------------------------------------------------*/
53/* Private constants ---------------------------------------------------------*/
54/* Private macros ------------------------------------------------------------*/
55
56/* Exported types ------------------------------------------------------------*/
57#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
67typedef struct
68{
69 uint32_t ClockErrorDetection;
73} LL_RNG_InitTypeDef;
74
78#endif /* USE_FULL_LL_DRIVER */
79/* Exported constants --------------------------------------------------------*/
89#define LL_RNG_CED_ENABLE 0x00000000U
90#define LL_RNG_CED_DISABLE RNG_CR_CED
95#if defined(RNG_CR_CONDRST)
101#define LL_RNG_CLKDIV_BY_1 (0x00000000UL)
102#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
103#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
104#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
105#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
106#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
107#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
108#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
109#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
110#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
111#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
112#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
113#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
114#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
115#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
116#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
125#define LL_RNG_NIST_COMPLIANT (0x00000000UL)
126#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC)
132#endif /* RNG_CR_CONDRST */
138#define LL_RNG_SR_DRDY RNG_SR_DRDY
139#define LL_RNG_SR_CECS RNG_SR_CECS
140#define LL_RNG_SR_SECS RNG_SR_SECS
141#define LL_RNG_SR_CEIS RNG_SR_CEIS
142#define LL_RNG_SR_SEIS RNG_SR_SEIS
152#define LL_RNG_CR_IE RNG_CR_IE
161/* Exported macro ------------------------------------------------------------*/
179#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
180
187#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
197/* Exported functions --------------------------------------------------------*/
213__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
214{
215 SET_BIT(RNGx->CR, RNG_CR_RNGEN);
216}
217
224__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
225{
226 CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
227}
228
235__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
236{
237 return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
238}
239
246__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
247{
248 CLEAR_BIT(RNGx->CR, RNG_CR_CED);
249}
250
257__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
258{
259 SET_BIT(RNGx->CR, RNG_CR_CED);
260}
261
268__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
269{
270 return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
271}
272
273#if defined(RNG_CR_CONDRST)
280__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
281{
282 SET_BIT(RNGx->CR, RNG_CR_CONDRST);
283}
284
291__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
292{
293 CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
294}
295
302__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
303{
304 return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
305}
306
313__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
314{
315 SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
316}
317
324__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
325{
326 return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
327}
328
335__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
336{
337 CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
338}
339
346__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
347{
348 SET_BIT(RNGx->CR, RNG_CR_NISTC);
349}
350
357__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
358{
359 return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
360}
361
369__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
370{
371 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
372}
373
380__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
381{
382 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
383}
384
392__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
393{
394 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
395}
396
403__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
404{
405 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
406}
407
415__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
416{
417 MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
418}
419
426__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
427{
428 return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
429}
430
454__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
455{
456 MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
457}
458
481__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
482{
483 return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
484}
485#endif /* RNG_CR_CONDRST */
501__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
502{
503 return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
504}
505
512__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
513{
514 return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
515}
516
523__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
524{
525 return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
526}
527
534__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
535{
536 return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
537}
538
545__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
546{
547 return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
548}
549
556__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
557{
558 WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
559}
560
567__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
568{
569 WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
570}
571
588__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
589{
590 SET_BIT(RNGx->CR, RNG_CR_IE);
591}
592
600__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
601{
602 CLEAR_BIT(RNGx->CR, RNG_CR_IE);
603}
604
612__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
613{
614 return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
615}
616
632__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
633{
634 return (uint32_t)(READ_REG(RNGx->DR));
635}
636
641#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
654__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
655{
657 WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
658
659 WRITE_REG(RNGx->HTCR, HTCFG);
660}
661
668__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
669{
671 WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
672
673 return (uint32_t)READ_REG(RNGx->HTCR);
674}
675
679#endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */
680#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
685ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
686void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
687ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
688
692#endif /* USE_FULL_LL_DRIVER */
693
702#endif /* RNG */
703
708#ifdef __cplusplus
709}
710#endif
711
712#endif /* __STM32H7xx_LL_RNG_H */
713
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
RNG.
Definition: stm32h723xx.h:1668
__IO uint32_t SR
Definition: stm32h723xx.h:1670
__IO uint32_t DR
Definition: stm32h723xx.h:1671
__IO uint32_t HTCR
Definition: stm32h723xx.h:1673
__IO uint32_t CR
Definition: stm32h723xx.h:1669