20#ifndef STM32H7xx_LL_RNG_H
21#define STM32H7xx_LL_RNG_H
48#define LL_RNG_HTCFG 0x17590ABCU
57#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
69 uint32_t ClockErrorDetection;
89#define LL_RNG_CED_ENABLE 0x00000000U
90#define LL_RNG_CED_DISABLE RNG_CR_CED
95#if defined(RNG_CR_CONDRST)
101#define LL_RNG_CLKDIV_BY_1 (0x00000000UL)
102#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
103#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
104#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
105#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
106#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
107#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
108#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
109#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
110#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
111#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
112#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
113#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
114#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
115#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
116#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
125#define LL_RNG_NIST_COMPLIANT (0x00000000UL)
126#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC)
138#define LL_RNG_SR_DRDY RNG_SR_DRDY
139#define LL_RNG_SR_CECS RNG_SR_CECS
140#define LL_RNG_SR_SECS RNG_SR_SECS
141#define LL_RNG_SR_CEIS RNG_SR_CEIS
142#define LL_RNG_SR_SEIS RNG_SR_SEIS
152#define LL_RNG_CR_IE RNG_CR_IE
179#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
187#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
213__STATIC_INLINE
void LL_RNG_Enable(
RNG_TypeDef *RNGx)
215 SET_BIT(RNGx->
CR, RNG_CR_RNGEN);
224__STATIC_INLINE
void LL_RNG_Disable(
RNG_TypeDef *RNGx)
226 CLEAR_BIT(RNGx->
CR, RNG_CR_RNGEN);
235__STATIC_INLINE uint32_t LL_RNG_IsEnabled(
RNG_TypeDef *RNGx)
237 return ((READ_BIT(RNGx->
CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
246__STATIC_INLINE
void LL_RNG_EnableClkErrorDetect(
RNG_TypeDef *RNGx)
248 CLEAR_BIT(RNGx->
CR, RNG_CR_CED);
257__STATIC_INLINE
void LL_RNG_DisableClkErrorDetect(
RNG_TypeDef *RNGx)
259 SET_BIT(RNGx->
CR, RNG_CR_CED);
268__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(
RNG_TypeDef *RNGx)
270 return ((READ_BIT(RNGx->
CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
273#if defined(RNG_CR_CONDRST)
280__STATIC_INLINE
void LL_RNG_EnableCondReset(
RNG_TypeDef *RNGx)
282 SET_BIT(RNGx->
CR, RNG_CR_CONDRST);
291__STATIC_INLINE
void LL_RNG_DisableCondReset(
RNG_TypeDef *RNGx)
293 CLEAR_BIT(RNGx->
CR, RNG_CR_CONDRST);
302__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(
RNG_TypeDef *RNGx)
304 return ((READ_BIT(RNGx->
CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
313__STATIC_INLINE
void LL_RNG_ConfigLock(
RNG_TypeDef *RNGx)
315 SET_BIT(RNGx->
CR, RNG_CR_CONFIGLOCK);
324__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(
RNG_TypeDef *RNGx)
326 return ((READ_BIT(RNGx->
CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
335__STATIC_INLINE
void LL_RNG_EnableNistCompliance(
RNG_TypeDef *RNGx)
337 CLEAR_BIT(RNGx->
CR, RNG_CR_NISTC);
346__STATIC_INLINE
void LL_RNG_DisableNistCompliance(
RNG_TypeDef *RNGx)
348 SET_BIT(RNGx->
CR, RNG_CR_NISTC);
357__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(
RNG_TypeDef *RNGx)
359 return ((READ_BIT(RNGx->
CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
369__STATIC_INLINE
void LL_RNG_SetConfig1(
RNG_TypeDef *RNGx, uint32_t Config1)
371 MODIFY_REG(RNGx->
CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
380__STATIC_INLINE uint32_t LL_RNG_GetConfig1(
RNG_TypeDef *RNGx)
382 return (uint32_t)(READ_BIT(RNGx->
CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
392__STATIC_INLINE
void LL_RNG_SetConfig2(
RNG_TypeDef *RNGx, uint32_t Config2)
394 MODIFY_REG(RNGx->
CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
403__STATIC_INLINE uint32_t LL_RNG_GetConfig2(
RNG_TypeDef *RNGx)
405 return (uint32_t)(READ_BIT(RNGx->
CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
415__STATIC_INLINE
void LL_RNG_SetConfig3(
RNG_TypeDef *RNGx, uint32_t Config3)
417 MODIFY_REG(RNGx->
CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
426__STATIC_INLINE uint32_t LL_RNG_GetConfig3(
RNG_TypeDef *RNGx)
428 return (uint32_t)(READ_BIT(RNGx->
CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
454__STATIC_INLINE
void LL_RNG_SetClockDivider(
RNG_TypeDef *RNGx, uint32_t Divider)
456 MODIFY_REG(RNGx->
CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
481__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(
RNG_TypeDef *RNGx)
483 return (uint32_t)READ_BIT(RNGx->
CR, RNG_CR_CLKDIV);
501__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(
RNG_TypeDef *RNGx)
503 return ((READ_BIT(RNGx->
SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
512__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(
RNG_TypeDef *RNGx)
514 return ((READ_BIT(RNGx->
SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
523__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(
RNG_TypeDef *RNGx)
525 return ((READ_BIT(RNGx->
SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
534__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(
RNG_TypeDef *RNGx)
536 return ((READ_BIT(RNGx->
SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
545__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(
RNG_TypeDef *RNGx)
547 return ((READ_BIT(RNGx->
SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
556__STATIC_INLINE
void LL_RNG_ClearFlag_CEIS(
RNG_TypeDef *RNGx)
558 WRITE_REG(RNGx->
SR, ~RNG_SR_CEIS);
567__STATIC_INLINE
void LL_RNG_ClearFlag_SEIS(
RNG_TypeDef *RNGx)
569 WRITE_REG(RNGx->
SR, ~RNG_SR_SEIS);
588__STATIC_INLINE
void LL_RNG_EnableIT(
RNG_TypeDef *RNGx)
590 SET_BIT(RNGx->
CR, RNG_CR_IE);
600__STATIC_INLINE
void LL_RNG_DisableIT(
RNG_TypeDef *RNGx)
602 CLEAR_BIT(RNGx->
CR, RNG_CR_IE);
612__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(
RNG_TypeDef *RNGx)
614 return ((READ_BIT(RNGx->
CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
632__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(
RNG_TypeDef *RNGx)
634 return (uint32_t)(READ_REG(RNGx->
DR));
641#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
654__STATIC_INLINE
void LL_RNG_SetHealthConfig(
RNG_TypeDef *RNGx, uint32_t HTCFG)
657 WRITE_REG(RNGx->
HTCR, LL_RNG_HTCFG);
659 WRITE_REG(RNGx->
HTCR, HTCFG);
668__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(
RNG_TypeDef *RNGx)
671 WRITE_REG(RNGx->
HTCR, LL_RNG_HTCFG);
673 return (uint32_t)READ_REG(RNGx->
HTCR);
680#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
685ErrorStatus LL_RNG_Init(
RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
686void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
RNG.
Definition: stm32h723xx.h:1668
__IO uint32_t SR
Definition: stm32h723xx.h:1670
__IO uint32_t DR
Definition: stm32h723xx.h:1671
__IO uint32_t HTCR
Definition: stm32h723xx.h:1673
__IO uint32_t CR
Definition: stm32h723xx.h:1669