RTEMS 6.1-rc1
stm32h7xx_ll_dac.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_LL_DAC_H
21#define STM32H7xx_LL_DAC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx.h"
29
34#if defined(DAC1) || defined(DAC2)
35
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
50/* Internal masks for DAC channels definition */
51/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
52/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
53/* - channel bits position into register SWTRIG */
54/* - channel register offset of data holding register DHRx */
55/* - channel register offset of data output register DORx */
56/* - channel register offset of sample-and-hold sample time register SHSRx */
57#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 1 */
59#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
60 CR, MCR, CCR, SHHR, SHRR of channel 2 */
61#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
62
63#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
64#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
65#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
66
67#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
68#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
69 DHR12Rx channel 1 (shifted left of 20 bits) */
70#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
71 DHR12Rx channel 1 (shifted left of 24 bits) */
72
73#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
74 DHR12Rx channel 1 (shifted left of 28 bits) */
75#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
76 DHR12Rx channel 1 (shifted left of 20 bits) */
77#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
78 DHR12Rx channel 1 (shifted left of 24 bits) */
79
80#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
81#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
82#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
83#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
84 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
85
86#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
87
88#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
89 DORx channel 2 (shifted left of 5 bits) */
90#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
91
92#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
93#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
94 SHSRx channel 2 (shifted left of 6 bits) */
95#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
96
97
98#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
99 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
100#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
101 to position 0 */
102#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
103 to position 0 */
104
105#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
106 channel 1 or 2 versus DHR12Rx channel 1
107 (shifted left of 28 bits) */
108#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
109 channel 1 or 2 versus DHR12Rx channel 1
110 (shifted left of 20 bits) */
111#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
112 channel 1 or 2 versus DHR12Rx channel 1
113 (shifted left of 24 bits) */
114#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
115 channel 1 or 2 versus DORx channel 1
116 (shifted left of 5 bits) */
117#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
118 channel 1 or 2 versus SHSRx channel 1
119 (shifted left of 6 bits) */
120
121/* DAC registers bits positions */
122#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
123#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
124#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
125
126/* Miscellaneous data */
127#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
128 bits (voltage range determined by analog voltage
129 references Vref+ and Vref-, refer to reference manual) */
130
136/* Private macros ------------------------------------------------------------*/
150#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
151 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
152
158/* Exported types ------------------------------------------------------------*/
159#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
168typedef struct
169{
170 uint32_t TriggerSource;
178 uint32_t WaveAutoGeneration;
184 uint32_t WaveAutoGenerationConfig;
197 uint32_t OutputBuffer;
203 uint32_t OutputConnection;
209 uint32_t OutputMode;
214} LL_DAC_InitTypeDef;
215
219#endif /* USE_FULL_LL_DRIVER */
220
221/* Exported constants --------------------------------------------------------*/
232/* DAC channel 1 flags */
233#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
234#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1)
235#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1)
237/* DAC channel 2 flags */
238#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
239#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2)
240#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2)
251#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
253#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
263#define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
264#define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
273#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL
274#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1)
283#define LL_DAC_TRIG_SOFTWARE 0x00000000U
284#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0)
285#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 )
286#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
287#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 )
288#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
289#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
290#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
291#define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 )
292#if defined (HRTIM1)
293#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0)
294#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 )
295#endif
296#define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
297#define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 )
298#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
299#if defined(TIM23)
300#define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
301#endif
302#if defined(TIM24)
303#define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
304#endif
305#if defined (DAC2)
306#define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
307#endif
316#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
317#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
318#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
327#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
328#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
329#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
330#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
331#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
332#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
333#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
334#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
335#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
336#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
337#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
338#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
347#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
348#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
349#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
350#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
351#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
352#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
353#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
354#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
355#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
356#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
357#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
358#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
367#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL
368#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)
377#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
378#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1)
387#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL
388#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0)
397#define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE)
398#define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO)
399#define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO)
400#define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO)
401#define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO)
402#define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO)
403#define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9)
404
405#define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE)
406#define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE)
407#define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)
408
409#define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO)
410#define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL)
418#define LL_DAC_RESOLUTION_12B 0x00000000UL
419#define LL_DAC_RESOLUTION_8B 0x00000002UL
428/* List of DAC registers intended to be used (most commonly) with */
429/* DMA transfer. */
430/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
431#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
432#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
433#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
447/* Delay for DAC channel voltage settling time from DAC channel startup */
448/* (transition from disable to enable). */
449/* Note: DAC channel startup time depends on board application environment: */
450/* impedance connected to DAC channel output. */
451/* The delay below is specified under conditions: */
452/* - voltage maximum transition (lowest to highest value) */
453/* - until voltage reaches final value +-1LSB */
454/* - DAC channel output buffer enabled */
455/* - load impedance of 5kOhm (min), 50pF (max) */
456/* Literal set to maximum value (refer to device datasheet, */
457/* parameter "tWAKEUP"). */
458/* Unit: us */
459#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL
461/* Delay for DAC channel voltage settling time. */
462/* Note: DAC channel startup time depends on board application environment: */
463/* impedance connected to DAC channel output. */
464/* The delay below is specified under conditions: */
465/* - voltage maximum transition (lowest to highest value) */
466/* - until voltage reaches final value +-1LSB */
467/* - DAC channel output buffer enabled */
468/* - load impedance of 5kOhm min, 50pF max */
469/* Literal set to maximum value (refer to device datasheet, */
470/* parameter "tSETTLING"). */
471/* Unit: us */
472#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL
482/* Exported macro ------------------------------------------------------------*/
500#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
501
508#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
509
532#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
533 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
534
548#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
549 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
550
562#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
563 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
564
583#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
584 __DAC_VOLTAGE__,\
585 __DAC_RESOLUTION__) \
586((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
587 / (__VREFANALOG_VOLTAGE__) \
588)
589
599/* Exported functions --------------------------------------------------------*/
623__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
624{
625 MODIFY_REG(DACx->CR,
626 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
627 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
628}
629
643__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
644{
645 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
646 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
647 );
648}
649
663__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
664{
665 MODIFY_REG(DACx->CCR,
666 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
667 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
668}
669
682__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
683{
684 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
685 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
686 );
687}
688
731__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
732{
733 MODIFY_REG(DACx->CR,
734 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
735 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
736}
737
777__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
778{
779 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
780 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
781 );
782}
783
799__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
800{
801 MODIFY_REG(DACx->CR,
802 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
803 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
804}
805
820__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
821{
822 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
823 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
824 );
825}
826
856__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
857{
858 MODIFY_REG(DACx->CR,
859 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
860 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
861}
862
886__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
887{
888 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
889 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
890 );
891}
892
922__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
923 uint32_t TriangleAmplitude)
924{
925 MODIFY_REG(DACx->CR,
926 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
927 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
928}
929
953__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
954{
955 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
956 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
957 );
958}
959
1004__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1005 uint32_t OutputBuffer, uint32_t OutputConnection)
1006{
1007 MODIFY_REG(DACx->MCR,
1008 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1009 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1010}
1011
1032__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1033{
1034 MODIFY_REG(DACx->MCR,
1035 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1036 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1037}
1038
1051__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1052{
1053 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1054 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1055 );
1056}
1057
1075__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1076{
1077 MODIFY_REG(DACx->MCR,
1078 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1079 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1080}
1081
1094__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1095{
1096 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1097 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1098 );
1099}
1100
1124__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1125{
1126 MODIFY_REG(DACx->MCR,
1127 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1128 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1129}
1130
1153__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1154{
1155 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1156 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1157 );
1158}
1159
1176__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1177{
1178 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1179 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1180
1181 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
1182}
1183
1195__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1196{
1197 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
1198 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1199
1200 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
1201}
1202
1215__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1216{
1217 MODIFY_REG(DACx->SHHR,
1218 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1219 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1220}
1221
1233__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1234{
1235 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1236 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1237 );
1238}
1239
1252__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1253{
1254 MODIFY_REG(DACx->SHRR,
1255 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1256 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1257}
1258
1270__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1271{
1272 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1273 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
1274 );
1275}
1276
1298__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1299{
1300 SET_BIT(DACx->CR,
1301 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1302}
1303
1316__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1317{
1318 CLEAR_BIT(DACx->CR,
1319 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1320}
1321
1333__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1334{
1335 return ((READ_BIT(DACx->CR,
1336 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1337 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1338}
1339
1372__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1373{
1374 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1375 /* DAC channel selected. */
1376 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
1377 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
1378}
1401__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1402{
1403 SET_BIT(DACx->CR,
1404 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1405}
1406
1417__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1418{
1419 CLEAR_BIT(DACx->CR,
1420 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1421}
1422
1434__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1435{
1436 return ((READ_BIT(DACx->CR,
1437 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1438 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1439}
1440
1459__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1460{
1461 SET_BIT(DACx->CR,
1462 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1463}
1464
1475__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1476{
1477 CLEAR_BIT(DACx->CR,
1478 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1479}
1480
1492__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1493{
1494 return ((READ_BIT(DACx->CR,
1495 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1496 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1497}
1498
1520__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1521{
1522 SET_BIT(DACx->SWTRIGR,
1523 (DAC_Channel & DAC_SWTR_CHX_MASK));
1524}
1525
1539__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1540{
1541 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1542 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1543
1544 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1545}
1546
1560__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1561{
1562 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1563 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1564
1565 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1566}
1567
1581__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1582{
1583 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1584 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1585
1586 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1587}
1588
1589
1601__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1602 uint32_t DataChannel2)
1603{
1604 MODIFY_REG(DACx->DHR12RD,
1605 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1606 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1607}
1608
1620__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1621 uint32_t DataChannel2)
1622{
1623 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1624 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1625 /* the 4 LSB must be taken into account for the shift value. */
1626 MODIFY_REG(DACx->DHR12LD,
1627 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1628 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1629}
1630
1642__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1643 uint32_t DataChannel2)
1644{
1645 MODIFY_REG(DACx->DHR8RD,
1646 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1647 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1648}
1649
1650
1665__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1666{
1667 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1668 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1669
1670 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1671}
1672
1688__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
1689{
1690 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
1691}
1692
1693
1700__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
1701{
1702 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
1703}
1704
1705
1712__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
1713{
1714 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
1715}
1716
1723__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
1724{
1725 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
1726}
1727
1728
1735__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
1736{
1737 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1738}
1739
1740
1747__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
1748{
1749 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1750}
1751
1752
1759__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1760{
1761 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1762}
1763
1764
1771__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1772{
1773 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1774}
1775
1776
1792__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1793{
1794 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1795}
1796
1797
1804__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1805{
1806 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1807}
1808
1809
1816__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1817{
1818 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1819}
1820
1821
1828__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1829{
1830 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1831}
1832
1833
1840__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
1841{
1842 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1843}
1844
1845
1852__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
1853{
1854 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1855}
1856
1857
1862#if defined(USE_FULL_LL_DRIVER) || defined(__rtems__)
1868ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
1869ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
1870void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1871
1875#endif /* USE_FULL_LL_DRIVER */
1876
1885#endif /* DAC1 || DAC2 */
1886
1891#ifdef __cplusplus
1892}
1893#endif
1894
1895#endif /* STM32H7xx_LL_DAC_H */
1896
__IO
#define __IO
Definition: core_cm4.h:239
DAC_SHRR_TREFRESH1
#define DAC_SHRR_TREFRESH1
Definition: stm32h723xx.h:6117
DAC_MCR_MODE1_1
#define DAC_MCR_MODE1_1
Definition: stm32h723xx.h:6086
DAC_DHR12L1_DACC1DHR
#define DAC_DHR12L1_DACC1DHR
Definition: stm32h723xx.h:5996
DAC_DHR12LD_DACC1DHR
#define DAC_DHR12LD_DACC1DHR
Definition: stm32h723xx.h:6029
DAC_CCR_OTRIM1
#define DAC_CCR_OTRIM1
Definition: stm32h723xx.h:6076
DAC_CR_MAMP1
#define DAC_CR_MAMP1
Definition: stm32h723xx.h:5924
DAC_DHR12RD_DACC2DHR
#define DAC_DHR12RD_DACC2DHR
Definition: stm32h723xx.h:6024
DAC_CR_CEN1
#define DAC_CR_CEN1
Definition: stm32h723xx.h:5938
DAC_SHHR_THOLD1
#define DAC_SHHR_THOLD1
Definition: stm32h723xx.h:6109
DAC_DHR12R1_DACC1DHR
#define DAC_DHR12R1_DACC1DHR
Definition: stm32h723xx.h:5991
DAC_DOR1_DACC1DOR
#define DAC_DOR1_DACC1DOR
Definition: stm32h723xx.h:6045
DAC_DHR12LD_DACC2DHR
#define DAC_DHR12LD_DACC2DHR
Definition: stm32h723xx.h:6032
DAC_CR_WAVE1
#define DAC_CR_WAVE1
Definition: stm32h723xx.h:5918
DAC_CR_DMAEN1
#define DAC_CR_DMAEN1
Definition: stm32h723xx.h:5932
DAC_CR_TEN1
#define DAC_CR_TEN1
Definition: stm32h723xx.h:5905
DAC_DHR8RD_DACC1DHR
#define DAC_DHR8RD_DACC1DHR
Definition: stm32h723xx.h:6037
DAC_SHSR1_TSAMPLE1
#define DAC_SHSR1_TSAMPLE1
Definition: stm32h723xx.h:6099
DAC_MCR_MODE1_2
#define DAC_MCR_MODE1_2
Definition: stm32h723xx.h:6087
DAC_CR_EN1
#define DAC_CR_EN1
Definition: stm32h723xx.h:5902
DAC_DHR12RD_DACC1DHR
#define DAC_DHR12RD_DACC1DHR
Definition: stm32h723xx.h:6021
DAC_DHR8R1_DACC1DHR
#define DAC_DHR8R1_DACC1DHR
Definition: stm32h723xx.h:6001
DAC_DHR8RD_DACC2DHR
#define DAC_DHR8RD_DACC2DHR
Definition: stm32h723xx.h:6040
DAC_MCR_MODE1_0
#define DAC_MCR_MODE1_0
Definition: stm32h723xx.h:6085
DAC_CR_TSEL1
#define DAC_CR_TSEL1
Definition: stm32h723xx.h:5909
stm32h7xx.h
CMSIS STM32H7xx Device Peripheral Access Layer Header File.
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32h723xx.h:480
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32h723xx.h:483
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32h723xx.h:470
DAC_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32h723xx.h:485
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32h723xx.h:471
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32h723xx.h:481
DAC_TypeDef::SHHR
__IO uint32_t SHHR
Definition: stm32h723xx.h:488
DAC_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h723xx.h:484
DAC_TypeDef::SHSR1
__IO uint32_t SHSR1
Definition: stm32h723xx.h:486
DAC_TypeDef::SHRR
__IO uint32_t SHRR
Definition: stm32h723xx.h:489
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32h723xx.h:479
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32h723xx.h:472
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32h723xx.h:478
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