RTEMS 6.1-rc1
stm32h7b3xxq.h
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1
33#ifndef STM32H7B3xxQ_H
34#define STM32H7B3xxQ_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
48typedef enum
49{
50/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
51 NonMaskableInt_IRQn = -14,
52 HardFault_IRQn = -13,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_PVM_IRQn = 1,
63 RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 FDCAN1_IT0_IRQn = 19,
81 FDCAN2_IT0_IRQn = 20,
82 FDCAN1_IT1_IRQn = 21,
83 FDCAN2_IT1_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_IRQn = 24,
86 TIM1_UP_IRQn = 25,
87 TIM1_TRG_COM_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 DFSDM2_IRQn = 42,
104 TIM8_BRK_TIM12_IRQn = 43,
105 TIM8_UP_TIM13_IRQn = 44,
106 TIM8_TRG_COM_TIM14_IRQn = 45,
107 TIM8_CC_IRQn = 46,
108 DMA1_Stream7_IRQn = 47,
109 FMC_IRQn = 48,
110 SDMMC1_IRQn = 49,
111 TIM5_IRQn = 50,
112 SPI3_IRQn = 51,
113 UART4_IRQn = 52,
114 UART5_IRQn = 53,
115 TIM6_DAC_IRQn = 54,
116 TIM7_IRQn = 55,
117 DMA2_Stream0_IRQn = 56,
118 DMA2_Stream1_IRQn = 57,
119 DMA2_Stream2_IRQn = 58,
120 DMA2_Stream3_IRQn = 59,
121 DMA2_Stream4_IRQn = 60,
122 FDCAN_CAL_IRQn = 63,
123 DFSDM1_FLT4_IRQn = 64,
124 DFSDM1_FLT5_IRQn = 65,
125 DFSDM1_FLT6_IRQn = 66,
126 DFSDM1_FLT7_IRQn = 67,
127 DMA2_Stream5_IRQn = 68,
128 DMA2_Stream6_IRQn = 69,
129 DMA2_Stream7_IRQn = 70,
130 USART6_IRQn = 71,
131 I2C3_EV_IRQn = 72,
132 I2C3_ER_IRQn = 73,
133 OTG_HS_EP1_OUT_IRQn = 74,
134 OTG_HS_EP1_IN_IRQn = 75,
135 OTG_HS_WKUP_IRQn = 76,
136 OTG_HS_IRQn = 77,
137 DCMI_PSSI_IRQn = 78,
138 CRYP_IRQn = 79,
139 HASH_RNG_IRQn = 80,
140 FPU_IRQn = 81,
141 UART7_IRQn = 82,
142 UART8_IRQn = 83,
143 SPI4_IRQn = 84,
144 SPI5_IRQn = 85,
145 SPI6_IRQn = 86,
146 SAI1_IRQn = 87,
147 LTDC_IRQn = 88,
148 LTDC_ER_IRQn = 89,
149 DMA2D_IRQn = 90,
150 SAI2_IRQn = 91,
151 OCTOSPI1_IRQn = 92,
152 LPTIM1_IRQn = 93,
153 CEC_IRQn = 94,
154 I2C4_EV_IRQn = 95,
155 I2C4_ER_IRQn = 96,
156 SPDIF_RX_IRQn = 97,
157 DMAMUX1_OVR_IRQn = 102,
158 DFSDM1_FLT0_IRQn = 110,
159 DFSDM1_FLT1_IRQn = 111,
160 DFSDM1_FLT2_IRQn = 112,
161 DFSDM1_FLT3_IRQn = 113,
162 SWPMI1_IRQn = 115,
163 TIM15_IRQn = 116,
164 TIM16_IRQn = 117,
165 TIM17_IRQn = 118,
166 MDIOS_WKUP_IRQn = 119,
167 MDIOS_IRQn = 120,
168 JPEG_IRQn = 121,
169 MDMA_IRQn = 122,
170 SDMMC2_IRQn = 124,
171 HSEM1_IRQn = 125,
172 DAC2_IRQn = 127,
173 DMAMUX2_OVR_IRQn = 128,
174 BDMA2_Channel0_IRQn = 129,
175 BDMA2_Channel1_IRQn = 130,
176 BDMA2_Channel2_IRQn = 131,
177 BDMA2_Channel3_IRQn = 132,
178 BDMA2_Channel4_IRQn = 133,
179 BDMA2_Channel5_IRQn = 134,
180 BDMA2_Channel6_IRQn = 135,
181 BDMA2_Channel7_IRQn = 136,
182 COMP_IRQn = 137 ,
183 LPTIM2_IRQn = 138,
184 LPTIM3_IRQn = 139,
185 UART9_IRQn = 140,
186 USART10_IRQn = 141,
187 LPUART1_IRQn = 142,
188 WWDG_RST_IRQn = 143,
189 CRS_IRQn = 144,
190 ECC_IRQn = 145,
191 DTS_IRQn = 147,
192 WAKEUP_PIN_IRQn = 149,
193 OCTOSPI2_IRQn = 150,
194 OTFDEC1_IRQn = 151,
195 OTFDEC2_IRQn = 152,
196 GFXMMU_IRQn = 153,
197 BDMA1_IRQn = 154,
198} IRQn_Type;
199
208#define SMPS
215#define __CM7_REV 0x0100U
216#define __MPU_PRESENT 1U
217#define __NVIC_PRIO_BITS 4U
218#define __Vendor_SysTickConfig 0U
219#define __FPU_PRESENT 1U
220#define __ICACHE_PRESENT 1U
221#define __DCACHE_PRESENT 1U
222#include "core_cm7.h"
231#include "system_stm32h7xx.h"
232#include <stdint.h>
233
242typedef struct
243{
244 __IO uint32_t ISR;
245 __IO uint32_t IER;
246 __IO uint32_t CR;
247 __IO uint32_t CFGR;
248 __IO uint32_t CFGR2;
249 __IO uint32_t SMPR1;
250 __IO uint32_t SMPR2;
251 __IO uint32_t PCSEL;
252 __IO uint32_t LTR1;
253 __IO uint32_t HTR1;
254 uint32_t RESERVED1;
255 uint32_t RESERVED2;
256 __IO uint32_t SQR1;
257 __IO uint32_t SQR2;
258 __IO uint32_t SQR3;
259 __IO uint32_t SQR4;
260 __IO uint32_t DR;
261 uint32_t RESERVED3;
262 uint32_t RESERVED4;
263 __IO uint32_t JSQR;
264 uint32_t RESERVED5[4];
265 __IO uint32_t OFR1;
266 __IO uint32_t OFR2;
267 __IO uint32_t OFR3;
268 __IO uint32_t OFR4;
269 uint32_t RESERVED6[4];
270 __IO uint32_t JDR1;
271 __IO uint32_t JDR2;
272 __IO uint32_t JDR3;
273 __IO uint32_t JDR4;
274 uint32_t RESERVED7[4];
275 __IO uint32_t AWD2CR;
276 __IO uint32_t AWD3CR;
277 uint32_t RESERVED8;
278 uint32_t RESERVED9;
279 __IO uint32_t LTR2;
280 __IO uint32_t HTR2;
281 __IO uint32_t LTR3;
282 __IO uint32_t HTR3;
283 __IO uint32_t DIFSEL;
284 __IO uint32_t CALFACT;
285 __IO uint32_t CALFACT2;
286} ADC_TypeDef;
287
288
289typedef struct
290{
291__IO uint32_t CSR;
292uint32_t RESERVED;
293__IO uint32_t CCR;
294__IO uint32_t CDR;
295__IO uint32_t CDR2;
297} ADC_Common_TypeDef;
298
299
304typedef struct
305{
306 __IO uint32_t CSR;
307 __IO uint32_t CCR;
308} VREFBUF_TypeDef;
309
310
315typedef struct
316{
317 __IO uint32_t CREL;
318 __IO uint32_t ENDN;
319 __IO uint32_t RESERVED1;
320 __IO uint32_t DBTP;
321 __IO uint32_t TEST;
322 __IO uint32_t RWD;
323 __IO uint32_t CCCR;
324 __IO uint32_t NBTP;
325 __IO uint32_t TSCC;
326 __IO uint32_t TSCV;
327 __IO uint32_t TOCC;
328 __IO uint32_t TOCV;
329 __IO uint32_t RESERVED2[4];
330 __IO uint32_t ECR;
331 __IO uint32_t PSR;
332 __IO uint32_t TDCR;
333 __IO uint32_t RESERVED3;
334 __IO uint32_t IR;
335 __IO uint32_t IE;
336 __IO uint32_t ILS;
337 __IO uint32_t ILE;
338 __IO uint32_t RESERVED4[8];
339 __IO uint32_t GFC;
340 __IO uint32_t SIDFC;
341 __IO uint32_t XIDFC;
342 __IO uint32_t RESERVED5;
343 __IO uint32_t XIDAM;
344 __IO uint32_t HPMS;
345 __IO uint32_t NDAT1;
346 __IO uint32_t NDAT2;
347 __IO uint32_t RXF0C;
348 __IO uint32_t RXF0S;
349 __IO uint32_t RXF0A;
350 __IO uint32_t RXBC;
351 __IO uint32_t RXF1C;
352 __IO uint32_t RXF1S;
353 __IO uint32_t RXF1A;
354 __IO uint32_t RXESC;
355 __IO uint32_t TXBC;
356 __IO uint32_t TXFQS;
357 __IO uint32_t TXESC;
358 __IO uint32_t TXBRP;
359 __IO uint32_t TXBAR;
360 __IO uint32_t TXBCR;
361 __IO uint32_t TXBTO;
362 __IO uint32_t TXBCF;
363 __IO uint32_t TXBTIE;
364 __IO uint32_t TXBCIE;
365 __IO uint32_t RESERVED6[2];
366 __IO uint32_t TXEFC;
367 __IO uint32_t TXEFS;
368 __IO uint32_t TXEFA;
369 __IO uint32_t RESERVED7;
370} FDCAN_GlobalTypeDef;
371
376typedef struct
377{
378 __IO uint32_t TTTMC;
379 __IO uint32_t TTRMC;
380 __IO uint32_t TTOCF;
381 __IO uint32_t TTMLM;
382 __IO uint32_t TURCF;
383 __IO uint32_t TTOCN;
384 __IO uint32_t TTGTP;
385 __IO uint32_t TTTMK;
386 __IO uint32_t TTIR;
387 __IO uint32_t TTIE;
388 __IO uint32_t TTILS;
389 __IO uint32_t TTOST;
390 __IO uint32_t TURNA;
391 __IO uint32_t TTLGT;
392 __IO uint32_t TTCTC;
393 __IO uint32_t TTCPT;
394 __IO uint32_t TTCSM;
395 __IO uint32_t RESERVED1[111];
396 __IO uint32_t TTTS;
397} TTCAN_TypeDef;
398
403typedef struct
404{
405 __IO uint32_t CREL;
406 __IO uint32_t CCFG;
407 __IO uint32_t CSTAT;
408 __IO uint32_t CWD;
409 __IO uint32_t IR;
410 __IO uint32_t IE;
411} FDCAN_ClockCalibrationUnit_TypeDef;
412
413
418typedef struct
419{
420 __IO uint32_t CR;
421 __IO uint32_t CFGR;
422 __IO uint32_t TXDR;
423 __IO uint32_t RXDR;
424 __IO uint32_t ISR;
425 __IO uint32_t IER;
426}CEC_TypeDef;
427
432typedef struct
433{
434 __IO uint32_t DR;
435 __IO uint32_t IDR;
436 __IO uint32_t CR;
437 uint32_t RESERVED2;
438 __IO uint32_t INIT;
439 __IO uint32_t POL;
440} CRC_TypeDef;
441
442
446typedef struct
447{
448__IO uint32_t CR;
449__IO uint32_t CFGR;
450__IO uint32_t ISR;
451__IO uint32_t ICR;
452} CRS_TypeDef;
453
454
459typedef struct
460{
461 __IO uint32_t CR;
462 __IO uint32_t SWTRIGR;
463 __IO uint32_t DHR12R1;
464 __IO uint32_t DHR12L1;
465 __IO uint32_t DHR8R1;
466 __IO uint32_t DHR12R2;
467 __IO uint32_t DHR12L2;
468 __IO uint32_t DHR8R2;
469 __IO uint32_t DHR12RD;
470 __IO uint32_t DHR12LD;
471 __IO uint32_t DHR8RD;
472 __IO uint32_t DOR1;
473 __IO uint32_t DOR2;
474 __IO uint32_t SR;
475 __IO uint32_t CCR;
476 __IO uint32_t MCR;
477 __IO uint32_t SHSR1;
478 __IO uint32_t SHSR2;
479 __IO uint32_t SHHR;
480 __IO uint32_t SHRR;
481} DAC_TypeDef;
482
486typedef struct
487{
488 __IO uint32_t FLTCR1;
489 __IO uint32_t FLTCR2;
490 __IO uint32_t FLTISR;
491 __IO uint32_t FLTICR;
492 __IO uint32_t FLTJCHGR;
493 __IO uint32_t FLTFCR;
494 __IO uint32_t FLTJDATAR;
495 __IO uint32_t FLTRDATAR;
496 __IO uint32_t FLTAWHTR;
497 __IO uint32_t FLTAWLTR;
498 __IO uint32_t FLTAWSR;
499 __IO uint32_t FLTAWCFR;
500 __IO uint32_t FLTEXMAX;
501 __IO uint32_t FLTEXMIN;
502 __IO uint32_t FLTCNVTIMR;
503} DFSDM_Filter_TypeDef;
504
508typedef struct
509{
510 __IO uint32_t CHCFGR1;
511 __IO uint32_t CHCFGR2;
512 __IO uint32_t CHAWSCDR;
514 __IO uint32_t CHWDATAR;
515 __IO uint32_t CHDATINR;
516 __IO uint32_t CHDLYR;
517} DFSDM_Channel_TypeDef;
518
522typedef struct
523{
524 __IO uint32_t IDCODE;
525 __IO uint32_t CR;
526 uint32_t RESERVED4[11];
527 __IO uint32_t APB3FZ1;
528 uint32_t RESERVED5;
529 __IO uint32_t APB1LFZ1;
530 uint32_t RESERVED6;
531 __IO uint32_t APB1HFZ1;
532 uint32_t RESERVED7;
533 __IO uint32_t APB2FZ1;
534 uint32_t RESERVED8;
535 __IO uint32_t APB4FZ1;
536}DBGMCU_TypeDef;
541typedef struct
542{
543 __IO uint32_t CR;
544 __IO uint32_t SR;
545 __IO uint32_t RISR;
546 __IO uint32_t IER;
547 __IO uint32_t MISR;
548 __IO uint32_t ICR;
549 __IO uint32_t ESCR;
550 __IO uint32_t ESUR;
551 __IO uint32_t CWSTRTR;
552 __IO uint32_t CWSIZER;
553 __IO uint32_t DR;
554} DCMI_TypeDef;
555
560typedef struct
561{
562 __IO uint32_t CR;
563 __IO uint32_t SR;
564 __IO uint32_t RIS;
565 __IO uint32_t IER;
566 __IO uint32_t MIS;
567 __IO uint32_t ICR;
568 __IO uint32_t RESERVED1[4];
569 __IO uint32_t DR;
570 __IO uint32_t RESERVED2[241];
571 __IO uint32_t HWCFGR;
572 __IO uint32_t VERR;
573 __IO uint32_t IPIDR;
574 __IO uint32_t SIDR;
575} PSSI_TypeDef;
576
581typedef struct
582{
583 __IO uint32_t CR;
584 __IO uint32_t NDTR;
585 __IO uint32_t PAR;
586 __IO uint32_t M0AR;
587 __IO uint32_t M1AR;
588 __IO uint32_t FCR;
589} DMA_Stream_TypeDef;
590
591typedef struct
592{
593 __IO uint32_t LISR;
594 __IO uint32_t HISR;
595 __IO uint32_t LIFCR;
596 __IO uint32_t HIFCR;
597} DMA_TypeDef;
598
599typedef struct
600{
601 __IO uint32_t CCR;
602 __IO uint32_t CNDTR;
603 __IO uint32_t CPAR;
604 __IO uint32_t CM0AR;
605 __IO uint32_t CM1AR;
606} BDMA_Channel_TypeDef;
607
608typedef struct
609{
610 __IO uint32_t ISR;
611 __IO uint32_t IFCR;
612} BDMA_TypeDef;
613
614typedef struct
615{
616 __IO uint32_t CCR;
617}DMAMUX_Channel_TypeDef;
618
619typedef struct
620{
621 __IO uint32_t CSR;
622 __IO uint32_t CFR;
623}DMAMUX_ChannelStatus_TypeDef;
624
625typedef struct
626{
627 __IO uint32_t RGCR;
628}DMAMUX_RequestGen_TypeDef;
629
630typedef struct
631{
632 __IO uint32_t RGSR;
633 __IO uint32_t RGCFR;
634}DMAMUX_RequestGenStatus_TypeDef;
635
639typedef struct
640{
641 __IO uint32_t GISR0;
642}MDMA_TypeDef;
643
644typedef struct
645{
646 __IO uint32_t CISR;
647 __IO uint32_t CIFCR;
648 __IO uint32_t CESR;
649 __IO uint32_t CCR;
650 __IO uint32_t CTCR;
651 __IO uint32_t CBNDTR;
652 __IO uint32_t CSAR;
653 __IO uint32_t CDAR;
654 __IO uint32_t CBRUR;
655 __IO uint32_t CLAR;
656 __IO uint32_t CTBR;
657 uint32_t RESERVED0;
658 __IO uint32_t CMAR;
659 __IO uint32_t CMDR;
660}MDMA_Channel_TypeDef;
661
666typedef struct
667{
668 __IO uint32_t CR;
669 __IO uint32_t ISR;
670 __IO uint32_t IFCR;
671 __IO uint32_t FGMAR;
672 __IO uint32_t FGOR;
673 __IO uint32_t BGMAR;
674 __IO uint32_t BGOR;
675 __IO uint32_t FGPFCCR;
676 __IO uint32_t FGCOLR;
677 __IO uint32_t BGPFCCR;
678 __IO uint32_t BGCOLR;
679 __IO uint32_t FGCMAR;
680 __IO uint32_t BGCMAR;
681 __IO uint32_t OPFCCR;
682 __IO uint32_t OCOLR;
683 __IO uint32_t OMAR;
684 __IO uint32_t OOR;
685 __IO uint32_t NLR;
686 __IO uint32_t LWR;
687 __IO uint32_t AMTCR;
688 uint32_t RESERVED[236];
689 __IO uint32_t FGCLUT[256];
690 __IO uint32_t BGCLUT[256];
691} DMA2D_TypeDef;
692
693
698typedef struct
699{
700__IO uint32_t RTSR1;
701__IO uint32_t FTSR1;
702__IO uint32_t SWIER1;
703__IO uint32_t D3PMR1;
704__IO uint32_t D3PCR1L;
705__IO uint32_t D3PCR1H;
706uint32_t RESERVED1[2];
707__IO uint32_t RTSR2;
708__IO uint32_t FTSR2;
709__IO uint32_t SWIER2;
710__IO uint32_t D3PMR2;
711__IO uint32_t D3PCR2L;
712__IO uint32_t D3PCR2H;
713uint32_t RESERVED2[2];
714__IO uint32_t RTSR3;
715__IO uint32_t FTSR3;
716__IO uint32_t SWIER3;
717__IO uint32_t D3PMR3;
718__IO uint32_t D3PCR3L;
719__IO uint32_t D3PCR3H;
720uint32_t RESERVED3[10];
721__IO uint32_t IMR1;
722__IO uint32_t EMR1;
723__IO uint32_t PR1;
724uint32_t RESERVED4;
725__IO uint32_t IMR2;
726__IO uint32_t EMR2;
727__IO uint32_t PR2;
728uint32_t RESERVED5;
729__IO uint32_t IMR3;
730__IO uint32_t EMR3;
731__IO uint32_t PR3;
732}EXTI_TypeDef;
733
743typedef struct
744{
745__IO uint32_t IMR1;
746__IO uint32_t EMR1;
747__IO uint32_t PR1;
748uint32_t RESERVED1;
749__IO uint32_t IMR2;
750__IO uint32_t EMR2;
751__IO uint32_t PR2;
752uint32_t RESERVED2;
753__IO uint32_t IMR3;
754__IO uint32_t EMR3;
755__IO uint32_t PR3;
756}EXTI_Core_TypeDef;
757
758
763typedef struct
764{
765 __IO uint32_t ACR;
766 __IO uint32_t KEYR1;
767 __IO uint32_t OPTKEYR;
768 __IO uint32_t CR1;
769 __IO uint32_t SR1;
770 __IO uint32_t CCR1;
771 __IO uint32_t OPTCR;
772 __IO uint32_t OPTSR_CUR;
773 __IO uint32_t OPTSR_PRG;
774 __IO uint32_t OPTCCR;
775 __IO uint32_t PRAR_CUR1;
776 __IO uint32_t PRAR_PRG1;
777 __IO uint32_t SCAR_CUR1;
778 __IO uint32_t SCAR_PRG1;
779 __IO uint32_t WPSN_CUR1;
780 __IO uint32_t WPSN_PRG1;
781 __IO uint32_t BOOT_CUR;
782 __IO uint32_t BOOT_PRG;
783 uint32_t RESERVED0[2];
784 __IO uint32_t CRCCR1;
785 __IO uint32_t CRCSADD1;
786 __IO uint32_t CRCEADD1;
787 __IO uint32_t CRCDATA;
788 __IO uint32_t ECC_FA1;
789 uint32_t RESERVED;
790 __IO uint32_t OTPBL_CUR;
791 __IO uint32_t OTPBL_PRG;
792 uint32_t RESERVED1[37];
793 __IO uint32_t KEYR2;
794 uint32_t RESERVED2;
795 __IO uint32_t CR2;
796 __IO uint32_t SR2;
797 __IO uint32_t CCR2;
798 uint32_t RESERVED3[4];
799 __IO uint32_t PRAR_CUR2;
800 __IO uint32_t PRAR_PRG2;
801 __IO uint32_t SCAR_CUR2;
802 __IO uint32_t SCAR_PRG2;
803 __IO uint32_t WPSN_CUR2;
804 __IO uint32_t WPSN_PRG2;
805 uint32_t RESERVED4[4];
806 __IO uint32_t CRCCR2;
807 __IO uint32_t CRCSADD2;
808 __IO uint32_t CRCEADD2;
809 __IO uint32_t CRCDATA2;
810 __IO uint32_t ECC_FA2;
811} FLASH_TypeDef;
812
817typedef struct
818{
819 __IO uint32_t BTCR[8];
820} FMC_Bank1_TypeDef;
821
826typedef struct
827{
828 __IO uint32_t BWTR[7];
829} FMC_Bank1E_TypeDef;
830
835typedef struct
836{
837 __IO uint32_t PCR2;
838 __IO uint32_t SR2;
839 __IO uint32_t PMEM2;
840 __IO uint32_t PATT2;
841 uint32_t RESERVED0;
842 __IO uint32_t ECCR2;
843} FMC_Bank2_TypeDef;
844
849typedef struct
850{
851 __IO uint32_t PCR;
852 __IO uint32_t SR;
853 __IO uint32_t PMEM;
854 __IO uint32_t PATT;
855 uint32_t RESERVED;
856 __IO uint32_t ECCR;
857} FMC_Bank3_TypeDef;
858
864typedef struct
865{
866 __IO uint32_t SDCR[2];
867 __IO uint32_t SDTR[2];
868 __IO uint32_t SDCMR;
869 __IO uint32_t SDRTR;
870 __IO uint32_t SDSR;
871} FMC_Bank5_6_TypeDef;
872
877typedef struct
878{
879 __IO uint32_t CR;
880 __IO uint32_t SR;
881 __IO uint32_t FCR;
882 __IO uint32_t CCR;
883 __IO uint32_t DVR;
884 uint32_t RESERVED1[3];
885 __IO uint32_t B0CR;
886 __IO uint32_t B1CR;
887 __IO uint32_t B2CR;
888 __IO uint32_t B3CR;
889 uint32_t RESERVED2[1012];
890 __IO uint32_t LUT[2048];
892} GFXMMU_TypeDef;
897typedef struct
898{
899 __IO uint32_t MODER;
900 __IO uint32_t OTYPER;
901 __IO uint32_t OSPEEDR;
902 __IO uint32_t PUPDR;
903 __IO uint32_t IDR;
904 __IO uint32_t ODR;
905 __IO uint32_t BSRR;
906 __IO uint32_t LCKR;
907 __IO uint32_t AFR[2];
908} GPIO_TypeDef;
909
914typedef struct
915{
916 __IO uint32_t CSR;
917 __IO uint32_t OTR;
918 __IO uint32_t HSOTR;
919} OPAMP_TypeDef;
920
925typedef struct
926{
927 uint32_t RESERVED1;
928 __IO uint32_t PMCR;
929 __IO uint32_t EXTICR[4];
930 __IO uint32_t CFGR;
931 uint32_t RESERVED2;
932 __IO uint32_t CCCSR;
933 __IO uint32_t CCVR;
934 __IO uint32_t CCCR;
936} SYSCFG_TypeDef;
937
942typedef struct
943{
944 __IO uint32_t CR1;
945 __IO uint32_t CR2;
946 __IO uint32_t OAR1;
947 __IO uint32_t OAR2;
948 __IO uint32_t TIMINGR;
949 __IO uint32_t TIMEOUTR;
950 __IO uint32_t ISR;
951 __IO uint32_t ICR;
952 __IO uint32_t PECR;
953 __IO uint32_t RXDR;
954 __IO uint32_t TXDR;
955} I2C_TypeDef;
956
961typedef struct
962{
963 __IO uint32_t KR;
964 __IO uint32_t PR;
965 __IO uint32_t RLR;
966 __IO uint32_t SR;
967 __IO uint32_t WINR;
968} IWDG_TypeDef;
969
970
974typedef struct
975{
976 __IO uint32_t CONFR0;
977 __IO uint32_t CONFR1;
978 __IO uint32_t CONFR2;
979 __IO uint32_t CONFR3;
980 __IO uint32_t CONFR4;
981 __IO uint32_t CONFR5;
982 __IO uint32_t CONFR6;
983 __IO uint32_t CONFR7;
984 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
985 __IO uint32_t CR;
986 __IO uint32_t SR;
987 __IO uint32_t CFR;
988 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
989 __IO uint32_t DIR;
990 __IO uint32_t DOR;
991 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
992 __IO uint32_t QMEM0[16];
993 __IO uint32_t QMEM1[16];
994 __IO uint32_t QMEM2[16];
995 __IO uint32_t QMEM3[16];
996 __IO uint32_t HUFFMIN[16];
997 __IO uint32_t HUFFBASE[32];
998 __IO uint32_t HUFFSYMB[84];
999 __IO uint32_t DHTMEM[103];
1000 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1001 __IO uint32_t HUFFENC_AC0[88];
1002 __IO uint32_t HUFFENC_AC1[88];
1003 __IO uint32_t HUFFENC_DC0[8];
1004 __IO uint32_t HUFFENC_DC1[8];
1006} JPEG_TypeDef;
1007
1012typedef struct
1013{
1014 uint32_t RESERVED0[2];
1015 __IO uint32_t SSCR;
1016 __IO uint32_t BPCR;
1017 __IO uint32_t AWCR;
1018 __IO uint32_t TWCR;
1019 __IO uint32_t GCR;
1020 uint32_t RESERVED1[2];
1021 __IO uint32_t SRCR;
1022 uint32_t RESERVED2[1];
1023 __IO uint32_t BCCR;
1024 uint32_t RESERVED3[1];
1025 __IO uint32_t IER;
1026 __IO uint32_t ISR;
1027 __IO uint32_t ICR;
1028 __IO uint32_t LIPCR;
1029 __IO uint32_t CPSR;
1030 __IO uint32_t CDSR;
1031} LTDC_TypeDef;
1032
1037typedef struct
1038{
1039 __IO uint32_t CR;
1040 __IO uint32_t WHPCR;
1041 __IO uint32_t WVPCR;
1042 __IO uint32_t CKCR;
1043 __IO uint32_t PFCR;
1044 __IO uint32_t CACR;
1045 __IO uint32_t DCCR;
1046 __IO uint32_t BFCR;
1047 uint32_t RESERVED0[2];
1048 __IO uint32_t CFBAR;
1049 __IO uint32_t CFBLR;
1050 __IO uint32_t CFBLNR;
1051 uint32_t RESERVED1[3];
1052 __IO uint32_t CLUTWR;
1054} LTDC_Layer_TypeDef;
1055
1060typedef struct
1061{
1062 __IO uint32_t CR1;
1063 __IO uint32_t CSR1;
1064 __IO uint32_t CR2;
1065 __IO uint32_t CR3;
1066 __IO uint32_t CPUCR;
1067 uint32_t RESERVED0;
1068 __IO uint32_t SRDCR;
1069 uint32_t RESERVED1;
1070 __IO uint32_t WKUPCR;
1071 __IO uint32_t WKUPFR;
1072 __IO uint32_t WKUPEPR;
1073} PWR_TypeDef;
1074
1079typedef struct
1080{
1081 __IO uint32_t CR;
1082 __IO uint32_t HSICFGR;
1083 __IO uint32_t CRRCR;
1084 __IO uint32_t CSICFGR;
1085 __IO uint32_t CFGR;
1086 uint32_t RESERVED1;
1087 __IO uint32_t CDCFGR1;
1088 __IO uint32_t CDCFGR2;
1089 __IO uint32_t SRDCFGR;
1090 uint32_t RESERVED2;
1091 __IO uint32_t PLLCKSELR;
1092 __IO uint32_t PLLCFGR;
1093 __IO uint32_t PLL1DIVR;
1094 __IO uint32_t PLL1FRACR;
1095 __IO uint32_t PLL2DIVR;
1096 __IO uint32_t PLL2FRACR;
1097 __IO uint32_t PLL3DIVR;
1098 __IO uint32_t PLL3FRACR;
1099 uint32_t RESERVED3;
1100 __IO uint32_t CDCCIPR;
1101 __IO uint32_t CDCCIP1R;
1102 __IO uint32_t CDCCIP2R;
1103 __IO uint32_t SRDCCIPR;
1104 uint32_t RESERVED4;
1105 __IO uint32_t CIER;
1106 __IO uint32_t CIFR;
1107 __IO uint32_t CICR;
1108 uint32_t RESERVED5;
1109 __IO uint32_t BDCR;
1110 __IO uint32_t CSR;
1111 uint32_t RESERVED6;
1112 __IO uint32_t AHB3RSTR;
1113 __IO uint32_t AHB1RSTR;
1114 __IO uint32_t AHB2RSTR;
1115 __IO uint32_t AHB4RSTR;
1116 __IO uint32_t APB3RSTR;
1117 __IO uint32_t APB1LRSTR;
1118 __IO uint32_t APB1HRSTR;
1119 __IO uint32_t APB2RSTR;
1120 __IO uint32_t APB4RSTR;
1121 uint32_t RESERVED7;
1122 uint32_t RESERVED8;
1123 __IO uint32_t SRDAMR;
1124 uint32_t RESERVED9;
1125 __IO uint32_t CKGAENR;
1126 uint32_t RESERVED10[31];
1127 __IO uint32_t RSR;
1128 __IO uint32_t AHB3ENR;
1129 __IO uint32_t AHB1ENR;
1130 __IO uint32_t AHB2ENR;
1131 __IO uint32_t AHB4ENR;
1132 __IO uint32_t APB3ENR;
1133 __IO uint32_t APB1LENR;
1134 __IO uint32_t APB1HENR;
1135 __IO uint32_t APB2ENR;
1136 __IO uint32_t APB4ENR;
1137 uint32_t RESERVED12;
1138 __IO uint32_t AHB3LPENR;
1139 __IO uint32_t AHB1LPENR;
1140 __IO uint32_t AHB2LPENR;
1141 __IO uint32_t AHB4LPENR;
1142 __IO uint32_t APB3LPENR;
1143 __IO uint32_t APB1LLPENR;
1144 __IO uint32_t APB1HLPENR;
1145 __IO uint32_t APB2LPENR;
1146 __IO uint32_t APB4LPENR;
1147 uint32_t RESERVED13[4];
1149} RCC_TypeDef;
1150
1151
1155typedef struct
1156{
1157 __IO uint32_t TR;
1158 __IO uint32_t DR;
1159 __IO uint32_t SSR;
1160 __IO uint32_t ICSR;
1161 __IO uint32_t PRER;
1162 __IO uint32_t WUTR;
1163 __IO uint32_t CR;
1164 uint32_t RESERVED0;
1165 uint32_t RESERVED1;
1166 __IO uint32_t WPR;
1167 __IO uint32_t CALR;
1168 __IO uint32_t SHIFTR;
1169 __IO uint32_t TSTR;
1170 __IO uint32_t TSDR;
1171 __IO uint32_t TSSSR;
1172 uint32_t RESERVED2;
1173 __IO uint32_t ALRMAR;
1174 __IO uint32_t ALRMASSR;
1175 __IO uint32_t ALRMBR;
1176 __IO uint32_t ALRMBSSR;
1177 __IO uint32_t SR;
1178 __IO uint32_t MISR;
1179 uint32_t RESERVED3;
1180 __IO uint32_t SCR;
1181 __IO uint32_t CFGR;
1182} RTC_TypeDef;
1183
1187typedef struct
1188{
1189 __IO uint32_t CR1;
1190 __IO uint32_t CR2;
1191 uint32_t RESERVED0;
1192 __IO uint32_t FLTCR;
1193 __IO uint32_t ATCR1;
1194 __IO uint32_t ATSEEDR;
1195 __IO uint32_t ATOR;
1196 uint32_t RESERVED1[4];
1197 __IO uint32_t IER;
1198 __IO uint32_t SR;
1199 __IO uint32_t MISR;
1200 uint32_t RESERVED2;
1201 __IO uint32_t SCR;
1202 __IO uint32_t COUNTR;
1203 uint32_t RESERVED3[3];
1204 __IO uint32_t CFGR;
1205 uint32_t RESERVED4[43];
1206 __IO uint32_t BKP0R;
1207 __IO uint32_t BKP1R;
1208 __IO uint32_t BKP2R;
1209 __IO uint32_t BKP3R;
1210 __IO uint32_t BKP4R;
1211 __IO uint32_t BKP5R;
1212 __IO uint32_t BKP6R;
1213 __IO uint32_t BKP7R;
1214 __IO uint32_t BKP8R;
1215 __IO uint32_t BKP9R;
1216 __IO uint32_t BKP10R;
1217 __IO uint32_t BKP11R;
1218 __IO uint32_t BKP12R;
1219 __IO uint32_t BKP13R;
1220 __IO uint32_t BKP14R;
1221 __IO uint32_t BKP15R;
1222 __IO uint32_t BKP16R;
1223 __IO uint32_t BKP17R;
1224 __IO uint32_t BKP18R;
1225 __IO uint32_t BKP19R;
1226 __IO uint32_t BKP20R;
1227 __IO uint32_t BKP21R;
1228 __IO uint32_t BKP22R;
1229 __IO uint32_t BKP23R;
1230 __IO uint32_t BKP24R;
1231 __IO uint32_t BKP25R;
1232 __IO uint32_t BKP26R;
1233 __IO uint32_t BKP27R;
1234 __IO uint32_t BKP28R;
1235 __IO uint32_t BKP29R;
1236 __IO uint32_t BKP30R;
1237 __IO uint32_t BKP31R;
1238} TAMP_TypeDef;
1239
1244typedef struct
1245{
1246 __IO uint32_t GCR;
1247 uint32_t RESERVED0[16];
1248 __IO uint32_t PDMCR;
1249 __IO uint32_t PDMDLY;
1250} SAI_TypeDef;
1251
1252typedef struct
1253{
1254 __IO uint32_t CR1;
1255 __IO uint32_t CR2;
1256 __IO uint32_t FRCR;
1257 __IO uint32_t SLOTR;
1258 __IO uint32_t IMR;
1259 __IO uint32_t SR;
1260 __IO uint32_t CLRFR;
1261 __IO uint32_t DR;
1262} SAI_Block_TypeDef;
1263
1268typedef struct
1269{
1270 __IO uint32_t CR;
1271 __IO uint32_t IMR;
1272 __IO uint32_t SR;
1273 __IO uint32_t IFCR;
1274 __IO uint32_t DR;
1275 __IO uint32_t CSR;
1276 __IO uint32_t DIR;
1277 uint32_t RESERVED2;
1278} SPDIFRX_TypeDef;
1279
1280
1285typedef struct
1286{
1287 __IO uint32_t POWER;
1288 __IO uint32_t CLKCR;
1289 __IO uint32_t ARG;
1290 __IO uint32_t CMD;
1291 __I uint32_t RESPCMD;
1292 __I uint32_t RESP1;
1293 __I uint32_t RESP2;
1294 __I uint32_t RESP3;
1295 __I uint32_t RESP4;
1296 __IO uint32_t DTIMER;
1297 __IO uint32_t DLEN;
1298 __IO uint32_t DCTRL;
1299 __I uint32_t DCOUNT;
1300 __I uint32_t STA;
1301 __IO uint32_t ICR;
1302 __IO uint32_t MASK;
1303 __IO uint32_t ACKTIME;
1304 uint32_t RESERVED0[3];
1305 __IO uint32_t IDMACTRL;
1306 __IO uint32_t IDMABSIZE;
1307 __IO uint32_t IDMABASE0;
1308 __IO uint32_t IDMABASE1;
1309 uint32_t RESERVED1[8];
1310 __IO uint32_t FIFO;
1311 uint32_t RESERVED2[222];
1312 __IO uint32_t IPVR;
1313} SDMMC_TypeDef;
1314
1315
1320typedef struct
1321{
1322 __IO uint32_t CR;
1323 __IO uint32_t CFGR;
1324} DLYB_TypeDef;
1325
1330typedef struct
1331{
1332 __IO uint32_t R[32];
1333 __IO uint32_t RLR[32];
1334 __IO uint32_t C1IER;
1335 __IO uint32_t C1ICR;
1336 __IO uint32_t C1ISR;
1337 __IO uint32_t C1MISR;
1338 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1339 __IO uint32_t CR;
1340 __IO uint32_t KEYR;
1342} HSEM_TypeDef;
1343
1344typedef struct
1345{
1346 __IO uint32_t IER;
1347 __IO uint32_t ICR;
1348 __IO uint32_t ISR;
1349 __IO uint32_t MISR;
1350} HSEM_Common_TypeDef;
1351
1356typedef struct
1357{
1358 __IO uint32_t CR1;
1359 __IO uint32_t CR2;
1360 __IO uint32_t CFG1;
1361 __IO uint32_t CFG2;
1362 __IO uint32_t IER;
1363 __IO uint32_t SR;
1364 __IO uint32_t IFCR;
1365 uint32_t RESERVED0;
1366 __IO uint32_t TXDR;
1367 uint32_t RESERVED1[3];
1368 __IO uint32_t RXDR;
1369 uint32_t RESERVED2[3];
1370 __IO uint32_t CRCPOLY;
1371 __IO uint32_t TXCRC;
1372 __IO uint32_t RXCRC;
1373 __IO uint32_t UDRDR;
1374 __IO uint32_t I2SCFGR;
1376} SPI_TypeDef;
1377
1381typedef struct
1382{
1383 __IO uint32_t CFGR1;
1384 uint32_t RESERVED0;
1385 __IO uint32_t T0VALR1;
1386 uint32_t RESERVED1;
1387 __IO uint32_t RAMPVALR;
1388 __IO uint32_t ITR1;
1389 uint32_t RESERVED2;
1390 __IO uint32_t DR;
1391 __IO uint32_t SR;
1392 __IO uint32_t ITENR;
1393 __IO uint32_t ICIFR;
1394 __IO uint32_t OR;
1395}
1396DTS_TypeDef;
1397
1402typedef struct
1403{
1404 __IO uint32_t CR1;
1405 __IO uint32_t CR2;
1406 __IO uint32_t SMCR;
1407 __IO uint32_t DIER;
1408 __IO uint32_t SR;
1409 __IO uint32_t EGR;
1410 __IO uint32_t CCMR1;
1411 __IO uint32_t CCMR2;
1412 __IO uint32_t CCER;
1413 __IO uint32_t CNT;
1414 __IO uint32_t PSC;
1415 __IO uint32_t ARR;
1416 __IO uint32_t RCR;
1417 __IO uint32_t CCR1;
1418 __IO uint32_t CCR2;
1419 __IO uint32_t CCR3;
1420 __IO uint32_t CCR4;
1421 __IO uint32_t BDTR;
1422 __IO uint32_t DCR;
1423 __IO uint32_t DMAR;
1424 uint32_t RESERVED1;
1425 __IO uint32_t CCMR3;
1426 __IO uint32_t CCR5;
1427 __IO uint32_t CCR6;
1428 __IO uint32_t AF1;
1429 __IO uint32_t AF2;
1430 __IO uint32_t TISEL;
1431} TIM_TypeDef;
1432
1436typedef struct
1437{
1438 __IO uint32_t ISR;
1439 __IO uint32_t ICR;
1440 __IO uint32_t IER;
1441 __IO uint32_t CFGR;
1442 __IO uint32_t CR;
1443 __IO uint32_t CMP;
1444 __IO uint32_t ARR;
1445 __IO uint32_t CNT;
1446 uint32_t RESERVED1;
1447 __IO uint32_t CFGR2;
1448} LPTIM_TypeDef;
1449
1453typedef struct
1454{
1455 __IO uint32_t SR;
1456 __IO uint32_t ICFR;
1457 __IO uint32_t OR;
1458} COMPOPT_TypeDef;
1459
1460typedef struct
1461{
1462 __IO uint32_t CFGR;
1463} COMP_TypeDef;
1464
1465typedef struct
1466{
1467 __IO uint32_t CFGR;
1468} COMP_Common_TypeDef;
1473typedef struct
1474{
1475 __IO uint32_t CR1;
1476 __IO uint32_t CR2;
1477 __IO uint32_t CR3;
1478 __IO uint32_t BRR;
1479 __IO uint32_t GTPR;
1480 __IO uint32_t RTOR;
1481 __IO uint32_t RQR;
1482 __IO uint32_t ISR;
1483 __IO uint32_t ICR;
1484 __IO uint32_t RDR;
1485 __IO uint32_t TDR;
1486 __IO uint32_t PRESC;
1487} USART_TypeDef;
1488
1492typedef struct
1493{
1494 __IO uint32_t CR;
1495 __IO uint32_t BRR;
1496 uint32_t RESERVED1;
1497 __IO uint32_t ISR;
1498 __IO uint32_t ICR;
1499 __IO uint32_t IER;
1500 __IO uint32_t RFL;
1501 __IO uint32_t TDR;
1502 __IO uint32_t RDR;
1503 __IO uint32_t OR;
1504} SWPMI_TypeDef;
1505
1510typedef struct
1511{
1512 __IO uint32_t CR;
1513 __IO uint32_t CFR;
1514 __IO uint32_t SR;
1515} WWDG_TypeDef;
1516
1517
1521typedef struct
1522{
1523 __IO uint32_t CR;
1524 __IO uint32_t SR;
1525 __IO uint32_t FAR;
1526 __IO uint32_t FDRL;
1527 __IO uint32_t FDRH;
1528 __IO uint32_t FECR;
1529} RAMECC_MonitorTypeDef;
1530
1531typedef struct
1532{
1533 __IO uint32_t IER;
1534} RAMECC_TypeDef;
1544typedef struct
1545{
1546 __IO uint32_t CR;
1547 __IO uint32_t SR;
1548 __IO uint32_t DIN;
1549 __IO uint32_t DOUT;
1550 __IO uint32_t DMACR;
1551 __IO uint32_t IMSCR;
1552 __IO uint32_t RISR;
1553 __IO uint32_t MISR;
1554 __IO uint32_t K0LR;
1555 __IO uint32_t K0RR;
1556 __IO uint32_t K1LR;
1557 __IO uint32_t K1RR;
1558 __IO uint32_t K2LR;
1559 __IO uint32_t K2RR;
1560 __IO uint32_t K3LR;
1561 __IO uint32_t K3RR;
1562 __IO uint32_t IV0LR;
1563 __IO uint32_t IV0RR;
1564 __IO uint32_t IV1LR;
1565 __IO uint32_t IV1RR;
1566 __IO uint32_t CSGCMCCM0R;
1567 __IO uint32_t CSGCMCCM1R;
1568 __IO uint32_t CSGCMCCM2R;
1569 __IO uint32_t CSGCMCCM3R;
1570 __IO uint32_t CSGCMCCM4R;
1571 __IO uint32_t CSGCMCCM5R;
1572 __IO uint32_t CSGCMCCM6R;
1573 __IO uint32_t CSGCMCCM7R;
1574 __IO uint32_t CSGCM0R;
1575 __IO uint32_t CSGCM1R;
1576 __IO uint32_t CSGCM2R;
1577 __IO uint32_t CSGCM3R;
1578 __IO uint32_t CSGCM4R;
1579 __IO uint32_t CSGCM5R;
1580 __IO uint32_t CSGCM6R;
1581 __IO uint32_t CSGCM7R;
1582} CRYP_TypeDef;
1583
1588typedef struct
1589{
1590 __IO uint32_t CR;
1591 __IO uint32_t DIN;
1592 __IO uint32_t STR;
1593 __IO uint32_t HR[5];
1594 __IO uint32_t IMR;
1595 __IO uint32_t SR;
1596 uint32_t RESERVED[52];
1597 __IO uint32_t CSR[54];
1598} HASH_TypeDef;
1599
1604typedef struct
1605{
1606 __IO uint32_t HR[8];
1607} HASH_DIGEST_TypeDef;
1608
1609
1614typedef struct
1615{
1616 __IO uint32_t CR;
1617 __IO uint32_t SR;
1618 __IO uint32_t DR;
1619 uint32_t RESERVED;
1620 __IO uint32_t HTCR;
1621} RNG_TypeDef;
1622
1627typedef struct
1628{
1629 __IO uint32_t CR;
1630 __IO uint32_t WRFR;
1631 __IO uint32_t CWRFR;
1632 __IO uint32_t RDFR;
1633 __IO uint32_t CRDFR;
1634 __IO uint32_t SR;
1635 __IO uint32_t CLRFR;
1636 uint32_t RESERVED[57];
1637 __IO uint32_t DINR0;
1638 __IO uint32_t DINR1;
1639 __IO uint32_t DINR2;
1640 __IO uint32_t DINR3;
1641 __IO uint32_t DINR4;
1642 __IO uint32_t DINR5;
1643 __IO uint32_t DINR6;
1644 __IO uint32_t DINR7;
1645 __IO uint32_t DINR8;
1646 __IO uint32_t DINR9;
1647 __IO uint32_t DINR10;
1648 __IO uint32_t DINR11;
1649 __IO uint32_t DINR12;
1650 __IO uint32_t DINR13;
1651 __IO uint32_t DINR14;
1652 __IO uint32_t DINR15;
1653 __IO uint32_t DINR16;
1654 __IO uint32_t DINR17;
1655 __IO uint32_t DINR18;
1656 __IO uint32_t DINR19;
1657 __IO uint32_t DINR20;
1658 __IO uint32_t DINR21;
1659 __IO uint32_t DINR22;
1660 __IO uint32_t DINR23;
1661 __IO uint32_t DINR24;
1662 __IO uint32_t DINR25;
1663 __IO uint32_t DINR26;
1664 __IO uint32_t DINR27;
1665 __IO uint32_t DINR28;
1666 __IO uint32_t DINR29;
1667 __IO uint32_t DINR30;
1668 __IO uint32_t DINR31;
1669 __IO uint32_t DOUTR0;
1670 __IO uint32_t DOUTR1;
1671 __IO uint32_t DOUTR2;
1672 __IO uint32_t DOUTR3;
1673 __IO uint32_t DOUTR4;
1674 __IO uint32_t DOUTR5;
1675 __IO uint32_t DOUTR6;
1676 __IO uint32_t DOUTR7;
1677 __IO uint32_t DOUTR8;
1678 __IO uint32_t DOUTR9;
1679 __IO uint32_t DOUTR10;
1680 __IO uint32_t DOUTR11;
1681 __IO uint32_t DOUTR12;
1682 __IO uint32_t DOUTR13;
1683 __IO uint32_t DOUTR14;
1684 __IO uint32_t DOUTR15;
1685 __IO uint32_t DOUTR16;
1686 __IO uint32_t DOUTR17;
1687 __IO uint32_t DOUTR18;
1688 __IO uint32_t DOUTR19;
1689 __IO uint32_t DOUTR20;
1690 __IO uint32_t DOUTR21;
1691 __IO uint32_t DOUTR22;
1692 __IO uint32_t DOUTR23;
1693 __IO uint32_t DOUTR24;
1694 __IO uint32_t DOUTR25;
1695 __IO uint32_t DOUTR26;
1696 __IO uint32_t DOUTR27;
1697 __IO uint32_t DOUTR28;
1698 __IO uint32_t DOUTR29;
1699 __IO uint32_t DOUTR30;
1700 __IO uint32_t DOUTR31;
1701} MDIOS_TypeDef;
1702
1703
1707typedef struct
1708{
1709 __IO uint32_t GOTGCTL;
1710 __IO uint32_t GOTGINT;
1711 __IO uint32_t GAHBCFG;
1712 __IO uint32_t GUSBCFG;
1713 __IO uint32_t GRSTCTL;
1714 __IO uint32_t GINTSTS;
1715 __IO uint32_t GINTMSK;
1716 __IO uint32_t GRXSTSR;
1717 __IO uint32_t GRXSTSP;
1718 __IO uint32_t GRXFSIZ;
1719 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1720 __IO uint32_t HNPTXSTS;
1721 uint32_t Reserved30[2];
1722 __IO uint32_t GCCFG;
1723 __IO uint32_t CID;
1724 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1725 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1726 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1727 __IO uint32_t GHWCFG3;
1728 uint32_t Reserved6;
1729 __IO uint32_t GLPMCFG;
1730 __IO uint32_t GPWRDN;
1731 __IO uint32_t GDFIFOCFG;
1732 __IO uint32_t GADPCTL;
1733 uint32_t Reserved43[39];
1734 __IO uint32_t HPTXFSIZ;
1735 __IO uint32_t DIEPTXF[0x0F];
1736} USB_OTG_GlobalTypeDef;
1737
1738
1742typedef struct
1743{
1744 __IO uint32_t DCFG;
1745 __IO uint32_t DCTL;
1746 __IO uint32_t DSTS;
1747 uint32_t Reserved0C;
1748 __IO uint32_t DIEPMSK;
1749 __IO uint32_t DOEPMSK;
1750 __IO uint32_t DAINT;
1751 __IO uint32_t DAINTMSK;
1752 uint32_t Reserved20;
1753 uint32_t Reserved9;
1754 __IO uint32_t DVBUSDIS;
1755 __IO uint32_t DVBUSPULSE;
1756 __IO uint32_t DTHRCTL;
1757 __IO uint32_t DIEPEMPMSK;
1758 __IO uint32_t DEACHINT;
1759 __IO uint32_t DEACHMSK;
1760 uint32_t Reserved40;
1761 __IO uint32_t DINEP1MSK;
1762 uint32_t Reserved44[15];
1763 __IO uint32_t DOUTEP1MSK;
1764} USB_OTG_DeviceTypeDef;
1765
1766
1770typedef struct
1771{
1772 __IO uint32_t DIEPCTL;
1773 uint32_t Reserved04;
1774 __IO uint32_t DIEPINT;
1775 uint32_t Reserved0C;
1776 __IO uint32_t DIEPTSIZ;
1777 __IO uint32_t DIEPDMA;
1778 __IO uint32_t DTXFSTS;
1779 uint32_t Reserved18;
1780} USB_OTG_INEndpointTypeDef;
1781
1782
1786typedef struct
1787{
1788 __IO uint32_t DOEPCTL;
1789 uint32_t Reserved04;
1790 __IO uint32_t DOEPINT;
1791 uint32_t Reserved0C;
1792 __IO uint32_t DOEPTSIZ;
1793 __IO uint32_t DOEPDMA;
1794 uint32_t Reserved18[2];
1795} USB_OTG_OUTEndpointTypeDef;
1796
1797
1801typedef struct
1802{
1803 __IO uint32_t HCFG;
1804 __IO uint32_t HFIR;
1805 __IO uint32_t HFNUM;
1806 uint32_t Reserved40C;
1807 __IO uint32_t HPTXSTS;
1808 __IO uint32_t HAINT;
1809 __IO uint32_t HAINTMSK;
1810} USB_OTG_HostTypeDef;
1811
1815typedef struct
1816{
1817 __IO uint32_t HCCHAR;
1818 __IO uint32_t HCSPLT;
1819 __IO uint32_t HCINT;
1820 __IO uint32_t HCINTMSK;
1821 __IO uint32_t HCTSIZ;
1822 __IO uint32_t HCDMA;
1823 uint32_t Reserved[2];
1824} USB_OTG_HostChannelTypeDef;
1833typedef struct
1834{
1835 __IO uint32_t CR;
1836 uint32_t RESERVED;
1837 __IO uint32_t DCR1;
1838 __IO uint32_t DCR2;
1839 __IO uint32_t DCR3;
1840 __IO uint32_t DCR4;
1841 uint32_t RESERVED1[2];
1842 __IO uint32_t SR;
1843 __IO uint32_t FCR;
1844 uint32_t RESERVED2[6];
1845 __IO uint32_t DLR;
1846 uint32_t RESERVED3;
1847 __IO uint32_t AR;
1848 uint32_t RESERVED4;
1849 __IO uint32_t DR;
1850 uint32_t RESERVED5[11];
1851 __IO uint32_t PSMKR;
1852 uint32_t RESERVED6;
1853 __IO uint32_t PSMAR;
1854 uint32_t RESERVED7;
1855 __IO uint32_t PIR;
1856 uint32_t RESERVED8[27];
1857 __IO uint32_t CCR;
1858 uint32_t RESERVED9;
1859 __IO uint32_t TCR;
1860 uint32_t RESERVED10;
1861 __IO uint32_t IR;
1862 uint32_t RESERVED11[3];
1863 __IO uint32_t ABR;
1864 uint32_t RESERVED12[3];
1865 __IO uint32_t LPTR;
1866 uint32_t RESERVED13[3];
1867 __IO uint32_t WPCCR;
1868 uint32_t RESERVED14;
1869 __IO uint32_t WPTCR;
1870 uint32_t RESERVED15;
1871 __IO uint32_t WPIR;
1872 uint32_t RESERVED16[3];
1873 __IO uint32_t WPABR;
1874 uint32_t RESERVED17[7];
1875 __IO uint32_t WCCR;
1876 uint32_t RESERVED18;
1877 __IO uint32_t WTCR;
1878 uint32_t RESERVED19;
1879 __IO uint32_t WIR;
1880 uint32_t RESERVED20[3];
1881 __IO uint32_t WABR;
1882 uint32_t RESERVED21[23];
1883 __IO uint32_t HLCR;
1884 uint32_t RESERVED22[122];
1885 __IO uint32_t HWCFGR;
1886 __IO uint32_t VER;
1887 __IO uint32_t ID;
1888 __IO uint32_t MID;
1889} OCTOSPI_TypeDef;
1890
1898typedef struct
1899{
1900 __IO uint32_t CR;
1901 __IO uint32_t PCR[3];
1902} OCTOSPIM_TypeDef;
1903
1911typedef struct
1912{
1913 __IO uint32_t REG_CONFIGR;
1914 __IO uint32_t REG_START_ADDR;
1915 __IO uint32_t REG_END_ADDR;
1916 __IO uint32_t REG_NONCER0;
1917 __IO uint32_t REG_NONCER1;
1918 __IO uint32_t REG_KEYR0;
1919 __IO uint32_t REG_KEYR1;
1920 __IO uint32_t REG_KEYR2;
1921 __IO uint32_t REG_KEYR3;
1922} OTFDEC_Region_TypeDef;
1923
1924typedef struct
1925{
1926 __IO uint32_t CR;
1927 uint32_t RESERVED1[191];
1928 __IO uint32_t ISR;
1929 __IO uint32_t ICR;
1930 __IO uint32_t IER;
1931 uint32_t RESERVED2[56];
1932 __IO uint32_t HWCFGR2;
1933 __IO uint32_t HWCFGR1;
1934 __IO uint32_t VERR;
1935 __IO uint32_t IPIDR;
1936 __IO uint32_t SIDR;
1937} OTFDEC_TypeDef;
1946typedef struct
1947{
1948 uint32_t RESERVED0[2036];
1949 __IO uint32_t AXI_PERIPH_ID_4;
1950 uint32_t AXI_PERIPH_ID_5;
1951 uint32_t AXI_PERIPH_ID_6;
1952 uint32_t AXI_PERIPH_ID_7;
1953 __IO uint32_t AXI_PERIPH_ID_0;
1954 __IO uint32_t AXI_PERIPH_ID_1;
1955 __IO uint32_t AXI_PERIPH_ID_2;
1956 __IO uint32_t AXI_PERIPH_ID_3;
1957 __IO uint32_t AXI_COMP_ID_0;
1958 __IO uint32_t AXI_COMP_ID_1;
1959 __IO uint32_t AXI_COMP_ID_2;
1960 __IO uint32_t AXI_COMP_ID_3;
1961 uint32_t RESERVED1[2];
1962 __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;
1963 uint32_t RESERVED2[6];
1964 __IO uint32_t AXI_TARG1_FN_MOD2;
1965 uint32_t RESERVED3;
1966 __IO uint32_t AXI_TARG1_FN_MOD_LB;
1967 uint32_t RESERVED4[54];
1968 __IO uint32_t AXI_TARG1_FN_MOD;
1969 uint32_t RESERVED5[959];
1970 __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;
1971 uint32_t RESERVED6[6];
1972 __IO uint32_t AXI_TARG2_FN_MOD2;
1973 uint32_t RESERVED7;
1974 __IO uint32_t AXI_TARG2_FN_MOD_LB;
1975 uint32_t RESERVED8[54];
1976 __IO uint32_t AXI_TARG2_FN_MOD;
1977 uint32_t RESERVED9[959];
1978 __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;
1979 uint32_t RESERVED10[1023];
1980 __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;
1981 uint32_t RESERVED11[1023];
1982 __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;
1983 uint32_t RESERVED12[1023];
1984 __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;
1985 uint32_t RESERVED13[1023];
1986 __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;
1987 uint32_t RESERVED14[6];
1988 __IO uint32_t AXI_TARG7_FN_MOD2;
1989 uint32_t RESERVED15;
1990 __IO uint32_t AXI_TARG7_FN_MOD_LB;
1991 uint32_t RESERVED16[54];
1992 __IO uint32_t AXI_TARG7_FN_MOD;
1993 uint32_t RESERVED17[959];
1994 __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM;
1995 uint32_t RESERVED117[6];
1996 __IO uint32_t AXI_TARG8_FN_MOD2;
1997 uint32_t RESERVED118[56];
1998 __IO uint32_t AXI_TARG8_FN_MOD;
1999 uint32_t RESERVED119[959];
2000 __IO uint32_t AXI_TARG9_FN_MOD_ISS_BM;
2001 uint32_t RESERVED120[6];
2002 __IO uint32_t AXI_TARG9_FN_MOD2;
2003 uint32_t RESERVED121[56];
2004 __IO uint32_t AXI_TARG9_FN_MOD;
2005 uint32_t RESERVED122[959];
2006 __IO uint32_t AXI_TARG10_FN_MOD_ISS_BM;
2007 uint32_t RESERVED123[6];
2008 __IO uint32_t AXI_TARG10_FN_MOD2;
2009 uint32_t RESERVED124[56];
2010 __IO uint32_t AXI_TARG10_FN_MOD;
2011 uint32_t RESERVED125[968];
2012 __IO uint32_t AXI_TARG10_FN_MOD_LB;
2013 uint32_t RESERVED126[55293];
2014 __IO uint32_t AXI_INI1_FN_MOD2;
2015 __IO uint32_t AXI_INI1_FN_MOD_AHB;
2016 uint32_t RESERVED18[53];
2017 __IO uint32_t AXI_INI1_READ_QOS;
2018 __IO uint32_t AXI_INI1_WRITE_QOS;
2019 __IO uint32_t AXI_INI1_FN_MOD;
2020 uint32_t RESERVED19[1021];
2021 __IO uint32_t AXI_INI2_READ_QOS;
2022 __IO uint32_t AXI_INI2_WRITE_QOS;
2023 __IO uint32_t AXI_INI2_FN_MOD;
2024 uint32_t RESERVED20[966];
2025 __IO uint32_t AXI_INI3_FN_MOD2;
2026 __IO uint32_t AXI_INI3_FN_MOD_AHB;
2027 uint32_t RESERVED21[53];
2028 __IO uint32_t AXI_INI3_READ_QOS;
2029 __IO uint32_t AXI_INI3_WRITE_QOS;
2030 __IO uint32_t AXI_INI3_FN_MOD;
2031 uint32_t RESERVED22[1021];
2032 __IO uint32_t AXI_INI4_READ_QOS;
2033 __IO uint32_t AXI_INI4_WRITE_QOS;
2034 __IO uint32_t AXI_INI4_FN_MOD;
2035 uint32_t RESERVED23[1021];
2036 __IO uint32_t AXI_INI5_READ_QOS;
2037 __IO uint32_t AXI_INI5_WRITE_QOS;
2038 __IO uint32_t AXI_INI5_FN_MOD;
2039 uint32_t RESERVED24[1021];
2040 __IO uint32_t AXI_INI6_READ_QOS;
2041 __IO uint32_t AXI_INI6_WRITE_QOS;
2042 __IO uint32_t AXI_INI6_FN_MOD;
2043 uint32_t RESERVED25[966];
2044 __IO uint32_t AXI_INI7_FN_MOD2;
2045 __IO uint32_t AXI_INI7_FN_MOD_AHB;
2046 uint32_t RESERVED26[53];
2047 __IO uint32_t AXI_INI7_READ_QOS;
2048 __IO uint32_t AXI_INI7_WRITE_QOS;
2049 __IO uint32_t AXI_INI7_FN_MOD;
2051} GPV_TypeDef;
2052
2056#define CD_ITCMRAM_BASE (0x00000000UL)
2057#define CD_DTCMRAM_BASE (0x20000000UL)
2058#define CD_AXIFLASH_BASE (0x08000000UL)
2060#define CD_AXISRAM1_BASE (0x24000000UL)
2061#define CD_AXISRAM2_BASE (0x24040000UL)
2062#define CD_AXISRAM3_BASE (0x240A0000UL)
2063#define CD_AHBSRAM1_BASE (0x30000000UL)
2064#define CD_AHBSRAM2_BASE (0x30010000UL)
2066#define SRD_BKPSRAM_BASE (0x38800000UL)
2067#define SRD_SRAM_BASE (0x38000000UL)
2069#define OCTOSPI1_BASE (0x90000000UL)
2070#define OCTOSPI2_BASE (0x70000000UL)
2072#define FLASH_BANK1_BASE (0x08000000UL)
2073#define FLASH_BANK2_BASE (0x08100000UL)
2074#define FLASH_END (0x081FFFFFUL)
2076/* Legacy define */
2077#define FLASH_BASE FLASH_BANK1_BASE
2078#define D1_AXISRAM_BASE CD_AXISRAM1_BASE
2079
2080#define FLASH_OTP_BASE (0x08FFF000UL)
2081#define FLASH_OTP_END (0x08FFF3FFUL)
2085#define UID_BASE (0x08FFF800UL)
2086#define FLASHSIZE_BASE (0x08FFF80CUL)
2087#define PACKAGE_BASE (0x08FFF80EUL)
2089#define PERIPH_BASE (0x40000000UL)
2091#define CD_APB1PERIPH_BASE PERIPH_BASE
2092#define CD_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2093#define CD_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2094#define CD_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2096#define CD_APB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2097#define CD_AHB3PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2099#define SRD_APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2100#define SRD_AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2103#define APB1PERIPH_BASE PERIPH_BASE
2104#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2105#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2106#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2107
2109#define MDMA_BASE (CD_AHB3PERIPH_BASE + 0x0000UL)
2110#define DMA2D_BASE (CD_AHB3PERIPH_BASE + 0x1000UL)
2111#define FLASH_R_BASE (CD_AHB3PERIPH_BASE + 0x2000UL)
2112#define JPGDEC_BASE (CD_AHB3PERIPH_BASE + 0x3000UL)
2113#define FMC_R_BASE (CD_AHB3PERIPH_BASE + 0x4000UL)
2114#define OCTOSPI1_R_BASE (CD_AHB3PERIPH_BASE + 0x5000UL)
2115#define DLYB_OCTOSPI1_BASE (CD_AHB3PERIPH_BASE + 0x6000UL)
2116#define SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x7000UL)
2117#define DLYB_SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x8000UL)
2118#define RAMECC_BASE (CD_AHB3PERIPH_BASE + 0x9000UL)
2119#define OCTOSPI2_R_BASE (CD_AHB3PERIPH_BASE + 0xA000UL)
2120#define DLYB_OCTOSPI2_BASE (CD_AHB3PERIPH_BASE + 0xB000UL)
2121#define OCTOSPIM_BASE (CD_AHB3PERIPH_BASE + 0xB400UL)
2122
2125#define DMA1_BASE (CD_AHB1PERIPH_BASE + 0x0000UL)
2126#define DMA2_BASE (CD_AHB1PERIPH_BASE + 0x0400UL)
2127#define DMAMUX1_BASE (CD_AHB1PERIPH_BASE + 0x0800UL)
2128#define ADC1_BASE (CD_AHB1PERIPH_BASE + 0x2000UL)
2129#define ADC2_BASE (CD_AHB1PERIPH_BASE + 0x2100UL)
2130#define ADC12_COMMON_BASE (CD_AHB1PERIPH_BASE + 0x2300UL)
2131#define CRC_BASE (CD_AHB1PERIPH_BASE + 0x3000UL)
2132
2134#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2135#define USB_OTG_GLOBAL_BASE (0x000UL)
2136#define USB_OTG_DEVICE_BASE (0x800UL)
2137#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2138#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2139#define USB_OTG_EP_REG_SIZE (0x20UL)
2140#define USB_OTG_HOST_BASE (0x400UL)
2141#define USB_OTG_HOST_PORT_BASE (0x440UL)
2142#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2143#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2144#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2145#define USB_OTG_FIFO_BASE (0x1000UL)
2146#define USB_OTG_FIFO_SIZE (0x1000UL)
2147
2150#define DCMI_BASE (CD_AHB2PERIPH_BASE + 0x0000UL)
2151#define PSSI_BASE (CD_AHB2PERIPH_BASE + 0x0400UL)
2152#define HSEM_BASE (CD_AHB2PERIPH_BASE + 0x0800UL)
2153#define CRYP_BASE (CD_AHB2PERIPH_BASE + 0x1000UL)
2154#define HASH_BASE (CD_AHB2PERIPH_BASE + 0x1400UL)
2155#define HASH_DIGEST_BASE (CD_AHB2PERIPH_BASE + 0x1710UL)
2156#define RNG_BASE (CD_AHB2PERIPH_BASE + 0x1800UL)
2157#define SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2400UL)
2158#define DLYB_SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2800UL)
2159#define BDMA1_BASE (CD_AHB2PERIPH_BASE + 0x2C00UL)
2160
2162#define GPIOA_BASE (SRD_AHB4PERIPH_BASE + 0x0000UL)
2163#define GPIOB_BASE (SRD_AHB4PERIPH_BASE + 0x0400UL)
2164#define GPIOC_BASE (SRD_AHB4PERIPH_BASE + 0x0800UL)
2165#define GPIOD_BASE (SRD_AHB4PERIPH_BASE + 0x0C00UL)
2166#define GPIOE_BASE (SRD_AHB4PERIPH_BASE + 0x1000UL)
2167#define GPIOF_BASE (SRD_AHB4PERIPH_BASE + 0x1400UL)
2168#define GPIOG_BASE (SRD_AHB4PERIPH_BASE + 0x1800UL)
2169#define GPIOH_BASE (SRD_AHB4PERIPH_BASE + 0x1C00UL)
2170#define GPIOI_BASE (SRD_AHB4PERIPH_BASE + 0x2000UL)
2171#define GPIOJ_BASE (SRD_AHB4PERIPH_BASE + 0x2400UL)
2172#define GPIOK_BASE (SRD_AHB4PERIPH_BASE + 0x2800UL)
2173#define RCC_BASE (SRD_AHB4PERIPH_BASE + 0x4400UL)
2174#define PWR_BASE (SRD_AHB4PERIPH_BASE + 0x4800UL)
2175#define BDMA2_BASE (SRD_AHB4PERIPH_BASE + 0x5400UL)
2176#define DMAMUX2_BASE (SRD_AHB4PERIPH_BASE + 0x5800UL)
2177
2179#define LTDC_BASE (CD_APB3PERIPH_BASE + 0x1000UL)
2180#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2181#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2182#define WWDG1_BASE (CD_APB3PERIPH_BASE + 0x3000UL)
2183
2185#define TIM2_BASE (CD_APB1PERIPH_BASE + 0x0000UL)
2186#define TIM3_BASE (CD_APB1PERIPH_BASE + 0x0400UL)
2187#define TIM4_BASE (CD_APB1PERIPH_BASE + 0x0800UL)
2188#define TIM5_BASE (CD_APB1PERIPH_BASE + 0x0C00UL)
2189#define TIM6_BASE (CD_APB1PERIPH_BASE + 0x1000UL)
2190#define TIM7_BASE (CD_APB1PERIPH_BASE + 0x1400UL)
2191#define TIM12_BASE (CD_APB1PERIPH_BASE + 0x1800UL)
2192#define TIM13_BASE (CD_APB1PERIPH_BASE + 0x1C00UL)
2193#define TIM14_BASE (CD_APB1PERIPH_BASE + 0x2000UL)
2194#define LPTIM1_BASE (CD_APB1PERIPH_BASE + 0x2400UL)
2195
2196#define SPI2_BASE (CD_APB1PERIPH_BASE + 0x3800UL)
2197#define SPI3_BASE (CD_APB1PERIPH_BASE + 0x3C00UL)
2198#define SPDIFRX_BASE (CD_APB1PERIPH_BASE + 0x4000UL)
2199#define USART2_BASE (CD_APB1PERIPH_BASE + 0x4400UL)
2200#define USART3_BASE (CD_APB1PERIPH_BASE + 0x4800UL)
2201#define UART4_BASE (CD_APB1PERIPH_BASE + 0x4C00UL)
2202#define UART5_BASE (CD_APB1PERIPH_BASE + 0x5000UL)
2203#define I2C1_BASE (CD_APB1PERIPH_BASE + 0x5400UL)
2204#define I2C2_BASE (CD_APB1PERIPH_BASE + 0x5800UL)
2205#define I2C3_BASE (CD_APB1PERIPH_BASE + 0x5C00UL)
2206#define CEC_BASE (CD_APB1PERIPH_BASE + 0x6C00UL)
2207#define DAC1_BASE (CD_APB1PERIPH_BASE + 0x7400UL)
2208#define UART7_BASE (CD_APB1PERIPH_BASE + 0x7800UL)
2209#define UART8_BASE (CD_APB1PERIPH_BASE + 0x7C00UL)
2210#define CRS_BASE (CD_APB1PERIPH_BASE + 0x8400UL)
2211#define SWPMI1_BASE (CD_APB1PERIPH_BASE + 0x8800UL)
2212#define OPAMP_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
2213#define OPAMP1_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
2214#define OPAMP2_BASE (CD_APB1PERIPH_BASE + 0x9010UL)
2215#define MDIOS_BASE (CD_APB1PERIPH_BASE + 0x9400UL)
2216#define FDCAN1_BASE (CD_APB1PERIPH_BASE + 0xA000UL)
2217#define FDCAN2_BASE (CD_APB1PERIPH_BASE + 0xA400UL)
2218#define FDCAN_CCU_BASE (CD_APB1PERIPH_BASE + 0xA800UL)
2219#define SRAMCAN_BASE (CD_APB1PERIPH_BASE + 0xAC00UL)
2220
2223#define TIM1_BASE (CD_APB2PERIPH_BASE + 0x0000UL)
2224#define TIM8_BASE (CD_APB2PERIPH_BASE + 0x0400UL)
2225#define USART1_BASE (CD_APB2PERIPH_BASE + 0x1000UL)
2226#define USART6_BASE (CD_APB2PERIPH_BASE + 0x1400UL)
2227#define UART9_BASE (CD_APB2PERIPH_BASE + 0x1800UL)
2228#define USART10_BASE (CD_APB2PERIPH_BASE + 0x1C00UL)
2229#define SPI1_BASE (CD_APB2PERIPH_BASE + 0x3000UL)
2230#define SPI4_BASE (CD_APB2PERIPH_BASE + 0x3400UL)
2231#define TIM15_BASE (CD_APB2PERIPH_BASE + 0x4000UL)
2232#define TIM16_BASE (CD_APB2PERIPH_BASE + 0x4400UL)
2233#define TIM17_BASE (CD_APB2PERIPH_BASE + 0x4800UL)
2234#define SPI5_BASE (CD_APB2PERIPH_BASE + 0x5000UL)
2235#define SAI1_BASE (CD_APB2PERIPH_BASE + 0x5800UL)
2236#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2237#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2238#define SAI2_BASE (CD_APB2PERIPH_BASE + 0x5C00UL)
2239#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2240#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2241#define DFSDM1_BASE (CD_APB2PERIPH_BASE + 0x7800UL)
2242#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2243#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2244#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2245#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2246#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2247#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2248#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2249#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2250#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2251#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2252#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2253#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2254#define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300UL)
2255#define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380UL)
2256#define DFSDM1_Filter6_BASE (DFSDM1_BASE + 0x400UL)
2257#define DFSDM1_Filter7_BASE (DFSDM1_BASE + 0x480UL)
2259#define EXTI_BASE (SRD_APB4PERIPH_BASE + 0x0000UL)
2260#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2261#define SYSCFG_BASE (SRD_APB4PERIPH_BASE + 0x0400UL)
2262#define LPUART1_BASE (SRD_APB4PERIPH_BASE + 0x0C00UL)
2263#define SPI6_BASE (SRD_APB4PERIPH_BASE + 0x1400UL)
2264#define I2C4_BASE (SRD_APB4PERIPH_BASE + 0x1C00UL)
2265#define LPTIM2_BASE (SRD_APB4PERIPH_BASE + 0x2400UL)
2266#define LPTIM3_BASE (SRD_APB4PERIPH_BASE + 0x2800UL)
2267#define DAC2_BASE (SRD_APB4PERIPH_BASE + 0x3400UL)
2268#define COMP12_BASE (SRD_APB4PERIPH_BASE + 0x3800UL)
2269#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2270#define COMP2_BASE (COMP12_BASE + 0x10UL)
2271#define VREFBUF_BASE (SRD_APB4PERIPH_BASE + 0x3C00UL)
2272#define RTC_BASE (SRD_APB4PERIPH_BASE + 0x4000UL)
2273#define TAMP_BASE (SRD_APB4PERIPH_BASE + 0x4400UL)
2274#define IWDG1_BASE (SRD_APB4PERIPH_BASE + 0x4800UL)
2275
2276#define DTS_BASE (SRD_APB4PERIPH_BASE + 0x6800UL)
2277
2278#define DFSDM2_BASE (SRD_APB4PERIPH_BASE + 0x6C00UL)
2279#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
2280#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
2281#define DFSDM2_FLT0_BASE (DFSDM2_BASE + 0x100UL)
2282
2285#define OTFDEC1_BASE (CD_AHB3PERIPH_BASE + 0xB800UL)
2286#define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL)
2287#define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL)
2288#define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL)
2289#define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL)
2290#define OTFDEC2_BASE (CD_AHB3PERIPH_BASE + 0xBC00UL)
2291#define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL)
2292#define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL)
2293#define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL)
2294#define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL)
2295#define GFXMMU_BASE (CD_AHB3PERIPH_BASE + 0xC000UL)
2296
2297#define BDMA1_Channel0_BASE (BDMA1_BASE + 0x0008UL)
2298#define BDMA1_Channel1_BASE (BDMA1_BASE + 0x001CUL)
2299#define BDMA1_Channel2_BASE (BDMA1_BASE + 0x0030UL)
2300#define BDMA1_Channel3_BASE (BDMA1_BASE + 0x0044UL)
2301#define BDMA1_Channel4_BASE (BDMA1_BASE + 0x0058UL)
2302#define BDMA1_Channel5_BASE (BDMA1_BASE + 0x006CUL)
2303#define BDMA1_Channel6_BASE (BDMA1_BASE + 0x0080UL)
2304#define BDMA1_Channel7_BASE (BDMA1_BASE + 0x0094UL)
2305
2306#define BDMA2_Channel0_BASE (BDMA2_BASE + 0x0008UL)
2307#define BDMA2_Channel1_BASE (BDMA2_BASE + 0x001CUL)
2308#define BDMA2_Channel2_BASE (BDMA2_BASE + 0x0030UL)
2309#define BDMA2_Channel3_BASE (BDMA2_BASE + 0x0044UL)
2310#define BDMA2_Channel4_BASE (BDMA2_BASE + 0x0058UL)
2311#define BDMA2_Channel5_BASE (BDMA2_BASE + 0x006CUL)
2312#define BDMA2_Channel6_BASE (BDMA2_BASE + 0x0080UL)
2313#define BDMA2_Channel7_BASE (BDMA2_BASE + 0x0094UL)
2314
2315
2316#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2317#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2318#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2319#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2320#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2321#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2322#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2323#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2324
2325#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2326#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2327#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2328#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2329#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2330#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2331#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2332#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2333
2334#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2335#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2336
2337#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2338#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2339#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2340#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2341#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2342#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2343#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2344#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2345
2346#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2347#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2348#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2349#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2350#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2351#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2352#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2353#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2354
2355
2356#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2357#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2358#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2359#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2360#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2361#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2362#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2363#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2364#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2365#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2366#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2367#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2368#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2369#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2370#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2371#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2372
2373#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2374#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2375#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2376#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2377#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2378#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2379#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2380#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2381
2382#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2383#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2384
2386#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2387#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2388#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2389#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2390#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2391
2392/* Debug MCU registers base address */
2393#define DBGMCU_BASE (0x5C001000UL)
2394
2395#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2396#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2397#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2398#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2399#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2400#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2401#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2402#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2403#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2404#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2405#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2406#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2407#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2408#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2409#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2410#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2411#define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
2412
2413/* GFXMMU virtual buffers base address */
2414#define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
2415#define GFXMMU_VIRTUAL_BUFFER0_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE)
2416#define GFXMMU_VIRTUAL_BUFFER1_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)
2417#define GFXMMU_VIRTUAL_BUFFER2_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)
2418#define GFXMMU_VIRTUAL_BUFFER3_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)
2419
2420#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)
2421#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
2422#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
2423
2424
2425#define GPV_BASE (PERIPH_BASE + 0x11000000UL)
2434#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2435#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2436#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2437#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2438#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2439#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2440#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2441#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2442#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2443#define RTC ((RTC_TypeDef *) RTC_BASE)
2444#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
2445#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2446
2447
2448#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2449#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2450#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2451#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2452#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2453#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2454#define USART2 ((USART_TypeDef *) USART2_BASE)
2455#define USART3 ((USART_TypeDef *) USART3_BASE)
2456#define USART6 ((USART_TypeDef *) USART6_BASE)
2457#define USART10 ((USART_TypeDef *) USART10_BASE)
2458#define UART7 ((USART_TypeDef *) UART7_BASE)
2459#define UART8 ((USART_TypeDef *) UART8_BASE)
2460#define UART9 ((USART_TypeDef *) UART9_BASE)
2461#define CRS ((CRS_TypeDef *) CRS_BASE)
2462#define UART4 ((USART_TypeDef *) UART4_BASE)
2463#define UART5 ((USART_TypeDef *) UART5_BASE)
2464#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2465#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2466#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2467#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2468#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2469#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2470#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2471#define CEC ((CEC_TypeDef *) CEC_BASE)
2472#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2473#define PWR ((PWR_TypeDef *) PWR_BASE)
2474#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2475#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2476#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2477#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2478#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2479#define DTS ((DTS_TypeDef *) DTS_BASE)
2480
2481#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2482#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2483#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2484#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2485#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2486#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2487#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2488#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2489
2490
2491#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2492#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2493#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2494#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2495#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2496#define USART1 ((USART_TypeDef *) USART1_BASE)
2497#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2498#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2499#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2500#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2501#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2502#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2503#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2504#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2505#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2506#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2507
2508#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2509#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2510#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2511#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2512#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2513#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2514#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2515#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2516#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2517#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2518#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2519#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2520#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2521#define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
2522#define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
2523#define DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)
2524#define DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)
2525#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
2526#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
2527#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)
2528#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2529#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2530#define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2531#define RCC ((RCC_TypeDef *) RCC_BASE)
2532#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2533#define CRC ((CRC_TypeDef *) CRC_BASE)
2534
2535#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2536#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2537#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2538#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2539#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2540#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2541#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2542#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2543#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2544#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2545#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2546
2547#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2548#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2549#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2550
2551#define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2552#define HASH ((HASH_TypeDef *) HASH_BASE)
2553#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2554#define RNG ((RNG_TypeDef *) RNG_BASE)
2555#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2556#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2557
2558#define BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)
2559#define BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)
2560#define BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)
2561#define BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)
2562#define BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)
2563#define BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)
2564#define BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)
2565#define BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)
2566#define BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)
2567
2568#define BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)
2569#define BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)
2570#define BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)
2571#define BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)
2572#define BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)
2573#define BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)
2574#define BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)
2575#define BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)
2576#define BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)
2577
2578#define RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)
2579#define RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)
2580#define RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)
2581#define RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)
2582
2583#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2584#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2585#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2586#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2587#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2588#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2589#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2590#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2591#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2592
2593
2594#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2595#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2596#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2597#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2598#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2599#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2600#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2601#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2602
2603#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2604#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2605
2606#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2607#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2608#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2609#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2610#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2611#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2612#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2613#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2614#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2615
2616#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2617#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2618#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2619#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2620#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2621#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2622#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2623#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2624#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2625
2626
2627#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2628#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2629#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2630#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2631#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2632#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2633#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2634#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2635#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2636#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2637#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2638#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2639#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2640#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2641#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2642#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2643#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2644
2645#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2646#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2647#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2648#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2649#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2650#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2651#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2652#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2653
2654#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2655#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2656
2657
2658#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2659#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2660#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2661#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2662#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2663
2664#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
2665#define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2666#define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2667#define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2668#define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2669#define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2670
2671#define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)
2672#define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)
2673#define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)
2674#define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)
2675#define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)
2676
2677#define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)
2678#define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)
2679#define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)
2680#define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)
2681#define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)
2682#define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
2683
2684#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2685#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2686
2687#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2688
2689#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2690#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2691#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2692
2693#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2694#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2695#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2696
2697#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2698
2699#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2700#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2701#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2702#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2703#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2704#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2705#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2706#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2707#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2708#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2709#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2710#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2711#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2712#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2713#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2714#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2715#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2716
2717
2718#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2719
2720/* Legacy defines */
2721#define USB_OTG_HS USB1_OTG_HS
2722#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2723
2724#define GPV ((GPV_TypeDef *) GPV_BASE)
2725
2737#define LSI_STARTUP_TIME 130U
2747/******************************************************************************/
2748/* Peripheral Registers_Bits_Definition */
2749/******************************************************************************/
2750
2751/******************************************************************************/
2752/* */
2753/* Analog to Digital Converter */
2754/* */
2755/******************************************************************************/
2756/******************************* ADC VERSION ********************************/
2757#define ADC_VER_V5_3
2758/******************** Bit definition for ADC_ISR register ********************/
2759#define ADC_ISR_ADRDY_Pos (0U)
2760#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
2761#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
2762#define ADC_ISR_EOSMP_Pos (1U)
2763#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
2764#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
2765#define ADC_ISR_EOC_Pos (2U)
2766#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
2767#define ADC_ISR_EOC ADC_ISR_EOC_Msk
2768#define ADC_ISR_EOS_Pos (3U)
2769#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
2770#define ADC_ISR_EOS ADC_ISR_EOS_Msk
2771#define ADC_ISR_OVR_Pos (4U)
2772#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
2773#define ADC_ISR_OVR ADC_ISR_OVR_Msk
2774#define ADC_ISR_JEOC_Pos (5U)
2775#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
2776#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
2777#define ADC_ISR_JEOS_Pos (6U)
2778#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
2779#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
2780#define ADC_ISR_AWD1_Pos (7U)
2781#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
2782#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
2783#define ADC_ISR_AWD2_Pos (8U)
2784#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
2785#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
2786#define ADC_ISR_AWD3_Pos (9U)
2787#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
2788#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
2789#define ADC_ISR_JQOVF_Pos (10U)
2790#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
2791#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
2792#define ADC_ISR_LDORDY_Pos (12U)
2793#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
2794#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
2796/******************** Bit definition for ADC_IER register ********************/
2797#define ADC_IER_ADRDYIE_Pos (0U)
2798#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
2799#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
2800#define ADC_IER_EOSMPIE_Pos (1U)
2801#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
2802#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
2803#define ADC_IER_EOCIE_Pos (2U)
2804#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
2805#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
2806#define ADC_IER_EOSIE_Pos (3U)
2807#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
2808#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
2809#define ADC_IER_OVRIE_Pos (4U)
2810#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
2811#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
2812#define ADC_IER_JEOCIE_Pos (5U)
2813#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
2814#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
2815#define ADC_IER_JEOSIE_Pos (6U)
2816#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
2817#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
2818#define ADC_IER_AWD1IE_Pos (7U)
2819#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
2820#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
2821#define ADC_IER_AWD2IE_Pos (8U)
2822#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
2823#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
2824#define ADC_IER_AWD3IE_Pos (9U)
2825#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
2826#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
2827#define ADC_IER_JQOVFIE_Pos (10U)
2828#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
2829#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
2831/******************** Bit definition for ADC_CR register ********************/
2832#define ADC_CR_ADEN_Pos (0U)
2833#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
2834#define ADC_CR_ADEN ADC_CR_ADEN_Msk
2835#define ADC_CR_ADDIS_Pos (1U)
2836#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
2837#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
2838#define ADC_CR_ADSTART_Pos (2U)
2839#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
2840#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
2841#define ADC_CR_JADSTART_Pos (3U)
2842#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
2843#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
2844#define ADC_CR_ADSTP_Pos (4U)
2845#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
2846#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
2847#define ADC_CR_JADSTP_Pos (5U)
2848#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
2849#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
2850#define ADC_CR_BOOST_Pos (8U)
2851#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos)
2852#define ADC_CR_BOOST ADC_CR_BOOST_Msk
2853#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos)
2854#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos)
2855#define ADC_CR_ADCALLIN_Pos (16U)
2856#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos)
2857#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk
2858#define ADC_CR_LINCALRDYW1_Pos (22U)
2859#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos)
2860#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk
2861#define ADC_CR_LINCALRDYW2_Pos (23U)
2862#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos)
2863#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk
2864#define ADC_CR_LINCALRDYW3_Pos (24U)
2865#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos)
2866#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk
2867#define ADC_CR_LINCALRDYW4_Pos (25U)
2868#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos)
2869#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk
2870#define ADC_CR_LINCALRDYW5_Pos (26U)
2871#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos)
2872#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk
2873#define ADC_CR_LINCALRDYW6_Pos (27U)
2874#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos)
2875#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk
2876#define ADC_CR_ADVREGEN_Pos (28U)
2877#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
2878#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
2879#define ADC_CR_DEEPPWD_Pos (29U)
2880#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
2881#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
2882#define ADC_CR_ADCALDIF_Pos (30U)
2883#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
2884#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
2885#define ADC_CR_ADCAL_Pos (31U)
2886#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
2887#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
2889/******************** Bit definition for ADC_CFGR register ********************/
2890#define ADC_CFGR_DMNGT_Pos (0U)
2891#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos)
2892#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk
2893#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos)
2894#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos)
2896#define ADC_CFGR_RES_Pos (2U)
2897#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos)
2898#define ADC_CFGR_RES ADC_CFGR_RES_Msk
2899#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
2900#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
2901#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos)
2903#define ADC_CFGR_EXTSEL_Pos (5U)
2904#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
2905#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
2906#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos)
2907#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos)
2908#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos)
2909#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos)
2910#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
2912#define ADC_CFGR_EXTEN_Pos (10U)
2913#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
2914#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
2915#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
2916#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
2918#define ADC_CFGR_OVRMOD_Pos (12U)
2919#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
2920#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
2921#define ADC_CFGR_CONT_Pos (13U)
2922#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
2923#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
2924#define ADC_CFGR_AUTDLY_Pos (14U)
2925#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
2926#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
2928#define ADC_CFGR_DISCEN_Pos (16U)
2929#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
2930#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
2932#define ADC_CFGR_DISCNUM_Pos (17U)
2933#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
2934#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
2935#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
2936#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
2937#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
2939#define ADC_CFGR_JDISCEN_Pos (20U)
2940#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
2941#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
2942#define ADC_CFGR_JQM_Pos (21U)
2943#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
2944#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
2945#define ADC_CFGR_AWD1SGL_Pos (22U)
2946#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
2947#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
2948#define ADC_CFGR_AWD1EN_Pos (23U)
2949#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
2950#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
2951#define ADC_CFGR_JAWD1EN_Pos (24U)
2952#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
2953#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
2954#define ADC_CFGR_JAUTO_Pos (25U)
2955#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
2956#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
2958#define ADC_CFGR_AWD1CH_Pos (26U)
2959#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
2960#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
2961#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
2962#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
2963#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
2964#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
2965#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
2967#define ADC_CFGR_JQDIS_Pos (31U)
2968#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
2969#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
2971/******************** Bit definition for ADC_CFGR2 register ********************/
2972#define ADC_CFGR2_ROVSE_Pos (0U)
2973#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
2974#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
2975#define ADC_CFGR2_JOVSE_Pos (1U)
2976#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
2977#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
2979#define ADC_CFGR2_OVSS_Pos (5U)
2980#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
2981#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
2982#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
2983#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
2984#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
2985#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
2987#define ADC_CFGR2_TROVS_Pos (9U)
2988#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
2989#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
2990#define ADC_CFGR2_ROVSM_Pos (10U)
2991#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
2992#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
2994#define ADC_CFGR2_RSHIFT1_Pos (11U)
2995#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
2996#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk
2997#define ADC_CFGR2_RSHIFT2_Pos (12U)
2998#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
2999#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk
3000#define ADC_CFGR2_RSHIFT3_Pos (13U)
3001#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
3002#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk
3003#define ADC_CFGR2_RSHIFT4_Pos (14U)
3004#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
3005#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk
3007#define ADC_CFGR2_OVSR_Pos (16U)
3008#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos)
3009#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
3010#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos)
3011#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos)
3012#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos)
3013#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos)
3014#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos)
3015#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos)
3016#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos)
3017#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos)
3018#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos)
3019#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos)
3021#define ADC_CFGR2_LSHIFT_Pos (28U)
3022#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos)
3023#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk
3024#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos)
3025#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos)
3026#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos)
3027#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos)
3029/******************** Bit definition for ADC_SMPR1 register ********************/
3030#define ADC_SMPR1_SMP0_Pos (0U)
3031#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
3032#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
3033#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
3034#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
3035#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
3037#define ADC_SMPR1_SMP1_Pos (3U)
3038#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
3039#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
3040#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
3041#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
3042#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
3044#define ADC_SMPR1_SMP2_Pos (6U)
3045#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
3046#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
3047#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
3048#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
3049#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
3051#define ADC_SMPR1_SMP3_Pos (9U)
3052#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
3053#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
3054#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
3055#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
3056#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
3058#define ADC_SMPR1_SMP4_Pos (12U)
3059#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
3060#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
3061#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
3062#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
3063#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
3065#define ADC_SMPR1_SMP5_Pos (15U)
3066#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
3067#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
3068#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
3069#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
3070#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
3072#define ADC_SMPR1_SMP6_Pos (18U)
3073#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
3074#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
3075#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
3076#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
3077#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
3079#define ADC_SMPR1_SMP7_Pos (21U)
3080#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
3081#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
3082#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
3083#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
3084#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
3086#define ADC_SMPR1_SMP8_Pos (24U)
3087#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
3088#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
3089#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
3090#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
3091#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
3093#define ADC_SMPR1_SMP9_Pos (27U)
3094#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
3095#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
3096#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
3097#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
3098#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
3100/******************** Bit definition for ADC_SMPR2 register ********************/
3101#define ADC_SMPR2_SMP10_Pos (0U)
3102#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
3103#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
3104#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
3105#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
3106#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
3108#define ADC_SMPR2_SMP11_Pos (3U)
3109#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
3110#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
3111#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
3112#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
3113#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
3115#define ADC_SMPR2_SMP12_Pos (6U)
3116#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
3117#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
3118#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
3119#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
3120#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
3122#define ADC_SMPR2_SMP13_Pos (9U)
3123#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
3124#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
3125#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
3126#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
3127#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
3129#define ADC_SMPR2_SMP14_Pos (12U)
3130#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
3131#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
3132#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
3133#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
3134#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
3136#define ADC_SMPR2_SMP15_Pos (15U)
3137#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
3138#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
3139#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
3140#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
3141#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
3143#define ADC_SMPR2_SMP16_Pos (18U)
3144#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
3145#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
3146#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
3147#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
3148#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
3150#define ADC_SMPR2_SMP17_Pos (21U)
3151#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
3152#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
3153#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
3154#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
3155#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
3157#define ADC_SMPR2_SMP18_Pos (24U)
3158#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
3159#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
3160#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
3161#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
3162#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
3164#define ADC_SMPR2_SMP19_Pos (27U)
3165#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos)
3166#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk
3167#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos)
3168#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos)
3169#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
3171/******************** Bit definition for ADC_PCSEL register ********************/
3172#define ADC_PCSEL_PCSEL_Pos (0U)
3173#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
3174#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk
3175#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos)
3176#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos)
3177#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos)
3178#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos)
3179#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos)
3180#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos)
3181#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos)
3182#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos)
3183#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos)
3184#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos)
3185#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos)
3186#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos)
3187#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos)
3188#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos)
3189#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos)
3190#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos)
3191#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos)
3192#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos)
3193#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos)
3194#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos)
3196/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3197#define ADC_LTR_LT_Pos (0U)
3198#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos)
3199#define ADC_LTR_LT ADC_LTR_LT_Msk
3201/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3202#define ADC_HTR_HT_Pos (0U)
3203#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos)
3204#define ADC_HTR_HT ADC_HTR_HT_Msk
3207/******************** Bit definition for ADC_SQR1 register ********************/
3208#define ADC_SQR1_L_Pos (0U)
3209#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3210#define ADC_SQR1_L ADC_SQR1_L_Msk
3211#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3212#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3213#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3214#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3216#define ADC_SQR1_SQ1_Pos (6U)
3217#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
3218#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
3219#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
3220#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
3221#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
3222#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
3223#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
3225#define ADC_SQR1_SQ2_Pos (12U)
3226#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
3227#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
3228#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
3229#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
3230#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
3231#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
3232#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
3234#define ADC_SQR1_SQ3_Pos (18U)
3235#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
3236#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
3237#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
3238#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
3239#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
3240#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
3241#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
3243#define ADC_SQR1_SQ4_Pos (24U)
3244#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
3245#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
3246#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
3247#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
3248#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
3249#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
3250#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
3252/******************** Bit definition for ADC_SQR2 register ********************/
3253#define ADC_SQR2_SQ5_Pos (0U)
3254#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
3255#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
3256#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
3257#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
3258#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
3259#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
3260#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
3262#define ADC_SQR2_SQ6_Pos (6U)
3263#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
3264#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
3265#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
3266#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
3267#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
3268#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
3269#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
3271#define ADC_SQR2_SQ7_Pos (12U)
3272#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3273#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3274#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3275#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3276#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3277#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3278#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3280#define ADC_SQR2_SQ8_Pos (18U)
3281#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3282#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3283#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3284#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3285#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3286#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3287#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3289#define ADC_SQR2_SQ9_Pos (24U)
3290#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3291#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3292#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3293#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3294#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3295#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3296#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3298/******************** Bit definition for ADC_SQR3 register ********************/
3299#define ADC_SQR3_SQ10_Pos (0U)
3300#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
3301#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
3302#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
3303#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
3304#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
3305#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
3306#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
3308#define ADC_SQR3_SQ11_Pos (6U)
3309#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
3310#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
3311#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
3312#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
3313#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
3314#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
3315#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
3317#define ADC_SQR3_SQ12_Pos (12U)
3318#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
3319#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
3320#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
3321#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
3322#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
3323#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
3324#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
3326#define ADC_SQR3_SQ13_Pos (18U)
3327#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
3328#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
3329#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
3330#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
3331#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
3332#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
3333#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
3335#define ADC_SQR3_SQ14_Pos (24U)
3336#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
3337#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
3338#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
3339#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
3340#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
3341#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
3342#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
3344/******************** Bit definition for ADC_SQR4 register ********************/
3345#define ADC_SQR4_SQ15_Pos (0U)
3346#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
3347#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
3348#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
3349#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
3350#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
3351#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
3352#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
3354#define ADC_SQR4_SQ16_Pos (6U)
3355#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
3356#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
3357#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
3358#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
3359#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
3360#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
3361#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
3362/******************** Bit definition for ADC_DR register ********************/
3363#define ADC_DR_RDATA_Pos (0U)
3364#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
3365#define ADC_DR_RDATA ADC_DR_RDATA_Msk
3367/******************** Bit definition for ADC_JSQR register ********************/
3368#define ADC_JSQR_JL_Pos (0U)
3369#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3370#define ADC_JSQR_JL ADC_JSQR_JL_Msk
3371#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3372#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3374#define ADC_JSQR_JEXTSEL_Pos (2U)
3375#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
3376#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
3377#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos)
3378#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos)
3379#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos)
3380#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos)
3381#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
3383#define ADC_JSQR_JEXTEN_Pos (7U)
3384#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
3385#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
3386#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
3387#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
3389#define ADC_JSQR_JSQ1_Pos (9U)
3390#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3391#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3392#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3393#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3394#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3395#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3396#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3398#define ADC_JSQR_JSQ2_Pos (15U)
3399#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3400#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3401#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3402#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3403#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3404#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3405#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3407#define ADC_JSQR_JSQ3_Pos (21U)
3408#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3409#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3410#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3411#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3412#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3413#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3414#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3416#define ADC_JSQR_JSQ4_Pos (27U)
3417#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3418#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3419#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3420#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3421#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3422#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3423#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3425/******************** Bit definition for ADC_OFR1 register ********************/
3426#define ADC_OFR1_OFFSET1_Pos (0U)
3427#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
3428#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
3429#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
3430#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
3431#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
3432#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
3433#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
3434#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
3435#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
3436#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
3437#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
3438#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
3439#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
3440#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
3441#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
3442#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
3443#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
3444#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
3445#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
3446#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
3447#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
3448#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
3449#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
3450#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
3451#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
3452#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
3453#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
3454#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
3456#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3457#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
3458#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
3459#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
3460#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
3461#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
3462#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
3463#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
3465#define ADC_OFR1_SSATE_Pos (31U)
3466#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos)
3467#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk
3470/******************** Bit definition for ADC_OFR2 register ********************/
3471#define ADC_OFR2_OFFSET2_Pos (0U)
3472#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
3473#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
3474#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
3475#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
3476#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
3477#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
3478#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
3479#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
3480#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
3481#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
3482#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
3483#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
3484#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
3485#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
3486#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
3487#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
3488#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
3489#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
3490#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
3491#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
3492#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
3493#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
3494#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
3495#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
3496#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
3497#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
3498#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
3499#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
3501#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3502#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
3503#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
3504#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
3505#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
3506#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
3507#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
3508#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
3510#define ADC_OFR2_SSATE_Pos (31U)
3511#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos)
3512#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk
3515/******************** Bit definition for ADC_OFR3 register ********************/
3516#define ADC_OFR3_OFFSET3_Pos (0U)
3517#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
3518#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
3519#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
3520#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
3521#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
3522#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
3523#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
3524#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
3525#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
3526#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
3527#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
3528#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
3529#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
3530#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
3531#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
3532#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
3533#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
3534#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
3535#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
3536#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
3537#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
3538#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
3539#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
3540#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
3541#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
3542#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
3543#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
3544#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
3546#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3547#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
3548#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
3549#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
3550#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
3551#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
3552#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
3553#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
3555#define ADC_OFR3_SSATE_Pos (31U)
3556#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos)
3557#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk
3560/******************** Bit definition for ADC_OFR4 register ********************/
3561#define ADC_OFR4_OFFSET4_Pos (0U)
3562#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
3563#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
3564#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
3565#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
3566#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
3567#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
3568#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
3569#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
3570#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
3571#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
3572#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
3573#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
3574#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
3575#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
3576#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
3577#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
3578#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
3579#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
3580#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
3581#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
3582#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
3583#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
3584#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
3585#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
3586#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
3587#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
3588#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
3589#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
3591#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3592#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
3593#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
3594#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
3595#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
3596#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
3597#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
3598#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
3600#define ADC_OFR4_SSATE_Pos (31U)
3601#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos)
3602#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk
3605/******************** Bit definition for ADC_JDR1 register ********************/
3606#define ADC_JDR1_JDATA_Pos (0U)
3607#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
3608#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3609#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos)
3610#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos)
3611#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos)
3612#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos)
3613#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos)
3614#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos)
3615#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos)
3616#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos)
3617#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos)
3618#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos)
3619#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos)
3620#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos)
3621#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos)
3622#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos)
3623#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos)
3624#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos)
3625#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos)
3626#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos)
3627#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos)
3628#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos)
3629#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos)
3630#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos)
3631#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos)
3632#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos)
3633#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos)
3634#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos)
3635#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos)
3636#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos)
3637#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos)
3638#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos)
3639#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos)
3640#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos)
3642/******************** Bit definition for ADC_JDR2 register ********************/
3643#define ADC_JDR2_JDATA_Pos (0U)
3644#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
3645#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3646#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos)
3647#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos)
3648#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos)
3649#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos)
3650#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos)
3651#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos)
3652#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos)
3653#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos)
3654#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos)
3655#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos)
3656#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos)
3657#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos)
3658#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos)
3659#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos)
3660#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos)
3661#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos)
3662#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos)
3663#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos)
3664#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos)
3665#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos)
3666#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos)
3667#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos)
3668#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos)
3669#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos)
3670#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos)
3671#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos)
3672#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos)
3673#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos)
3674#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos)
3675#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos)
3676#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos)
3677#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos)
3679/******************** Bit definition for ADC_JDR3 register ********************/
3680#define ADC_JDR3_JDATA_Pos (0U)
3681#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
3682#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3683#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos)
3684#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos)
3685#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos)
3686#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos)
3687#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos)
3688#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos)
3689#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos)
3690#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos)
3691#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos)
3692#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos)
3693#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos)
3694#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos)
3695#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos)
3696#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos)
3697#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos)
3698#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos)
3699#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos)
3700#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos)
3701#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos)
3702#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos)
3703#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos)
3704#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos)
3705#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos)
3706#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos)
3707#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos)
3708#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos)
3709#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos)
3710#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos)
3711#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos)
3712#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos)
3713#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos)
3714#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos)
3716/******************** Bit definition for ADC_JDR4 register ********************/
3717#define ADC_JDR4_JDATA_Pos (0U)
3718#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
3719#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3720#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos)
3721#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos)
3722#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos)
3723#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos)
3724#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos)
3725#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos)
3726#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos)
3727#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos)
3728#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos)
3729#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos)
3730#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos)
3731#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos)
3732#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos)
3733#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos)
3734#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos)
3735#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos)
3736#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
3737#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos)
3738#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos)
3739#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos)
3740#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos)
3741#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos)
3742#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos)
3743#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos)
3744#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos)
3745#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos)
3746#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos)
3747#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos)
3748#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos)
3749#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos)
3750#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos)
3751#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos)
3753/******************** Bit definition for ADC_AWD2CR register ********************/
3754#define ADC_AWD2CR_AWD2CH_Pos (0U)
3755#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
3756#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
3757#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
3758#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
3759#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
3760#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
3761#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
3762#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
3763#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
3764#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
3765#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
3766#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
3767#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
3768#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
3769#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
3770#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
3771#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
3772#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
3773#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
3774#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
3775#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
3776#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
3778/******************** Bit definition for ADC_AWD3CR register ********************/
3779#define ADC_AWD3CR_AWD3CH_Pos (0U)
3780#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
3781#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
3782#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
3783#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
3784#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
3785#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
3786#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
3787#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
3788#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
3789#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
3790#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
3791#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
3792#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
3793#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
3794#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
3795#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
3796#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
3797#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
3798#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
3799#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
3800#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
3801#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
3803/******************** Bit definition for ADC_DIFSEL register ********************/
3804#define ADC_DIFSEL_DIFSEL_Pos (0U)
3805#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
3806#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
3807#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
3808#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
3809#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
3810#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
3811#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
3812#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
3813#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
3814#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
3815#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
3816#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
3817#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
3818#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
3819#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
3820#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
3821#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
3822#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
3823#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
3824#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
3825#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
3826#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
3828/******************** Bit definition for ADC_CALFACT register ********************/
3829#define ADC_CALFACT_CALFACT_S_Pos (0U)
3830#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
3831#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
3832#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
3833#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
3834#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
3835#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
3836#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
3837#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
3838#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
3839#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
3840#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
3841#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
3842#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
3843#define ADC_CALFACT_CALFACT_D_Pos (16U)
3844#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
3845#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
3846#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
3847#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
3848#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
3849#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
3850#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
3851#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
3852#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
3853#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
3854#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
3855#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
3856#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
3858/******************** Bit definition for ADC_CALFACT2 register ********************/
3859#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3860#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
3861#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk
3862#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
3863#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
3864#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
3865#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
3866#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
3867#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
3868#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
3869#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
3870#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
3871#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
3872#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
3873#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
3874#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
3875#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
3876#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
3877#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
3878#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
3879#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
3880#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
3881#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
3882#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
3883#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
3884#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
3885#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
3886#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3887#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3888#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3889#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3890#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3891#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3893/************************* ADC Common registers *****************************/
3894/******************** Bit definition for ADC_CSR register ********************/
3895#define ADC_CSR_ADRDY_MST_Pos (0U)
3896#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
3897#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
3898#define ADC_CSR_EOSMP_MST_Pos (1U)
3899#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
3900#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
3901#define ADC_CSR_EOC_MST_Pos (2U)
3902#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
3903#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
3904#define ADC_CSR_EOS_MST_Pos (3U)
3905#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
3906#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
3907#define ADC_CSR_OVR_MST_Pos (4U)
3908#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
3909#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
3910#define ADC_CSR_JEOC_MST_Pos (5U)
3911#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
3912#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
3913#define ADC_CSR_JEOS_MST_Pos (6U)
3914#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
3915#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
3916#define ADC_CSR_AWD1_MST_Pos (7U)
3917#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
3918#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
3919#define ADC_CSR_AWD2_MST_Pos (8U)
3920#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
3921#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
3922#define ADC_CSR_AWD3_MST_Pos (9U)
3923#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
3924#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
3925#define ADC_CSR_JQOVF_MST_Pos (10U)
3926#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
3927#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
3928#define ADC_CSR_ADRDY_SLV_Pos (16U)
3929#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
3930#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
3931#define ADC_CSR_EOSMP_SLV_Pos (17U)
3932#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
3933#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
3934#define ADC_CSR_EOC_SLV_Pos (18U)
3935#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
3936#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
3937#define ADC_CSR_EOS_SLV_Pos (19U)
3938#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
3939#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
3940#define ADC_CSR_OVR_SLV_Pos (20U)
3941#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
3942#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
3943#define ADC_CSR_JEOC_SLV_Pos (21U)
3944#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
3945#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
3946#define ADC_CSR_JEOS_SLV_Pos (22U)
3947#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
3948#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
3949#define ADC_CSR_AWD1_SLV_Pos (23U)
3950#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
3951#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
3952#define ADC_CSR_AWD2_SLV_Pos (24U)
3953#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
3954#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
3955#define ADC_CSR_AWD3_SLV_Pos (25U)
3956#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
3957#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
3958#define ADC_CSR_JQOVF_SLV_Pos (26U)
3959#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
3960#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
3962/******************** Bit definition for ADC_CCR register ********************/
3963#define ADC_CCR_DUAL_Pos (0U)
3964#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
3965#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
3966#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
3967#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
3968#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
3969#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
3970#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
3972#define ADC_CCR_DELAY_Pos (8U)
3973#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
3974#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
3975#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
3976#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
3977#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
3978#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
3981#define ADC_CCR_DAMDF_Pos (14U)
3982#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos)
3983#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk
3984#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos)
3985#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos)
3987#define ADC_CCR_CKMODE_Pos (16U)
3988#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
3989#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
3990#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
3991#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
3993#define ADC_CCR_PRESC_Pos (18U)
3994#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
3995#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
3996#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
3997#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
3998#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
3999#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
4001#define ADC_CCR_VREFEN_Pos (22U)
4002#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
4003#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
4004#define ADC_CCR_TSEN_Pos (23U)
4005#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
4006#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
4007#define ADC_CCR_VBATEN_Pos (24U)
4008#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
4009#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
4011/******************** Bit definition for ADC_CDR register *******************/
4012#define ADC_CDR_RDATA_MST_Pos (0U)
4013#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
4014#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
4016#define ADC_CDR_RDATA_SLV_Pos (16U)
4017#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
4018#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
4020/******************** Bit definition for ADC_CDR2 register ******************/
4021#define ADC_CDR2_RDATA_ALT_Pos (0U)
4022#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
4023#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk
4026/******************************************************************************/
4027/* */
4028/* VREFBUF */
4029/* */
4030/******************************************************************************/
4031/******************* Bit definition for VREFBUF_CSR register ****************/
4032#define VREFBUF_CSR_ENVR_Pos (0U)
4033#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
4034#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
4035#define VREFBUF_CSR_HIZ_Pos (1U)
4036#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
4037#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
4038#define VREFBUF_CSR_VRR_Pos (3U)
4039#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
4040#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
4041#define VREFBUF_CSR_VRS_Pos (4U)
4042#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos)
4043#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
4045#define VREFBUF_CSR_VRS_OUT1 (0U)
4046#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4047#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
4048#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk
4049#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4050#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
4051#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk
4052#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4053#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
4054#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk
4056/******************* Bit definition for VREFBUF_CCR register ****************/
4057#define VREFBUF_CCR_TRIM_Pos (0U)
4058#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
4059#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
4061/******************************************************************************/
4062/* */
4063/* Flexible Datarate Controller Area Network */
4064/* */
4065/******************************************************************************/
4067/***************** Bit definition for FDCAN_CREL register *******************/
4068#define FDCAN_CREL_DAY_Pos (0U)
4069#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
4070#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
4071#define FDCAN_CREL_MON_Pos (8U)
4072#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
4073#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
4074#define FDCAN_CREL_YEAR_Pos (16U)
4075#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
4076#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
4077#define FDCAN_CREL_SUBSTEP_Pos (20U)
4078#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
4079#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
4080#define FDCAN_CREL_STEP_Pos (24U)
4081#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
4082#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
4083#define FDCAN_CREL_REL_Pos (28U)
4084#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
4085#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
4087/***************** Bit definition for FDCAN_ENDN register *******************/
4088#define FDCAN_ENDN_ETV_Pos (0U)
4089#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
4090#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
4092/***************** Bit definition for FDCAN_DBTP register *******************/
4093#define FDCAN_DBTP_DSJW_Pos (0U)
4094#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
4095#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
4096#define FDCAN_DBTP_DTSEG2_Pos (4U)
4097#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
4098#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
4099#define FDCAN_DBTP_DTSEG1_Pos (8U)
4100#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
4101#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
4102#define FDCAN_DBTP_DBRP_Pos (16U)
4103#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
4104#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
4105#define FDCAN_DBTP_TDC_Pos (23U)
4106#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
4107#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
4109/***************** Bit definition for FDCAN_TEST register *******************/
4110#define FDCAN_TEST_LBCK_Pos (4U)
4111#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
4112#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
4113#define FDCAN_TEST_TX_Pos (5U)
4114#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4115#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4116#define FDCAN_TEST_RX_Pos (7U)
4117#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4118#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4120/***************** Bit definition for FDCAN_RWD register ********************/
4121#define FDCAN_RWD_WDC_Pos (0U)
4122#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4123#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4124#define FDCAN_RWD_WDV_Pos (8U)
4125#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4126#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4128/***************** Bit definition for FDCAN_CCCR register ********************/
4129#define FDCAN_CCCR_INIT_Pos (0U)
4130#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4131#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4132#define FDCAN_CCCR_CCE_Pos (1U)
4133#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4134#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4135#define FDCAN_CCCR_ASM_Pos (2U)
4136#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4137#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4138#define FDCAN_CCCR_CSA_Pos (3U)
4139#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4140#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4141#define FDCAN_CCCR_CSR_Pos (4U)
4142#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4143#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4144#define FDCAN_CCCR_MON_Pos (5U)
4145#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4146#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4147#define FDCAN_CCCR_DAR_Pos (6U)
4148#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4149#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4150#define FDCAN_CCCR_TEST_Pos (7U)
4151#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4152#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4153#define FDCAN_CCCR_FDOE_Pos (8U)
4154#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4155#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4156#define FDCAN_CCCR_BRSE_Pos (9U)
4157#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4158#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4159#define FDCAN_CCCR_PXHD_Pos (12U)
4160#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4161#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4162#define FDCAN_CCCR_EFBI_Pos (13U)
4163#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4164#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4165#define FDCAN_CCCR_TXP_Pos (14U)
4166#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4167#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4168#define FDCAN_CCCR_NISO_Pos (15U)
4169#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4170#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4172/***************** Bit definition for FDCAN_NBTP register ********************/
4173#define FDCAN_NBTP_NTSEG2_Pos (0U)
4174#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4175#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4176#define FDCAN_NBTP_NTSEG1_Pos (8U)
4177#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4178#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4179#define FDCAN_NBTP_NBRP_Pos (16U)
4180#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4181#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4182#define FDCAN_NBTP_NSJW_Pos (25U)
4183#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4184#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4186/***************** Bit definition for FDCAN_TSCC register ********************/
4187#define FDCAN_TSCC_TSS_Pos (0U)
4188#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4189#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4190#define FDCAN_TSCC_TCP_Pos (16U)
4191#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4192#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4194/***************** Bit definition for FDCAN_TSCV register ********************/
4195#define FDCAN_TSCV_TSC_Pos (0U)
4196#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4197#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4199/***************** Bit definition for FDCAN_TOCC register ********************/
4200#define FDCAN_TOCC_ETOC_Pos (0U)
4201#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4202#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4203#define FDCAN_TOCC_TOS_Pos (1U)
4204#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4205#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4206#define FDCAN_TOCC_TOP_Pos (16U)
4207#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4208#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4210/***************** Bit definition for FDCAN_TOCV register ********************/
4211#define FDCAN_TOCV_TOC_Pos (0U)
4212#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4213#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4215/***************** Bit definition for FDCAN_ECR register *********************/
4216#define FDCAN_ECR_TEC_Pos (0U)
4217#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4218#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4219#define FDCAN_ECR_REC_Pos (8U)
4220#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4221#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4222#define FDCAN_ECR_RP_Pos (15U)
4223#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4224#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4225#define FDCAN_ECR_CEL_Pos (16U)
4226#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4227#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4229/***************** Bit definition for FDCAN_PSR register *********************/
4230#define FDCAN_PSR_LEC_Pos (0U)
4231#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4232#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4233#define FDCAN_PSR_ACT_Pos (3U)
4234#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4235#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4236#define FDCAN_PSR_EP_Pos (5U)
4237#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4238#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4239#define FDCAN_PSR_EW_Pos (6U)
4240#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4241#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4242#define FDCAN_PSR_BO_Pos (7U)
4243#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4244#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4245#define FDCAN_PSR_DLEC_Pos (8U)
4246#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4247#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4248#define FDCAN_PSR_RESI_Pos (11U)
4249#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4250#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4251#define FDCAN_PSR_RBRS_Pos (12U)
4252#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4253#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4254#define FDCAN_PSR_REDL_Pos (13U)
4255#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4256#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4257#define FDCAN_PSR_PXE_Pos (14U)
4258#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4259#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4260#define FDCAN_PSR_TDCV_Pos (16U)
4261#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4262#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4264/***************** Bit definition for FDCAN_TDCR register ********************/
4265#define FDCAN_TDCR_TDCF_Pos (0U)
4266#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4267#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4268#define FDCAN_TDCR_TDCO_Pos (8U)
4269#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4270#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4272/***************** Bit definition for FDCAN_IR register **********************/
4273#define FDCAN_IR_RF0N_Pos (0U)
4274#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4275#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4276#define FDCAN_IR_RF0W_Pos (1U)
4277#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos)
4278#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk
4279#define FDCAN_IR_RF0F_Pos (2U)
4280#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4281#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4282#define FDCAN_IR_RF0L_Pos (3U)
4283#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4284#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4285#define FDCAN_IR_RF1N_Pos (4U)
4286#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4287#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4288#define FDCAN_IR_RF1W_Pos (5U)
4289#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos)
4290#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk
4291#define FDCAN_IR_RF1F_Pos (6U)
4292#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4293#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4294#define FDCAN_IR_RF1L_Pos (7U)
4295#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4296#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4297#define FDCAN_IR_HPM_Pos (8U)
4298#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4299#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4300#define FDCAN_IR_TC_Pos (9U)
4301#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4302#define FDCAN_IR_TC FDCAN_IR_TC_Msk
4303#define FDCAN_IR_TCF_Pos (10U)
4304#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4305#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4306#define FDCAN_IR_TFE_Pos (11U)
4307#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4308#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4309#define FDCAN_IR_TEFN_Pos (12U)
4310#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4311#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4312#define FDCAN_IR_TEFW_Pos (13U)
4313#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos)
4314#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk
4315#define FDCAN_IR_TEFF_Pos (14U)
4316#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4317#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4318#define FDCAN_IR_TEFL_Pos (15U)
4319#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4320#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4321#define FDCAN_IR_TSW_Pos (16U)
4322#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4323#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4324#define FDCAN_IR_MRAF_Pos (17U)
4325#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4326#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4327#define FDCAN_IR_TOO_Pos (18U)
4328#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4329#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4330#define FDCAN_IR_DRX_Pos (19U)
4331#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos)
4332#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk
4333#define FDCAN_IR_ELO_Pos (22U)
4334#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4335#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4336#define FDCAN_IR_EP_Pos (23U)
4337#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4338#define FDCAN_IR_EP FDCAN_IR_EP_Msk
4339#define FDCAN_IR_EW_Pos (24U)
4340#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4341#define FDCAN_IR_EW FDCAN_IR_EW_Msk
4342#define FDCAN_IR_BO_Pos (25U)
4343#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4344#define FDCAN_IR_BO FDCAN_IR_BO_Msk
4345#define FDCAN_IR_WDI_Pos (26U)
4346#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4347#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4348#define FDCAN_IR_PEA_Pos (27U)
4349#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4350#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4351#define FDCAN_IR_PED_Pos (28U)
4352#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4353#define FDCAN_IR_PED FDCAN_IR_PED_Msk
4354#define FDCAN_IR_ARA_Pos (29U)
4355#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4356#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4358/***************** Bit definition for FDCAN_IE register **********************/
4359#define FDCAN_IE_RF0NE_Pos (0U)
4360#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4361#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4362#define FDCAN_IE_RF0WE_Pos (1U)
4363#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos)
4364#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk
4365#define FDCAN_IE_RF0FE_Pos (2U)
4366#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4367#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4368#define FDCAN_IE_RF0LE_Pos (3U)
4369#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4370#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4371#define FDCAN_IE_RF1NE_Pos (4U)
4372#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4373#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4374#define FDCAN_IE_RF1WE_Pos (5U)
4375#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos)
4376#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
4377#define FDCAN_IE_RF1FE_Pos (6U)
4378#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4379#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4380#define FDCAN_IE_RF1LE_Pos (7U)
4381#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4382#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4383#define FDCAN_IE_HPME_Pos (8U)
4384#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4385#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4386#define FDCAN_IE_TCE_Pos (9U)
4387#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4388#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4389#define FDCAN_IE_TCFE_Pos (10U)
4390#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4391#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4392#define FDCAN_IE_TFEE_Pos (11U)
4393#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4394#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4395#define FDCAN_IE_TEFNE_Pos (12U)
4396#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4397#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4398#define FDCAN_IE_TEFWE_Pos (13U)
4399#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos)
4400#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk
4401#define FDCAN_IE_TEFFE_Pos (14U)
4402#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4403#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4404#define FDCAN_IE_TEFLE_Pos (15U)
4405#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4406#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4407#define FDCAN_IE_TSWE_Pos (16U)
4408#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4409#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4410#define FDCAN_IE_MRAFE_Pos (17U)
4411#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4412#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4413#define FDCAN_IE_TOOE_Pos (18U)
4414#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4415#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4416#define FDCAN_IE_DRXE_Pos (19U)
4417#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos)
4418#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk
4419#define FDCAN_IE_BECE_Pos (20U)
4420#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos)
4421#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk
4422#define FDCAN_IE_BEUE_Pos (21U)
4423#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos)
4424#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk
4425#define FDCAN_IE_ELOE_Pos (22U)
4426#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4427#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4428#define FDCAN_IE_EPE_Pos (23U)
4429#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4430#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4431#define FDCAN_IE_EWE_Pos (24U)
4432#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4433#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4434#define FDCAN_IE_BOE_Pos (25U)
4435#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4436#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4437#define FDCAN_IE_WDIE_Pos (26U)
4438#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4439#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4440#define FDCAN_IE_PEAE_Pos (27U)
4441#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4442#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4443#define FDCAN_IE_PEDE_Pos (28U)
4444#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4445#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4446#define FDCAN_IE_ARAE_Pos (29U)
4447#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4448#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4450/***************** Bit definition for FDCAN_ILS register **********************/
4451#define FDCAN_ILS_RF0NL_Pos (0U)
4452#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos)
4453#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk
4454#define FDCAN_ILS_RF0WL_Pos (1U)
4455#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos)
4456#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk
4457#define FDCAN_ILS_RF0FL_Pos (2U)
4458#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos)
4459#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk
4460#define FDCAN_ILS_RF0LL_Pos (3U)
4461#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos)
4462#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk
4463#define FDCAN_ILS_RF1NL_Pos (4U)
4464#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos)
4465#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk
4466#define FDCAN_ILS_RF1WL_Pos (5U)
4467#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos)
4468#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk
4469#define FDCAN_ILS_RF1FL_Pos (6U)
4470#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos)
4471#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk
4472#define FDCAN_ILS_RF1LL_Pos (7U)
4473#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos)
4474#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk
4475#define FDCAN_ILS_HPML_Pos (8U)
4476#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos)
4477#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk
4478#define FDCAN_ILS_TCL_Pos (9U)
4479#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos)
4480#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk
4481#define FDCAN_ILS_TCFL_Pos (10U)
4482#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos)
4483#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk
4484#define FDCAN_ILS_TFEL_Pos (11U)
4485#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos)
4486#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk
4487#define FDCAN_ILS_TEFNL_Pos (12U)
4488#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos)
4489#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk
4490#define FDCAN_ILS_TEFWL_Pos (13U)
4491#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos)
4492#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk
4493#define FDCAN_ILS_TEFFL_Pos (14U)
4494#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos)
4495#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk
4496#define FDCAN_ILS_TEFLL_Pos (15U)
4497#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos)
4498#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk
4499#define FDCAN_ILS_TSWL_Pos (16U)
4500#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos)
4501#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk
4502#define FDCAN_ILS_MRAFE_Pos (17U)
4503#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos)
4504#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
4505#define FDCAN_ILS_TOOE_Pos (18U)
4506#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos)
4507#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk
4508#define FDCAN_ILS_DRXE_Pos (19U)
4509#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos)
4510#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk
4511#define FDCAN_ILS_BECE_Pos (20U)
4512#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos)
4513#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk
4514#define FDCAN_ILS_BEUE_Pos (21U)
4515#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos)
4516#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk
4517#define FDCAN_ILS_ELOE_Pos (22U)
4518#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos)
4519#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk
4520#define FDCAN_ILS_EPE_Pos (23U)
4521#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos)
4522#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk
4523#define FDCAN_ILS_EWE_Pos (24U)
4524#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos)
4525#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk
4526#define FDCAN_ILS_BOE_Pos (25U)
4527#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos)
4528#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk
4529#define FDCAN_ILS_WDIE_Pos (26U)
4530#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos)
4531#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk
4532#define FDCAN_ILS_PEAE_Pos (27U)
4533#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos)
4534#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk
4535#define FDCAN_ILS_PEDE_Pos (28U)
4536#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos)
4537#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk
4538#define FDCAN_ILS_ARAE_Pos (29U)
4539#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos)
4540#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk
4542/***************** Bit definition for FDCAN_ILE register **********************/
4543#define FDCAN_ILE_EINT0_Pos (0U)
4544#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4545#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4546#define FDCAN_ILE_EINT1_Pos (1U)
4547#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4548#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4550/***************** Bit definition for FDCAN_GFC register **********************/
4551#define FDCAN_GFC_RRFE_Pos (0U)
4552#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos)
4553#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk
4554#define FDCAN_GFC_RRFS_Pos (1U)
4555#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos)
4556#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk
4557#define FDCAN_GFC_ANFE_Pos (2U)
4558#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos)
4559#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk
4560#define FDCAN_GFC_ANFS_Pos (4U)
4561#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos)
4562#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk
4564/***************** Bit definition for FDCAN_SIDFC register ********************/
4565#define FDCAN_SIDFC_FLSSA_Pos (2U)
4566#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
4567#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk
4568#define FDCAN_SIDFC_LSS_Pos (16U)
4569#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos)
4570#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk
4572/***************** Bit definition for FDCAN_XIDFC register ********************/
4573#define FDCAN_XIDFC_FLESA_Pos (2U)
4574#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
4575#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk
4576#define FDCAN_XIDFC_LSE_Pos (16U)
4577#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos)
4578#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk
4580/***************** Bit definition for FDCAN_XIDAM register ********************/
4581#define FDCAN_XIDAM_EIDM_Pos (0U)
4582#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4583#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4585/***************** Bit definition for FDCAN_HPMS register *********************/
4586#define FDCAN_HPMS_BIDX_Pos (0U)
4587#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos)
4588#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4589#define FDCAN_HPMS_MSI_Pos (6U)
4590#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4591#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4592#define FDCAN_HPMS_FIDX_Pos (8U)
4593#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos)
4594#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4595#define FDCAN_HPMS_FLST_Pos (15U)
4596#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4597#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4599/***************** Bit definition for FDCAN_NDAT1 register ********************/
4600#define FDCAN_NDAT1_ND0_Pos (0U)
4601#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos)
4602#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk
4603#define FDCAN_NDAT1_ND1_Pos (1U)
4604#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos)
4605#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk
4606#define FDCAN_NDAT1_ND2_Pos (2U)
4607#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos)
4608#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk
4609#define FDCAN_NDAT1_ND3_Pos (3U)
4610#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos)
4611#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk
4612#define FDCAN_NDAT1_ND4_Pos (4U)
4613#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos)
4614#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk
4615#define FDCAN_NDAT1_ND5_Pos (5U)
4616#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos)
4617#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk
4618#define FDCAN_NDAT1_ND6_Pos (6U)
4619#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos)
4620#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk
4621#define FDCAN_NDAT1_ND7_Pos (7U)
4622#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos)
4623#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk
4624#define FDCAN_NDAT1_ND8_Pos (8U)
4625#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos)
4626#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk
4627#define FDCAN_NDAT1_ND9_Pos (9U)
4628#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos)
4629#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk
4630#define FDCAN_NDAT1_ND10_Pos (10U)
4631#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos)
4632#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
4633#define FDCAN_NDAT1_ND11_Pos (11U)
4634#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos)
4635#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk
4636#define FDCAN_NDAT1_ND12_Pos (12U)
4637#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos)
4638#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk
4639#define FDCAN_NDAT1_ND13_Pos (13U)
4640#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos)
4641#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk
4642#define FDCAN_NDAT1_ND14_Pos (14U)
4643#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos)
4644#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk
4645#define FDCAN_NDAT1_ND15_Pos (15U)
4646#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos)
4647#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk
4648#define FDCAN_NDAT1_ND16_Pos (16U)
4649#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos)
4650#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk
4651#define FDCAN_NDAT1_ND17_Pos (17U)
4652#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos)
4653#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk
4654#define FDCAN_NDAT1_ND18_Pos (18U)
4655#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos)
4656#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk
4657#define FDCAN_NDAT1_ND19_Pos (19U)
4658#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos)
4659#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk
4660#define FDCAN_NDAT1_ND20_Pos (20U)
4661#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos)
4662#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk
4663#define FDCAN_NDAT1_ND21_Pos (21U)
4664#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos)
4665#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk
4666#define FDCAN_NDAT1_ND22_Pos (22U)
4667#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos)
4668#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk
4669#define FDCAN_NDAT1_ND23_Pos (23U)
4670#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos)
4671#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk
4672#define FDCAN_NDAT1_ND24_Pos (24U)
4673#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos)
4674#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk
4675#define FDCAN_NDAT1_ND25_Pos (25U)
4676#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos)
4677#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk
4678#define FDCAN_NDAT1_ND26_Pos (26U)
4679#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos)
4680#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk
4681#define FDCAN_NDAT1_ND27_Pos (27U)
4682#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos)
4683#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk
4684#define FDCAN_NDAT1_ND28_Pos (28U)
4685#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos)
4686#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk
4687#define FDCAN_NDAT1_ND29_Pos (29U)
4688#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos)
4689#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk
4690#define FDCAN_NDAT1_ND30_Pos (30U)
4691#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos)
4692#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk
4693#define FDCAN_NDAT1_ND31_Pos (31U)
4694#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos)
4695#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk
4697/***************** Bit definition for FDCAN_NDAT2 register ********************/
4698#define FDCAN_NDAT2_ND32_Pos (0U)
4699#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos)
4700#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk
4701#define FDCAN_NDAT2_ND33_Pos (1U)
4702#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos)
4703#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk
4704#define FDCAN_NDAT2_ND34_Pos (2U)
4705#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos)
4706#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk
4707#define FDCAN_NDAT2_ND35_Pos (3U)
4708#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos)
4709#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk
4710#define FDCAN_NDAT2_ND36_Pos (4U)
4711#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos)
4712#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk
4713#define FDCAN_NDAT2_ND37_Pos (5U)
4714#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos)
4715#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk
4716#define FDCAN_NDAT2_ND38_Pos (6U)
4717#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos)
4718#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk
4719#define FDCAN_NDAT2_ND39_Pos (7U)
4720#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos)
4721#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk
4722#define FDCAN_NDAT2_ND40_Pos (8U)
4723#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos)
4724#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk
4725#define FDCAN_NDAT2_ND41_Pos (9U)
4726#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos)
4727#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk
4728#define FDCAN_NDAT2_ND42_Pos (10U)
4729#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos)
4730#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk
4731#define FDCAN_NDAT2_ND43_Pos (11U)
4732#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos)
4733#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk
4734#define FDCAN_NDAT2_ND44_Pos (12U)
4735#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos)
4736#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk
4737#define FDCAN_NDAT2_ND45_Pos (13U)
4738#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos)
4739#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk
4740#define FDCAN_NDAT2_ND46_Pos (14U)
4741#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos)
4742#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk
4743#define FDCAN_NDAT2_ND47_Pos (15U)
4744#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos)
4745#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk
4746#define FDCAN_NDAT2_ND48_Pos (16U)
4747#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos)
4748#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk
4749#define FDCAN_NDAT2_ND49_Pos (17U)
4750#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos)
4751#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk
4752#define FDCAN_NDAT2_ND50_Pos (18U)
4753#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos)
4754#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk
4755#define FDCAN_NDAT2_ND51_Pos (19U)
4756#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos)
4757#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk
4758#define FDCAN_NDAT2_ND52_Pos (20U)
4759#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos)
4760#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
4761#define FDCAN_NDAT2_ND53_Pos (21U)
4762#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos)
4763#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk
4764#define FDCAN_NDAT2_ND54_Pos (22U)
4765#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos)
4766#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk
4767#define FDCAN_NDAT2_ND55_Pos (23U)
4768#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos)
4769#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk
4770#define FDCAN_NDAT2_ND56_Pos (24U)
4771#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos)
4772#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk
4773#define FDCAN_NDAT2_ND57_Pos (25U)
4774#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos)
4775#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk
4776#define FDCAN_NDAT2_ND58_Pos (26U)
4777#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos)
4778#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk
4779#define FDCAN_NDAT2_ND59_Pos (27U)
4780#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos)
4781#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk
4782#define FDCAN_NDAT2_ND60_Pos (28U)
4783#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos)
4784#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk
4785#define FDCAN_NDAT2_ND61_Pos (29U)
4786#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos)
4787#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk
4788#define FDCAN_NDAT2_ND62_Pos (30U)
4789#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos)
4790#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk
4791#define FDCAN_NDAT2_ND63_Pos (31U)
4792#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos)
4793#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk
4795/***************** Bit definition for FDCAN_RXF0C register ********************/
4796#define FDCAN_RXF0C_F0SA_Pos (2U)
4797#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
4798#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk
4799#define FDCAN_RXF0C_F0S_Pos (16U)
4800#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos)
4801#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk
4802#define FDCAN_RXF0C_F0WM_Pos (24U)
4803#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
4804#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk
4805#define FDCAN_RXF0C_F0OM_Pos (31U)
4806#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos)
4807#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk
4809/***************** Bit definition for FDCAN_RXF0S register ********************/
4810#define FDCAN_RXF0S_F0FL_Pos (0U)
4811#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
4812#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
4813#define FDCAN_RXF0S_F0GI_Pos (8U)
4814#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
4815#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
4816#define FDCAN_RXF0S_F0PI_Pos (16U)
4817#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
4818#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
4819#define FDCAN_RXF0S_F0F_Pos (24U)
4820#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
4821#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
4822#define FDCAN_RXF0S_RF0L_Pos (25U)
4823#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
4824#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
4826/***************** Bit definition for FDCAN_RXF0A register ********************/
4827#define FDCAN_RXF0A_F0AI_Pos (0U)
4828#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
4829#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
4831/***************** Bit definition for FDCAN_RXBC register ********************/
4832#define FDCAN_RXBC_RBSA_Pos (2U)
4833#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
4834#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk
4836/***************** Bit definition for FDCAN_RXF1C register ********************/
4837#define FDCAN_RXF1C_F1SA_Pos (2U)
4838#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
4839#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk
4840#define FDCAN_RXF1C_F1S_Pos (16U)
4841#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos)
4842#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk
4843#define FDCAN_RXF1C_F1WM_Pos (24U)
4844#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
4845#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk
4846#define FDCAN_RXF1C_F1OM_Pos (31U)
4847#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos)
4848#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk
4850/***************** Bit definition for FDCAN_RXF1S register ********************/
4851#define FDCAN_RXF1S_F1FL_Pos (0U)
4852#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
4853#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
4854#define FDCAN_RXF1S_F1GI_Pos (8U)
4855#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
4856#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
4857#define FDCAN_RXF1S_F1PI_Pos (16U)
4858#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
4859#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
4860#define FDCAN_RXF1S_F1F_Pos (24U)
4861#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
4862#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
4863#define FDCAN_RXF1S_RF1L_Pos (25U)
4864#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
4865#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
4867/***************** Bit definition for FDCAN_RXF1A register ********************/
4868#define FDCAN_RXF1A_F1AI_Pos (0U)
4869#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
4870#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
4872/***************** Bit definition for FDCAN_RXESC register ********************/
4873#define FDCAN_RXESC_F0DS_Pos (0U)
4874#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos)
4875#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk
4876#define FDCAN_RXESC_F1DS_Pos (4U)
4877#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos)
4878#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk
4879#define FDCAN_RXESC_RBDS_Pos (8U)
4880#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos)
4881#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk
4883/***************** Bit definition for FDCAN_TXBC register *********************/
4884#define FDCAN_TXBC_TBSA_Pos (2U)
4885#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
4886#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk
4887#define FDCAN_TXBC_NDTB_Pos (16U)
4888#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
4889#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk
4890#define FDCAN_TXBC_TFQS_Pos (24U)
4891#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos)
4892#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk
4893#define FDCAN_TXBC_TFQM_Pos (30U)
4894#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
4895#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
4897/***************** Bit definition for FDCAN_TXFQS register *********************/
4898#define FDCAN_TXFQS_TFFL_Pos (0U)
4899#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
4900#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
4901#define FDCAN_TXFQS_TFGI_Pos (8U)
4902#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
4903#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
4904#define FDCAN_TXFQS_TFQPI_Pos (16U)
4905#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
4906#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
4907#define FDCAN_TXFQS_TFQF_Pos (21U)
4908#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
4909#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
4911/***************** Bit definition for FDCAN_TXESC register *********************/
4912#define FDCAN_TXESC_TBDS_Pos (0U)
4913#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos)
4914#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk
4916/***************** Bit definition for FDCAN_TXBRP register *********************/
4917#define FDCAN_TXBRP_TRP_Pos (0U)
4918#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
4919#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
4921/***************** Bit definition for FDCAN_TXBAR register *********************/
4922#define FDCAN_TXBAR_AR_Pos (0U)
4923#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
4924#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
4926/***************** Bit definition for FDCAN_TXBCR register *********************/
4927#define FDCAN_TXBCR_CR_Pos (0U)
4928#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
4929#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
4931/***************** Bit definition for FDCAN_TXBTO register *********************/
4932#define FDCAN_TXBTO_TO_Pos (0U)
4933#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
4934#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
4936/***************** Bit definition for FDCAN_TXBCF register *********************/
4937#define FDCAN_TXBCF_CF_Pos (0U)
4938#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
4939#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
4941/***************** Bit definition for FDCAN_TXBTIE register ********************/
4942#define FDCAN_TXBTIE_TIE_Pos (0U)
4943#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
4944#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
4946/***************** Bit definition for FDCAN_ TXBCIE register *******************/
4947#define FDCAN_TXBCIE_CFIE_Pos (0U)
4948#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
4949#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
4951/***************** Bit definition for FDCAN_TXEFC register *********************/
4952#define FDCAN_TXEFC_EFSA_Pos (2U)
4953#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
4954#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk
4955#define FDCAN_TXEFC_EFS_Pos (16U)
4956#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos)
4957#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk
4958#define FDCAN_TXEFC_EFWM_Pos (24U)
4959#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
4960#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk
4962/***************** Bit definition for FDCAN_TXEFS register *********************/
4963#define FDCAN_TXEFS_EFFL_Pos (0U)
4964#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
4965#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
4966#define FDCAN_TXEFS_EFGI_Pos (8U)
4967#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
4968#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
4969#define FDCAN_TXEFS_EFPI_Pos (16U)
4970#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
4971#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
4972#define FDCAN_TXEFS_EFF_Pos (24U)
4973#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
4974#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
4975#define FDCAN_TXEFS_TEFL_Pos (25U)
4976#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
4977#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
4979/***************** Bit definition for FDCAN_TXEFA register *********************/
4980#define FDCAN_TXEFA_EFAI_Pos (0U)
4981#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
4982#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
4984/***************** Bit definition for FDCAN_TTTMC register *********************/
4985#define FDCAN_TTTMC_TMSA_Pos (2U)
4986#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
4987#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk
4988#define FDCAN_TTTMC_TME_Pos (16U)
4989#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos)
4990#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk
4992/***************** Bit definition for FDCAN_TTRMC register *********************/
4993#define FDCAN_TTRMC_RID_Pos (0U)
4994#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
4995#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk
4996#define FDCAN_TTRMC_XTD_Pos (30U)
4997#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos)
4998#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk
4999#define FDCAN_TTRMC_RMPS_Pos (31U)
5000#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos)
5001#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk
5003/***************** Bit definition for FDCAN_TTOCF register *********************/
5004#define FDCAN_TTOCF_OM_Pos (0U)
5005#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos)
5006#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk
5007#define FDCAN_TTOCF_GEN_Pos (3U)
5008#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos)
5009#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk
5010#define FDCAN_TTOCF_TM_Pos (4U)
5011#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos)
5012#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk
5013#define FDCAN_TTOCF_LDSDL_Pos (5U)
5014#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
5015#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk
5016#define FDCAN_TTOCF_IRTO_Pos (8U)
5017#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
5018#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk
5019#define FDCAN_TTOCF_EECS_Pos (15U)
5020#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos)
5021#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk
5022#define FDCAN_TTOCF_AWL_Pos (16U)
5023#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos)
5024#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk
5025#define FDCAN_TTOCF_EGTF_Pos (24U)
5026#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos)
5027#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk
5028#define FDCAN_TTOCF_ECC_Pos (25U)
5029#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos)
5030#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk
5031#define FDCAN_TTOCF_EVTP_Pos (26U)
5032#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos)
5033#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk
5035/***************** Bit definition for FDCAN_TTMLM register *********************/
5036#define FDCAN_TTMLM_CCM_Pos (0U)
5037#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos)
5038#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk
5039#define FDCAN_TTMLM_CSS_Pos (6U)
5040#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos)
5041#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk
5042#define FDCAN_TTMLM_TXEW_Pos (8U)
5043#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos)
5044#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk
5045#define FDCAN_TTMLM_ENTT_Pos (16U)
5046#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
5047#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk
5049/***************** Bit definition for FDCAN_TURCF register *********************/
5050#define FDCAN_TURCF_NCL_Pos (0U)
5051#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
5052#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk
5053#define FDCAN_TURCF_DC_Pos (16U)
5054#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos)
5055#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk
5056#define FDCAN_TURCF_ELT_Pos (31U)
5057#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos)
5058#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk
5060/***************** Bit definition for FDCAN_TTOCN register ********************/
5061#define FDCAN_TTOCN_SGT_Pos (0U)
5062#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos)
5063#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk
5064#define FDCAN_TTOCN_ECS_Pos (1U)
5065#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos)
5066#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk
5067#define FDCAN_TTOCN_SWP_Pos (2U)
5068#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos)
5069#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk
5070#define FDCAN_TTOCN_SWS_Pos (3U)
5071#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos)
5072#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk
5073#define FDCAN_TTOCN_RTIE_Pos (5U)
5074#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos)
5075#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk
5076#define FDCAN_TTOCN_TMC_Pos (6U)
5077#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos)
5078#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk
5079#define FDCAN_TTOCN_TTIE_Pos (8U)
5080#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos)
5081#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk
5082#define FDCAN_TTOCN_GCS_Pos (9U)
5083#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos)
5084#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk
5085#define FDCAN_TTOCN_FGP_Pos (10U)
5086#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos)
5087#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk
5088#define FDCAN_TTOCN_TMG_Pos (11U)
5089#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos)
5090#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk
5091#define FDCAN_TTOCN_NIG_Pos (12U)
5092#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos)
5093#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk
5094#define FDCAN_TTOCN_ESCN_Pos (13U)
5095#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos)
5096#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk
5097#define FDCAN_TTOCN_LCKC_Pos (15U)
5098#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos)
5099#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk
5101/***************** Bit definition for FDCAN_TTGTP register ********************/
5102#define FDCAN_TTGTP_TP_Pos (0U)
5103#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
5104#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk
5105#define FDCAN_TTGTP_CTP_Pos (16U)
5106#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
5107#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk
5109/***************** Bit definition for FDCAN_TTTMK register ********************/
5110#define FDCAN_TTTMK_TM_Pos (0U)
5111#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
5112#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk
5113#define FDCAN_TTTMK_TICC_Pos (16U)
5114#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos)
5115#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk
5116#define FDCAN_TTTMK_LCKM_Pos (31U)
5117#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos)
5118#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk
5120/***************** Bit definition for FDCAN_TTIR register ********************/
5121#define FDCAN_TTIR_SBC_Pos (0U)
5122#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos)
5123#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk
5124#define FDCAN_TTIR_SMC_Pos (1U)
5125#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos)
5126#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk
5127#define FDCAN_TTIR_CSM_Pos (2U)
5128#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos)
5129#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk
5130#define FDCAN_TTIR_SOG_Pos (3U)
5131#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos)
5132#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk
5133#define FDCAN_TTIR_RTMI_Pos (4U)
5134#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos)
5135#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk
5136#define FDCAN_TTIR_TTMI_Pos (5U)
5137#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos)
5138#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk
5139#define FDCAN_TTIR_SWE_Pos (6U)
5140#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos)
5141#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk
5142#define FDCAN_TTIR_GTW_Pos (7U)
5143#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos)
5144#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
5145#define FDCAN_TTIR_GTD_Pos (8U)
5146#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos)
5147#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk
5148#define FDCAN_TTIR_GTE_Pos (9U)
5149#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos)
5150#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk
5151#define FDCAN_TTIR_TXU_Pos (10U)
5152#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos)
5153#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk
5154#define FDCAN_TTIR_TXO_Pos (11U)
5155#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos)
5156#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk
5157#define FDCAN_TTIR_SE1_Pos (12U)
5158#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos)
5159#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk
5160#define FDCAN_TTIR_SE2_Pos (13U)
5161#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos)
5162#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk
5163#define FDCAN_TTIR_ELC_Pos (14U)
5164#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos)
5165#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk
5166#define FDCAN_TTIR_IWT_Pos (15U)
5167#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos)
5168#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk
5169#define FDCAN_TTIR_WT_Pos (16U)
5170#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos)
5171#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk
5172#define FDCAN_TTIR_AW_Pos (17U)
5173#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos)
5174#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk
5175#define FDCAN_TTIR_CER_Pos (18U)
5176#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos)
5177#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk
5179/***************** Bit definition for FDCAN_TTIE register ********************/
5180#define FDCAN_TTIE_SBCE_Pos (0U)
5181#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos)
5182#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk
5183#define FDCAN_TTIE_SMCE_Pos (1U)
5184#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos)
5185#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk
5186#define FDCAN_TTIE_CSME_Pos (2U)
5187#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos)
5188#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk
5189#define FDCAN_TTIE_SOGE_Pos (3U)
5190#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos)
5191#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk
5192#define FDCAN_TTIE_RTMIE_Pos (4U)
5193#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos)
5194#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk
5195#define FDCAN_TTIE_TTMIE_Pos (5U)
5196#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos)
5197#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk
5198#define FDCAN_TTIE_SWEE_Pos (6U)
5199#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos)
5200#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk
5201#define FDCAN_TTIE_GTWE_Pos (7U)
5202#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos)
5203#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk
5204#define FDCAN_TTIE_GTDE_Pos (8U)
5205#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos)
5206#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk
5207#define FDCAN_TTIE_GTEE_Pos (9U)
5208#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos)
5209#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk
5210#define FDCAN_TTIE_TXUE_Pos (10U)
5211#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos)
5212#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk
5213#define FDCAN_TTIE_TXOE_Pos (11U)
5214#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos)
5215#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk
5216#define FDCAN_TTIE_SE1E_Pos (12U)
5217#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos)
5218#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk
5219#define FDCAN_TTIE_SE2E_Pos (13U)
5220#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos)
5221#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk
5222#define FDCAN_TTIE_ELCE_Pos (14U)
5223#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos)
5224#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk
5225#define FDCAN_TTIE_IWTE_Pos (15U)
5226#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos)
5227#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk
5228#define FDCAN_TTIE_WTE_Pos (16U)
5229#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos)
5230#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk
5231#define FDCAN_TTIE_AWE_Pos (17U)
5232#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos)
5233#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk
5234#define FDCAN_TTIE_CERE_Pos (18U)
5235#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos)
5236#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk
5238/***************** Bit definition for FDCAN_TTILS register ********************/
5239#define FDCAN_TTILS_SBCS_Pos (0U)
5240#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos)
5241#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk
5242#define FDCAN_TTILS_SMCS_Pos (1U)
5243#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos)
5244#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk
5245#define FDCAN_TTILS_CSMS_Pos (2U)
5246#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos)
5247#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk
5248#define FDCAN_TTILS_SOGS_Pos (3U)
5249#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos)
5250#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk
5251#define FDCAN_TTILS_RTMIS_Pos (4U)
5252#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos)
5253#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk
5254#define FDCAN_TTILS_TTMIS_Pos (5U)
5255#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos)
5256#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk
5257#define FDCAN_TTILS_SWES_Pos (6U)
5258#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos)
5259#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk
5260#define FDCAN_TTILS_GTWS_Pos (7U)
5261#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos)
5262#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk
5263#define FDCAN_TTILS_GTDS_Pos (8U)
5264#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos)
5265#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk
5266#define FDCAN_TTILS_GTES_Pos (9U)
5267#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos)
5268#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk
5269#define FDCAN_TTILS_TXUS_Pos (10U)
5270#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos)
5271#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk
5272#define FDCAN_TTILS_TXOS_Pos (11U)
5273#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos)
5274#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk
5275#define FDCAN_TTILS_SE1S_Pos (12U)
5276#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos)
5277#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk
5278#define FDCAN_TTILS_SE2S_Pos (13U)
5279#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos)
5280#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk
5281#define FDCAN_TTILS_ELCS_Pos (14U)
5282#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos)
5283#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk
5284#define FDCAN_TTILS_IWTS_Pos (15U)
5285#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos)
5286#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk
5287#define FDCAN_TTILS_WTS_Pos (16U)
5288#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos)
5289#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk
5290#define FDCAN_TTILS_AWS_Pos (17U)
5291#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos)
5292#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk
5293#define FDCAN_TTILS_CERS_Pos (18U)
5294#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos)
5295#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk
5297/***************** Bit definition for FDCAN_TTOST register ********************/
5298#define FDCAN_TTOST_EL_Pos (0U)
5299#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos)
5300#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk
5301#define FDCAN_TTOST_MS_Pos (2U)
5302#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos)
5303#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk
5304#define FDCAN_TTOST_SYS_Pos (4U)
5305#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos)
5306#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk
5307#define FDCAN_TTOST_QGTP_Pos (6U)
5308#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos)
5309#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk
5310#define FDCAN_TTOST_QCS_Pos (7U)
5311#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos)
5312#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk
5313#define FDCAN_TTOST_RTO_Pos (8U)
5314#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos)
5315#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk
5316#define FDCAN_TTOST_WGTD_Pos (22U)
5317#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos)
5318#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk
5319#define FDCAN_TTOST_GFI_Pos (23U)
5320#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos)
5321#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk
5322#define FDCAN_TTOST_TMP_Pos (24U)
5323#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos)
5324#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk
5325#define FDCAN_TTOST_GSI_Pos (27U)
5326#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos)
5327#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk
5328#define FDCAN_TTOST_WFE_Pos (28U)
5329#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos)
5330#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk
5331#define FDCAN_TTOST_AWE_Pos (29U)
5332#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos)
5333#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk
5334#define FDCAN_TTOST_WECS_Pos (30U)
5335#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos)
5336#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk
5337#define FDCAN_TTOST_SPL_Pos (31U)
5338#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos)
5339#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk
5341/***************** Bit definition for FDCAN_TURNA register ********************/
5342#define FDCAN_TURNA_NAV_Pos (0U)
5343#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
5344#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk
5346/***************** Bit definition for FDCAN_TTLGT register ********************/
5347#define FDCAN_TTLGT_LT_Pos (0U)
5348#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
5349#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk
5350#define FDCAN_TTLGT_GT_Pos (16U)
5351#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
5352#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk
5354/***************** Bit definition for FDCAN_TTCTC register ********************/
5355#define FDCAN_TTCTC_CT_Pos (0U)
5356#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
5357#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk
5358#define FDCAN_TTCTC_CC_Pos (16U)
5359#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos)
5360#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk
5362/***************** Bit definition for FDCAN_TTCPT register ********************/
5363#define FDCAN_TTCPT_CCV_Pos (0U)
5364#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos)
5365#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk
5366#define FDCAN_TTCPT_SWV_Pos (16U)
5367#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
5368#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk
5370/***************** Bit definition for FDCAN_TTCSM register ********************/
5371#define FDCAN_TTCSM_CSM_Pos (0U)
5372#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
5373#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk
5375/***************** Bit definition for FDCAN_TTTS register *********************/
5376#define FDCAN_TTTS_SWTSEL_Pos (0U)
5377#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
5378#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk
5379#define FDCAN_TTTS_EVTSEL_Pos (4U)
5380#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
5381#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk
5383/********************************************************************************/
5384/* */
5385/* FDCANCCU (Clock Calibration unit) */
5386/* */
5387/********************************************************************************/
5388
5389/***************** Bit definition for FDCANCCU_CREL register ******************/
5390#define FDCANCCU_CREL_DAY_Pos (0U)
5391#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos)
5392#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk
5393#define FDCANCCU_CREL_MON_Pos (8U)
5394#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos)
5395#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk
5396#define FDCANCCU_CREL_YEAR_Pos (16U)
5397#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos)
5398#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk
5399#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5400#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
5401#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk
5402#define FDCANCCU_CREL_STEP_Pos (24U)
5403#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos)
5404#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk
5405#define FDCANCCU_CREL_REL_Pos (28U)
5406#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos)
5407#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk
5409/***************** Bit definition for FDCANCCU_CCFG register ******************/
5410#define FDCANCCU_CCFG_TQBT_Pos (0U)
5411#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
5412#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk
5413#define FDCANCCU_CCFG_BCC_Pos (6U)
5414#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos)
5415#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk
5416#define FDCANCCU_CCFG_CFL_Pos (7U)
5417#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos)
5418#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk
5419#define FDCANCCU_CCFG_OCPM_Pos (8U)
5420#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
5421#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk
5422#define FDCANCCU_CCFG_CDIV_Pos (16U)
5423#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
5424#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk
5425#define FDCANCCU_CCFG_SWR_Pos (31U)
5426#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos)
5427#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk
5429/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5430#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5431#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
5432#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk
5433#define FDCANCCU_CSTAT_TQC_Pos (18U)
5434#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
5435#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk
5436#define FDCANCCU_CSTAT_CALS_Pos (30U)
5437#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
5438#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk
5440/****************** Bit definition for FDCANCCU_CWD register ******************/
5441#define FDCANCCU_CWD_WDC_Pos (0U)
5442#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
5443#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk
5444#define FDCANCCU_CWD_WDV_Pos (16U)
5445#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
5446#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk
5448/****************** Bit definition for FDCANCCU_IR register *******************/
5449#define FDCANCCU_IR_CWE_Pos (0U)
5450#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos)
5451#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk
5452#define FDCANCCU_IR_CSC_Pos (1U)
5453#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos)
5454#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk
5456/****************** Bit definition for FDCANCCU_IE register *******************/
5457#define FDCANCCU_IE_CWEE_Pos (0U)
5458#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos)
5459#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk
5460#define FDCANCCU_IE_CSCE_Pos (1U)
5461#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos)
5462#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk
5464/******************************************************************************/
5465/* */
5466/* HDMI-CEC (CEC) */
5467/* */
5468/******************************************************************************/
5469
5470/******************* Bit definition for CEC_CR register *********************/
5471#define CEC_CR_CECEN_Pos (0U)
5472#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5473#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5474#define CEC_CR_TXSOM_Pos (1U)
5475#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5476#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5477#define CEC_CR_TXEOM_Pos (2U)
5478#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5479#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5481/******************* Bit definition for CEC_CFGR register *******************/
5482#define CEC_CFGR_SFT_Pos (0U)
5483#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5484#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5485#define CEC_CFGR_RXTOL_Pos (3U)
5486#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5487#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5488#define CEC_CFGR_BRESTP_Pos (4U)
5489#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5490#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5491#define CEC_CFGR_BREGEN_Pos (5U)
5492#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5493#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5494#define CEC_CFGR_LBPEGEN_Pos (6U)
5495#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5496#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5497#define CEC_CFGR_SFTOPT_Pos (8U)
5498#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5499#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5500#define CEC_CFGR_BRDNOGEN_Pos (7U)
5501#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5502#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5503#define CEC_CFGR_OAR_Pos (16U)
5504#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5505#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5506#define CEC_CFGR_LSTN_Pos (31U)
5507#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5508#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5510/******************* Bit definition for CEC_TXDR register *******************/
5511#define CEC_TXDR_TXD_Pos (0U)
5512#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5513#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5515/******************* Bit definition for CEC_RXDR register *******************/
5516#define CEC_RXDR_RXD_Pos (0U)
5517#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5518#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5520/******************* Bit definition for CEC_ISR register ********************/
5521#define CEC_ISR_RXBR_Pos (0U)
5522#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5523#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5524#define CEC_ISR_RXEND_Pos (1U)
5525#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5526#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5527#define CEC_ISR_RXOVR_Pos (2U)
5528#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5529#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5530#define CEC_ISR_BRE_Pos (3U)
5531#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5532#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5533#define CEC_ISR_SBPE_Pos (4U)
5534#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5535#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5536#define CEC_ISR_LBPE_Pos (5U)
5537#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5538#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5539#define CEC_ISR_RXACKE_Pos (6U)
5540#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5541#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5542#define CEC_ISR_ARBLST_Pos (7U)
5543#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5544#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5545#define CEC_ISR_TXBR_Pos (8U)
5546#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5547#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5548#define CEC_ISR_TXEND_Pos (9U)
5549#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5550#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5551#define CEC_ISR_TXUDR_Pos (10U)
5552#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5553#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5554#define CEC_ISR_TXERR_Pos (11U)
5555#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5556#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5557#define CEC_ISR_TXACKE_Pos (12U)
5558#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5559#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5561/******************* Bit definition for CEC_IER register ********************/
5562#define CEC_IER_RXBRIE_Pos (0U)
5563#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5564#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5565#define CEC_IER_RXENDIE_Pos (1U)
5566#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5567#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5568#define CEC_IER_RXOVRIE_Pos (2U)
5569#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5570#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5571#define CEC_IER_BREIE_Pos (3U)
5572#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5573#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5574#define CEC_IER_SBPEIE_Pos (4U)
5575#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5576#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5577#define CEC_IER_LBPEIE_Pos (5U)
5578#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5579#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5580#define CEC_IER_RXACKEIE_Pos (6U)
5581#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5582#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5583#define CEC_IER_ARBLSTIE_Pos (7U)
5584#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5585#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5586#define CEC_IER_TXBRIE_Pos (8U)
5587#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5588#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5589#define CEC_IER_TXENDIE_Pos (9U)
5590#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5591#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5592#define CEC_IER_TXUDRIE_Pos (10U)
5593#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5594#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5595#define CEC_IER_TXERRIE_Pos (11U)
5596#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5597#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5598#define CEC_IER_TXACKEIE_Pos (12U)
5599#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5600#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5602/******************************************************************************/
5603/* */
5604/* CRC calculation unit */
5605/* */
5606/******************************************************************************/
5607/******************* Bit definition for CRC_DR register *********************/
5608#define CRC_DR_DR_Pos (0U)
5609#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5610#define CRC_DR_DR CRC_DR_DR_Msk
5612/******************* Bit definition for CRC_IDR register ********************/
5613#define CRC_IDR_IDR_Pos (0U)
5614#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
5615#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5617/******************** Bit definition for CRC_CR register ********************/
5618#define CRC_CR_RESET_Pos (0U)
5619#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5620#define CRC_CR_RESET CRC_CR_RESET_Msk
5621#define CRC_CR_POLYSIZE_Pos (3U)
5622#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5623#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5624#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5625#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5626#define CRC_CR_REV_IN_Pos (5U)
5627#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5628#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5629#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5630#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5631#define CRC_CR_REV_OUT_Pos (7U)
5632#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5633#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5635/******************* Bit definition for CRC_INIT register *******************/
5636#define CRC_INIT_INIT_Pos (0U)
5637#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5638#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5640/******************* Bit definition for CRC_POL register ********************/
5641#define CRC_POL_POL_Pos (0U)
5642#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5643#define CRC_POL_POL CRC_POL_POL_Msk
5645/******************************************************************************/
5646/* */
5647/* CRS Clock Recovery System */
5648/******************************************************************************/
5649
5650/******************* Bit definition for CRS_CR register *********************/
5651#define CRS_CR_SYNCOKIE_Pos (0U)
5652#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5653#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5654#define CRS_CR_SYNCWARNIE_Pos (1U)
5655#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5656#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5657#define CRS_CR_ERRIE_Pos (2U)
5658#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5659#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5660#define CRS_CR_ESYNCIE_Pos (3U)
5661#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5662#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5663#define CRS_CR_CEN_Pos (5U)
5664#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5665#define CRS_CR_CEN CRS_CR_CEN_Msk
5666#define CRS_CR_AUTOTRIMEN_Pos (6U)
5667#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5668#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5669#define CRS_CR_SWSYNC_Pos (7U)
5670#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5671#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5672#define CRS_CR_TRIM_Pos (8U)
5673#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5674#define CRS_CR_TRIM CRS_CR_TRIM_Msk
5676/******************* Bit definition for CRS_CFGR register *********************/
5677#define CRS_CFGR_RELOAD_Pos (0U)
5678#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5679#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5680#define CRS_CFGR_FELIM_Pos (16U)
5681#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5682#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5684#define CRS_CFGR_SYNCDIV_Pos (24U)
5685#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5686#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5687#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5688#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5689#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5691#define CRS_CFGR_SYNCSRC_Pos (28U)
5692#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5693#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5694#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5695#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5697#define CRS_CFGR_SYNCPOL_Pos (31U)
5698#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5699#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5701/******************* Bit definition for CRS_ISR register *********************/
5702#define CRS_ISR_SYNCOKF_Pos (0U)
5703#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5704#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5705#define CRS_ISR_SYNCWARNF_Pos (1U)
5706#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5707#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5708#define CRS_ISR_ERRF_Pos (2U)
5709#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5710#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5711#define CRS_ISR_ESYNCF_Pos (3U)
5712#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5713#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5714#define CRS_ISR_SYNCERR_Pos (8U)
5715#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
5716#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
5717#define CRS_ISR_SYNCMISS_Pos (9U)
5718#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
5719#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
5720#define CRS_ISR_TRIMOVF_Pos (10U)
5721#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
5722#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
5723#define CRS_ISR_FEDIR_Pos (15U)
5724#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
5725#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
5726#define CRS_ISR_FECAP_Pos (16U)
5727#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
5728#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
5730/******************* Bit definition for CRS_ICR register *********************/
5731#define CRS_ICR_SYNCOKC_Pos (0U)
5732#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
5733#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
5734#define CRS_ICR_SYNCWARNC_Pos (1U)
5735#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
5736#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
5737#define CRS_ICR_ERRC_Pos (2U)
5738#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
5739#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
5740#define CRS_ICR_ESYNCC_Pos (3U)
5741#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
5742#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
5744/******************************************************************************/
5745/* */
5746/* Crypto Processor */
5747/* */
5748/******************************************************************************/
5749/******************************** CRYP VER **********************************/
5750#define CRYP_VER_2_2
5751/******************* Bits definition for CRYP_CR register ********************/
5752#define CRYP_CR_ALGODIR_Pos (2U)
5753#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos)
5754#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5755
5756#define CRYP_CR_ALGOMODE_Pos (3U)
5757#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos)
5758#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5759#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos)
5760#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos)
5761#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos)
5762#define CRYP_CR_ALGOMODE_TDES_ECB (0U)
5763#define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5764#define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos)
5765#define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5766#define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5767#define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos)
5768#define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5769#define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5770#define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos)
5771#define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5772#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5773#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos)
5774#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5775#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5776#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos)
5777#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5778#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5779#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos)
5780#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5781#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5782#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos)
5783#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5784#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
5785#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos)
5786#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
5787#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
5788#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos)
5789#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
5790
5791#define CRYP_CR_DATATYPE_Pos (6U)
5792#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos)
5793#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5794#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos)
5795#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos)
5796#define CRYP_CR_KEYSIZE_Pos (8U)
5797#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos)
5798#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5799#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos)
5800#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos)
5801#define CRYP_CR_FFLUSH_Pos (14U)
5802#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos)
5803#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5804#define CRYP_CR_CRYPEN_Pos (15U)
5805#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos)
5806#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5807
5808#define CRYP_CR_GCM_CCMPH_Pos (16U)
5809#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos)
5810#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5811#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos)
5812#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos)
5813#define CRYP_CR_ALGOMODE_3 (0x00080000U)
5814#define CRYP_CR_NPBLB_Pos (20U)
5815#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos)
5816#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
5817
5818/****************** Bits definition for CRYP_SR register *********************/
5819#define CRYP_SR_IFEM_Pos (0U)
5820#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos)
5821#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5822#define CRYP_SR_IFNF_Pos (1U)
5823#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos)
5824#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5825#define CRYP_SR_OFNE_Pos (2U)
5826#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos)
5827#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5828#define CRYP_SR_OFFU_Pos (3U)
5829#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos)
5830#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5831#define CRYP_SR_BUSY_Pos (4U)
5832#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos)
5833#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5834/****************** Bits definition for CRYP_DMACR register ******************/
5835#define CRYP_DMACR_DIEN_Pos (0U)
5836#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos)
5837#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5838#define CRYP_DMACR_DOEN_Pos (1U)
5839#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos)
5840#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5841/***************** Bits definition for CRYP_IMSCR register ******************/
5842#define CRYP_IMSCR_INIM_Pos (0U)
5843#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos)
5844#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5845#define CRYP_IMSCR_OUTIM_Pos (1U)
5846#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos)
5847#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5848/****************** Bits definition for CRYP_RISR register *******************/
5849#define CRYP_RISR_INRIS_Pos (0U)
5850#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos)
5851#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5852#define CRYP_RISR_OUTRIS_Pos (1U)
5853#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos)
5854#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5855/****************** Bits definition for CRYP_MISR register *******************/
5856#define CRYP_MISR_INMIS_Pos (0U)
5857#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos)
5858#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5859#define CRYP_MISR_OUTMIS_Pos (1U)
5860#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos)
5861#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5862
5863/******************************************************************************/
5864/* */
5865/* Digital to Analog Converter */
5866/* */
5867/******************************************************************************/
5868/******************** Bit definition for DAC_CR register ********************/
5869#define DAC_CR_EN1_Pos (0U)
5870#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5871#define DAC_CR_EN1 DAC_CR_EN1_Msk
5872#define DAC_CR_TEN1_Pos (1U)
5873#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5874#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5876#define DAC_CR_TSEL1_Pos (2U)
5877#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
5878#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5879#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5880#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5881#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5882#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
5885#define DAC_CR_WAVE1_Pos (6U)
5886#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5887#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5888#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5889#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5891#define DAC_CR_MAMP1_Pos (8U)
5892#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5893#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5894#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5895#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5896#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5897#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5899#define DAC_CR_DMAEN1_Pos (12U)
5900#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5901#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5902#define DAC_CR_DMAUDRIE1_Pos (13U)
5903#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5904#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5905#define DAC_CR_CEN1_Pos (14U)
5906#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
5907#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
5909#define DAC_CR_EN2_Pos (16U)
5910#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5911#define DAC_CR_EN2 DAC_CR_EN2_Msk
5912#define DAC_CR_TEN2_Pos (17U)
5913#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5914#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5916#define DAC_CR_TSEL2_Pos (18U)
5917#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
5918#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5919#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5920#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5921#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5922#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
5925#define DAC_CR_WAVE2_Pos (22U)
5926#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5927#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5928#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5929#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5931#define DAC_CR_MAMP2_Pos (24U)
5932#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5933#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5934#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5935#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5936#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5937#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5939#define DAC_CR_DMAEN2_Pos (28U)
5940#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5941#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5942#define DAC_CR_DMAUDRIE2_Pos (29U)
5943#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5944#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5945#define DAC_CR_CEN2_Pos (30U)
5946#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
5947#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
5949/***************** Bit definition for DAC_SWTRIGR register ******************/
5950#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5951#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5952#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5953#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5954#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5955#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5957/***************** Bit definition for DAC_DHR12R1 register ******************/
5958#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5959#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5960#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5962/***************** Bit definition for DAC_DHR12L1 register ******************/
5963#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5964#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5965#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5967/****************** Bit definition for DAC_DHR8R1 register ******************/
5968#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5969#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5970#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5972/***************** Bit definition for DAC_DHR12R2 register ******************/
5973#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5974#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5975#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5977/***************** Bit definition for DAC_DHR12L2 register ******************/
5978#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5979#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5980#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5982/****************** Bit definition for DAC_DHR8R2 register ******************/
5983#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5984#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5985#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5987/***************** Bit definition for DAC_DHR12RD register ******************/
5988#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5989#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5990#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5991#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5992#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5993#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5995/***************** Bit definition for DAC_DHR12LD register ******************/
5996#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5997#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5998#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5999#define DAC_DHR12LD_DACC2DHR_Pos (20U)
6000#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
6001#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
6003/****************** Bit definition for DAC_DHR8RD register ******************/
6004#define DAC_DHR8RD_DACC1DHR_Pos (0U)
6005#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
6006#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
6007#define DAC_DHR8RD_DACC2DHR_Pos (8U)
6008#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
6009#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
6011/******************* Bit definition for DAC_DOR1 register *******************/
6012#define DAC_DOR1_DACC1DOR_Pos (0U)
6013#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
6014#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
6016/******************* Bit definition for DAC_DOR2 register *******************/
6017#define DAC_DOR2_DACC2DOR_Pos (0U)
6018#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
6019#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
6021/******************** Bit definition for DAC_SR register ********************/
6022#define DAC_SR_DMAUDR1_Pos (13U)
6023#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
6024#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
6025#define DAC_SR_CAL_FLAG1_Pos (14U)
6026#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
6027#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
6028#define DAC_SR_BWST1_Pos (15U)
6029#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos)
6030#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6032#define DAC_SR_DMAUDR2_Pos (29U)
6033#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6034#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6035#define DAC_SR_CAL_FLAG2_Pos (30U)
6036#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6037#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6038#define DAC_SR_BWST2_Pos (31U)
6039#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6040#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6042/******************* Bit definition for DAC_CCR register ********************/
6043#define DAC_CCR_OTRIM1_Pos (0U)
6044#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6045#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6046#define DAC_CCR_OTRIM2_Pos (16U)
6047#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6048#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6050/******************* Bit definition for DAC_MCR register *******************/
6051#define DAC_MCR_MODE1_Pos (0U)
6052#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6053#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6054#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6055#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6056#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6058#define DAC_MCR_MODE2_Pos (16U)
6059#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6060#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6061#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6062#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6063#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6065/****************** Bit definition for DAC_SHSR1 register ******************/
6066#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6067#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6068#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6070/****************** Bit definition for DAC_SHSR2 register ******************/
6071#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6072#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6073#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6075/****************** Bit definition for DAC_SHHR register ******************/
6076#define DAC_SHHR_THOLD1_Pos (0U)
6077#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6078#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6079#define DAC_SHHR_THOLD2_Pos (16U)
6080#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6081#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6083/****************** Bit definition for DAC_SHRR register ******************/
6084#define DAC_SHRR_TREFRESH1_Pos (0U)
6085#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6086#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6087#define DAC_SHRR_TREFRESH2_Pos (16U)
6088#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6089#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6091/******************************************************************************/
6092/* */
6093/* DCMI */
6094/* */
6095/******************************************************************************/
6096/******************** Bits definition for DCMI_CR register ******************/
6097#define DCMI_CR_CAPTURE_Pos (0U)
6098#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6099#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6100#define DCMI_CR_CM_Pos (1U)
6101#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6102#define DCMI_CR_CM DCMI_CR_CM_Msk
6103#define DCMI_CR_CROP_Pos (2U)
6104#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6105#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6106#define DCMI_CR_JPEG_Pos (3U)
6107#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6108#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6109#define DCMI_CR_ESS_Pos (4U)
6110#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6111#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6112#define DCMI_CR_PCKPOL_Pos (5U)
6113#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6114#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6115#define DCMI_CR_HSPOL_Pos (6U)
6116#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6117#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6118#define DCMI_CR_VSPOL_Pos (7U)
6119#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6120#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6121#define DCMI_CR_FCRC_0 (0x00000100U)
6122#define DCMI_CR_FCRC_1 (0x00000200U)
6123#define DCMI_CR_EDM_0 (0x00000400U)
6124#define DCMI_CR_EDM_1 (0x00000800U)
6125#define DCMI_CR_CRE_Pos (12U)
6126#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6127#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6128#define DCMI_CR_ENABLE_Pos (14U)
6129#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6130#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6131#define DCMI_CR_BSM_Pos (16U)
6132#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6133#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6134#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6135#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6136#define DCMI_CR_OEBS_Pos (18U)
6137#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6138#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6139#define DCMI_CR_LSM_Pos (19U)
6140#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6141#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6142#define DCMI_CR_OELS_Pos (20U)
6143#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6144#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6145
6146/******************** Bits definition for DCMI_SR register ******************/
6147#define DCMI_SR_HSYNC_Pos (0U)
6148#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6149#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6150#define DCMI_SR_VSYNC_Pos (1U)
6151#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6152#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6153#define DCMI_SR_FNE_Pos (2U)
6154#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6155#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6156
6157/******************** Bits definition for DCMI_RIS register ****************/
6158#define DCMI_RIS_FRAME_RIS_Pos (0U)
6159#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6160#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6161#define DCMI_RIS_OVR_RIS_Pos (1U)
6162#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6163#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6164#define DCMI_RIS_ERR_RIS_Pos (2U)
6165#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6166#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6167#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6168#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6169#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6170#define DCMI_RIS_LINE_RIS_Pos (4U)
6171#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6172#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6173
6174/******************** Bits definition for DCMI_IER register *****************/
6175#define DCMI_IER_FRAME_IE_Pos (0U)
6176#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6177#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6178#define DCMI_IER_OVR_IE_Pos (1U)
6179#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6180#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6181#define DCMI_IER_ERR_IE_Pos (2U)
6182#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6183#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6184#define DCMI_IER_VSYNC_IE_Pos (3U)
6185#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6186#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6187#define DCMI_IER_LINE_IE_Pos (4U)
6188#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6189#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6190
6191
6192/******************** Bits definition for DCMI_MIS register *****************/
6193#define DCMI_MIS_FRAME_MIS_Pos (0U)
6194#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6195#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6196#define DCMI_MIS_OVR_MIS_Pos (1U)
6197#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6198#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6199#define DCMI_MIS_ERR_MIS_Pos (2U)
6200#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6201#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6202#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6203#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6204#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6205#define DCMI_MIS_LINE_MIS_Pos (4U)
6206#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6207#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6208
6209
6210/******************** Bits definition for DCMI_ICR register *****************/
6211#define DCMI_ICR_FRAME_ISC_Pos (0U)
6212#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6213#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6214#define DCMI_ICR_OVR_ISC_Pos (1U)
6215#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6216#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6217#define DCMI_ICR_ERR_ISC_Pos (2U)
6218#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6219#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6220#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6221#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6222#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6223#define DCMI_ICR_LINE_ISC_Pos (4U)
6224#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6225#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6226
6227
6228/******************** Bits definition for DCMI_ESCR register ******************/
6229#define DCMI_ESCR_FSC_Pos (0U)
6230#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6231#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6232#define DCMI_ESCR_LSC_Pos (8U)
6233#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6234#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6235#define DCMI_ESCR_LEC_Pos (16U)
6236#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6237#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6238#define DCMI_ESCR_FEC_Pos (24U)
6239#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6240#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6241
6242/******************** Bits definition for DCMI_ESUR register ******************/
6243#define DCMI_ESUR_FSU_Pos (0U)
6244#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6245#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6246#define DCMI_ESUR_LSU_Pos (8U)
6247#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6248#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6249#define DCMI_ESUR_LEU_Pos (16U)
6250#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6251#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6252#define DCMI_ESUR_FEU_Pos (24U)
6253#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6254#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6255
6256/******************** Bits definition for DCMI_CWSTRT register ******************/
6257#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6258#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6259#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6260#define DCMI_CWSTRT_VST_Pos (16U)
6261#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6262#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6263
6264/******************** Bits definition for DCMI_CWSIZE register ******************/
6265#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6266#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6267#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6268#define DCMI_CWSIZE_VLINE_Pos (16U)
6269#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6270#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6271
6272/******************** Bits definition for DCMI_DR register ******************/
6273#define DCMI_DR_BYTE0_Pos (0U)
6274#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6275#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6276#define DCMI_DR_BYTE1_Pos (8U)
6277#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6278#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6279#define DCMI_DR_BYTE2_Pos (16U)
6280#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6281#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6282#define DCMI_DR_BYTE3_Pos (24U)
6283#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6284#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6285
6286/******************************************************************************/
6287/* */
6288/* Digital Filter for Sigma Delta Modulators */
6289/* */
6290/******************************************************************************/
6291
6292/**************** DFSDM channel configuration registers ********************/
6293
6294/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6295#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6296#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6297#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6298#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6299#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6300#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6301#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6302#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6303#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6304#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6305#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6306#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6307#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6308#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6309#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6310#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6311#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6312#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6313#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6314#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6315#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6316#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6317#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6318#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6319#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6320#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6321#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6322#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6323#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6324#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6325#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6326#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6327#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6328#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6329#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6330#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6331#define DFSDM_CHCFGR1_SITP_Pos (0U)
6332#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6333#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6334#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6335#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6337/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6338#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6339#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6340#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6341#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6342#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6343#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6345/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6346#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6347#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6348#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6349#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6350#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6351#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6352#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6353#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6354#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6355#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6356#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6357#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6358#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6359#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6361/**************** Bit definition for DFSDM_CHWDATR register *******************/
6362#define DFSDM_CHWDATR_WDATA_Pos (0U)
6363#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6364#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6366/**************** Bit definition for DFSDM_CHDATINR register *****************/
6367#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6368#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6369#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6370#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6371#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6372#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6374/**************** Bit definition for DFSDM_CHDLYR register *****************/
6375#define DFSDM_CHDLYR_PLSSKP_Pos (0U)
6376#define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)
6377#define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk
6378/************************ DFSDM module registers ****************************/
6379
6380/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6381#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6382#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6383#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6384#define DFSDM_FLTCR1_FAST_Pos (29U)
6385#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6386#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6387#define DFSDM_FLTCR1_RCH_Pos (24U)
6388#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6389#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6390#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6391#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6392#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6393#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6394#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6395#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6396#define DFSDM_FLTCR1_RCONT_Pos (18U)
6397#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6398#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6399#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6400#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6401#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6402#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6403#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6404#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6405#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6406#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6407#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6408#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6409#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6410#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6411#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6412#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6413#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6414#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6416#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6417#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6418#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6419#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6420#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6421#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6422#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6423#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6424#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6425#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6426#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6427#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6428#define DFSDM_FLTCR1_DFEN_Pos (0U)
6429#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6430#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6432/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6433#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6434#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6435#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6436#define DFSDM_FLTCR2_EXCH_Pos (8U)
6437#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6438#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6439#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6440#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6441#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6442#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6443#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6444#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6445#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6446#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6447#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6448#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6449#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6450#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6451#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6452#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6453#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6454#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6455#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6456#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6457#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6458#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6459#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6461/******************** Bit definition for DFSDM_FLTISR register *******************/
6462#define DFSDM_FLTISR_SCDF_Pos (24U)
6463#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6464#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6465#define DFSDM_FLTISR_CKABF_Pos (16U)
6466#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6467#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6468#define DFSDM_FLTISR_RCIP_Pos (14U)
6469#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6470#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6471#define DFSDM_FLTISR_JCIP_Pos (13U)
6472#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6473#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6474#define DFSDM_FLTISR_AWDF_Pos (4U)
6475#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6476#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6477#define DFSDM_FLTISR_ROVRF_Pos (3U)
6478#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6479#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6480#define DFSDM_FLTISR_JOVRF_Pos (2U)
6481#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6482#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6483#define DFSDM_FLTISR_REOCF_Pos (1U)
6484#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6485#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6486#define DFSDM_FLTISR_JEOCF_Pos (0U)
6487#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6488#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6490/******************** Bit definition for DFSDM_FLTICR register *******************/
6491#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6492#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6493#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6494#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6495#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6496#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6497#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6498#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6499#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6500#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6501#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6502#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6504/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6505#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6506#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6507#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6509/******************** Bit definition for DFSDM_FLTFCR register *******************/
6510#define DFSDM_FLTFCR_FORD_Pos (29U)
6511#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6512#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6513#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6514#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6515#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6516#define DFSDM_FLTFCR_FOSR_Pos (16U)
6517#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6518#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6519#define DFSDM_FLTFCR_IOSR_Pos (0U)
6520#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6521#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6523/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6524#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6525#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6526#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6527#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6528#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6529#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6531/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6532#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6533#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6534#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6535#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6536#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6537#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6538#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6539#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6540#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6542/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6543#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6544#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6545#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6546#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6547#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6548#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6550/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6551#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6552#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6553#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6554#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6555#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6556#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6558/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6559#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6560#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6561#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6562#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6563#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6564#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6566/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6567#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6568#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6569#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6570#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6571#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6572#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6574/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6575#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6576#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6577#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6578#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6579#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6580#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6582/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6583#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6584#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6585#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6586#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6587#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6588#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6590/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6591#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6592#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6593#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6595/******************************************************************************/
6596/* */
6597/* BDMA Controller */
6598/* */
6599/******************************************************************************/
6600
6601/******************* Bit definition for BDMA_ISR register ********************/
6602#define BDMA_ISR_GIF0_Pos (0U)
6603#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos)
6604#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk
6605#define BDMA_ISR_TCIF0_Pos (1U)
6606#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos)
6607#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk
6608#define BDMA_ISR_HTIF0_Pos (2U)
6609#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos)
6610#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk
6611#define BDMA_ISR_TEIF0_Pos (3U)
6612#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos)
6613#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk
6614#define BDMA_ISR_GIF1_Pos (4U)
6615#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos)
6616#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk
6617#define BDMA_ISR_TCIF1_Pos (5U)
6618#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos)
6619#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk
6620#define BDMA_ISR_HTIF1_Pos (6U)
6621#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos)
6622#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk
6623#define BDMA_ISR_TEIF1_Pos (7U)
6624#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos)
6625#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk
6626#define BDMA_ISR_GIF2_Pos (8U)
6627#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos)
6628#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk
6629#define BDMA_ISR_TCIF2_Pos (9U)
6630#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos)
6631#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk
6632#define BDMA_ISR_HTIF2_Pos (10U)
6633#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos)
6634#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk
6635#define BDMA_ISR_TEIF2_Pos (11U)
6636#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos)
6637#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk
6638#define BDMA_ISR_GIF3_Pos (12U)
6639#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos)
6640#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk
6641#define BDMA_ISR_TCIF3_Pos (13U)
6642#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos)
6643#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk
6644#define BDMA_ISR_HTIF3_Pos (14U)
6645#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos)
6646#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk
6647#define BDMA_ISR_TEIF3_Pos (15U)
6648#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos)
6649#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk
6650#define BDMA_ISR_GIF4_Pos (16U)
6651#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos)
6652#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk
6653#define BDMA_ISR_TCIF4_Pos (17U)
6654#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos)
6655#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk
6656#define BDMA_ISR_HTIF4_Pos (18U)
6657#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos)
6658#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk
6659#define BDMA_ISR_TEIF4_Pos (19U)
6660#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos)
6661#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk
6662#define BDMA_ISR_GIF5_Pos (20U)
6663#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos)
6664#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk
6665#define BDMA_ISR_TCIF5_Pos (21U)
6666#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos)
6667#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk
6668#define BDMA_ISR_HTIF5_Pos (22U)
6669#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos)
6670#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk
6671#define BDMA_ISR_TEIF5_Pos (23U)
6672#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos)
6673#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk
6674#define BDMA_ISR_GIF6_Pos (24U)
6675#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
6676#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk
6677#define BDMA_ISR_TCIF6_Pos (25U)
6678#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos)
6679#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk
6680#define BDMA_ISR_HTIF6_Pos (26U)
6681#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos)
6682#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk
6683#define BDMA_ISR_TEIF6_Pos (27U)
6684#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos)
6685#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk
6686#define BDMA_ISR_GIF7_Pos (28U)
6687#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos)
6688#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk
6689#define BDMA_ISR_TCIF7_Pos (29U)
6690#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos)
6691#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk
6692#define BDMA_ISR_HTIF7_Pos (30U)
6693#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos)
6694#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk
6695#define BDMA_ISR_TEIF7_Pos (31U)
6696#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos)
6697#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk
6699/******************* Bit definition for BDMA_IFCR register *******************/
6700#define BDMA_IFCR_CGIF0_Pos (0U)
6701#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos)
6702#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk
6703#define BDMA_IFCR_CTCIF0_Pos (1U)
6704#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos)
6705#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk
6706#define BDMA_IFCR_CHTIF0_Pos (2U)
6707#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos)
6708#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk
6709#define BDMA_IFCR_CTEIF0_Pos (3U)
6710#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos)
6711#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk
6712#define BDMA_IFCR_CGIF1_Pos (4U)
6713#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos)
6714#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk
6715#define BDMA_IFCR_CTCIF1_Pos (5U)
6716#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos)
6717#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk
6718#define BDMA_IFCR_CHTIF1_Pos (6U)
6719#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos)
6720#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk
6721#define BDMA_IFCR_CTEIF1_Pos (7U)
6722#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos)
6723#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk
6724#define BDMA_IFCR_CGIF2_Pos (8U)
6725#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos)
6726#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk
6727#define BDMA_IFCR_CTCIF2_Pos (9U)
6728#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos)
6729#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk
6730#define BDMA_IFCR_CHTIF2_Pos (10U)
6731#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos)
6732#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk
6733#define BDMA_IFCR_CTEIF2_Pos (11U)
6734#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos)
6735#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk
6736#define BDMA_IFCR_CGIF3_Pos (12U)
6737#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos)
6738#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk
6739#define BDMA_IFCR_CTCIF3_Pos (13U)
6740#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos)
6741#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk
6742#define BDMA_IFCR_CHTIF3_Pos (14U)
6743#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos)
6744#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk
6745#define BDMA_IFCR_CTEIF3_Pos (15U)
6746#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos)
6747#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk
6748#define BDMA_IFCR_CGIF4_Pos (16U)
6749#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos)
6750#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk
6751#define BDMA_IFCR_CTCIF4_Pos (17U)
6752#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos)
6753#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk
6754#define BDMA_IFCR_CHTIF4_Pos (18U)
6755#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos)
6756#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk
6757#define BDMA_IFCR_CTEIF4_Pos (19U)
6758#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos)
6759#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk
6760#define BDMA_IFCR_CGIF5_Pos (20U)
6761#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos)
6762#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk
6763#define BDMA_IFCR_CTCIF5_Pos (21U)
6764#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos)
6765#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk
6766#define BDMA_IFCR_CHTIF5_Pos (22U)
6767#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos)
6768#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk
6769#define BDMA_IFCR_CTEIF5_Pos (23U)
6770#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos)
6771#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk
6772#define BDMA_IFCR_CGIF6_Pos (24U)
6773#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos)
6774#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk
6775#define BDMA_IFCR_CTCIF6_Pos (25U)
6776#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos)
6777#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk
6778#define BDMA_IFCR_CHTIF6_Pos (26U)
6779#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos)
6780#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk
6781#define BDMA_IFCR_CTEIF6_Pos (27U)
6782#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos)
6783#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk
6784#define BDMA_IFCR_CGIF7_Pos (28U)
6785#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos)
6786#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk
6787#define BDMA_IFCR_CTCIF7_Pos (29U)
6788#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos)
6789#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk
6790#define BDMA_IFCR_CHTIF7_Pos (30U)
6791#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos)
6792#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk
6793#define BDMA_IFCR_CTEIF7_Pos (31U)
6794#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos)
6795#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk
6797/******************* Bit definition for BDMA_CCR register ********************/
6798#define BDMA_CCR_EN_Pos (0U)
6799#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos)
6800#define BDMA_CCR_EN BDMA_CCR_EN_Msk
6801#define BDMA_CCR_TCIE_Pos (1U)
6802#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos)
6803#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
6804#define BDMA_CCR_HTIE_Pos (2U)
6805#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos)
6806#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk
6807#define BDMA_CCR_TEIE_Pos (3U)
6808#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos)
6809#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk
6810#define BDMA_CCR_DIR_Pos (4U)
6811#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos)
6812#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk
6813#define BDMA_CCR_CIRC_Pos (5U)
6814#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos)
6815#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk
6816#define BDMA_CCR_PINC_Pos (6U)
6817#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos)
6818#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk
6819#define BDMA_CCR_MINC_Pos (7U)
6820#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos)
6821#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk
6823#define BDMA_CCR_PSIZE_Pos (8U)
6824#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos)
6825#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk
6826#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos)
6827#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos)
6829#define BDMA_CCR_MSIZE_Pos (10U)
6830#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos)
6831#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk
6832#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos)
6833#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos)
6835#define BDMA_CCR_PL_Pos (12U)
6836#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos)
6837#define BDMA_CCR_PL BDMA_CCR_PL_Msk
6838#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos)
6839#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos)
6841#define BDMA_CCR_MEM2MEM_Pos (14U)
6842#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos)
6843#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk
6844#define BDMA_CCR_DBM_Pos (15U)
6845#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos)
6846#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk
6847#define BDMA_CCR_CT_Pos (16U)
6848#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos)
6849#define BDMA_CCR_CT BDMA_CCR_CT_Msk
6851/****************** Bit definition for BDMA_CNDTR register *******************/
6852#define BDMA_CNDTR_NDT_Pos (0U)
6853#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
6854#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk
6856/****************** Bit definition for BDMA_CPAR register ********************/
6857#define BDMA_CPAR_PA_Pos (0U)
6858#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
6859#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk
6861/****************** Bit definition for BDMA_CM0AR register ********************/
6862#define BDMA_CM0AR_MA_Pos (0U)
6863#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
6864#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk
6866/****************** Bit definition for BDMA_CM1AR register ********************/
6867#define BDMA_CM1AR_MA_Pos (0U)
6868#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
6869#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk
6871/******************************************************************************/
6872/* */
6873/* DMA Controller */
6874/* */
6875/******************************************************************************/
6876/******************** Bits definition for DMA_SxCR register *****************/
6877#define DMA_SxCR_MBURST_Pos (23U)
6878#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6879#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6880#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6881#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6882#define DMA_SxCR_PBURST_Pos (21U)
6883#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6884#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6885#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6886#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6887#define DMA_SxCR_TRBUFF_Pos (20U)
6888#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos)
6889#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk
6890#define DMA_SxCR_CT_Pos (19U)
6891#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6892#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6893#define DMA_SxCR_DBM_Pos (18U)
6894#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6895#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6896#define DMA_SxCR_PL_Pos (16U)
6897#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6898#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6899#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6900#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6901#define DMA_SxCR_PINCOS_Pos (15U)
6902#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6903#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6904#define DMA_SxCR_MSIZE_Pos (13U)
6905#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6906#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6907#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6908#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6909#define DMA_SxCR_PSIZE_Pos (11U)
6910#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6911#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
6912#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6913#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6914#define DMA_SxCR_MINC_Pos (10U)
6915#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6916#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6917#define DMA_SxCR_PINC_Pos (9U)
6918#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6919#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6920#define DMA_SxCR_CIRC_Pos (8U)
6921#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6922#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6923#define DMA_SxCR_DIR_Pos (6U)
6924#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6925#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6926#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6927#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6928#define DMA_SxCR_PFCTRL_Pos (5U)
6929#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6930#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6931#define DMA_SxCR_TCIE_Pos (4U)
6932#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6933#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6934#define DMA_SxCR_HTIE_Pos (3U)
6935#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6936#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6937#define DMA_SxCR_TEIE_Pos (2U)
6938#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6939#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6940#define DMA_SxCR_DMEIE_Pos (1U)
6941#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6942#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6943#define DMA_SxCR_EN_Pos (0U)
6944#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6945#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6947/******************** Bits definition for DMA_SxCNDTR register **************/
6948#define DMA_SxNDT_Pos (0U)
6949#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6950#define DMA_SxNDT DMA_SxNDT_Msk
6951#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6952#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6953#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6954#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6955#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6956#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6957#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6958#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6959#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6960#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6961#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6962#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6963#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6964#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6965#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6966#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6968/******************** Bits definition for DMA_SxFCR register ****************/
6969#define DMA_SxFCR_FEIE_Pos (7U)
6970#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6971#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6972#define DMA_SxFCR_FS_Pos (3U)
6973#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6974#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6975#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6976#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6977#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6978#define DMA_SxFCR_DMDIS_Pos (2U)
6979#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6980#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6981#define DMA_SxFCR_FTH_Pos (0U)
6982#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6983#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6984#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6985#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6987/******************** Bits definition for DMA_LISR register *****************/
6988#define DMA_LISR_TCIF3_Pos (27U)
6989#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6990#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6991#define DMA_LISR_HTIF3_Pos (26U)
6992#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6993#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6994#define DMA_LISR_TEIF3_Pos (25U)
6995#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6996#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6997#define DMA_LISR_DMEIF3_Pos (24U)
6998#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6999#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
7000#define DMA_LISR_FEIF3_Pos (22U)
7001#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
7002#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
7003#define DMA_LISR_TCIF2_Pos (21U)
7004#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
7005#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
7006#define DMA_LISR_HTIF2_Pos (20U)
7007#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
7008#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
7009#define DMA_LISR_TEIF2_Pos (19U)
7010#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
7011#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
7012#define DMA_LISR_DMEIF2_Pos (18U)
7013#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
7014#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
7015#define DMA_LISR_FEIF2_Pos (16U)
7016#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
7017#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
7018#define DMA_LISR_TCIF1_Pos (11U)
7019#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
7020#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
7021#define DMA_LISR_HTIF1_Pos (10U)
7022#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
7023#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
7024#define DMA_LISR_TEIF1_Pos (9U)
7025#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
7026#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
7027#define DMA_LISR_DMEIF1_Pos (8U)
7028#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
7029#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
7030#define DMA_LISR_FEIF1_Pos (6U)
7031#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
7032#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
7033#define DMA_LISR_TCIF0_Pos (5U)
7034#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
7035#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
7036#define DMA_LISR_HTIF0_Pos (4U)
7037#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
7038#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
7039#define DMA_LISR_TEIF0_Pos (3U)
7040#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
7041#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
7042#define DMA_LISR_DMEIF0_Pos (2U)
7043#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
7044#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
7045#define DMA_LISR_FEIF0_Pos (0U)
7046#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
7047#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
7049/******************** Bits definition for DMA_HISR register *****************/
7050#define DMA_HISR_TCIF7_Pos (27U)
7051#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
7052#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
7053#define DMA_HISR_HTIF7_Pos (26U)
7054#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
7055#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
7056#define DMA_HISR_TEIF7_Pos (25U)
7057#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
7058#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
7059#define DMA_HISR_DMEIF7_Pos (24U)
7060#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
7061#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
7062#define DMA_HISR_FEIF7_Pos (22U)
7063#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
7064#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
7065#define DMA_HISR_TCIF6_Pos (21U)
7066#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
7067#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
7068#define DMA_HISR_HTIF6_Pos (20U)
7069#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
7070#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
7071#define DMA_HISR_TEIF6_Pos (19U)
7072#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
7073#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
7074#define DMA_HISR_DMEIF6_Pos (18U)
7075#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
7076#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
7077#define DMA_HISR_FEIF6_Pos (16U)
7078#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
7079#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
7080#define DMA_HISR_TCIF5_Pos (11U)
7081#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
7082#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
7083#define DMA_HISR_HTIF5_Pos (10U)
7084#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
7085#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
7086#define DMA_HISR_TEIF5_Pos (9U)
7087#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
7088#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
7089#define DMA_HISR_DMEIF5_Pos (8U)
7090#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
7091#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
7092#define DMA_HISR_FEIF5_Pos (6U)
7093#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
7094#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
7095#define DMA_HISR_TCIF4_Pos (5U)
7096#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
7097#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
7098#define DMA_HISR_HTIF4_Pos (4U)
7099#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
7100#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
7101#define DMA_HISR_TEIF4_Pos (3U)
7102#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
7103#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
7104#define DMA_HISR_DMEIF4_Pos (2U)
7105#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
7106#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
7107#define DMA_HISR_FEIF4_Pos (0U)
7108#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
7109#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
7111/******************** Bits definition for DMA_LIFCR register ****************/
7112#define DMA_LIFCR_CTCIF3_Pos (27U)
7113#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
7114#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
7115#define DMA_LIFCR_CHTIF3_Pos (26U)
7116#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
7117#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
7118#define DMA_LIFCR_CTEIF3_Pos (25U)
7119#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
7120#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
7121#define DMA_LIFCR_CDMEIF3_Pos (24U)
7122#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
7123#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
7124#define DMA_LIFCR_CFEIF3_Pos (22U)
7125#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
7126#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
7127#define DMA_LIFCR_CTCIF2_Pos (21U)
7128#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
7129#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
7130#define DMA_LIFCR_CHTIF2_Pos (20U)
7131#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
7132#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
7133#define DMA_LIFCR_CTEIF2_Pos (19U)
7134#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
7135#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
7136#define DMA_LIFCR_CDMEIF2_Pos (18U)
7137#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
7138#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
7139#define DMA_LIFCR_CFEIF2_Pos (16U)
7140#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
7141#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
7142#define DMA_LIFCR_CTCIF1_Pos (11U)
7143#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
7144#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
7145#define DMA_LIFCR_CHTIF1_Pos (10U)
7146#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
7147#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
7148#define DMA_LIFCR_CTEIF1_Pos (9U)
7149#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
7150#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
7151#define DMA_LIFCR_CDMEIF1_Pos (8U)
7152#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
7153#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
7154#define DMA_LIFCR_CFEIF1_Pos (6U)
7155#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
7156#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
7157#define DMA_LIFCR_CTCIF0_Pos (5U)
7158#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
7159#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
7160#define DMA_LIFCR_CHTIF0_Pos (4U)
7161#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
7162#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
7163#define DMA_LIFCR_CTEIF0_Pos (3U)
7164#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
7165#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
7166#define DMA_LIFCR_CDMEIF0_Pos (2U)
7167#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
7168#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
7169#define DMA_LIFCR_CFEIF0_Pos (0U)
7170#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
7171#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
7173/******************** Bits definition for DMA_HIFCR register ****************/
7174#define DMA_HIFCR_CTCIF7_Pos (27U)
7175#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
7176#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
7177#define DMA_HIFCR_CHTIF7_Pos (26U)
7178#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
7179#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
7180#define DMA_HIFCR_CTEIF7_Pos (25U)
7181#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
7182#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
7183#define DMA_HIFCR_CDMEIF7_Pos (24U)
7184#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
7185#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
7186#define DMA_HIFCR_CFEIF7_Pos (22U)
7187#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
7188#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
7189#define DMA_HIFCR_CTCIF6_Pos (21U)
7190#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
7191#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
7192#define DMA_HIFCR_CHTIF6_Pos (20U)
7193#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
7194#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
7195#define DMA_HIFCR_CTEIF6_Pos (19U)
7196#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
7197#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
7198#define DMA_HIFCR_CDMEIF6_Pos (18U)
7199#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
7200#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
7201#define DMA_HIFCR_CFEIF6_Pos (16U)
7202#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
7203#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
7204#define DMA_HIFCR_CTCIF5_Pos (11U)
7205#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
7206#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
7207#define DMA_HIFCR_CHTIF5_Pos (10U)
7208#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
7209#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
7210#define DMA_HIFCR_CTEIF5_Pos (9U)
7211#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
7212#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
7213#define DMA_HIFCR_CDMEIF5_Pos (8U)
7214#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
7215#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
7216#define DMA_HIFCR_CFEIF5_Pos (6U)
7217#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
7218#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
7219#define DMA_HIFCR_CTCIF4_Pos (5U)
7220#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
7221#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
7222#define DMA_HIFCR_CHTIF4_Pos (4U)
7223#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
7224#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
7225#define DMA_HIFCR_CTEIF4_Pos (3U)
7226#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
7227#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
7228#define DMA_HIFCR_CDMEIF4_Pos (2U)
7229#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
7230#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
7231#define DMA_HIFCR_CFEIF4_Pos (0U)
7232#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
7233#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
7235/****************** Bit definition for DMA_SxPAR register ********************/
7236#define DMA_SxPAR_PA_Pos (0U)
7237#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
7238#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
7240/****************** Bit definition for DMA_SxM0AR register ********************/
7241#define DMA_SxM0AR_M0A_Pos (0U)
7242#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
7243#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
7245/****************** Bit definition for DMA_SxM1AR register ********************/
7246#define DMA_SxM1AR_M1A_Pos (0U)
7247#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
7248#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
7250/******************************************************************************/
7251/* */
7252/* DMAMUX Controller */
7253/* */
7254/******************************************************************************/
7255/******************** Bits definition for DMAMUX_CxCR register **************/
7256#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
7257#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7258#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
7259#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7260#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7261#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7262#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7263#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7264#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7265#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7266#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
7267#define DMAMUX_CxCR_SOIE_Pos (8U)
7268#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
7269#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
7270#define DMAMUX_CxCR_EGE_Pos (9U)
7271#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
7272#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
7273#define DMAMUX_CxCR_SE_Pos (16U)
7274#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
7275#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
7276#define DMAMUX_CxCR_SPOL_Pos (17U)
7277#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
7278#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
7279#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
7280#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
7281#define DMAMUX_CxCR_NBREQ_Pos (19U)
7282#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
7283#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
7284#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
7285#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
7286#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
7287#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
7288#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
7289#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
7290#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
7291#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
7292#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
7293#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
7294#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
7295#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
7296#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
7298/******************** Bits definition for DMAMUX_CSR register **************/
7299#define DMAMUX_CSR_SOF0_Pos (0U)
7300#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
7301#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
7302#define DMAMUX_CSR_SOF1_Pos (1U)
7303#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
7304#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
7305#define DMAMUX_CSR_SOF2_Pos (2U)
7306#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
7307#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
7308#define DMAMUX_CSR_SOF3_Pos (3U)
7309#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
7310#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
7311#define DMAMUX_CSR_SOF4_Pos (4U)
7312#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
7313#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
7314#define DMAMUX_CSR_SOF5_Pos (5U)
7315#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
7316#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
7317#define DMAMUX_CSR_SOF6_Pos (6U)
7318#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
7319#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
7320#define DMAMUX_CSR_SOF7_Pos (7U)
7321#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
7322#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
7323#define DMAMUX_CSR_SOF8_Pos (8U)
7324#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
7325#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
7326#define DMAMUX_CSR_SOF9_Pos (9U)
7327#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
7328#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
7329#define DMAMUX_CSR_SOF10_Pos (10U)
7330#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
7331#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
7332#define DMAMUX_CSR_SOF11_Pos (11U)
7333#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
7334#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
7335#define DMAMUX_CSR_SOF12_Pos (12U)
7336#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
7337#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
7338#define DMAMUX_CSR_SOF13_Pos (13U)
7339#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
7340#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
7341#define DMAMUX_CSR_SOF14_Pos (14U)
7342#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
7343#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
7344#define DMAMUX_CSR_SOF15_Pos (15U)
7345#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
7346#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
7348/******************** Bits definition for DMAMUX_CFR register **************/
7349#define DMAMUX_CFR_CSOF0_Pos (0U)
7350#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
7351#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
7352#define DMAMUX_CFR_CSOF1_Pos (1U)
7353#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
7354#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
7355#define DMAMUX_CFR_CSOF2_Pos (2U)
7356#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
7357#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
7358#define DMAMUX_CFR_CSOF3_Pos (3U)
7359#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
7360#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
7361#define DMAMUX_CFR_CSOF4_Pos (4U)
7362#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
7363#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
7364#define DMAMUX_CFR_CSOF5_Pos (5U)
7365#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
7366#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
7367#define DMAMUX_CFR_CSOF6_Pos (6U)
7368#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
7369#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
7370#define DMAMUX_CFR_CSOF7_Pos (7U)
7371#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
7372#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
7373#define DMAMUX_CFR_CSOF8_Pos (8U)
7374#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
7375#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
7376#define DMAMUX_CFR_CSOF9_Pos (9U)
7377#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
7378#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
7379#define DMAMUX_CFR_CSOF10_Pos (10U)
7380#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
7381#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
7382#define DMAMUX_CFR_CSOF11_Pos (11U)
7383#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
7384#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
7385#define DMAMUX_CFR_CSOF12_Pos (12U)
7386#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
7387#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
7388#define DMAMUX_CFR_CSOF13_Pos (13U)
7389#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
7390#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
7391#define DMAMUX_CFR_CSOF14_Pos (14U)
7392#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
7393#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
7394#define DMAMUX_CFR_CSOF15_Pos (15U)
7395#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
7396#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
7398/******************** Bits definition for DMAMUX_RGxCR register ************/
7399#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
7400#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
7401#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
7402#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
7403#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
7404#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
7405#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
7406#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
7407#define DMAMUX_RGxCR_OIE_Pos (8U)
7408#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
7409#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
7410#define DMAMUX_RGxCR_GE_Pos (16U)
7411#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
7412#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
7413#define DMAMUX_RGxCR_GPOL_Pos (17U)
7414#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
7415#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
7416#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
7417#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
7418#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
7419#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
7420#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
7421#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
7422#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
7423#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
7424#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
7425#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
7427/******************** Bits definition for DMAMUX_RGSR register **************/
7428#define DMAMUX_RGSR_OF0_Pos (0U)
7429#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
7430#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
7431#define DMAMUX_RGSR_OF1_Pos (1U)
7432#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
7433#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
7434#define DMAMUX_RGSR_OF2_Pos (2U)
7435#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
7436#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
7437#define DMAMUX_RGSR_OF3_Pos (3U)
7438#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
7439#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
7440#define DMAMUX_RGSR_OF4_Pos (4U)
7441#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos)
7442#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
7443#define DMAMUX_RGSR_OF5_Pos (5U)
7444#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos)
7445#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
7446#define DMAMUX_RGSR_OF6_Pos (6U)
7447#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos)
7448#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
7449#define DMAMUX_RGSR_OF7_Pos (7U)
7450#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos)
7451#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
7453/******************** Bits definition for DMAMUX_RGCFR register **************/
7454#define DMAMUX_RGCFR_COF0_Pos (0U)
7455#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
7456#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
7457#define DMAMUX_RGCFR_COF1_Pos (1U)
7458#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
7459#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
7460#define DMAMUX_RGCFR_COF2_Pos (2U)
7461#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
7462#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
7463#define DMAMUX_RGCFR_COF3_Pos (3U)
7464#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
7465#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
7466#define DMAMUX_RGCFR_COF4_Pos (4U)
7467#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos)
7468#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
7469#define DMAMUX_RGCFR_COF5_Pos (5U)
7470#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos)
7471#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
7472#define DMAMUX_RGCFR_COF6_Pos (6U)
7473#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos)
7474#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
7475#define DMAMUX_RGCFR_COF7_Pos (7U)
7476#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos)
7477#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
7479/******************************************************************************/
7480/* */
7481/* AHB Master DMA2D Controller (DMA2D) */
7482/* */
7483/******************************************************************************/
7484
7485/******************** Bit definition for DMA2D_CR register ******************/
7486
7487#define DMA2D_CR_START_Pos (0U)
7488#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
7489#define DMA2D_CR_START DMA2D_CR_START_Msk
7490#define DMA2D_CR_SUSP_Pos (1U)
7491#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
7492#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
7493#define DMA2D_CR_ABORT_Pos (2U)
7494#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
7495#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
7496#define DMA2D_CR_LOM_Pos (6U)
7497#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos)
7498#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk
7499#define DMA2D_CR_TEIE_Pos (8U)
7500#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
7501#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
7502#define DMA2D_CR_TCIE_Pos (9U)
7503#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
7504#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
7505#define DMA2D_CR_TWIE_Pos (10U)
7506#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
7507#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
7508#define DMA2D_CR_CAEIE_Pos (11U)
7509#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
7510#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
7511#define DMA2D_CR_CTCIE_Pos (12U)
7512#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
7513#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
7514#define DMA2D_CR_CEIE_Pos (13U)
7515#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
7516#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
7517#define DMA2D_CR_MODE_Pos (16U)
7518#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos)
7519#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
7520#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
7521#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
7522#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos)
7524/******************** Bit definition for DMA2D_ISR register *****************/
7525
7526#define DMA2D_ISR_TEIF_Pos (0U)
7527#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
7528#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
7529#define DMA2D_ISR_TCIF_Pos (1U)
7530#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
7531#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
7532#define DMA2D_ISR_TWIF_Pos (2U)
7533#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
7534#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
7535#define DMA2D_ISR_CAEIF_Pos (3U)
7536#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
7537#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
7538#define DMA2D_ISR_CTCIF_Pos (4U)
7539#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
7540#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
7541#define DMA2D_ISR_CEIF_Pos (5U)
7542#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
7543#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
7545/******************** Bit definition for DMA2D_IFCR register ****************/
7546
7547#define DMA2D_IFCR_CTEIF_Pos (0U)
7548#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
7549#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
7550#define DMA2D_IFCR_CTCIF_Pos (1U)
7551#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
7552#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
7553#define DMA2D_IFCR_CTWIF_Pos (2U)
7554#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
7555#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
7556#define DMA2D_IFCR_CAECIF_Pos (3U)
7557#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
7558#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
7559#define DMA2D_IFCR_CCTCIF_Pos (4U)
7560#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
7561#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
7562#define DMA2D_IFCR_CCEIF_Pos (5U)
7563#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
7564#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
7566/******************** Bit definition for DMA2D_FGMAR register ***************/
7567
7568#define DMA2D_FGMAR_MA_Pos (0U)
7569#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
7570#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
7572/******************** Bit definition for DMA2D_FGOR register ****************/
7573
7574#define DMA2D_FGOR_LO_Pos (0U)
7575#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos)
7576#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
7578/******************** Bit definition for DMA2D_BGMAR register ***************/
7579
7580#define DMA2D_BGMAR_MA_Pos (0U)
7581#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
7582#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
7584/******************** Bit definition for DMA2D_BGOR register ****************/
7585
7586#define DMA2D_BGOR_LO_Pos (0U)
7587#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos)
7588#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
7590/******************** Bit definition for DMA2D_FGPFCCR register *************/
7591
7592#define DMA2D_FGPFCCR_CM_Pos (0U)
7593#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
7594#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
7595#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
7596#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
7597#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
7598#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
7599#define DMA2D_FGPFCCR_CCM_Pos (4U)
7600#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
7601#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
7602#define DMA2D_FGPFCCR_START_Pos (5U)
7603#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
7604#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
7605#define DMA2D_FGPFCCR_CS_Pos (8U)
7606#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
7607#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
7608#define DMA2D_FGPFCCR_AM_Pos (16U)
7609#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
7610#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
7611#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
7612#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
7613#define DMA2D_FGPFCCR_CSS_Pos (18U)
7614#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
7615#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
7616#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
7617#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
7618#define DMA2D_FGPFCCR_AI_Pos (20U)
7619#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
7620#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
7621#define DMA2D_FGPFCCR_RBS_Pos (21U)
7622#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
7623#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
7624#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7625#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
7626#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
7628/******************** Bit definition for DMA2D_FGCOLR register **************/
7629
7630#define DMA2D_FGCOLR_BLUE_Pos (0U)
7631#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
7632#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
7633#define DMA2D_FGCOLR_GREEN_Pos (8U)
7634#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
7635#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
7636#define DMA2D_FGCOLR_RED_Pos (16U)
7637#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
7638#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
7640/******************** Bit definition for DMA2D_BGPFCCR register *************/
7641
7642#define DMA2D_BGPFCCR_CM_Pos (0U)
7643#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
7644#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
7645#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
7646#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
7647#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
7648#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
7649#define DMA2D_BGPFCCR_CCM_Pos (4U)
7650#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
7651#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
7652#define DMA2D_BGPFCCR_START_Pos (5U)
7653#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
7654#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
7655#define DMA2D_BGPFCCR_CS_Pos (8U)
7656#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
7657#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
7658#define DMA2D_BGPFCCR_AM_Pos (16U)
7659#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
7660#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
7661#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
7662#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
7663#define DMA2D_BGPFCCR_AI_Pos (20U)
7664#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
7665#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
7666#define DMA2D_BGPFCCR_RBS_Pos (21U)
7667#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
7668#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
7669#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7670#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
7671#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
7673/******************** Bit definition for DMA2D_BGCOLR register **************/
7674
7675#define DMA2D_BGCOLR_BLUE_Pos (0U)
7676#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
7677#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
7678#define DMA2D_BGCOLR_GREEN_Pos (8U)
7679#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
7680#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
7681#define DMA2D_BGCOLR_RED_Pos (16U)
7682#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
7683#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
7685/******************** Bit definition for DMA2D_FGCMAR register **************/
7686
7687#define DMA2D_FGCMAR_MA_Pos (0U)
7688#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
7689#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
7691/******************** Bit definition for DMA2D_BGCMAR register **************/
7692
7693#define DMA2D_BGCMAR_MA_Pos (0U)
7694#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
7695#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
7697/******************** Bit definition for DMA2D_OPFCCR register **************/
7698
7699#define DMA2D_OPFCCR_CM_Pos (0U)
7700#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
7701#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
7702#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
7703#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
7704#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
7705#define DMA2D_OPFCCR_SB_Pos (8U)
7706#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos)
7707#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk
7708#define DMA2D_OPFCCR_AI_Pos (20U)
7709#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
7710#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
7711#define DMA2D_OPFCCR_RBS_Pos (21U)
7712#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
7713#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
7715/******************** Bit definition for DMA2D_OCOLR register ***************/
7716
7719#define DMA2D_OCOLR_BLUE_1_Pos (0U)
7720#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
7721#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk
7722#define DMA2D_OCOLR_GREEN_1_Pos (8U)
7723#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
7724#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk
7725#define DMA2D_OCOLR_RED_1_Pos (16U)
7726#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
7727#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk
7728#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
7729#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
7730#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk
7733#define DMA2D_OCOLR_BLUE_2_Pos (0U)
7734#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
7735#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk
7736#define DMA2D_OCOLR_GREEN_2_Pos (5U)
7737#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
7738#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk
7739#define DMA2D_OCOLR_RED_2_Pos (11U)
7740#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
7741#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk
7744#define DMA2D_OCOLR_BLUE_3_Pos (0U)
7745#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
7746#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk
7747#define DMA2D_OCOLR_GREEN_3_Pos (5U)
7748#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
7749#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk
7750#define DMA2D_OCOLR_RED_3_Pos (10U)
7751#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
7752#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk
7753#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
7754#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
7755#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk
7758#define DMA2D_OCOLR_BLUE_4_Pos (0U)
7759#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
7760#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk
7761#define DMA2D_OCOLR_GREEN_4_Pos (4U)
7762#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
7763#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk
7764#define DMA2D_OCOLR_RED_4_Pos (8U)
7765#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
7766#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk
7767#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
7768#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
7769#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk
7771/******************** Bit definition for DMA2D_OMAR register ****************/
7772
7773#define DMA2D_OMAR_MA_Pos (0U)
7774#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
7775#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
7777/******************** Bit definition for DMA2D_OOR register *****************/
7778
7779#define DMA2D_OOR_LO_Pos (0U)
7780#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos)
7781#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
7783/******************** Bit definition for DMA2D_NLR register *****************/
7784
7785#define DMA2D_NLR_NL_Pos (0U)
7786#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
7787#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
7788#define DMA2D_NLR_PL_Pos (16U)
7789#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
7790#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
7792/******************** Bit definition for DMA2D_LWR register *****************/
7793
7794#define DMA2D_LWR_LW_Pos (0U)
7795#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
7796#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
7798/******************** Bit definition for DMA2D_AMTCR register ***************/
7799
7800#define DMA2D_AMTCR_EN_Pos (0U)
7801#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
7802#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
7803#define DMA2D_AMTCR_DT_Pos (8U)
7804#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
7805#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
7808/******************** Bit definition for DMA2D_FGCLUT register **************/
7809
7810/******************** Bit definition for DMA2D_BGCLUT register **************/
7811
7812
7813/******************************************************************************/
7814/* */
7815/* External Interrupt/Event Controller */
7816/* */
7817/******************************************************************************/
7818/****************** Bit definition for EXTI_RTSR1 register *******************/
7819#define EXTI_RTSR1_TR_Pos (0U)
7820#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
7821#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk
7822#define EXTI_RTSR1_TR0_Pos (0U)
7823#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos)
7824#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk
7825#define EXTI_RTSR1_TR1_Pos (1U)
7826#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos)
7827#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk
7828#define EXTI_RTSR1_TR2_Pos (2U)
7829#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos)
7830#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk
7831#define EXTI_RTSR1_TR3_Pos (3U)
7832#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos)
7833#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk
7834#define EXTI_RTSR1_TR4_Pos (4U)
7835#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos)
7836#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk
7837#define EXTI_RTSR1_TR5_Pos (5U)
7838#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos)
7839#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk
7840#define EXTI_RTSR1_TR6_Pos (6U)
7841#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos)
7842#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk
7843#define EXTI_RTSR1_TR7_Pos (7U)
7844#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos)
7845#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk
7846#define EXTI_RTSR1_TR8_Pos (8U)
7847#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos)
7848#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk
7849#define EXTI_RTSR1_TR9_Pos (9U)
7850#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos)
7851#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk
7852#define EXTI_RTSR1_TR10_Pos (10U)
7853#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos)
7854#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk
7855#define EXTI_RTSR1_TR11_Pos (11U)
7856#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos)
7857#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk
7858#define EXTI_RTSR1_TR12_Pos (12U)
7859#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos)
7860#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk
7861#define EXTI_RTSR1_TR13_Pos (13U)
7862#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos)
7863#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk
7864#define EXTI_RTSR1_TR14_Pos (14U)
7865#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos)
7866#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk
7867#define EXTI_RTSR1_TR15_Pos (15U)
7868#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos)
7869#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk
7870#define EXTI_RTSR1_TR16_Pos (16U)
7871#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos)
7872#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk
7873#define EXTI_RTSR1_TR17_Pos (17U)
7874#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos)
7875#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk
7876#define EXTI_RTSR1_TR18_Pos (18U)
7877#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos)
7878#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk
7879#define EXTI_RTSR1_TR19_Pos (19U)
7880#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos)
7881#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk
7882#define EXTI_RTSR1_TR20_Pos (20U)
7883#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos)
7884#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk
7885#define EXTI_RTSR1_TR21_Pos (21U)
7886#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos)
7887#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk
7889/****************** Bit definition for EXTI_FTSR1 register *******************/
7890#define EXTI_FTSR1_TR_Pos (0U)
7891#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
7892#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk
7893#define EXTI_FTSR1_TR0_Pos (0U)
7894#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos)
7895#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk
7896#define EXTI_FTSR1_TR1_Pos (1U)
7897#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos)
7898#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk
7899#define EXTI_FTSR1_TR2_Pos (2U)
7900#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos)
7901#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk
7902#define EXTI_FTSR1_TR3_Pos (3U)
7903#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos)
7904#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk
7905#define EXTI_FTSR1_TR4_Pos (4U)
7906#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos)
7907#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk
7908#define EXTI_FTSR1_TR5_Pos (5U)
7909#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos)
7910#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk
7911#define EXTI_FTSR1_TR6_Pos (6U)
7912#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos)
7913#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk
7914#define EXTI_FTSR1_TR7_Pos (7U)
7915#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos)
7916#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk
7917#define EXTI_FTSR1_TR8_Pos (8U)
7918#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos)
7919#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk
7920#define EXTI_FTSR1_TR9_Pos (9U)
7921#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos)
7922#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk
7923#define EXTI_FTSR1_TR10_Pos (10U)
7924#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos)
7925#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk
7926#define EXTI_FTSR1_TR11_Pos (11U)
7927#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos)
7928#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk
7929#define EXTI_FTSR1_TR12_Pos (12U)
7930#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos)
7931#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk
7932#define EXTI_FTSR1_TR13_Pos (13U)
7933#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos)
7934#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk
7935#define EXTI_FTSR1_TR14_Pos (14U)
7936#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos)
7937#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk
7938#define EXTI_FTSR1_TR15_Pos (15U)
7939#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos)
7940#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk
7941#define EXTI_FTSR1_TR16_Pos (16U)
7942#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos)
7943#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk
7944#define EXTI_FTSR1_TR17_Pos (17U)
7945#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos)
7946#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk
7947#define EXTI_FTSR1_TR18_Pos (18U)
7948#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos)
7949#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk
7950#define EXTI_FTSR1_TR19_Pos (19U)
7951#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos)
7952#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk
7953#define EXTI_FTSR1_TR20_Pos (20U)
7954#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos)
7955#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk
7956#define EXTI_FTSR1_TR21_Pos (21U)
7957#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos)
7958#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk
7960/****************** Bit definition for EXTI_SWIER1 register ******************/
7961#define EXTI_SWIER1_SWIER0_Pos (0U)
7962#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos)
7963#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk
7964#define EXTI_SWIER1_SWIER1_Pos (1U)
7965#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos)
7966#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk
7967#define EXTI_SWIER1_SWIER2_Pos (2U)
7968#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos)
7969#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk
7970#define EXTI_SWIER1_SWIER3_Pos (3U)
7971#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos)
7972#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk
7973#define EXTI_SWIER1_SWIER4_Pos (4U)
7974#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos)
7975#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk
7976#define EXTI_SWIER1_SWIER5_Pos (5U)
7977#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos)
7978#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk
7979#define EXTI_SWIER1_SWIER6_Pos (6U)
7980#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos)
7981#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk
7982#define EXTI_SWIER1_SWIER7_Pos (7U)
7983#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos)
7984#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk
7985#define EXTI_SWIER1_SWIER8_Pos (8U)
7986#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos)
7987#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk
7988#define EXTI_SWIER1_SWIER9_Pos (9U)
7989#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos)
7990#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk
7991#define EXTI_SWIER1_SWIER10_Pos (10U)
7992#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos)
7993#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk
7994#define EXTI_SWIER1_SWIER11_Pos (11U)
7995#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos)
7996#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk
7997#define EXTI_SWIER1_SWIER12_Pos (12U)
7998#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos)
7999#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk
8000#define EXTI_SWIER1_SWIER13_Pos (13U)
8001#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos)
8002#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk
8003#define EXTI_SWIER1_SWIER14_Pos (14U)
8004#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos)
8005#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk
8006#define EXTI_SWIER1_SWIER15_Pos (15U)
8007#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos)
8008#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk
8009#define EXTI_SWIER1_SWIER16_Pos (16U)
8010#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
8011#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk
8012#define EXTI_SWIER1_SWIER17_Pos (17U)
8013#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos)
8014#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk
8015#define EXTI_SWIER1_SWIER18_Pos (18U)
8016#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos)
8017#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk
8018#define EXTI_SWIER1_SWIER19_Pos (19U)
8019#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos)
8020#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk
8021#define EXTI_SWIER1_SWIER20_Pos (20U)
8022#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos)
8023#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk
8024#define EXTI_SWIER1_SWIER21_Pos (21U)
8025#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos)
8026#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk
8028/****************** Bit definition for EXTI_D3PMR1 register ******************/
8029#define EXTI_D3PMR1_MR0_Pos (0U)
8030#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos)
8031#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk
8032#define EXTI_D3PMR1_MR1_Pos (1U)
8033#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos)
8034#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk
8035#define EXTI_D3PMR1_MR2_Pos (2U)
8036#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos)
8037#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk
8038#define EXTI_D3PMR1_MR3_Pos (3U)
8039#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos)
8040#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk
8041#define EXTI_D3PMR1_MR4_Pos (4U)
8042#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos)
8043#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk
8044#define EXTI_D3PMR1_MR5_Pos (5U)
8045#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos)
8046#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk
8047#define EXTI_D3PMR1_MR6_Pos (6U)
8048#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos)
8049#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk
8050#define EXTI_D3PMR1_MR7_Pos (7U)
8051#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos)
8052#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk
8053#define EXTI_D3PMR1_MR8_Pos (8U)
8054#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos)
8055#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk
8056#define EXTI_D3PMR1_MR9_Pos (9U)
8057#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos)
8058#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk
8059#define EXTI_D3PMR1_MR10_Pos (10U)
8060#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos)
8061#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk
8062#define EXTI_D3PMR1_MR11_Pos (11U)
8063#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos)
8064#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk
8065#define EXTI_D3PMR1_MR12_Pos (12U)
8066#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos)
8067#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk
8068#define EXTI_D3PMR1_MR13_Pos (13U)
8069#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos)
8070#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk
8071#define EXTI_D3PMR1_MR14_Pos (14U)
8072#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos)
8073#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk
8074#define EXTI_D3PMR1_MR15_Pos (15U)
8075#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos)
8076#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk
8077#define EXTI_D3PMR1_MR19_Pos (19U)
8078#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos)
8079#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk
8080#define EXTI_D3PMR1_MR20_Pos (20U)
8081#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos)
8082#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk
8083#define EXTI_D3PMR1_MR21_Pos (21U)
8084#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos)
8085#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk
8086#define EXTI_D3PMR1_MR25_Pos (24U)
8087#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos)
8088#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk
8090/******************* Bit definition for EXTI_D3PCR1L register ****************/
8091#define EXTI_D3PCR1L_PCS0_Pos (0U)
8092#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
8093#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk
8094#define EXTI_D3PCR1L_PCS1_Pos (2U)
8095#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
8096#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk
8097#define EXTI_D3PCR1L_PCS2_Pos (4U)
8098#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
8099#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk
8100#define EXTI_D3PCR1L_PCS3_Pos (6U)
8101#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
8102#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk
8103#define EXTI_D3PCR1L_PCS4_Pos (8U)
8104#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
8105#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk
8106#define EXTI_D3PCR1L_PCS5_Pos (10U)
8107#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
8108#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk
8109#define EXTI_D3PCR1L_PCS6_Pos (12U)
8110#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
8111#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk
8112#define EXTI_D3PCR1L_PCS7_Pos (14U)
8113#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
8114#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk
8115#define EXTI_D3PCR1L_PCS8_Pos (16U)
8116#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
8117#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk
8118#define EXTI_D3PCR1L_PCS9_Pos (18U)
8119#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
8120#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk
8121#define EXTI_D3PCR1L_PCS10_Pos (20U)
8122#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
8123#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk
8124#define EXTI_D3PCR1L_PCS11_Pos (22U)
8125#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
8126#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk
8127#define EXTI_D3PCR1L_PCS12_Pos (24U)
8128#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
8129#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk
8130#define EXTI_D3PCR1L_PCS13_Pos (26U)
8131#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
8132#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk
8133#define EXTI_D3PCR1L_PCS14_Pos (28U)
8134#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
8135#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk
8136#define EXTI_D3PCR1L_PCS15_Pos (30U)
8137#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
8138#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk
8140/******************* Bit definition for EXTI_D3PCR1H register ****************/
8141#define EXTI_D3PCR1H_PCS19_Pos (6U)
8142#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
8143#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk
8144#define EXTI_D3PCR1H_PCS20_Pos (8U)
8145#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
8146#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk
8147#define EXTI_D3PCR1H_PCS21_Pos (10U)
8148#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
8149#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk
8150#define EXTI_D3PCR1H_PCS25_Pos (18U)
8151#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
8152#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk
8154/****************** Bit definition for EXTI_RTSR2 register *******************/
8155#define EXTI_RTSR2_TR_Pos (17U)
8156#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos)
8157#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk
8158#define EXTI_RTSR2_TR49_Pos (17U)
8159#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos)
8160#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk
8161#define EXTI_RTSR2_TR51_Pos (19U)
8162#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos)
8163#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk
8165/****************** Bit definition for EXTI_FTSR2 register *******************/
8166#define EXTI_FTSR2_TR_Pos (17U)
8167#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos)
8168#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk
8169#define EXTI_FTSR2_TR49_Pos (17U)
8170#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos)
8171#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk
8172#define EXTI_FTSR2_TR51_Pos (19U)
8173#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos)
8174#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk
8176/****************** Bit definition for EXTI_SWIER2 register ******************/
8177#define EXTI_SWIER2_SWIER49_Pos (17U)
8178#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos)
8179#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk
8180#define EXTI_SWIER2_SWIER51_Pos (19U)
8181#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos)
8182#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk
8184/****************** Bit definition for EXTI_D3PMR2 register ******************/
8185#define EXTI_D3PMR2_MR34_Pos (2U)
8186#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos)
8187#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk
8188#define EXTI_D3PMR2_MR35_Pos (3U)
8189#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos)
8190#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk
8191#define EXTI_D3PMR2_MR41_Pos (9U)
8192#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos)
8193#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk
8194#define EXTI_D3PMR2_MR48_Pos (16U)
8195#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos)
8196#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk
8197#define EXTI_D3PMR2_MR49_Pos (17U)
8198#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos)
8199#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk
8200#define EXTI_D3PMR2_MR50_Pos (18U)
8201#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos)
8202#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk
8203#define EXTI_D3PMR2_MR51_Pos (19U)
8204#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos)
8205#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk
8206/******************* Bit definition for EXTI_D3PCR2L register ****************/
8207#define EXTI_D3PCR2L_PCS34_Pos (4U)
8208#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
8209#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk
8210#define EXTI_D3PCR2L_PCS35_Pos (6U)
8211#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
8212#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk
8213#define EXTI_D3PCR2L_PCS41_Pos (18U)
8214#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
8215#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk
8218/******************* Bit definition for EXTI_D3PCR2H register ****************/
8219#define EXTI_D3PCR2H_PCS48_Pos (0U)
8220#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
8221#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk
8222#define EXTI_D3PCR2H_PCS49_Pos (2U)
8223#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
8224#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk
8225#define EXTI_D3PCR2H_PCS50_Pos (4U)
8226#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
8227#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk
8228#define EXTI_D3PCR2H_PCS51_Pos (6U)
8229#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
8230#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk
8231/****************** Bit definition for EXTI_RTSR3 register *******************/
8232#define EXTI_RTSR3_TR_Pos (18U)
8233#define EXTI_RTSR3_TR_Msk (0x9UL << EXTI_RTSR3_TR_Pos)
8234#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk
8235#define EXTI_RTSR3_TR82_Pos (18U)
8236#define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos)
8237#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk
8238#define EXTI_RTSR3_TR85_Pos (21U)
8239#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos)
8240#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk
8242/****************** Bit definition for EXTI_FTSR3 register *******************/
8243#define EXTI_FTSR3_TR_Pos (18U)
8244#define EXTI_FTSR3_TR_Msk (0x9UL << EXTI_FTSR3_TR_Pos)
8245#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk
8246#define EXTI_FTSR3_TR82_Pos (18U)
8247#define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos)
8248#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk
8249#define EXTI_FTSR3_TR85_Pos (21U)
8250#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos)
8251#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk
8253/****************** Bit definition for EXTI_SWIER3 register ******************/
8254#define EXTI_SWIER3_SWI_Pos (18U)
8255#define EXTI_SWIER3_SWI_Msk (0x9UL << EXTI_SWIER3_SWI_Pos)
8256#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk
8257#define EXTI_SWIER3_SWIER82_Pos (18U)
8258#define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos)
8259#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk
8260#define EXTI_SWIER3_SWIER85_Pos (21U)
8261#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos)
8262#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk
8264/****************** Bit definition for EXTI_D3PMR3 register ******************/
8265#define EXTI_D3PMR3_MR88_Pos (24U)
8266#define EXTI_D3PMR3_MR88_Msk (0x1UL << EXTI_D3PMR3_MR88_Pos)
8267#define EXTI_D3PMR3_MR88 EXTI_D3PMR3_MR88_Msk
8269/******************* Bit definition for EXTI_D3PCR3H register ****************/
8270#define EXTI_D3PCR3H_PCS88_Pos (16U)
8271#define EXTI_D3PCR3H_PCS88_Msk (0x3UL << EXTI_D3PCR3H_PCS88_Pos)
8272#define EXTI_D3PCR3H_PCS88 EXTI_D3PCR3H_PCS88_Msk
8274/******************* Bit definition for EXTI_IMR1 register *******************/
8275#define EXTI_IMR1_IM_Pos (0U)
8276#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
8277#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
8278#define EXTI_IMR1_IM0_Pos (0U)
8279#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
8280#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
8281#define EXTI_IMR1_IM1_Pos (1U)
8282#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
8283#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
8284#define EXTI_IMR1_IM2_Pos (2U)
8285#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
8286#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
8287#define EXTI_IMR1_IM3_Pos (3U)
8288#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
8289#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
8290#define EXTI_IMR1_IM4_Pos (4U)
8291#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
8292#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
8293#define EXTI_IMR1_IM5_Pos (5U)
8294#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
8295#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
8296#define EXTI_IMR1_IM6_Pos (6U)
8297#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
8298#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
8299#define EXTI_IMR1_IM7_Pos (7U)
8300#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
8301#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
8302#define EXTI_IMR1_IM8_Pos (8U)
8303#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
8304#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
8305#define EXTI_IMR1_IM9_Pos (9U)
8306#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
8307#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
8308#define EXTI_IMR1_IM10_Pos (10U)
8309#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
8310#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
8311#define EXTI_IMR1_IM11_Pos (11U)
8312#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
8313#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
8314#define EXTI_IMR1_IM12_Pos (12U)
8315#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
8316#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
8317#define EXTI_IMR1_IM13_Pos (13U)
8318#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
8319#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
8320#define EXTI_IMR1_IM14_Pos (14U)
8321#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
8322#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
8323#define EXTI_IMR1_IM15_Pos (15U)
8324#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
8325#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
8326#define EXTI_IMR1_IM16_Pos (16U)
8327#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
8328#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
8329#define EXTI_IMR1_IM17_Pos (17U)
8330#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
8331#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
8332#define EXTI_IMR1_IM18_Pos (18U)
8333#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
8334#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
8335#define EXTI_IMR1_IM19_Pos (19U)
8336#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
8337#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
8338#define EXTI_IMR1_IM20_Pos (20U)
8339#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
8340#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
8341#define EXTI_IMR1_IM21_Pos (21U)
8342#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
8343#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
8344#define EXTI_IMR1_IM22_Pos (22U)
8345#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
8346#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
8347#define EXTI_IMR1_IM23_Pos (23U)
8348#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
8349#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
8350#define EXTI_IMR1_IM24_Pos (24U)
8351#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
8352#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
8353#define EXTI_IMR1_IM25_Pos (25U)
8354#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
8355#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
8356#define EXTI_IMR1_IM26_Pos (26U)
8357#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
8358#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
8359#define EXTI_IMR1_IM27_Pos (27U)
8360#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
8361#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
8362#define EXTI_IMR1_IM28_Pos (28U)
8363#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
8364#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
8365#define EXTI_IMR1_IM29_Pos (29U)
8366#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
8367#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
8368#define EXTI_IMR1_IM30_Pos (30U)
8369#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
8370#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
8371#define EXTI_IMR1_IM31_Pos (31U)
8372#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
8373#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
8375/******************* Bit definition for EXTI_EMR1 register *******************/
8376#define EXTI_EMR1_EM_Pos (0U)
8377#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
8378#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk
8379#define EXTI_EMR1_EM0_Pos (0U)
8380#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
8381#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
8382#define EXTI_EMR1_EM1_Pos (1U)
8383#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
8384#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
8385#define EXTI_EMR1_EM2_Pos (2U)
8386#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
8387#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
8388#define EXTI_EMR1_EM3_Pos (3U)
8389#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
8390#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
8391#define EXTI_EMR1_EM4_Pos (4U)
8392#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
8393#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
8394#define EXTI_EMR1_EM5_Pos (5U)
8395#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
8396#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
8397#define EXTI_EMR1_EM6_Pos (6U)
8398#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
8399#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
8400#define EXTI_EMR1_EM7_Pos (7U)
8401#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
8402#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
8403#define EXTI_EMR1_EM8_Pos (8U)
8404#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
8405#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
8406#define EXTI_EMR1_EM9_Pos (9U)
8407#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
8408#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
8409#define EXTI_EMR1_EM10_Pos (10U)
8410#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
8411#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
8412#define EXTI_EMR1_EM11_Pos (11U)
8413#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
8414#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
8415#define EXTI_EMR1_EM12_Pos (12U)
8416#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
8417#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
8418#define EXTI_EMR1_EM13_Pos (13U)
8419#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
8420#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
8421#define EXTI_EMR1_EM14_Pos (14U)
8422#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
8423#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
8424#define EXTI_EMR1_EM15_Pos (15U)
8425#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
8426#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
8427#define EXTI_EMR1_EM16_Pos (16U)
8428#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
8429#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
8430#define EXTI_EMR1_EM17_Pos (17U)
8431#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
8432#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
8433#define EXTI_EMR1_EM18_Pos (18U)
8434#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
8435#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
8436#define EXTI_EMR1_EM20_Pos (20U)
8437#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
8438#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
8439#define EXTI_EMR1_EM21_Pos (21U)
8440#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
8441#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
8442#define EXTI_EMR1_EM22_Pos (22U)
8443#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
8444#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
8445#define EXTI_EMR1_EM23_Pos (23U)
8446#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
8447#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
8448#define EXTI_EMR1_EM24_Pos (24U)
8449#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
8450#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
8451#define EXTI_EMR1_EM25_Pos (25U)
8452#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
8453#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
8454#define EXTI_EMR1_EM26_Pos (26U)
8455#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
8456#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
8457#define EXTI_EMR1_EM27_Pos (27U)
8458#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
8459#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
8460#define EXTI_EMR1_EM28_Pos (28U)
8461#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
8462#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
8463#define EXTI_EMR1_EM29_Pos (29U)
8464#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
8465#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
8466#define EXTI_EMR1_EM30_Pos (30U)
8467#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
8468#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
8469#define EXTI_EMR1_EM31_Pos (31U)
8470#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
8471#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
8473/******************* Bit definition for EXTI_PR1 register ********************/
8474#define EXTI_PR1_PR_Pos (0U)
8475#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos)
8476#define EXTI_PR1_PR EXTI_PR1_PR_Msk
8477#define EXTI_PR1_PR0_Pos (0U)
8478#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos)
8479#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk
8480#define EXTI_PR1_PR1_Pos (1U)
8481#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos)
8482#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk
8483#define EXTI_PR1_PR2_Pos (2U)
8484#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos)
8485#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk
8486#define EXTI_PR1_PR3_Pos (3U)
8487#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos)
8488#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk
8489#define EXTI_PR1_PR4_Pos (4U)
8490#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos)
8491#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk
8492#define EXTI_PR1_PR5_Pos (5U)
8493#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos)
8494#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk
8495#define EXTI_PR1_PR6_Pos (6U)
8496#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos)
8497#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk
8498#define EXTI_PR1_PR7_Pos (7U)
8499#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos)
8500#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk
8501#define EXTI_PR1_PR8_Pos (8U)
8502#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
8503#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk
8504#define EXTI_PR1_PR9_Pos (9U)
8505#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos)
8506#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk
8507#define EXTI_PR1_PR10_Pos (10U)
8508#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos)
8509#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk
8510#define EXTI_PR1_PR11_Pos (11U)
8511#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos)
8512#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk
8513#define EXTI_PR1_PR12_Pos (12U)
8514#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos)
8515#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk
8516#define EXTI_PR1_PR13_Pos (13U)
8517#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos)
8518#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk
8519#define EXTI_PR1_PR14_Pos (14U)
8520#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos)
8521#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk
8522#define EXTI_PR1_PR15_Pos (15U)
8523#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos)
8524#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk
8525#define EXTI_PR1_PR16_Pos (16U)
8526#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos)
8527#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk
8528#define EXTI_PR1_PR17_Pos (17U)
8529#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos)
8530#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk
8531#define EXTI_PR1_PR18_Pos (18U)
8532#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos)
8533#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk
8534#define EXTI_PR1_PR19_Pos (19U)
8535#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos)
8536#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk
8537#define EXTI_PR1_PR20_Pos (20U)
8538#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos)
8539#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk
8540#define EXTI_PR1_PR21_Pos (21U)
8541#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos)
8542#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk
8544/******************* Bit definition for EXTI_IMR2 register *******************/
8545#define EXTI_IMR2_IM_Pos (0U)
8546#define EXTI_IMR2_IM_Msk (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)
8547#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
8548#define EXTI_IMR2_IM32_Pos (0U)
8549#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
8550#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
8551#define EXTI_IMR2_IM33_Pos (1U)
8552#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
8553#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
8554#define EXTI_IMR2_IM34_Pos (2U)
8555#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
8556#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
8557#define EXTI_IMR2_IM35_Pos (3U)
8558#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
8559#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
8560#define EXTI_IMR2_IM36_Pos (4U)
8561#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
8562#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
8563#define EXTI_IMR2_IM37_Pos (5U)
8564#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
8565#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
8566#define EXTI_IMR2_IM38_Pos (6U)
8567#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
8568#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
8569#define EXTI_IMR2_IM39_Pos (7U)
8570#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
8571#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
8572#define EXTI_IMR2_IM40_Pos (8U)
8573#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
8574#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
8575#define EXTI_IMR2_IM41_Pos (9U)
8576#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
8577#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
8578#define EXTI_IMR2_IM42_Pos (10U)
8579#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
8580#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
8581#define EXTI_IMR2_IM43_Pos (11U)
8582#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)
8583#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk
8584#define EXTI_IMR2_IM47_Pos (15U)
8585#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos)
8586#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk
8587#define EXTI_IMR2_IM48_Pos (16U)
8588#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos)
8589#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk
8590#define EXTI_IMR2_IM49_Pos (17U)
8591#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos)
8592#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk
8593#define EXTI_IMR2_IM50_Pos (18U)
8594#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos)
8595#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk
8596#define EXTI_IMR2_IM51_Pos (19U)
8597#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos)
8598#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk
8599#define EXTI_IMR2_IM52_Pos (20U)
8600#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos)
8601#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk
8602#define EXTI_IMR2_IM53_Pos (21U)
8603#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos)
8604#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk
8605#define EXTI_IMR2_IM54_Pos (22U)
8606#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos)
8607#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk
8608#define EXTI_IMR2_IM55_Pos (23U)
8609#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos)
8610#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk
8611#define EXTI_IMR2_IM56_Pos (24U)
8612#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos)
8613#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk
8614#define EXTI_IMR2_IM57_Pos (25U)
8615#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos)
8616#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk
8617#define EXTI_IMR2_IM58_Pos (26U)
8618#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos)
8619#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk
8620#define EXTI_IMR2_IM59_Pos (27U)
8621#define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos)
8622#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk
8623#define EXTI_IMR2_IM60_Pos (28U)
8624#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
8625#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk
8626#define EXTI_IMR2_IM61_Pos (29U)
8627#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos)
8628#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk
8629#define EXTI_IMR2_IM62_Pos (30U)
8630#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos)
8631#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk
8632#define EXTI_IMR2_IM63_Pos (31U)
8633#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos)
8634#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk
8636/******************* Bit definition for EXTI_EMR2 register *******************/
8637#define EXTI_EMR2_EM_Pos (0U)
8638#define EXTI_EMR2_EM_Msk (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)
8639#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
8640#define EXTI_EMR2_EM32_Pos (0U)
8641#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
8642#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
8643#define EXTI_EMR2_EM33_Pos (1U)
8644#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
8645#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
8646#define EXTI_EMR2_EM34_Pos (2U)
8647#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
8648#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
8649#define EXTI_EMR2_EM35_Pos (3U)
8650#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
8651#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
8652#define EXTI_EMR2_EM36_Pos (4U)
8653#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
8654#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
8655#define EXTI_EMR2_EM37_Pos (5U)
8656#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
8657#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
8658#define EXTI_EMR2_EM38_Pos (6U)
8659#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
8660#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
8661#define EXTI_EMR2_EM39_Pos (7U)
8662#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
8663#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
8664#define EXTI_EMR2_EM40_Pos (8U)
8665#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
8666#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
8667#define EXTI_EMR2_EM41_Pos (9U)
8668#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
8669#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
8670#define EXTI_EMR2_EM42_Pos (10U)
8671#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
8672#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
8673#define EXTI_EMR2_EM43_Pos (11U)
8674#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos)
8675#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk
8676#define EXTI_EMR2_EM47_Pos (15U)
8677#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos)
8678#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk
8679#define EXTI_EMR2_EM48_Pos (16U)
8680#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos)
8681#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk
8682#define EXTI_EMR2_EM49_Pos (17U)
8683#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos)
8684#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk
8685#define EXTI_EMR2_EM50_Pos (18U)
8686#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos)
8687#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk
8688#define EXTI_EMR2_EM51_Pos (19U)
8689#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos)
8690#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk
8691#define EXTI_EMR2_EM52_Pos (20U)
8692#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos)
8693#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk
8694#define EXTI_EMR2_EM53_Pos (21U)
8695#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos)
8696#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk
8697#define EXTI_EMR2_EM54_Pos (22U)
8698#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos)
8699#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk
8700#define EXTI_EMR2_EM55_Pos (23U)
8701#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos)
8702#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk
8703#define EXTI_EMR2_EM56_Pos (24U)
8704#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos)
8705#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk
8706#define EXTI_EMR2_EM57_Pos (25U)
8707#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos)
8708#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk
8709#define EXTI_EMR2_EM58_Pos (26U)
8710#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos)
8711#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk
8712#define EXTI_EMR2_EM59_Pos (27U)
8713#define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos)
8714#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk
8715#define EXTI_EMR2_EM60_Pos (28U)
8716#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos)
8717#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk
8718#define EXTI_EMR2_EM61_Pos (29U)
8719#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos)
8720#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk
8721#define EXTI_EMR2_EM62_Pos (30U)
8722#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos)
8723#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk
8724#define EXTI_EMR2_EM63_Pos (31U)
8725#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos)
8726#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk
8728/******************* Bit definition for EXTI_PR2 register ********************/
8729#define EXTI_PR2_PR_Pos (17U)
8730#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos)
8731#define EXTI_PR2_PR EXTI_PR2_PR_Msk
8732#define EXTI_PR2_PR49_Pos (17U)
8733#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos)
8734#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk
8735#define EXTI_PR2_PR51_Pos (19U)
8736#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos)
8737#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk
8739/******************* Bit definition for EXTI_IMR3 register *******************/
8740#define EXTI_IMR3_IM_Pos (0U)
8741#define EXTI_IMR3_IM_Msk (0x01A527FFUL << EXTI_IMR3_IM_Pos)
8742#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk
8743#define EXTI_IMR3_IM64_Pos (0U)
8744#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos)
8745#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk
8746#define EXTI_IMR3_IM65_Pos (1U)
8747#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos)
8748#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk
8749#define EXTI_IMR3_IM66_Pos (2U)
8750#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos)
8751#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk
8752#define EXTI_IMR3_IM67_Pos (3U)
8753#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos)
8754#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk
8755#define EXTI_IMR3_IM68_Pos (4U)
8756#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos)
8757#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk
8758#define EXTI_IMR3_IM69_Pos (5U)
8759#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos)
8760#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk
8761#define EXTI_IMR3_IM70_Pos (6U)
8762#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos)
8763#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk
8764#define EXTI_IMR3_IM71_Pos (7U)
8765#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos)
8766#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk
8767#define EXTI_IMR3_IM72_Pos (8U)
8768#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos)
8769#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk
8770#define EXTI_IMR3_IM73_Pos (9U)
8771#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos)
8772#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk
8773#define EXTI_IMR3_IM74_Pos (10U)
8774#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos)
8775#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk
8776#define EXTI_IMR3_IM77_Pos (13U)
8777#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos)
8778#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk
8779#define EXTI_IMR3_IM80_Pos (16U)
8780#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos)
8781#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk
8782#define EXTI_IMR3_IM82_Pos (18U)
8783#define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos)
8784#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk
8785#define EXTI_IMR3_IM85_Pos (21U)
8786#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos)
8787#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk
8788#define EXTI_IMR3_IM87_Pos (23U)
8789#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos)
8790#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk
8793#define EXTI_IMR3_IM88_Pos (24U)
8794#define EXTI_IMR3_IM88_Msk (0x1UL << EXTI_IMR3_IM88_Pos)
8795#define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk
8797/******************* Bit definition for EXTI_EMR3 register *******************/
8798#define EXTI_EMR3_EM_Pos (0U)
8799#define EXTI_EMR3_EM_Msk (0x01A527FFUL << EXTI_EMR3_EM_Pos)
8800#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk
8801#define EXTI_EMR3_EM64_Pos (0U)
8802#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos)
8803#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk
8804#define EXTI_EMR3_EM65_Pos (1U)
8805#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos)
8806#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk
8807#define EXTI_EMR3_EM66_Pos (2U)
8808#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos)
8809#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk
8810#define EXTI_EMR3_EM67_Pos (3U)
8811#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos)
8812#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk
8813#define EXTI_EMR3_EM68_Pos (4U)
8814#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos)
8815#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk
8816#define EXTI_EMR3_EM69_Pos (5U)
8817#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos)
8818#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk
8819#define EXTI_EMR3_EM70_Pos (6U)
8820#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos)
8821#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk
8822#define EXTI_EMR3_EM71_Pos (7U)
8823#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos)
8824#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk
8825#define EXTI_EMR3_EM72_Pos (8U)
8826#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos)
8827#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk
8828#define EXTI_EMR3_EM73_Pos (9U)
8829#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos)
8830#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk
8831#define EXTI_EMR3_EM74_Pos (10U)
8832#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos)
8833#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk
8834#define EXTI_EMR3_EM77_Pos (13U)
8835#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos)
8836#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk
8837#define EXTI_EMR3_EM80_Pos (16U)
8838#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos)
8839#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk
8840#define EXTI_EMR3_EM81_Pos (17U)
8841#define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos)
8842#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk
8843#define EXTI_EMR3_EM82_Pos (18U)
8844#define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos)
8845#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk
8846#define EXTI_EMR3_EM85_Pos (21U)
8847#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos)
8848#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk
8849#define EXTI_EMR3_EM87_Pos (23U)
8850#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos)
8851#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk
8853#define EXTI_EMR3_EM88_Pos (24U)
8854#define EXTI_EMR3_EM88_Msk (0x1UL << EXTI_EMR3_EM88_Pos)
8855#define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk
8857/******************* Bit definition for EXTI_PR3 register ********************/
8858#define EXTI_PR3_PR_Pos (18U)
8859#define EXTI_PR3_PR_Msk (0x9UL << EXTI_PR3_PR_Pos)
8860#define EXTI_PR3_PR EXTI_PR3_PR_Msk
8861#define EXTI_PR3_PR82_Pos (18U)
8862#define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos)
8863#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk
8864#define EXTI_PR3_PR85_Pos (21U)
8865#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos)
8866#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk
8867/******************************************************************************/
8868/* */
8869/* FLASH */
8870/* */
8871/******************************************************************************/
8872/*
8873* @brief FLASH Global Defines
8874*/
8875#define FLASH_SIZE_DATA_REGISTER 0x08FFF80CU
8876#define FLASH_SECTOR_TOTAL 128U /* 128 sectors */
8877#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
8878 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
8879 (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
8880#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
8881#define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
8882#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
8883#define FLASH_NB_32BITWORD_IN_FLASHWORD 4U /* 128 bits */
8884#define DUAL_BANK /* Dual-bank Flash */
8885
8886/******************* Bits definition for FLASH_ACR register **********************/
8887#define FLASH_ACR_LATENCY_Pos (0U)
8888#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
8889#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
8890#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
8891#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
8892#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
8893#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
8894#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
8895#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
8896#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
8897#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
8898
8899#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
8900#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
8901#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
8902#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
8903#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
8905/* Legacy FLASH Latency defines */
8906#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
8907#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
8908#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
8909#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
8910#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
8911#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
8912#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
8913#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
8914/******************* Bits definition for FLASH_CR register ***********************/
8915#define FLASH_CR_LOCK_Pos (0U)
8916#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
8917#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
8918#define FLASH_CR_PG_Pos (1U)
8919#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
8920#define FLASH_CR_PG FLASH_CR_PG_Msk
8921#define FLASH_CR_SER_Pos (2U)
8922#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
8923#define FLASH_CR_SER FLASH_CR_SER_Msk
8924#define FLASH_CR_BER_Pos (3U)
8925#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos)
8926#define FLASH_CR_BER FLASH_CR_BER_Msk
8927#define FLASH_CR_FW_Pos (4U)
8928#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos)
8929#define FLASH_CR_FW FLASH_CR_FW_Msk
8930#define FLASH_CR_START_Pos (5U)
8931#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos)
8932#define FLASH_CR_START FLASH_CR_START_Msk
8933#define FLASH_CR_SNB_Pos (6U)
8934#define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos)
8935#define FLASH_CR_SNB FLASH_CR_SNB_Msk
8936#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
8937#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
8938#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
8939#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
8940#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
8941#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos)
8942#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos)
8943#define FLASH_CR_CRC_EN_Pos (15U)
8944#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos)
8945#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
8946#define FLASH_CR_EOPIE_Pos (16U)
8947#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
8948#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
8949#define FLASH_CR_WRPERRIE_Pos (17U)
8950#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos)
8951#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
8952#define FLASH_CR_PGSERRIE_Pos (18U)
8953#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos)
8954#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
8955#define FLASH_CR_STRBERRIE_Pos (19U)
8956#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos)
8957#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
8958#define FLASH_CR_INCERRIE_Pos (21U)
8959#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos)
8960#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
8961#define FLASH_CR_RDPERRIE_Pos (23U)
8962#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos)
8963#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
8964#define FLASH_CR_RDSERRIE_Pos (24U)
8965#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos)
8966#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
8967#define FLASH_CR_SNECCERRIE_Pos (25U)
8968#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos)
8969#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
8970#define FLASH_CR_DBECCERRIE_Pos (26U)
8971#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos)
8972#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
8973#define FLASH_CR_CRCENDIE_Pos (27U)
8974#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos)
8975#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
8976#define FLASH_CR_CRCRDERRIE_Pos (28U)
8977#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
8978#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
8980/******************* Bits definition for FLASH_SR register ***********************/
8981#define FLASH_SR_BSY_Pos (0U)
8982#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
8983#define FLASH_SR_BSY FLASH_SR_BSY_Msk
8984#define FLASH_SR_WBNE_Pos (1U)
8985#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos)
8986#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
8987#define FLASH_SR_QW_Pos (2U)
8988#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos)
8989#define FLASH_SR_QW FLASH_SR_QW_Msk
8990#define FLASH_SR_CRC_BUSY_Pos (3U)
8991#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos)
8992#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
8993#define FLASH_SR_EOP_Pos (16U)
8994#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
8995#define FLASH_SR_EOP FLASH_SR_EOP_Msk
8996#define FLASH_SR_WRPERR_Pos (17U)
8997#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
8998#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
8999#define FLASH_SR_PGSERR_Pos (18U)
9000#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
9001#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
9002#define FLASH_SR_STRBERR_Pos (19U)
9003#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos)
9004#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
9005#define FLASH_SR_INCERR_Pos (21U)
9006#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos)
9007#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
9008#define FLASH_SR_RDPERR_Pos (23U)
9009#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos)
9010#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
9011#define FLASH_SR_RDSERR_Pos (24U)
9012#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos)
9013#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
9014#define FLASH_SR_SNECCERR_Pos (25U)
9015#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos)
9016#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
9017#define FLASH_SR_DBECCERR_Pos (26U)
9018#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos)
9019#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
9020#define FLASH_SR_CRCEND_Pos (27U)
9021#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos)
9022#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
9023#define FLASH_SR_CRCRDERR_Pos (28U)
9024#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos)
9025#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
9027/******************* Bits definition for FLASH_CCR register *******************/
9028#define FLASH_CCR_CLR_EOP_Pos (16U)
9029#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos)
9030#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
9031#define FLASH_CCR_CLR_WRPERR_Pos (17U)
9032#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
9033#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
9034#define FLASH_CCR_CLR_PGSERR_Pos (18U)
9035#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
9036#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
9037#define FLASH_CCR_CLR_STRBERR_Pos (19U)
9038#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
9039#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
9040#define FLASH_CCR_CLR_INCERR_Pos (21U)
9041#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
9042#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
9043#define FLASH_CCR_CLR_RDPERR_Pos (23U)
9044#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
9045#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
9046#define FLASH_CCR_CLR_RDSERR_Pos (24U)
9047#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
9048#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
9049#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
9050#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
9051#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
9052#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
9053#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
9054#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
9055#define FLASH_CCR_CLR_CRCEND_Pos (27U)
9056#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
9057#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
9058#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
9059#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
9060#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
9062/******************* Bits definition for FLASH_OPTCR register *******************/
9063#define FLASH_OPTCR_OPTLOCK_Pos (0U)
9064#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
9065#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
9066#define FLASH_OPTCR_OPTSTART_Pos (1U)
9067#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
9068#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
9069#define FLASH_OPTCR_MER_Pos (4U)
9070#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos)
9071#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
9072#define FLASH_OPTCR_PG_OTP_Pos (5U)
9073#define FLASH_OPTCR_PG_OTP_Msk (0x1UL << FLASH_OPTCR_PG_OTP_Pos)
9074#define FLASH_OPTCR_PG_OTP FLASH_OPTCR_PG_OTP_Msk
9075#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
9076#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
9077#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
9078#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
9079#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)
9080#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
9082/******************* Bits definition for FLASH_OPTSR register ***************/
9083#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
9084#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
9085#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
9086#define FLASH_OPTSR_BOR_LEV_Pos (2U)
9087#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
9088#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
9089#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
9090#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
9091#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
9092#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
9093#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
9094#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
9095#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
9096#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
9097#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
9098#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
9099#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
9100#define FLASH_OPTSR_RDP_Pos (8U)
9101#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos)
9102#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
9103#define FLASH_OPTSR_VDDMMC_HSLV_Pos (16U)
9104#define FLASH_OPTSR_VDDMMC_HSLV_Msk (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos)
9105#define FLASH_OPTSR_VDDMMC_HSLV FLASH_OPTSR_VDDMMC_HSLV_Msk
9106#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
9107#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
9108#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
9109#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
9110#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
9111#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
9112#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
9113#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
9114#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
9115#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
9116#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
9117#define FLASH_OPTSR_SECURITY_Pos (21U)
9118#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos)
9119#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
9120#define FLASH_OPTSR_IO_HSLV_Pos (29U)
9121#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
9122#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
9123#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
9124#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
9125#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
9126#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
9127#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos)
9128#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
9130/******************* Bits definition for FLASH_OPTCCR register *******************/
9131#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
9132#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
9133#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
9135/******************* Bits definition for FLASH_PRAR register *********************/
9136#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
9137#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
9138#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
9139#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
9140#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
9141#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
9142#define FLASH_PRAR_DMEP_Pos (31U)
9143#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos)
9144#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
9146/******************* Bits definition for FLASH_SCAR register *********************/
9147#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
9148#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
9149#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
9150#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
9151#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
9152#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
9153#define FLASH_SCAR_DMES_Pos (31U)
9154#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos)
9155#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
9157/******************* Bits definition for FLASH_WPSN register *********************/
9158#define FLASH_WPSN_WRPSN_Pos (0U)
9159#define FLASH_WPSN_WRPSN_Msk (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)
9160#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
9162/******************* Bits definition for FLASH_BOOT_CUR register ****************/
9163#define FLASH_BOOT_ADD0_Pos (0U)
9164#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos)
9165#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk
9166#define FLASH_BOOT_ADD1_Pos (16U)
9167#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos)
9168#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk
9171/******************* Bits definition for FLASH_CRCCR register ********************/
9172#define FLASH_CRCCR_CRC_SECT_Pos (0U)
9173#define FLASH_CRCCR_CRC_SECT_Msk (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos)
9174#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
9175#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
9176#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
9177#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
9178#define FLASH_CRCCR_ADD_SECT_Pos (9U)
9179#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
9180#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
9181#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
9182#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
9183#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
9184#define FLASH_CRCCR_START_CRC_Pos (16U)
9185#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos)
9186#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
9187#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
9188#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
9189#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
9190#define FLASH_CRCCR_CRC_BURST_Pos (20U)
9191#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
9192#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
9193#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
9194#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
9195#define FLASH_CRCCR_ALL_BANK_Pos (22U)
9196#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
9197#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
9199/******************* Bits definition for FLASH_CRCSADD register ****************/
9200#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
9201#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
9202#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
9204/******************* Bits definition for FLASH_CRCEADD register ****************/
9205#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
9206#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
9207#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
9209/******************* Bits definition for FLASH_CRCDATA register ***************/
9210#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
9211#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
9212#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
9214/******************* Bits definition for FLASH_ECC_FA register *******************/
9215#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
9216#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
9217#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
9218#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos (31U)
9219#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos)
9220#define FLASH_ECC_FA_OTP_FAIL_ECC FLASH_ECC_FA_OTP_FAIL_ECC_Msk
9222/******************* Bits definition for FLASH_OTPBL register *******************/
9223#define FLASH_OTPBL_LOCKBL_Pos (0U)
9224#define FLASH_OTPBL_LOCKBL_Msk (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos)
9225#define FLASH_OTPBL_LOCKBL FLASH_OTPBL_LOCKBL_Msk
9227/******************************************************************************/
9228/* */
9229/* Flexible Memory Controller */
9230/* */
9231/******************************************************************************/
9232/****************** Bit definition for FMC_BCR1 register *******************/
9233#define FMC_BCR1_CCLKEN_Pos (20U)
9234#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
9235#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
9236#define FMC_BCR1_WFDIS_Pos (21U)
9237#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
9238#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
9240#define FMC_BCR1_BMAP_Pos (24U)
9241#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos)
9242#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk
9243#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos)
9244#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos)
9246#define FMC_BCR1_FMCEN_Pos (31U)
9247#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos)
9248#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk
9249/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
9250#define FMC_BCRx_MBKEN_Pos (0U)
9251#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
9252#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
9253#define FMC_BCRx_MUXEN_Pos (1U)
9254#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
9255#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
9257#define FMC_BCRx_MTYP_Pos (2U)
9258#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
9259#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
9260#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
9261#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
9263#define FMC_BCRx_MWID_Pos (4U)
9264#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
9265#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
9266#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
9267#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
9269#define FMC_BCRx_FACCEN_Pos (6U)
9270#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
9271#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
9272#define FMC_BCRx_BURSTEN_Pos (8U)
9273#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
9274#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
9275#define FMC_BCRx_WAITPOL_Pos (9U)
9276#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
9277#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
9278#define FMC_BCRx_WAITCFG_Pos (11U)
9279#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
9280#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
9281#define FMC_BCRx_WREN_Pos (12U)
9282#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
9283#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
9284#define FMC_BCRx_WAITEN_Pos (13U)
9285#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
9286#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
9287#define FMC_BCRx_EXTMOD_Pos (14U)
9288#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
9289#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
9290#define FMC_BCRx_ASYNCWAIT_Pos (15U)
9291#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
9292#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
9294#define FMC_BCRx_CPSIZE_Pos (16U)
9295#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
9296#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
9297#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
9298#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
9299#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
9301#define FMC_BCRx_CBURSTRW_Pos (19U)
9302#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
9303#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
9305/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
9306#define FMC_BTRx_ADDSET_Pos (0U)
9307#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
9308#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
9309#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
9310#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
9311#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
9312#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
9314#define FMC_BTRx_ADDHLD_Pos (4U)
9315#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
9316#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
9317#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
9318#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
9319#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
9320#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
9322#define FMC_BTRx_DATAST_Pos (8U)
9323#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
9324#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
9325#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
9326#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
9327#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
9328#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
9329#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
9330#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
9331#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
9332#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
9334#define FMC_BTRx_BUSTURN_Pos (16U)
9335#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
9336#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
9337#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
9338#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
9339#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
9340#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
9342#define FMC_BTRx_CLKDIV_Pos (20U)
9343#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
9344#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
9345#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
9346#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
9347#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
9348#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
9350#define FMC_BTRx_DATLAT_Pos (24U)
9351#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
9352#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
9353#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
9354#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
9355#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
9356#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
9358#define FMC_BTRx_ACCMOD_Pos (28U)
9359#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
9360#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
9361#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
9362#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
9364/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
9365#define FMC_BWTRx_ADDSET_Pos (0U)
9366#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
9367#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
9368#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
9369#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
9370#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
9371#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
9373#define FMC_BWTRx_ADDHLD_Pos (4U)
9374#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
9375#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
9376#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
9377#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
9378#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
9379#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
9381#define FMC_BWTRx_DATAST_Pos (8U)
9382#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
9383#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
9384#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
9385#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
9386#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
9387#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
9388#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
9389#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
9390#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
9391#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
9393#define FMC_BWTRx_BUSTURN_Pos (16U)
9394#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
9395#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
9396#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
9397#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
9398#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
9399#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
9401#define FMC_BWTRx_ACCMOD_Pos (28U)
9402#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
9403#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
9404#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
9405#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
9407/****************** Bit definition for FMC_PCR register *******************/
9408#define FMC_PCR_PWAITEN_Pos (1U)
9409#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
9410#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
9411#define FMC_PCR_PBKEN_Pos (2U)
9412#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
9413#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
9415#define FMC_PCR_PWID_Pos (4U)
9416#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
9417#define FMC_PCR_PWID FMC_PCR_PWID_Msk
9418#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
9419#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
9421#define FMC_PCR_ECCEN_Pos (6U)
9422#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
9423#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
9425#define FMC_PCR_TCLR_Pos (9U)
9426#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
9427#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
9428#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
9429#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
9430#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
9431#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
9433#define FMC_PCR_TAR_Pos (13U)
9434#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
9435#define FMC_PCR_TAR FMC_PCR_TAR_Msk
9436#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
9437#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
9438#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
9439#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
9441#define FMC_PCR_ECCPS_Pos (17U)
9442#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
9443#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
9444#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
9445#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
9446#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
9448/******************* Bit definition for FMC_SR register *******************/
9449#define FMC_SR_IRS_Pos (0U)
9450#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
9451#define FMC_SR_IRS FMC_SR_IRS_Msk
9452#define FMC_SR_ILS_Pos (1U)
9453#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
9454#define FMC_SR_ILS FMC_SR_ILS_Msk
9455#define FMC_SR_IFS_Pos (2U)
9456#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
9457#define FMC_SR_IFS FMC_SR_IFS_Msk
9458#define FMC_SR_IREN_Pos (3U)
9459#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
9460#define FMC_SR_IREN FMC_SR_IREN_Msk
9461#define FMC_SR_ILEN_Pos (4U)
9462#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
9463#define FMC_SR_ILEN FMC_SR_ILEN_Msk
9464#define FMC_SR_IFEN_Pos (5U)
9465#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
9466#define FMC_SR_IFEN FMC_SR_IFEN_Msk
9467#define FMC_SR_FEMPT_Pos (6U)
9468#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
9469#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
9471/****************** Bit definition for FMC_PMEM register ******************/
9472#define FMC_PMEM_MEMSET_Pos (0U)
9473#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
9474#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
9475#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
9476#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
9477#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
9478#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
9479#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
9480#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
9481#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
9482#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
9484#define FMC_PMEM_MEMWAIT_Pos (8U)
9485#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
9486#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
9487#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
9488#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
9489#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
9490#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
9491#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
9492#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
9493#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
9494#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
9496#define FMC_PMEM_MEMHOLD_Pos (16U)
9497#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
9498#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
9499#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
9500#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
9501#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
9502#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
9503#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
9504#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
9505#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
9506#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
9508#define FMC_PMEM_MEMHIZ_Pos (24U)
9509#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
9510#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
9511#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
9512#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
9513#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
9514#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
9515#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
9516#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
9517#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
9518#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
9520/****************** Bit definition for FMC_PATT register ******************/
9521#define FMC_PATT_ATTSET_Pos (0U)
9522#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
9523#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
9524#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
9525#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
9526#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
9527#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
9528#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
9529#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
9530#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
9531#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
9533#define FMC_PATT_ATTWAIT_Pos (8U)
9534#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
9535#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
9536#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
9537#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
9538#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
9539#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
9540#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
9541#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
9542#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
9543#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
9545#define FMC_PATT_ATTHOLD_Pos (16U)
9546#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
9547#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
9548#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
9549#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
9550#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
9551#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
9552#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
9553#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
9554#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
9555#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
9557#define FMC_PATT_ATTHIZ_Pos (24U)
9558#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
9559#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
9560#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
9561#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
9562#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
9563#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
9564#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
9565#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
9566#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
9567#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
9569/****************** Bit definition for FMC_ECCR3 register ******************/
9570#define FMC_ECCR3_ECC3_Pos (0U)
9571#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
9572#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
9574/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
9575#define FMC_SDCRx_NC_Pos (0U)
9576#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos)
9577#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk
9578#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos)
9579#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos)
9581#define FMC_SDCRx_NR_Pos (2U)
9582#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos)
9583#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk
9584#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos)
9585#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos)
9587#define FMC_SDCRx_MWID_Pos (4U)
9588#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos)
9589#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk
9590#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos)
9591#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos)
9593#define FMC_SDCRx_NB_Pos (6U)
9594#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos)
9595#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk
9597#define FMC_SDCRx_CAS_Pos (7U)
9598#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos)
9599#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk
9600#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos)
9601#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos)
9603#define FMC_SDCRx_WP_Pos (9U)
9604#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos)
9605#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk
9607#define FMC_SDCRx_SDCLK_Pos (10U)
9608#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos)
9609#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk
9610#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos)
9611#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
9613#define FMC_SDCRx_RBURST_Pos (12U)
9614#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos)
9615#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk
9617#define FMC_SDCRx_RPIPE_Pos (13U)
9618#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos)
9619#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk
9620#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos)
9621#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos)
9623/****************** Bit definition for FMC_SDTRx(1,2) register ******************/
9624#define FMC_SDTRx_TMRD_Pos (0U)
9625#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos)
9626#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk
9627#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos)
9628#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos)
9629#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos)
9630#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos)
9632#define FMC_SDTRx_TXSR_Pos (4U)
9633#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos)
9634#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk
9635#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos)
9636#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos)
9637#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos)
9638#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos)
9640#define FMC_SDTRx_TRAS_Pos (8U)
9641#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos)
9642#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk
9643#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos)
9644#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos)
9645#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos)
9646#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos)
9648#define FMC_SDTRx_TRC_Pos (12U)
9649#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos)
9650#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk
9651#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos)
9652#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos)
9653#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos)
9655#define FMC_SDTRx_TWR_Pos (16U)
9656#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos)
9657#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk
9658#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos)
9659#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos)
9660#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos)
9662#define FMC_SDTRx_TRP_Pos (20U)
9663#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos)
9664#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk
9665#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos)
9666#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos)
9667#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos)
9669#define FMC_SDTRx_TRCD_Pos (24U)
9670#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos)
9671#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk
9672#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos)
9673#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos)
9674#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos)
9676/****************** Bit definition for FMC_SDCMR register ******************/
9677#define FMC_SDCMR_MODE_Pos (0U)
9678#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
9679#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
9680#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
9681#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
9682#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos)
9684#define FMC_SDCMR_CTB2_Pos (3U)
9685#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
9686#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
9688#define FMC_SDCMR_CTB1_Pos (4U)
9689#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
9690#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
9692#define FMC_SDCMR_NRFS_Pos (5U)
9693#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
9694#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
9695#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
9696#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
9697#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
9698#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
9700#define FMC_SDCMR_MRD_Pos (9U)
9701#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
9702#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
9704/****************** Bit definition for FMC_SDRTR register ******************/
9705#define FMC_SDRTR_CRE_Pos (0U)
9706#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
9707#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
9709#define FMC_SDRTR_COUNT_Pos (1U)
9710#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
9711#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
9713#define FMC_SDRTR_REIE_Pos (14U)
9714#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
9715#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
9717/****************** Bit definition for FMC_SDSR register ******************/
9718#define FMC_SDSR_RE_Pos (0U)
9719#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
9720#define FMC_SDSR_RE FMC_SDSR_RE_Msk
9722#define FMC_SDSR_MODES1_Pos (1U)
9723#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
9724#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
9725#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
9726#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
9728#define FMC_SDSR_MODES2_Pos (3U)
9729#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
9730#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
9731#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
9732#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
9734/******************************************************************************/
9735/* */
9736/* Graphic MMU (GFXMMU) */
9737/* */
9738/******************************************************************************/
9739/****************** Bits definition for GFXMMU_CR register ********************/
9740#define GFXMMU_CR_B0OIE_Pos (0U)
9741#define GFXMMU_CR_B0OIE_Msk (0x1UL << GFXMMU_CR_B0OIE_Pos)
9742#define GFXMMU_CR_B0OIE GFXMMU_CR_B0OIE_Msk
9743#define GFXMMU_CR_B1OIE_Pos (1U)
9744#define GFXMMU_CR_B1OIE_Msk (0x1UL << GFXMMU_CR_B1OIE_Pos)
9745#define GFXMMU_CR_B1OIE GFXMMU_CR_B1OIE_Msk
9746#define GFXMMU_CR_B2OIE_Pos (2U)
9747#define GFXMMU_CR_B2OIE_Msk (0x1UL << GFXMMU_CR_B2OIE_Pos)
9748#define GFXMMU_CR_B2OIE GFXMMU_CR_B2OIE_Msk
9749#define GFXMMU_CR_B3OIE_Pos (3U)
9750#define GFXMMU_CR_B3OIE_Msk (0x1UL << GFXMMU_CR_B3OIE_Pos)
9751#define GFXMMU_CR_B3OIE GFXMMU_CR_B3OIE_Msk
9752#define GFXMMU_CR_AMEIE_Pos (4U)
9753#define GFXMMU_CR_AMEIE_Msk (0x1UL << GFXMMU_CR_AMEIE_Pos)
9754#define GFXMMU_CR_AMEIE GFXMMU_CR_AMEIE_Msk
9755#define GFXMMU_CR_192BM_Pos (6U)
9756#define GFXMMU_CR_192BM_Msk (0x1UL << GFXMMU_CR_192BM_Pos)
9757#define GFXMMU_CR_192BM GFXMMU_CR_192BM_Msk
9758#define GFXMMU_CR_CE_Pos (7U)
9759#define GFXMMU_CR_CE_Msk (0x1UL << GFXMMU_CR_CE_Pos)
9760#define GFXMMU_CR_CE GFXMMU_CR_CE_Msk
9761#define GFXMMU_CR_CL_Pos (8U)
9762#define GFXMMU_CR_CL_Msk (0x1UL << GFXMMU_CR_CL_Pos)
9763#define GFXMMU_CR_CL GFXMMU_CR_CL_Msk
9764#define GFXMMU_CR_CLB_Pos (9U)
9765#define GFXMMU_CR_CLB_Msk (0x3UL << GFXMMU_CR_CLB_Pos)
9766#define GFXMMU_CR_CLB GFXMMU_CR_CLB_Msk
9767#define GFXMMU_CR_CLB_0 (0x1UL << GFXMMU_CR_CLB_Pos)
9768#define GFXMMU_CR_CLB_1 (0x2UL << GFXMMU_CR_CLB_Pos)
9769#define GFXMMU_CR_FC_Pos (11U)
9770#define GFXMMU_CR_FC_Msk (0x1UL << GFXMMU_CR_FC_Pos)
9771#define GFXMMU_CR_FC GFXMMU_CR_FC_Msk
9772#define GFXMMU_CR_PD_Pos (12U)
9773#define GFXMMU_CR_PD_Msk (0x1UL << GFXMMU_CR_PD_Pos)
9774#define GFXMMU_CR_PD GFXMMU_CR_PD_Msk
9775#define GFXMMU_CR_OC_Pos (16U)
9776#define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos)
9777#define GFXMMU_CR_OC GFXMMU_CR_OC_Msk
9778#define GFXMMU_CR_OB_Pos (17U)
9779#define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos)
9780#define GFXMMU_CR_OB GFXMMU_CR_OB_Msk
9782/****************** Bits definition for GFXMMU_SR register ********************/
9783#define GFXMMU_SR_B0OF_Pos (0U)
9784#define GFXMMU_SR_B0OF_Msk (0x1UL << GFXMMU_SR_B0OF_Pos)
9785#define GFXMMU_SR_B0OF GFXMMU_SR_B0OF_Msk
9786#define GFXMMU_SR_B1OF_Pos (1U)
9787#define GFXMMU_SR_B1OF_Msk (0x1UL << GFXMMU_SR_B1OF_Pos)
9788#define GFXMMU_SR_B1OF GFXMMU_SR_B1OF_Msk
9789#define GFXMMU_SR_B2OF_Pos (2U)
9790#define GFXMMU_SR_B2OF_Msk (0x1UL << GFXMMU_SR_B2OF_Pos)
9791#define GFXMMU_SR_B2OF GFXMMU_SR_B2OF_Msk
9792#define GFXMMU_SR_B3OF_Pos (3U)
9793#define GFXMMU_SR_B3OF_Msk (0x1UL << GFXMMU_SR_B3OF_Pos)
9794#define GFXMMU_SR_B3OF GFXMMU_SR_B3OF_Msk
9795#define GFXMMU_SR_AMEF_Pos (4U)
9796#define GFXMMU_SR_AMEF_Msk (0x1UL << GFXMMU_SR_AMEF_Pos)
9797#define GFXMMU_SR_AMEF GFXMMU_SR_AMEF_Msk
9799/****************** Bits definition for GFXMMU_FCR register *******************/
9800#define GFXMMU_FCR_CB0OF_Pos (0U)
9801#define GFXMMU_FCR_CB0OF_Msk (0x1UL << GFXMMU_FCR_CB0OF_Pos)
9802#define GFXMMU_FCR_CB0OF GFXMMU_FCR_CB0OF_Msk
9803#define GFXMMU_FCR_CB1OF_Pos (1U)
9804#define GFXMMU_FCR_CB1OF_Msk (0x1UL << GFXMMU_FCR_CB1OF_Pos)
9805#define GFXMMU_FCR_CB1OF GFXMMU_FCR_CB1OF_Msk
9806#define GFXMMU_FCR_CB2OF_Pos (2U)
9807#define GFXMMU_FCR_CB2OF_Msk (0x1UL << GFXMMU_FCR_CB2OF_Pos)
9808#define GFXMMU_FCR_CB2OF GFXMMU_FCR_CB2OF_Msk
9809#define GFXMMU_FCR_CB3OF_Pos (3U)
9810#define GFXMMU_FCR_CB3OF_Msk (0x1UL << GFXMMU_FCR_CB3OF_Pos)
9811#define GFXMMU_FCR_CB3OF GFXMMU_FCR_CB3OF_Msk
9812#define GFXMMU_FCR_CAMEF_Pos (4U)
9813#define GFXMMU_FCR_CAMEF_Msk (0x1UL << GFXMMU_FCR_CAMEF_Pos)
9814#define GFXMMU_FCR_CAMEF GFXMMU_FCR_CAMEF_Msk
9816/****************** Bits definition for GFXMMU_CCR register *******************/
9817#define GFXMMU_CCR_FF_Pos (0U)
9818#define GFXMMU_CCR_FF_Msk (0x1UL << GFXMMU_CCR_FF_Pos)
9819#define GFXMMU_CCR_FF GFXMMU_CCR_FF_Msk
9820#define GFXMMU_CCR_FI_Pos (1U)
9821#define GFXMMU_CCR_FI_Msk (0x1UL << GFXMMU_CCR_FI_Pos)
9822#define GFXMMU_CCR_FI GFXMMU_CCR_FI_Msk
9824/****************** Bits definition for GFXMMU_DVR register *******************/
9825#define GFXMMU_DVR_DV_Pos (0U)
9826#define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)
9827#define GFXMMU_DVR_DV GFXMMU_DVR_DV_Msk
9829/****************** Bits definition for GFXMMU_B0CR register ******************/
9830#define GFXMMU_B0CR_PBO_Pos (4U)
9831#define GFXMMU_B0CR_PBO_Msk (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)
9832#define GFXMMU_B0CR_PBO GFXMMU_B0CR_PBO_Msk
9833#define GFXMMU_B0CR_PBBA_Pos (23U)
9834#define GFXMMU_B0CR_PBBA_Msk (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)
9835#define GFXMMU_B0CR_PBBA GFXMMU_B0CR_PBBA_Msk
9837/****************** Bits definition for GFXMMU_B1CR register ******************/
9838#define GFXMMU_B1CR_PBO_Pos (4U)
9839#define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)
9840#define GFXMMU_B1CR_PBO GFXMMU_B1CR_PBO_Msk
9841#define GFXMMU_B1CR_PBBA_Pos (23U)
9842#define GFXMMU_B1CR_PBBA_Msk (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)
9843#define GFXMMU_B1CR_PBBA GFXMMU_B1CR_PBBA_Msk
9845/****************** Bits definition for GFXMMU_B2CR register ******************/
9846#define GFXMMU_B2CR_PBO_Pos (4U)
9847#define GFXMMU_B2CR_PBO_Msk (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)
9848#define GFXMMU_B2CR_PBO GFXMMU_B2CR_PBO_Msk
9849#define GFXMMU_B2CR_PBBA_Pos (23U)
9850#define GFXMMU_B2CR_PBBA_Msk (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)
9851#define GFXMMU_B2CR_PBBA GFXMMU_B2CR_PBBA_Msk
9853/****************** Bits definition for GFXMMU_B3CR register ******************/
9854#define GFXMMU_B3CR_PBO_Pos (4U)
9855#define GFXMMU_B3CR_PBO_Msk (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)
9856#define GFXMMU_B3CR_PBO GFXMMU_B3CR_PBO_Msk
9857#define GFXMMU_B3CR_PBBA_Pos (23U)
9858#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)
9859#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk
9861/****************** Bits definition for GFXMMU_LUTxL register *****************/
9862#define GFXMMU_LUTxL_EN_Pos (0U)
9863#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos)
9864#define GFXMMU_LUTxL_EN GFXMMU_LUTxL_EN_Msk
9865#define GFXMMU_LUTxL_FVB_Pos (8U)
9866#define GFXMMU_LUTxL_FVB_Msk (0xFFUL << GFXMMU_LUTxL_FVB_Pos)
9867#define GFXMMU_LUTxL_FVB GFXMMU_LUTxL_FVB_Msk
9868#define GFXMMU_LUTxL_LVB_Pos (16U)
9869#define GFXMMU_LUTxL_LVB_Msk (0xFFUL << GFXMMU_LUTxL_LVB_Pos)
9870#define GFXMMU_LUTxL_LVB GFXMMU_LUTxL_LVB_Msk
9872/****************** Bits definition for GFXMMU_LUTxH register *****************/
9873#define GFXMMU_LUTxH_LO_Pos (4U)
9874#define GFXMMU_LUTxH_LO_Msk (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)
9875#define GFXMMU_LUTxH_LO GFXMMU_LUTxH_LO_Msk
9877/******************************************************************************/
9878/* */
9879/* General Purpose I/O */
9880/* */
9881/******************************************************************************/
9882/****************** Bits definition for GPIO_MODER register *****************/
9883#define GPIO_MODER_MODE0_Pos (0U)
9884#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
9885#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
9886#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
9887#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
9889#define GPIO_MODER_MODE1_Pos (2U)
9890#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
9891#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
9892#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
9893#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
9895#define GPIO_MODER_MODE2_Pos (4U)
9896#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
9897#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
9898#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
9899#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
9901#define GPIO_MODER_MODE3_Pos (6U)
9902#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
9903#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
9904#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
9905#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
9907#define GPIO_MODER_MODE4_Pos (8U)
9908#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
9909#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
9910#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
9911#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
9913#define GPIO_MODER_MODE5_Pos (10U)
9914#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
9915#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
9916#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
9917#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
9919#define GPIO_MODER_MODE6_Pos (12U)
9920#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
9921#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
9922#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
9923#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
9925#define GPIO_MODER_MODE7_Pos (14U)
9926#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
9927#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
9928#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
9929#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
9931#define GPIO_MODER_MODE8_Pos (16U)
9932#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
9933#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
9934#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
9935#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
9937#define GPIO_MODER_MODE9_Pos (18U)
9938#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
9939#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
9940#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
9941#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
9943#define GPIO_MODER_MODE10_Pos (20U)
9944#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
9945#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
9946#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
9947#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
9949#define GPIO_MODER_MODE11_Pos (22U)
9950#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
9951#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
9952#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
9953#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
9955#define GPIO_MODER_MODE12_Pos (24U)
9956#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
9957#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
9958#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
9959#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
9961#define GPIO_MODER_MODE13_Pos (26U)
9962#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
9963#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
9964#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
9965#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
9967#define GPIO_MODER_MODE14_Pos (28U)
9968#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
9969#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
9970#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
9971#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
9973#define GPIO_MODER_MODE15_Pos (30U)
9974#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
9975#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
9976#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
9977#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
9979/****************** Bits definition for GPIO_OTYPER register ****************/
9980#define GPIO_OTYPER_OT0_Pos (0U)
9981#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
9982#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9983#define GPIO_OTYPER_OT1_Pos (1U)
9984#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
9985#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9986#define GPIO_OTYPER_OT2_Pos (2U)
9987#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
9988#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9989#define GPIO_OTYPER_OT3_Pos (3U)
9990#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
9991#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9992#define GPIO_OTYPER_OT4_Pos (4U)
9993#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
9994#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9995#define GPIO_OTYPER_OT5_Pos (5U)
9996#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
9997#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9998#define GPIO_OTYPER_OT6_Pos (6U)
9999#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
10000#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
10001#define GPIO_OTYPER_OT7_Pos (7U)
10002#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
10003#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
10004#define GPIO_OTYPER_OT8_Pos (8U)
10005#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
10006#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
10007#define GPIO_OTYPER_OT9_Pos (9U)
10008#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
10009#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
10010#define GPIO_OTYPER_OT10_Pos (10U)
10011#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
10012#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
10013#define GPIO_OTYPER_OT11_Pos (11U)
10014#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
10015#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
10016#define GPIO_OTYPER_OT12_Pos (12U)
10017#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
10018#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
10019#define GPIO_OTYPER_OT13_Pos (13U)
10020#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
10021#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
10022#define GPIO_OTYPER_OT14_Pos (14U)
10023#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
10024#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
10025#define GPIO_OTYPER_OT15_Pos (15U)
10026#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
10027#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
10028
10029/****************** Bits definition for GPIO_OSPEEDR register ***************/
10030#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
10031#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
10032#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
10033#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
10034#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
10036#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
10037#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
10038#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
10039#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
10040#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
10042#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
10043#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
10044#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
10045#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
10046#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
10048#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
10049#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
10050#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
10051#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
10052#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
10054#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
10055#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
10056#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
10057#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
10058#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
10060#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
10061#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
10062#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
10063#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
10064#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
10066#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
10067#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
10068#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
10069#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
10070#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
10072#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
10073#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
10074#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
10075#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
10076#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
10078#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
10079#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
10080#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
10081#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
10082#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
10084#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
10085#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
10086#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
10087#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
10088#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
10090#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
10091#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
10092#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
10093#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
10094#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
10096#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
10097#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
10098#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
10099#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
10100#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
10102#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
10103#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
10104#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
10105#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
10106#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
10108#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
10109#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
10110#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
10111#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
10112#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
10114#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
10115#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
10116#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
10117#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
10118#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
10120#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
10121#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
10122#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
10123#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
10124#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
10126/****************** Bits definition for GPIO_PUPDR register *****************/
10127#define GPIO_PUPDR_PUPD0_Pos (0U)
10128#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
10129#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
10130#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
10131#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
10133#define GPIO_PUPDR_PUPD1_Pos (2U)
10134#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
10135#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
10136#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
10137#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
10139#define GPIO_PUPDR_PUPD2_Pos (4U)
10140#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
10141#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
10142#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
10143#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
10145#define GPIO_PUPDR_PUPD3_Pos (6U)
10146#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
10147#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
10148#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
10149#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
10151#define GPIO_PUPDR_PUPD4_Pos (8U)
10152#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
10153#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
10154#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
10155#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
10157#define GPIO_PUPDR_PUPD5_Pos (10U)
10158#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
10159#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
10160#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
10161#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
10163#define GPIO_PUPDR_PUPD6_Pos (12U)
10164#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
10165#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
10166#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
10167#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
10169#define GPIO_PUPDR_PUPD7_Pos (14U)
10170#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
10171#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
10172#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
10173#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
10175#define GPIO_PUPDR_PUPD8_Pos (16U)
10176#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
10177#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
10178#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
10179#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
10181#define GPIO_PUPDR_PUPD9_Pos (18U)
10182#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
10183#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
10184#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
10185#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
10187#define GPIO_PUPDR_PUPD10_Pos (20U)
10188#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
10189#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
10190#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
10191#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
10193#define GPIO_PUPDR_PUPD11_Pos (22U)
10194#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
10195#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
10196#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
10197#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
10199#define GPIO_PUPDR_PUPD12_Pos (24U)
10200#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
10201#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
10202#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
10203#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
10205#define GPIO_PUPDR_PUPD13_Pos (26U)
10206#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
10207#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
10208#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
10209#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
10211#define GPIO_PUPDR_PUPD14_Pos (28U)
10212#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
10213#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
10214#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
10215#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
10217#define GPIO_PUPDR_PUPD15_Pos (30U)
10218#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
10219#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
10220#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
10221#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
10223/****************** Bits definition for GPIO_IDR register *******************/
10224#define GPIO_IDR_ID0_Pos (0U)
10225#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
10226#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
10227#define GPIO_IDR_ID1_Pos (1U)
10228#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
10229#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
10230#define GPIO_IDR_ID2_Pos (2U)
10231#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
10232#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
10233#define GPIO_IDR_ID3_Pos (3U)
10234#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
10235#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
10236#define GPIO_IDR_ID4_Pos (4U)
10237#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
10238#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
10239#define GPIO_IDR_ID5_Pos (5U)
10240#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
10241#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
10242#define GPIO_IDR_ID6_Pos (6U)
10243#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
10244#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
10245#define GPIO_IDR_ID7_Pos (7U)
10246#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
10247#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
10248#define GPIO_IDR_ID8_Pos (8U)
10249#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
10250#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
10251#define GPIO_IDR_ID9_Pos (9U)
10252#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
10253#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
10254#define GPIO_IDR_ID10_Pos (10U)
10255#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
10256#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
10257#define GPIO_IDR_ID11_Pos (11U)
10258#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
10259#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
10260#define GPIO_IDR_ID12_Pos (12U)
10261#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
10262#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
10263#define GPIO_IDR_ID13_Pos (13U)
10264#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
10265#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
10266#define GPIO_IDR_ID14_Pos (14U)
10267#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
10268#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
10269#define GPIO_IDR_ID15_Pos (15U)
10270#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
10271#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
10272
10273/****************** Bits definition for GPIO_ODR register *******************/
10274#define GPIO_ODR_OD0_Pos (0U)
10275#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
10276#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
10277#define GPIO_ODR_OD1_Pos (1U)
10278#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
10279#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
10280#define GPIO_ODR_OD2_Pos (2U)
10281#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
10282#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
10283#define GPIO_ODR_OD3_Pos (3U)
10284#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
10285#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
10286#define GPIO_ODR_OD4_Pos (4U)
10287#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
10288#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
10289#define GPIO_ODR_OD5_Pos (5U)
10290#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
10291#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
10292#define GPIO_ODR_OD6_Pos (6U)
10293#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
10294#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
10295#define GPIO_ODR_OD7_Pos (7U)
10296#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
10297#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
10298#define GPIO_ODR_OD8_Pos (8U)
10299#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
10300#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
10301#define GPIO_ODR_OD9_Pos (9U)
10302#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
10303#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
10304#define GPIO_ODR_OD10_Pos (10U)
10305#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
10306#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
10307#define GPIO_ODR_OD11_Pos (11U)
10308#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
10309#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
10310#define GPIO_ODR_OD12_Pos (12U)
10311#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
10312#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
10313#define GPIO_ODR_OD13_Pos (13U)
10314#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
10315#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
10316#define GPIO_ODR_OD14_Pos (14U)
10317#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
10318#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
10319#define GPIO_ODR_OD15_Pos (15U)
10320#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
10321#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
10322
10323/****************** Bits definition for GPIO_BSRR register ******************/
10324#define GPIO_BSRR_BS0_Pos (0U)
10325#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
10326#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
10327#define GPIO_BSRR_BS1_Pos (1U)
10328#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
10329#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
10330#define GPIO_BSRR_BS2_Pos (2U)
10331#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
10332#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
10333#define GPIO_BSRR_BS3_Pos (3U)
10334#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
10335#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
10336#define GPIO_BSRR_BS4_Pos (4U)
10337#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
10338#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
10339#define GPIO_BSRR_BS5_Pos (5U)
10340#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
10341#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
10342#define GPIO_BSRR_BS6_Pos (6U)
10343#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
10344#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
10345#define GPIO_BSRR_BS7_Pos (7U)
10346#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
10347#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
10348#define GPIO_BSRR_BS8_Pos (8U)
10349#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
10350#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
10351#define GPIO_BSRR_BS9_Pos (9U)
10352#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
10353#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
10354#define GPIO_BSRR_BS10_Pos (10U)
10355#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
10356#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
10357#define GPIO_BSRR_BS11_Pos (11U)
10358#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
10359#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
10360#define GPIO_BSRR_BS12_Pos (12U)
10361#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
10362#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
10363#define GPIO_BSRR_BS13_Pos (13U)
10364#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
10365#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
10366#define GPIO_BSRR_BS14_Pos (14U)
10367#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
10368#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
10369#define GPIO_BSRR_BS15_Pos (15U)
10370#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
10371#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
10372#define GPIO_BSRR_BR0_Pos (16U)
10373#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
10374#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
10375#define GPIO_BSRR_BR1_Pos (17U)
10376#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
10377#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
10378#define GPIO_BSRR_BR2_Pos (18U)
10379#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
10380#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
10381#define GPIO_BSRR_BR3_Pos (19U)
10382#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
10383#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
10384#define GPIO_BSRR_BR4_Pos (20U)
10385#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
10386#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
10387#define GPIO_BSRR_BR5_Pos (21U)
10388#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
10389#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
10390#define GPIO_BSRR_BR6_Pos (22U)
10391#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
10392#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
10393#define GPIO_BSRR_BR7_Pos (23U)
10394#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
10395#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
10396#define GPIO_BSRR_BR8_Pos (24U)
10397#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
10398#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
10399#define GPIO_BSRR_BR9_Pos (25U)
10400#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
10401#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
10402#define GPIO_BSRR_BR10_Pos (26U)
10403#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
10404#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
10405#define GPIO_BSRR_BR11_Pos (27U)
10406#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
10407#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
10408#define GPIO_BSRR_BR12_Pos (28U)
10409#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
10410#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
10411#define GPIO_BSRR_BR13_Pos (29U)
10412#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
10413#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
10414#define GPIO_BSRR_BR14_Pos (30U)
10415#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
10416#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
10417#define GPIO_BSRR_BR15_Pos (31U)
10418#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
10419#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
10420
10421/****************** Bit definition for GPIO_LCKR register *********************/
10422#define GPIO_LCKR_LCK0_Pos (0U)
10423#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
10424#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
10425#define GPIO_LCKR_LCK1_Pos (1U)
10426#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
10427#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10428#define GPIO_LCKR_LCK2_Pos (2U)
10429#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
10430#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10431#define GPIO_LCKR_LCK3_Pos (3U)
10432#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
10433#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10434#define GPIO_LCKR_LCK4_Pos (4U)
10435#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
10436#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10437#define GPIO_LCKR_LCK5_Pos (5U)
10438#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
10439#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10440#define GPIO_LCKR_LCK6_Pos (6U)
10441#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
10442#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10443#define GPIO_LCKR_LCK7_Pos (7U)
10444#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
10445#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10446#define GPIO_LCKR_LCK8_Pos (8U)
10447#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
10448#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10449#define GPIO_LCKR_LCK9_Pos (9U)
10450#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
10451#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10452#define GPIO_LCKR_LCK10_Pos (10U)
10453#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
10454#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10455#define GPIO_LCKR_LCK11_Pos (11U)
10456#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
10457#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10458#define GPIO_LCKR_LCK12_Pos (12U)
10459#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
10460#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10461#define GPIO_LCKR_LCK13_Pos (13U)
10462#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
10463#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10464#define GPIO_LCKR_LCK14_Pos (14U)
10465#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
10466#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10467#define GPIO_LCKR_LCK15_Pos (15U)
10468#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
10469#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10470#define GPIO_LCKR_LCKK_Pos (16U)
10471#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
10472#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10473
10474/****************** Bit definition for GPIO_AFRL register ********************/
10475#define GPIO_AFRL_AFSEL0_Pos (0U)
10476#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
10477#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
10478#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
10479#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
10480#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
10481#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
10482#define GPIO_AFRL_AFSEL1_Pos (4U)
10483#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
10484#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
10485#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
10486#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
10487#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
10488#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
10489#define GPIO_AFRL_AFSEL2_Pos (8U)
10490#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
10491#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
10492#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
10493#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
10494#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
10495#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
10496#define GPIO_AFRL_AFSEL3_Pos (12U)
10497#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
10498#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
10499#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
10500#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
10501#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
10502#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
10503#define GPIO_AFRL_AFSEL4_Pos (16U)
10504#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
10505#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
10506#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
10507#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
10508#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
10509#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
10510#define GPIO_AFRL_AFSEL5_Pos (20U)
10511#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
10512#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
10513#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
10514#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
10515#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
10516#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
10517#define GPIO_AFRL_AFSEL6_Pos (24U)
10518#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
10519#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
10520#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
10521#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
10522#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
10523#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
10524#define GPIO_AFRL_AFSEL7_Pos (28U)
10525#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
10526#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
10527#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
10528#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
10529#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
10530#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
10532/* Legacy defines */
10533#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
10534#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
10535#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
10536#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
10537#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
10538#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
10539#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
10540#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
10541
10542/****************** Bit definition for GPIO_AFRH register ********************/
10543#define GPIO_AFRH_AFSEL8_Pos (0U)
10544#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
10545#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
10546#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
10547#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
10548#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
10549#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
10550#define GPIO_AFRH_AFSEL9_Pos (4U)
10551#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
10552#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
10553#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
10554#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
10555#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
10556#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
10557#define GPIO_AFRH_AFSEL10_Pos (8U)
10558#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
10559#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
10560#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
10561#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
10562#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
10563#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
10564#define GPIO_AFRH_AFSEL11_Pos (12U)
10565#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
10566#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
10567#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
10568#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
10569#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
10570#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
10571#define GPIO_AFRH_AFSEL12_Pos (16U)
10572#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
10573#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
10574#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
10575#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
10576#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
10577#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
10578#define GPIO_AFRH_AFSEL13_Pos (20U)
10579#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
10580#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
10581#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
10582#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
10583#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
10584#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
10585#define GPIO_AFRH_AFSEL14_Pos (24U)
10586#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
10587#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
10588#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
10589#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
10590#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
10591#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
10592#define GPIO_AFRH_AFSEL15_Pos (28U)
10593#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
10594#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
10595#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
10596#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
10597#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
10598#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
10600/* Legacy defines */
10601#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
10602#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
10603#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
10604#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
10605#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
10606#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
10607#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
10608#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
10609
10610/******************************************************************************/
10611/* */
10612/* HSEM HW Semaphore */
10613/* */
10614/******************************************************************************/
10615/******************** Bit definition for HSEM_R register ********************/
10616#define HSEM_R_PROCID_Pos (0U)
10617#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)
10618#define HSEM_R_PROCID HSEM_R_PROCID_Msk
10619#define HSEM_R_COREID_Pos (8U)
10620#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos)
10621#define HSEM_R_COREID HSEM_R_COREID_Msk
10622#define HSEM_R_LOCK_Pos (31U)
10623#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)
10624#define HSEM_R_LOCK HSEM_R_LOCK_Msk
10626/******************** Bit definition for HSEM_RLR register ******************/
10627#define HSEM_RLR_PROCID_Pos (0U)
10628#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)
10629#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk
10630#define HSEM_RLR_COREID_Pos (8U)
10631#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos)
10632#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk
10633#define HSEM_RLR_LOCK_Pos (31U)
10634#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)
10635#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk
10637/******************** Bit definition for HSEM_C1IER register *****************/
10638#define HSEM_C1IER_ISE0_Pos (0U)
10639#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)
10640#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk
10641#define HSEM_C1IER_ISE1_Pos (1U)
10642#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)
10643#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk
10644#define HSEM_C1IER_ISE2_Pos (2U)
10645#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)
10646#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk
10647#define HSEM_C1IER_ISE3_Pos (3U)
10648#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)
10649#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk
10650#define HSEM_C1IER_ISE4_Pos (4U)
10651#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)
10652#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk
10653#define HSEM_C1IER_ISE5_Pos (5U)
10654#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)
10655#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk
10656#define HSEM_C1IER_ISE6_Pos (6U)
10657#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)
10658#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk
10659#define HSEM_C1IER_ISE7_Pos (7U)
10660#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)
10661#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk
10662#define HSEM_C1IER_ISE8_Pos (8U)
10663#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)
10664#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk
10665#define HSEM_C1IER_ISE9_Pos (9U)
10666#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)
10667#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk
10668#define HSEM_C1IER_ISE10_Pos (10U)
10669#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)
10670#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk
10671#define HSEM_C1IER_ISE11_Pos (11U)
10672#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)
10673#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk
10674#define HSEM_C1IER_ISE12_Pos (12U)
10675#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)
10676#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk
10677#define HSEM_C1IER_ISE13_Pos (13U)
10678#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)
10679#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk
10680#define HSEM_C1IER_ISE14_Pos (14U)
10681#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)
10682#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
10683#define HSEM_C1IER_ISE15_Pos (15U)
10684#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)
10685#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk
10686#define HSEM_C1IER_ISE16_Pos (16U)
10687#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos)
10688#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk
10689#define HSEM_C1IER_ISE17_Pos (17U)
10690#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos)
10691#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk
10692#define HSEM_C1IER_ISE18_Pos (18U)
10693#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos)
10694#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk
10695#define HSEM_C1IER_ISE19_Pos (19U)
10696#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos)
10697#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk
10698#define HSEM_C1IER_ISE20_Pos (20U)
10699#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos)
10700#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk
10701#define HSEM_C1IER_ISE21_Pos (21U)
10702#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos)
10703#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk
10704#define HSEM_C1IER_ISE22_Pos (22U)
10705#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos)
10706#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk
10707#define HSEM_C1IER_ISE23_Pos (23U)
10708#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos)
10709#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk
10710#define HSEM_C1IER_ISE24_Pos (24U)
10711#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos)
10712#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk
10713#define HSEM_C1IER_ISE25_Pos (25U)
10714#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos)
10715#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk
10716#define HSEM_C1IER_ISE26_Pos (26U)
10717#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos)
10718#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk
10719#define HSEM_C1IER_ISE27_Pos (27U)
10720#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos)
10721#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk
10722#define HSEM_C1IER_ISE28_Pos (28U)
10723#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos)
10724#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk
10725#define HSEM_C1IER_ISE29_Pos (29U)
10726#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos)
10727#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk
10728#define HSEM_C1IER_ISE30_Pos (30U)
10729#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos)
10730#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk
10731#define HSEM_C1IER_ISE31_Pos (31U)
10732#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos)
10733#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk
10735/******************** Bit definition for HSEM_C1ICR register *****************/
10736#define HSEM_C1ICR_ISC0_Pos (0U)
10737#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)
10738#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk
10739#define HSEM_C1ICR_ISC1_Pos (1U)
10740#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)
10741#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk
10742#define HSEM_C1ICR_ISC2_Pos (2U)
10743#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)
10744#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk
10745#define HSEM_C1ICR_ISC3_Pos (3U)
10746#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)
10747#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk
10748#define HSEM_C1ICR_ISC4_Pos (4U)
10749#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)
10750#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk
10751#define HSEM_C1ICR_ISC5_Pos (5U)
10752#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)
10753#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk
10754#define HSEM_C1ICR_ISC6_Pos (6U)
10755#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)
10756#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk
10757#define HSEM_C1ICR_ISC7_Pos (7U)
10758#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)
10759#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk
10760#define HSEM_C1ICR_ISC8_Pos (8U)
10761#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)
10762#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk
10763#define HSEM_C1ICR_ISC9_Pos (9U)
10764#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)
10765#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk
10766#define HSEM_C1ICR_ISC10_Pos (10U)
10767#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)
10768#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk
10769#define HSEM_C1ICR_ISC11_Pos (11U)
10770#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)
10771#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk
10772#define HSEM_C1ICR_ISC12_Pos (12U)
10773#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)
10774#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk
10775#define HSEM_C1ICR_ISC13_Pos (13U)
10776#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)
10777#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk
10778#define HSEM_C1ICR_ISC14_Pos (14U)
10779#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)
10780#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk
10781#define HSEM_C1ICR_ISC15_Pos (15U)
10782#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)
10783#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk
10784#define HSEM_C1ICR_ISC16_Pos (16U)
10785#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos)
10786#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk
10787#define HSEM_C1ICR_ISC17_Pos (17U)
10788#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos)
10789#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk
10790#define HSEM_C1ICR_ISC18_Pos (18U)
10791#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos)
10792#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk
10793#define HSEM_C1ICR_ISC19_Pos (19U)
10794#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos)
10795#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk
10796#define HSEM_C1ICR_ISC20_Pos (20U)
10797#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos)
10798#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk
10799#define HSEM_C1ICR_ISC21_Pos (21U)
10800#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos)
10801#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk
10802#define HSEM_C1ICR_ISC22_Pos (22U)
10803#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos)
10804#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk
10805#define HSEM_C1ICR_ISC23_Pos (23U)
10806#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos)
10807#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk
10808#define HSEM_C1ICR_ISC24_Pos (24U)
10809#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos)
10810#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
10811#define HSEM_C1ICR_ISC25_Pos (25U)
10812#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos)
10813#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk
10814#define HSEM_C1ICR_ISC26_Pos (26U)
10815#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos)
10816#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk
10817#define HSEM_C1ICR_ISC27_Pos (27U)
10818#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos)
10819#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk
10820#define HSEM_C1ICR_ISC28_Pos (28U)
10821#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos)
10822#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk
10823#define HSEM_C1ICR_ISC29_Pos (29U)
10824#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos)
10825#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk
10826#define HSEM_C1ICR_ISC30_Pos (30U)
10827#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos)
10828#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk
10829#define HSEM_C1ICR_ISC31_Pos (31U)
10830#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos)
10831#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk
10833/******************** Bit definition for HSEM_C1ISR register *****************/
10834#define HSEM_C1ISR_ISF0_Pos (0U)
10835#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)
10836#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk
10837#define HSEM_C1ISR_ISF1_Pos (1U)
10838#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)
10839#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk
10840#define HSEM_C1ISR_ISF2_Pos (2U)
10841#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)
10842#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk
10843#define HSEM_C1ISR_ISF3_Pos (3U)
10844#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)
10845#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk
10846#define HSEM_C1ISR_ISF4_Pos (4U)
10847#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)
10848#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk
10849#define HSEM_C1ISR_ISF5_Pos (5U)
10850#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)
10851#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk
10852#define HSEM_C1ISR_ISF6_Pos (6U)
10853#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)
10854#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk
10855#define HSEM_C1ISR_ISF7_Pos (7U)
10856#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)
10857#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk
10858#define HSEM_C1ISR_ISF8_Pos (8U)
10859#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)
10860#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk
10861#define HSEM_C1ISR_ISF9_Pos (9U)
10862#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)
10863#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk
10864#define HSEM_C1ISR_ISF10_Pos (10U)
10865#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)
10866#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk
10867#define HSEM_C1ISR_ISF11_Pos (11U)
10868#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)
10869#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk
10870#define HSEM_C1ISR_ISF12_Pos (12U)
10871#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)
10872#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk
10873#define HSEM_C1ISR_ISF13_Pos (13U)
10874#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)
10875#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk
10876#define HSEM_C1ISR_ISF14_Pos (14U)
10877#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)
10878#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk
10879#define HSEM_C1ISR_ISF15_Pos (15U)
10880#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)
10881#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk
10882#define HSEM_C1ISR_ISF16_Pos (16U)
10883#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos)
10884#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk
10885#define HSEM_C1ISR_ISF17_Pos (17U)
10886#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos)
10887#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk
10888#define HSEM_C1ISR_ISF18_Pos (18U)
10889#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos)
10890#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk
10891#define HSEM_C1ISR_ISF19_Pos (19U)
10892#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos)
10893#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk
10894#define HSEM_C1ISR_ISF20_Pos (20U)
10895#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos)
10896#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk
10897#define HSEM_C1ISR_ISF21_Pos (21U)
10898#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos)
10899#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk
10900#define HSEM_C1ISR_ISF22_Pos (22U)
10901#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos)
10902#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk
10903#define HSEM_C1ISR_ISF23_Pos (23U)
10904#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos)
10905#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk
10906#define HSEM_C1ISR_ISF24_Pos (24U)
10907#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos)
10908#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk
10909#define HSEM_C1ISR_ISF25_Pos (25U)
10910#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos)
10911#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk
10912#define HSEM_C1ISR_ISF26_Pos (26U)
10913#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos)
10914#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk
10915#define HSEM_C1ISR_ISF27_Pos (27U)
10916#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos)
10917#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk
10918#define HSEM_C1ISR_ISF28_Pos (28U)
10919#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos)
10920#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk
10921#define HSEM_C1ISR_ISF29_Pos (29U)
10922#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos)
10923#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk
10924#define HSEM_C1ISR_ISF30_Pos (30U)
10925#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos)
10926#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk
10927#define HSEM_C1ISR_ISF31_Pos (31U)
10928#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos)
10929#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk
10931/******************** Bit definition for HSEM_C1MISR register *****************/
10932#define HSEM_C1MISR_MISF0_Pos (0U)
10933#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)
10934#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk
10935#define HSEM_C1MISR_MISF1_Pos (1U)
10936#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)
10937#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk
10938#define HSEM_C1MISR_MISF2_Pos (2U)
10939#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)
10940#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk
10941#define HSEM_C1MISR_MISF3_Pos (3U)
10942#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)
10943#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk
10944#define HSEM_C1MISR_MISF4_Pos (4U)
10945#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)
10946#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk
10947#define HSEM_C1MISR_MISF5_Pos (5U)
10948#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)
10949#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk
10950#define HSEM_C1MISR_MISF6_Pos (6U)
10951#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)
10952#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk
10953#define HSEM_C1MISR_MISF7_Pos (7U)
10954#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)
10955#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk
10956#define HSEM_C1MISR_MISF8_Pos (8U)
10957#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)
10958#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk
10959#define HSEM_C1MISR_MISF9_Pos (9U)
10960#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)
10961#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk
10962#define HSEM_C1MISR_MISF10_Pos (10U)
10963#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)
10964#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk
10965#define HSEM_C1MISR_MISF11_Pos (11U)
10966#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)
10967#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk
10968#define HSEM_C1MISR_MISF12_Pos (12U)
10969#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)
10970#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk
10971#define HSEM_C1MISR_MISF13_Pos (13U)
10972#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)
10973#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk
10974#define HSEM_C1MISR_MISF14_Pos (14U)
10975#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)
10976#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk
10977#define HSEM_C1MISR_MISF15_Pos (15U)
10978#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)
10979#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk
10980#define HSEM_C1MISR_MISF16_Pos (16U)
10981#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos)
10982#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk
10983#define HSEM_C1MISR_MISF17_Pos (17U)
10984#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos)
10985#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk
10986#define HSEM_C1MISR_MISF18_Pos (18U)
10987#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos)
10988#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk
10989#define HSEM_C1MISR_MISF19_Pos (19U)
10990#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos)
10991#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk
10992#define HSEM_C1MISR_MISF20_Pos (20U)
10993#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos)
10994#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk
10995#define HSEM_C1MISR_MISF21_Pos (21U)
10996#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos)
10997#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk
10998#define HSEM_C1MISR_MISF22_Pos (22U)
10999#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos)
11000#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk
11001#define HSEM_C1MISR_MISF23_Pos (23U)
11002#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos)
11003#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk
11004#define HSEM_C1MISR_MISF24_Pos (24U)
11005#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos)
11006#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk
11007#define HSEM_C1MISR_MISF25_Pos (25U)
11008#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos)
11009#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk
11010#define HSEM_C1MISR_MISF26_Pos (26U)
11011#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos)
11012#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk
11013#define HSEM_C1MISR_MISF27_Pos (27U)
11014#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos)
11015#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk
11016#define HSEM_C1MISR_MISF28_Pos (28U)
11017#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos)
11018#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk
11019#define HSEM_C1MISR_MISF29_Pos (29U)
11020#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos)
11021#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk
11022#define HSEM_C1MISR_MISF30_Pos (30U)
11023#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos)
11024#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk
11025#define HSEM_C1MISR_MISF31_Pos (31U)
11026#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos)
11027#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk
11029/******************** Bit definition for HSEM_CR register *****************/
11030#define HSEM_CR_COREID_Pos (8U)
11031#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos)
11032#define HSEM_CR_COREID HSEM_CR_COREID_Msk
11033#define HSEM_CR_KEY_Pos (16U)
11034#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)
11035#define HSEM_CR_KEY HSEM_CR_KEY_Msk
11037/******************** Bit definition for HSEM_KEYR register *****************/
11038#define HSEM_KEYR_KEY_Pos (16U)
11039#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)
11040#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk
11042/******************************************************************************/
11043/* */
11044/* HASH */
11045/* */
11046/******************************************************************************/
11047/****************** Bits definition for HASH_CR register ********************/
11048#define HASH_CR_INIT_Pos (2U)
11049#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos)
11050#define HASH_CR_INIT HASH_CR_INIT_Msk
11051#define HASH_CR_DMAE_Pos (3U)
11052#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos)
11053#define HASH_CR_DMAE HASH_CR_DMAE_Msk
11054#define HASH_CR_DATATYPE_Pos (4U)
11055#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos)
11056#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
11057#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos)
11058#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos)
11059#define HASH_CR_MODE_Pos (6U)
11060#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos)
11061#define HASH_CR_MODE HASH_CR_MODE_Msk
11062#define HASH_CR_ALGO_Pos (7U)
11063#define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos)
11064#define HASH_CR_ALGO HASH_CR_ALGO_Msk
11065#define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos)
11066#define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos)
11067#define HASH_CR_NBW_Pos (8U)
11068#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos)
11069#define HASH_CR_NBW HASH_CR_NBW_Msk
11070#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos)
11071#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos)
11072#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos)
11073#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos)
11074#define HASH_CR_DINNE_Pos (12U)
11075#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos)
11076#define HASH_CR_DINNE HASH_CR_DINNE_Msk
11077#define HASH_CR_MDMAT_Pos (13U)
11078#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos)
11079#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
11080#define HASH_CR_LKEY_Pos (16U)
11081#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos)
11082#define HASH_CR_LKEY HASH_CR_LKEY_Msk
11083
11084/****************** Bits definition for HASH_STR register *******************/
11085#define HASH_STR_NBLW_Pos (0U)
11086#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos)
11087#define HASH_STR_NBLW HASH_STR_NBLW_Msk
11088#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos)
11089#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos)
11090#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos)
11091#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos)
11092#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos)
11093#define HASH_STR_DCAL_Pos (8U)
11094#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos)
11095#define HASH_STR_DCAL HASH_STR_DCAL_Msk
11096
11097/****************** Bits definition for HASH_IMR register *******************/
11098#define HASH_IMR_DINIE_Pos (0U)
11099#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos)
11100#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
11101#define HASH_IMR_DCIE_Pos (1U)
11102#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos)
11103#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
11104
11105/****************** Bits definition for HASH_SR register ********************/
11106#define HASH_SR_DINIS_Pos (0U)
11107#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos)
11108#define HASH_SR_DINIS HASH_SR_DINIS_Msk
11109#define HASH_SR_DCIS_Pos (1U)
11110#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos)
11111#define HASH_SR_DCIS HASH_SR_DCIS_Msk
11112#define HASH_SR_DMAS_Pos (2U)
11113#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos)
11114#define HASH_SR_DMAS HASH_SR_DMAS_Msk
11115#define HASH_SR_BUSY_Pos (3U)
11116#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos)
11117#define HASH_SR_BUSY HASH_SR_BUSY_Msk
11118/******************************************************************************/
11119/* */
11120/* Inter-integrated Circuit Interface (I2C) */
11121/* */
11122/******************************************************************************/
11123/******************* Bit definition for I2C_CR1 register *******************/
11124#define I2C_CR1_PE_Pos (0U)
11125#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
11126#define I2C_CR1_PE I2C_CR1_PE_Msk
11127#define I2C_CR1_TXIE_Pos (1U)
11128#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
11129#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
11130#define I2C_CR1_RXIE_Pos (2U)
11131#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
11132#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
11133#define I2C_CR1_ADDRIE_Pos (3U)
11134#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
11135#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
11136#define I2C_CR1_NACKIE_Pos (4U)
11137#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
11138#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
11139#define I2C_CR1_STOPIE_Pos (5U)
11140#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
11141#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
11142#define I2C_CR1_TCIE_Pos (6U)
11143#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
11144#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
11145#define I2C_CR1_ERRIE_Pos (7U)
11146#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
11147#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
11148#define I2C_CR1_DNF_Pos (8U)
11149#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
11150#define I2C_CR1_DNF I2C_CR1_DNF_Msk
11151#define I2C_CR1_ANFOFF_Pos (12U)
11152#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
11153#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
11154#define I2C_CR1_TXDMAEN_Pos (14U)
11155#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
11156#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
11157#define I2C_CR1_RXDMAEN_Pos (15U)
11158#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
11159#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
11160#define I2C_CR1_SBC_Pos (16U)
11161#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
11162#define I2C_CR1_SBC I2C_CR1_SBC_Msk
11163#define I2C_CR1_NOSTRETCH_Pos (17U)
11164#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
11165#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
11166#define I2C_CR1_WUPEN_Pos (18U)
11167#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
11168#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
11169#define I2C_CR1_GCEN_Pos (19U)
11170#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
11171#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
11172#define I2C_CR1_SMBHEN_Pos (20U)
11173#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
11174#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
11175#define I2C_CR1_SMBDEN_Pos (21U)
11176#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
11177#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
11178#define I2C_CR1_ALERTEN_Pos (22U)
11179#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
11180#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
11181#define I2C_CR1_PECEN_Pos (23U)
11182#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
11183#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
11185/****************** Bit definition for I2C_CR2 register ********************/
11186#define I2C_CR2_SADD_Pos (0U)
11187#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
11188#define I2C_CR2_SADD I2C_CR2_SADD_Msk
11189#define I2C_CR2_RD_WRN_Pos (10U)
11190#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
11191#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
11192#define I2C_CR2_ADD10_Pos (11U)
11193#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
11194#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
11195#define I2C_CR2_HEAD10R_Pos (12U)
11196#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
11197#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
11198#define I2C_CR2_START_Pos (13U)
11199#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
11200#define I2C_CR2_START I2C_CR2_START_Msk
11201#define I2C_CR2_STOP_Pos (14U)
11202#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
11203#define I2C_CR2_STOP I2C_CR2_STOP_Msk
11204#define I2C_CR2_NACK_Pos (15U)
11205#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
11206#define I2C_CR2_NACK I2C_CR2_NACK_Msk
11207#define I2C_CR2_NBYTES_Pos (16U)
11208#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
11209#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
11210#define I2C_CR2_RELOAD_Pos (24U)
11211#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
11212#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
11213#define I2C_CR2_AUTOEND_Pos (25U)
11214#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
11215#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
11216#define I2C_CR2_PECBYTE_Pos (26U)
11217#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
11218#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
11220/******************* Bit definition for I2C_OAR1 register ******************/
11221#define I2C_OAR1_OA1_Pos (0U)
11222#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
11223#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
11224#define I2C_OAR1_OA1MODE_Pos (10U)
11225#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
11226#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
11227#define I2C_OAR1_OA1EN_Pos (15U)
11228#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
11229#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
11231/******************* Bit definition for I2C_OAR2 register ******************/
11232#define I2C_OAR2_OA2_Pos (1U)
11233#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
11234#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
11235#define I2C_OAR2_OA2MSK_Pos (8U)
11236#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
11237#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
11238#define I2C_OAR2_OA2NOMASK 0x00000000UL
11239#define I2C_OAR2_OA2MASK01_Pos (8U)
11240#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
11241#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
11242#define I2C_OAR2_OA2MASK02_Pos (9U)
11243#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
11244#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
11245#define I2C_OAR2_OA2MASK03_Pos (8U)
11246#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
11247#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
11248#define I2C_OAR2_OA2MASK04_Pos (10U)
11249#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
11250#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
11251#define I2C_OAR2_OA2MASK05_Pos (8U)
11252#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
11253#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
11254#define I2C_OAR2_OA2MASK06_Pos (9U)
11255#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
11256#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
11257#define I2C_OAR2_OA2MASK07_Pos (8U)
11258#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
11259#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
11260#define I2C_OAR2_OA2EN_Pos (15U)
11261#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
11262#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
11264/******************* Bit definition for I2C_TIMINGR register *******************/
11265#define I2C_TIMINGR_SCLL_Pos (0U)
11266#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
11267#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
11268#define I2C_TIMINGR_SCLH_Pos (8U)
11269#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
11270#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
11271#define I2C_TIMINGR_SDADEL_Pos (16U)
11272#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
11273#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
11274#define I2C_TIMINGR_SCLDEL_Pos (20U)
11275#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
11276#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
11277#define I2C_TIMINGR_PRESC_Pos (28U)
11278#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
11279#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
11281/******************* Bit definition for I2C_TIMEOUTR register *******************/
11282#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
11283#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
11284#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
11285#define I2C_TIMEOUTR_TIDLE_Pos (12U)
11286#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
11287#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
11288#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
11289#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
11290#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
11291#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
11292#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
11293#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
11294#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
11295#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
11296#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
11298/****************** Bit definition for I2C_ISR register *********************/
11299#define I2C_ISR_TXE_Pos (0U)
11300#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
11301#define I2C_ISR_TXE I2C_ISR_TXE_Msk
11302#define I2C_ISR_TXIS_Pos (1U)
11303#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
11304#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
11305#define I2C_ISR_RXNE_Pos (2U)
11306#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
11307#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
11308#define I2C_ISR_ADDR_Pos (3U)
11309#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
11310#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
11311#define I2C_ISR_NACKF_Pos (4U)
11312#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
11313#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
11314#define I2C_ISR_STOPF_Pos (5U)
11315#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
11316#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
11317#define I2C_ISR_TC_Pos (6U)
11318#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
11319#define I2C_ISR_TC I2C_ISR_TC_Msk
11320#define I2C_ISR_TCR_Pos (7U)
11321#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
11322#define I2C_ISR_TCR I2C_ISR_TCR_Msk
11323#define I2C_ISR_BERR_Pos (8U)
11324#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
11325#define I2C_ISR_BERR I2C_ISR_BERR_Msk
11326#define I2C_ISR_ARLO_Pos (9U)
11327#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
11328#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
11329#define I2C_ISR_OVR_Pos (10U)
11330#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
11331#define I2C_ISR_OVR I2C_ISR_OVR_Msk
11332#define I2C_ISR_PECERR_Pos (11U)
11333#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
11334#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
11335#define I2C_ISR_TIMEOUT_Pos (12U)
11336#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
11337#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
11338#define I2C_ISR_ALERT_Pos (13U)
11339#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
11340#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
11341#define I2C_ISR_BUSY_Pos (15U)
11342#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
11343#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
11344#define I2C_ISR_DIR_Pos (16U)
11345#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
11346#define I2C_ISR_DIR I2C_ISR_DIR_Msk
11347#define I2C_ISR_ADDCODE_Pos (17U)
11348#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
11349#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
11351/****************** Bit definition for I2C_ICR register *********************/
11352#define I2C_ICR_ADDRCF_Pos (3U)
11353#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
11354#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
11355#define I2C_ICR_NACKCF_Pos (4U)
11356#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
11357#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
11358#define I2C_ICR_STOPCF_Pos (5U)
11359#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
11360#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
11361#define I2C_ICR_BERRCF_Pos (8U)
11362#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
11363#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
11364#define I2C_ICR_ARLOCF_Pos (9U)
11365#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
11366#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
11367#define I2C_ICR_OVRCF_Pos (10U)
11368#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
11369#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
11370#define I2C_ICR_PECCF_Pos (11U)
11371#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
11372#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
11373#define I2C_ICR_TIMOUTCF_Pos (12U)
11374#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
11375#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
11376#define I2C_ICR_ALERTCF_Pos (13U)
11377#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
11378#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
11380/****************** Bit definition for I2C_PECR register *********************/
11381#define I2C_PECR_PEC_Pos (0U)
11382#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
11383#define I2C_PECR_PEC I2C_PECR_PEC_Msk
11385/****************** Bit definition for I2C_RXDR register *********************/
11386#define I2C_RXDR_RXDATA_Pos (0U)
11387#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
11388#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
11390/****************** Bit definition for I2C_TXDR register *********************/
11391#define I2C_TXDR_TXDATA_Pos (0U)
11392#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
11393#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
11395/******************************************************************************/
11396/* */
11397/* Independent WATCHDOG */
11398/* */
11399/******************************************************************************/
11400/******************* Bit definition for IWDG_KR register ********************/
11401#define IWDG_KR_KEY_Pos (0U)
11402#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
11403#define IWDG_KR_KEY IWDG_KR_KEY_Msk
11405/******************* Bit definition for IWDG_PR register ********************/
11406#define IWDG_PR_PR_Pos (0U)
11407#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
11408#define IWDG_PR_PR IWDG_PR_PR_Msk
11409#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
11410#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
11411#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
11413/******************* Bit definition for IWDG_RLR register *******************/
11414#define IWDG_RLR_RL_Pos (0U)
11415#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
11416#define IWDG_RLR_RL IWDG_RLR_RL_Msk
11418/******************* Bit definition for IWDG_SR register ********************/
11419#define IWDG_SR_PVU_Pos (0U)
11420#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
11421#define IWDG_SR_PVU IWDG_SR_PVU_Msk
11422#define IWDG_SR_RVU_Pos (1U)
11423#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
11424#define IWDG_SR_RVU IWDG_SR_RVU_Msk
11425#define IWDG_SR_WVU_Pos (2U)
11426#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
11427#define IWDG_SR_WVU IWDG_SR_WVU_Msk
11429/******************* Bit definition for IWDG_KR register ********************/
11430#define IWDG_WINR_WIN_Pos (0U)
11431#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
11432#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
11434/******************************************************************************/
11435/* */
11436/* JPEG Encoder/Decoder */
11437/* */
11438/******************************************************************************/
11439/******************** Bit definition for CONFR0 register ********************/
11440#define JPEG_CONFR0_START_Pos (0U)
11441#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos)
11442#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk
11444/******************** Bit definition for CONFR1 register ********************/
11445#define JPEG_CONFR1_NF_Pos (0U)
11446#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos)
11447#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk
11448#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos)
11449#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos)
11450#define JPEG_CONFR1_DE_Pos (3U)
11451#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos)
11452#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk
11453#define JPEG_CONFR1_COLORSPACE_Pos (4U)
11454#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)
11455#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk
11456#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)
11457#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)
11458#define JPEG_CONFR1_NS_Pos (6U)
11459#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos)
11460#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk
11461#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos)
11462#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos)
11463#define JPEG_CONFR1_HDR_Pos (8U)
11464#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos)
11465#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk
11466#define JPEG_CONFR1_YSIZE_Pos (16U)
11467#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)
11468#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk
11470/******************** Bit definition for CONFR2 register ********************/
11471#define JPEG_CONFR2_NMCU_Pos (0U)
11472#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)
11473#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk
11475/******************** Bit definition for CONFR3 register ********************/
11476#define JPEG_CONFR3_XSIZE_Pos (16U)
11477#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)
11478#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk
11480/******************** Bit definition for CONFR4 register ********************/
11481#define JPEG_CONFR4_HD_Pos (0U)
11482#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos)
11483#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk
11484#define JPEG_CONFR4_HA_Pos (1U)
11485#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos)
11486#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk
11487#define JPEG_CONFR4_QT_Pos (2U)
11488#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos)
11489#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk
11490#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos)
11491#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos)
11492#define JPEG_CONFR4_NB_Pos (4U)
11493#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos)
11494#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk
11495#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos)
11496#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos)
11497#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos)
11498#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos)
11499#define JPEG_CONFR4_VSF_Pos (8U)
11500#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos)
11501#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk
11502#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos)
11503#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos)
11504#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos)
11505#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos)
11506#define JPEG_CONFR4_HSF_Pos (12U)
11507#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos)
11508#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk
11509#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos)
11510#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos)
11511#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos)
11512#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos)
11514/******************** Bit definition for CONFR5 register ********************/
11515#define JPEG_CONFR5_HD_Pos (0U)
11516#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos)
11517#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk
11518#define JPEG_CONFR5_HA_Pos (1U)
11519#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos)
11520#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk
11521#define JPEG_CONFR5_QT_Pos (2U)
11522#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos)
11523#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk
11524#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos)
11525#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos)
11526#define JPEG_CONFR5_NB_Pos (4U)
11527#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos)
11528#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk
11529#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos)
11530#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos)
11531#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos)
11532#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos)
11533#define JPEG_CONFR5_VSF_Pos (8U)
11534#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos)
11535#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk
11536#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos)
11537#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos)
11538#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos)
11539#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos)
11540#define JPEG_CONFR5_HSF_Pos (12U)
11541#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos)
11542#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk
11543#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos)
11544#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos)
11545#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos)
11546#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos)
11548/******************** Bit definition for CONFR6 register ********************/
11549#define JPEG_CONFR6_HD_Pos (0U)
11550#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos)
11551#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk
11552#define JPEG_CONFR6_HA_Pos (1U)
11553#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos)
11554#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk
11555#define JPEG_CONFR6_QT_Pos (2U)
11556#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos)
11557#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk
11558#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos)
11559#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos)
11560#define JPEG_CONFR6_NB_Pos (4U)
11561#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos)
11562#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk
11563#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos)
11564#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos)
11565#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos)
11566#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos)
11567#define JPEG_CONFR6_VSF_Pos (8U)
11568#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos)
11569#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk
11570#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos)
11571#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos)
11572#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos)
11573#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos)
11574#define JPEG_CONFR6_HSF_Pos (12U)
11575#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos)
11576#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk
11577#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos)
11578#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos)
11579#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos)
11580#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos)
11582/******************** Bit definition for CONFR7 register ********************/
11583#define JPEG_CONFR7_HD_Pos (0U)
11584#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos)
11585#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk
11586#define JPEG_CONFR7_HA_Pos (1U)
11587#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos)
11588#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk
11589#define JPEG_CONFR7_QT_Pos (2U)
11590#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos)
11591#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk
11592#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos)
11593#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos)
11594#define JPEG_CONFR7_NB_Pos (4U)
11595#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos)
11596#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk
11597#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos)
11598#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos)
11599#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos)
11600#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos)
11601#define JPEG_CONFR7_VSF_Pos (8U)
11602#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos)
11603#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk
11604#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos)
11605#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos)
11606#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos)
11607#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos)
11608#define JPEG_CONFR7_HSF_Pos (12U)
11609#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos)
11610#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk
11611#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos)
11612#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos)
11613#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos)
11614#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos)
11616/******************** Bit definition for CR register ********************/
11617#define JPEG_CR_JCEN_Pos (0U)
11618#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos)
11619#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk
11620#define JPEG_CR_IFTIE_Pos (1U)
11621#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos)
11622#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk
11623#define JPEG_CR_IFNFIE_Pos (2U)
11624#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos)
11625#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk
11626#define JPEG_CR_OFTIE_Pos (3U)
11627#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos)
11628#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk
11629#define JPEG_CR_OFNEIE_Pos (4U)
11630#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos)
11631#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk
11632#define JPEG_CR_EOCIE_Pos (5U)
11633#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos)
11634#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk
11635#define JPEG_CR_HPDIE_Pos (6U)
11636#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos)
11637#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk
11638#define JPEG_CR_IFF_Pos (13U)
11639#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos)
11640#define JPEG_CR_IFF JPEG_CR_IFF_Msk
11641#define JPEG_CR_OFF_Pos (14U)
11642#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos)
11643#define JPEG_CR_OFF JPEG_CR_OFF_Msk
11645/******************** Bit definition for SR register ********************/
11646#define JPEG_SR_IFTF_Pos (1U)
11647#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos)
11648#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk
11649#define JPEG_SR_IFNFF_Pos (2U)
11650#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos)
11651#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk
11652#define JPEG_SR_OFTF_Pos (3U)
11653#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos)
11654#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk
11655#define JPEG_SR_OFNEF_Pos (4U)
11656#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos)
11657#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk
11658#define JPEG_SR_EOCF_Pos (5U)
11659#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos)
11660#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk
11661#define JPEG_SR_HPDF_Pos (6U)
11662#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos)
11663#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk
11664#define JPEG_SR_COF_Pos (7U)
11665#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos)
11666#define JPEG_SR_COF JPEG_SR_COF_Msk
11668/******************** Bit definition for CFR register ********************/
11669#define JPEG_CFR_CEOCF_Pos (4U)
11670#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos)
11671#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk
11672#define JPEG_CFR_CHPDF_Pos (5U)
11673#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos)
11674#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk
11676/******************** Bit definition for DIR register ********************/
11677#define JPEG_DIR_DATAIN_Pos (0U)
11678#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)
11679#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk
11681/******************** Bit definition for DOR register ********************/
11682#define JPEG_DOR_DATAOUT_Pos (0U)
11683#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)
11684#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk
11686/******************************************************************************/
11687/* */
11688/* LCD-TFT Display Controller (LTDC) */
11689/* */
11690/******************************************************************************/
11691
11692/******************** Bit definition for LTDC_SSCR register *****************/
11693
11694#define LTDC_SSCR_VSH_Pos (0U)
11695#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
11696#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
11697#define LTDC_SSCR_HSW_Pos (16U)
11698#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
11699#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
11701/******************** Bit definition for LTDC_BPCR register *****************/
11702
11703#define LTDC_BPCR_AVBP_Pos (0U)
11704#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
11705#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
11706#define LTDC_BPCR_AHBP_Pos (16U)
11707#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
11708#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
11710/******************** Bit definition for LTDC_AWCR register *****************/
11711
11712#define LTDC_AWCR_AAH_Pos (0U)
11713#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
11714#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
11715#define LTDC_AWCR_AAW_Pos (16U)
11716#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
11717#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
11719/******************** Bit definition for LTDC_TWCR register *****************/
11720
11721#define LTDC_TWCR_TOTALH_Pos (0U)
11722#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
11723#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
11724#define LTDC_TWCR_TOTALW_Pos (16U)
11725#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
11726#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
11728/******************** Bit definition for LTDC_GCR register ******************/
11729
11730#define LTDC_GCR_LTDCEN_Pos (0U)
11731#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
11732#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
11733#define LTDC_GCR_DBW_Pos (4U)
11734#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
11735#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
11736#define LTDC_GCR_DGW_Pos (8U)
11737#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
11738#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
11739#define LTDC_GCR_DRW_Pos (12U)
11740#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
11741#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
11742#define LTDC_GCR_DEN_Pos (16U)
11743#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
11744#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
11745#define LTDC_GCR_PCPOL_Pos (28U)
11746#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
11747#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
11748#define LTDC_GCR_DEPOL_Pos (29U)
11749#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
11750#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
11751#define LTDC_GCR_VSPOL_Pos (30U)
11752#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
11753#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
11754#define LTDC_GCR_HSPOL_Pos (31U)
11755#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
11756#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
11759/******************** Bit definition for LTDC_SRCR register *****************/
11760
11761#define LTDC_SRCR_IMR_Pos (0U)
11762#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
11763#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
11764#define LTDC_SRCR_VBR_Pos (1U)
11765#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
11766#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
11768/******************** Bit definition for LTDC_BCCR register *****************/
11769
11770#define LTDC_BCCR_BCBLUE_Pos (0U)
11771#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
11772#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
11773#define LTDC_BCCR_BCGREEN_Pos (8U)
11774#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
11775#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
11776#define LTDC_BCCR_BCRED_Pos (16U)
11777#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
11778#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
11780/******************** Bit definition for LTDC_IER register ******************/
11781
11782#define LTDC_IER_LIE_Pos (0U)
11783#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
11784#define LTDC_IER_LIE LTDC_IER_LIE_Msk
11785#define LTDC_IER_FUIE_Pos (1U)
11786#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
11787#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
11788#define LTDC_IER_TERRIE_Pos (2U)
11789#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
11790#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
11791#define LTDC_IER_RRIE_Pos (3U)
11792#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
11793#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
11795/******************** Bit definition for LTDC_ISR register ******************/
11796
11797#define LTDC_ISR_LIF_Pos (0U)
11798#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
11799#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
11800#define LTDC_ISR_FUIF_Pos (1U)
11801#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
11802#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
11803#define LTDC_ISR_TERRIF_Pos (2U)
11804#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
11805#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
11806#define LTDC_ISR_RRIF_Pos (3U)
11807#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
11808#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
11810/******************** Bit definition for LTDC_ICR register ******************/
11811
11812#define LTDC_ICR_CLIF_Pos (0U)
11813#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
11814#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
11815#define LTDC_ICR_CFUIF_Pos (1U)
11816#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
11817#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
11818#define LTDC_ICR_CTERRIF_Pos (2U)
11819#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
11820#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
11821#define LTDC_ICR_CRRIF_Pos (3U)
11822#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
11823#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
11825/******************** Bit definition for LTDC_LIPCR register ****************/
11826
11827#define LTDC_LIPCR_LIPOS_Pos (0U)
11828#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
11829#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
11831/******************** Bit definition for LTDC_CPSR register *****************/
11832
11833#define LTDC_CPSR_CYPOS_Pos (0U)
11834#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
11835#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
11836#define LTDC_CPSR_CXPOS_Pos (16U)
11837#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
11838#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
11840/******************** Bit definition for LTDC_CDSR register *****************/
11841
11842#define LTDC_CDSR_VDES_Pos (0U)
11843#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
11844#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
11845#define LTDC_CDSR_HDES_Pos (1U)
11846#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
11847#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
11848#define LTDC_CDSR_VSYNCS_Pos (2U)
11849#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
11850#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
11851#define LTDC_CDSR_HSYNCS_Pos (3U)
11852#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
11853#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
11855/******************** Bit definition for LTDC_LxCR register *****************/
11856
11857#define LTDC_LxCR_LEN_Pos (0U)
11858#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
11859#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
11860#define LTDC_LxCR_COLKEN_Pos (1U)
11861#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
11862#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
11863#define LTDC_LxCR_CLUTEN_Pos (4U)
11864#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
11865#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
11867/******************** Bit definition for LTDC_LxWHPCR register **************/
11868
11869#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
11870#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
11871#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
11872#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
11873#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
11874#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
11876/******************** Bit definition for LTDC_LxWVPCR register **************/
11877
11878#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
11879#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
11880#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
11881#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
11882#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
11883#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
11885/******************** Bit definition for LTDC_LxCKCR register ***************/
11886
11887#define LTDC_LxCKCR_CKBLUE_Pos (0U)
11888#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
11889#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
11890#define LTDC_LxCKCR_CKGREEN_Pos (8U)
11891#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
11892#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
11893#define LTDC_LxCKCR_CKRED_Pos (16U)
11894#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
11895#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
11897/******************** Bit definition for LTDC_LxPFCR register ***************/
11898
11899#define LTDC_LxPFCR_PF_Pos (0U)
11900#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
11901#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
11903/******************** Bit definition for LTDC_LxCACR register ***************/
11904
11905#define LTDC_LxCACR_CONSTA_Pos (0U)
11906#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
11907#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
11909/******************** Bit definition for LTDC_LxDCCR register ***************/
11910
11911#define LTDC_LxDCCR_DCBLUE_Pos (0U)
11912#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
11913#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
11914#define LTDC_LxDCCR_DCGREEN_Pos (8U)
11915#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
11916#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
11917#define LTDC_LxDCCR_DCRED_Pos (16U)
11918#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
11919#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
11920#define LTDC_LxDCCR_DCALPHA_Pos (24U)
11921#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
11922#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
11924/******************** Bit definition for LTDC_LxBFCR register ***************/
11925
11926#define LTDC_LxBFCR_BF2_Pos (0U)
11927#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
11928#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
11929#define LTDC_LxBFCR_BF1_Pos (8U)
11930#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
11931#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
11933/******************** Bit definition for LTDC_LxCFBAR register **************/
11934
11935#define LTDC_LxCFBAR_CFBADD_Pos (0U)
11936#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
11937#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
11939/******************** Bit definition for LTDC_LxCFBLR register **************/
11940
11941#define LTDC_LxCFBLR_CFBLL_Pos (0U)
11942#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
11943#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
11944#define LTDC_LxCFBLR_CFBP_Pos (16U)
11945#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
11946#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
11948/******************** Bit definition for LTDC_LxCFBLNR register *************/
11949
11950#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
11951#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
11952#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
11954/******************** Bit definition for LTDC_LxCLUTWR register *************/
11955
11956#define LTDC_LxCLUTWR_BLUE_Pos (0U)
11957#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
11958#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
11959#define LTDC_LxCLUTWR_GREEN_Pos (8U)
11960#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
11961#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
11962#define LTDC_LxCLUTWR_RED_Pos (16U)
11963#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
11964#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
11965#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
11966#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
11967#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
11969/******************************************************************************/
11970/* */
11971/* MDMA */
11972/* */
11973/******************************************************************************/
11974/******************** Bit definition for MDMA_GISR0 register ****************/
11975#define MDMA_GISR0_GIF0_Pos (0U)
11976#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos)
11977#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk
11978#define MDMA_GISR0_GIF1_Pos (1U)
11979#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos)
11980#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk
11981#define MDMA_GISR0_GIF2_Pos (2U)
11982#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos)
11983#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk
11984#define MDMA_GISR0_GIF3_Pos (3U)
11985#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos)
11986#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk
11987#define MDMA_GISR0_GIF4_Pos (4U)
11988#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos)
11989#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk
11990#define MDMA_GISR0_GIF5_Pos (5U)
11991#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos)
11992#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk
11993#define MDMA_GISR0_GIF6_Pos (6U)
11994#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos)
11995#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk
11996#define MDMA_GISR0_GIF7_Pos (7U)
11997#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos)
11998#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk
11999#define MDMA_GISR0_GIF8_Pos (8U)
12000#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos)
12001#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk
12002#define MDMA_GISR0_GIF9_Pos (9U)
12003#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos)
12004#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk
12005#define MDMA_GISR0_GIF10_Pos (10U)
12006#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos)
12007#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk
12008#define MDMA_GISR0_GIF11_Pos (11U)
12009#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos)
12010#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk
12011#define MDMA_GISR0_GIF12_Pos (12U)
12012#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos)
12013#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk
12014#define MDMA_GISR0_GIF13_Pos (13U)
12015#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos)
12016#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk
12017#define MDMA_GISR0_GIF14_Pos (14U)
12018#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos)
12019#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk
12020#define MDMA_GISR0_GIF15_Pos (15U)
12021#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos)
12022#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk
12024/******************** Bit definition for MDMA_CxISR register ****************/
12025#define MDMA_CISR_TEIF_Pos (0U)
12026#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos)
12027#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk
12028#define MDMA_CISR_CTCIF_Pos (1U)
12029#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos)
12030#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk
12031#define MDMA_CISR_BRTIF_Pos (2U)
12032#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos)
12033#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk
12034#define MDMA_CISR_BTIF_Pos (3U)
12035#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos)
12036#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk
12037#define MDMA_CISR_TCIF_Pos (4U)
12038#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
12039#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk
12040#define MDMA_CISR_CRQA_Pos (16U)
12041#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos)
12042#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk
12044/******************** Bit definition for MDMA_CxIFCR register ****************/
12045#define MDMA_CIFCR_CTEIF_Pos (0U)
12046#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos)
12047#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk
12048#define MDMA_CIFCR_CCTCIF_Pos (1U)
12049#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
12050#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk
12051#define MDMA_CIFCR_CBRTIF_Pos (2U)
12052#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
12053#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk
12054#define MDMA_CIFCR_CBTIF_Pos (3U)
12055#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos)
12056#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk
12057#define MDMA_CIFCR_CLTCIF_Pos (4U)
12058#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
12059#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk
12061/******************** Bit definition for MDMA_CxESR register ****************/
12062#define MDMA_CESR_TEA_Pos (0U)
12063#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos)
12064#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk
12065#define MDMA_CESR_TED_Pos (7U)
12066#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos)
12067#define MDMA_CESR_TED MDMA_CESR_TED_Msk
12068#define MDMA_CESR_TELD_Pos (8U)
12069#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos)
12070#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk
12071#define MDMA_CESR_TEMD_Pos (9U)
12072#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos)
12073#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk
12074#define MDMA_CESR_ASE_Pos (10U)
12075#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos)
12076#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk
12077#define MDMA_CESR_BSE_Pos (11U)
12078#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos)
12079#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk
12081/******************** Bit definition for MDMA_CxCR register ****************/
12082#define MDMA_CCR_EN_Pos (0U)
12083#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos)
12084#define MDMA_CCR_EN MDMA_CCR_EN_Msk
12085#define MDMA_CCR_TEIE_Pos (1U)
12086#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos)
12087#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk
12088#define MDMA_CCR_CTCIE_Pos (2U)
12089#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos)
12090#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk
12091#define MDMA_CCR_BRTIE_Pos (3U)
12092#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos)
12093#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk
12094#define MDMA_CCR_BTIE_Pos (4U)
12095#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos)
12096#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk
12097#define MDMA_CCR_TCIE_Pos (5U)
12098#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos)
12099#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk
12100#define MDMA_CCR_PL_Pos (6U)
12101#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos)
12102#define MDMA_CCR_PL MDMA_CCR_PL_Msk
12103#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos)
12104#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos)
12105#define MDMA_CCR_BEX_Pos (12U)
12106#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos)
12107#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk
12108#define MDMA_CCR_HEX_Pos (13U)
12109#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos)
12110#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk
12111#define MDMA_CCR_WEX_Pos (14U)
12112#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos)
12113#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk
12114#define MDMA_CCR_SWRQ_Pos (16U)
12115#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos)
12116#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk
12118/******************** Bit definition for MDMA_CxTCR register ****************/
12119#define MDMA_CTCR_SINC_Pos (0U)
12120#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos)
12121#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk
12122#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos)
12123#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos)
12124#define MDMA_CTCR_DINC_Pos (2U)
12125#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos)
12126#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk
12127#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos)
12128#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos)
12129#define MDMA_CTCR_SSIZE_Pos (4U)
12130#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos)
12131#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk
12132#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos)
12133#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos)
12134#define MDMA_CTCR_DSIZE_Pos (6U)
12135#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos)
12136#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk
12137#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos)
12138#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos)
12139#define MDMA_CTCR_SINCOS_Pos (8U)
12140#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos)
12141#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk
12142#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos)
12143#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos)
12144#define MDMA_CTCR_DINCOS_Pos (10U)
12145#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos)
12146#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk
12147#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos)
12148#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos)
12149#define MDMA_CTCR_SBURST_Pos (12U)
12150#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos)
12151#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk
12152#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos)
12153#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos)
12154#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos)
12155#define MDMA_CTCR_DBURST_Pos (15U)
12156#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos)
12157#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk
12158#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos)
12159#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos)
12160#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos)
12161#define MDMA_CTCR_TLEN_Pos (18U)
12162#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos)
12163#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk
12164#define MDMA_CTCR_PKE_Pos (25U)
12165#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos)
12166#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
12167#define MDMA_CTCR_PAM_Pos (26U)
12168#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos)
12169#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk
12170#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos)
12171#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos)
12172#define MDMA_CTCR_TRGM_Pos (28U)
12173#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos)
12174#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk
12175#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos)
12176#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos)
12177#define MDMA_CTCR_SWRM_Pos (30U)
12178#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos)
12179#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk
12180#define MDMA_CTCR_BWM_Pos (31U)
12181#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos)
12182#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk
12184/******************** Bit definition for MDMA_CxBNDTR register ****************/
12185#define MDMA_CBNDTR_BNDT_Pos (0U)
12186#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
12187#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk
12188#define MDMA_CBNDTR_BRSUM_Pos (18U)
12189#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
12190#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk
12191#define MDMA_CBNDTR_BRDUM_Pos (19U)
12192#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
12193#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk
12194#define MDMA_CBNDTR_BRC_Pos (20U)
12195#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
12196#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk
12198/******************** Bit definition for MDMA_CxSAR register ****************/
12199#define MDMA_CSAR_SAR_Pos (0U)
12200#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
12201#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk
12203/******************** Bit definition for MDMA_CxDAR register ****************/
12204#define MDMA_CDAR_DAR_Pos (0U)
12205#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
12206#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk
12208/******************** Bit definition for MDMA_CxBRUR ************************/
12209#define MDMA_CBRUR_SUV_Pos (0U)
12210#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
12211#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk
12212#define MDMA_CBRUR_DUV_Pos (16U)
12213#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
12214#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk
12216/******************** Bit definition for MDMA_CxLAR *************************/
12217#define MDMA_CLAR_LAR_Pos (0U)
12218#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
12219#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk
12221/******************** Bit definition for MDMA_CxTBR) ************************/
12222#define MDMA_CTBR_TSEL_Pos (0U)
12223#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos)
12224#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk
12225#define MDMA_CTBR_SBUS_Pos (16U)
12226#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos)
12227#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk
12228#define MDMA_CTBR_DBUS_Pos (17U)
12229#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos)
12230#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk
12232/******************** Bit definition for MDMA_CxMAR) ************************/
12233#define MDMA_CMAR_MAR_Pos (0U)
12234#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
12235#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk
12237/******************** Bit definition for MDMA_CxMDR) ************************/
12238#define MDMA_CMDR_MDR_Pos (0U)
12239#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
12240#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk
12242/******************************************************************************/
12243/* */
12244/* Operational Amplifier (OPAMP) */
12245/* */
12246/******************************************************************************/
12247/********************* Bit definition for OPAMPx_CSR register ***************/
12248#define OPAMP_CSR_OPAMPxEN_Pos (0U)
12249#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
12250#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
12251#define OPAMP_CSR_FORCEVP_Pos (1U)
12252#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
12253#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
12255#define OPAMP_CSR_VPSEL_Pos (2U)
12256#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
12257#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
12258#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
12259#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
12261#define OPAMP_CSR_VMSEL_Pos (5U)
12262#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
12263#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
12264#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
12265#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
12267#define OPAMP_CSR_OPAHSM_Pos (8U)
12268#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos)
12269#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk
12270#define OPAMP_CSR_CALON_Pos (11U)
12271#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
12272#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
12274#define OPAMP_CSR_CALSEL_Pos (12U)
12275#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
12276#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
12277#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
12278#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
12280#define OPAMP_CSR_PGGAIN_Pos (14U)
12281#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
12282#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
12283#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
12284#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
12285#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
12286#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
12288#define OPAMP_CSR_USERTRIM_Pos (18U)
12289#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
12290#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
12291#define OPAMP_CSR_TSTREF_Pos (29U)
12292#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
12293#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
12294#define OPAMP_CSR_CALOUT_Pos (30U)
12295#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
12296#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
12298/********************* Bit definition for OPAMP1_CSR register ***************/
12299#define OPAMP1_CSR_OPAEN_Pos (0U)
12300#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
12301#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
12302#define OPAMP1_CSR_FORCEVP_Pos (1U)
12303#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
12304#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
12306#define OPAMP1_CSR_VPSEL_Pos (2U)
12307#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
12308#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
12309#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
12310#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
12312#define OPAMP1_CSR_VMSEL_Pos (5U)
12313#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
12314#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
12315#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
12316#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
12318#define OPAMP1_CSR_OPAHSM_Pos (8U)
12319#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
12320#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk
12321#define OPAMP1_CSR_CALON_Pos (11U)
12322#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
12323#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
12325#define OPAMP1_CSR_CALSEL_Pos (12U)
12326#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
12327#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
12328#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
12329#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
12331#define OPAMP1_CSR_PGGAIN_Pos (14U)
12332#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
12333#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
12334#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
12335#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
12336#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
12337#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
12339#define OPAMP1_CSR_USERTRIM_Pos (18U)
12340#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
12341#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
12342#define OPAMP1_CSR_TSTREF_Pos (29U)
12343#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
12344#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
12345#define OPAMP1_CSR_CALOUT_Pos (30U)
12346#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
12347#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
12349/********************* Bit definition for OPAMP2_CSR register ***************/
12350#define OPAMP2_CSR_OPAEN_Pos (0U)
12351#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
12352#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
12353#define OPAMP2_CSR_FORCEVP_Pos (1U)
12354#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
12355#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
12357#define OPAMP2_CSR_VPSEL_Pos (2U)
12358#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
12359#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
12360#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
12361#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
12363#define OPAMP2_CSR_VMSEL_Pos (5U)
12364#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
12365#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
12366#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
12367#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
12369#define OPAMP2_CSR_OPAHSM_Pos (8U)
12370#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
12371#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk
12372#define OPAMP2_CSR_CALON_Pos (11U)
12373#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
12374#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
12376#define OPAMP2_CSR_CALSEL_Pos (12U)
12377#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
12378#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
12379#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
12380#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
12382#define OPAMP2_CSR_PGGAIN_Pos (14U)
12383#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
12384#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
12385#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
12386#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
12387#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
12388#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
12390#define OPAMP2_CSR_USERTRIM_Pos (18U)
12391#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
12392#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
12393#define OPAMP2_CSR_TSTREF_Pos (29U)
12394#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
12395#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
12396#define OPAMP2_CSR_CALOUT_Pos (30U)
12397#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
12398#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
12400/******************* Bit definition for OPAMP_OTR register ******************/
12401#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
12402#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
12403#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
12404#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
12405#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
12406#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
12408/******************* Bit definition for OPAMP1_OTR register ******************/
12409#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
12410#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
12411#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
12412#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
12413#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
12414#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
12416/******************* Bit definition for OPAMP2_OTR register ******************/
12417#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
12418#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
12419#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
12420#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
12421#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
12422#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
12424/******************* Bit definition for OPAMP_HSOTR register ****************/
12425#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
12426#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
12427#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk
12428#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
12429#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
12430#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk
12432/******************* Bit definition for OPAMP1_HSOTR register ****************/
12433#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
12434#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
12435#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
12436#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
12437#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
12438#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
12440/******************* Bit definition for OPAMP2_HSOTR register ****************/
12441#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
12442#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
12443#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
12444#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
12445#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
12446#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
12448/******************************************************************************/
12449/* */
12450/* Parallel Synchronous Slave Interface (PSSI ) */
12451/* */
12452/******************************************************************************/
12453
12454/******************** Bit definition for PSSI_CR register *******************/
12455#define PSSI_CR_OUTEN_Pos (31U)
12456#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos)
12457#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk
12458#define PSSI_CR_DMAEN_Pos (30U)
12459#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos)
12460#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk
12461#define PSSI_CR_DERDYCFG_Pos (18U)
12462#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos)
12463#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk
12464#define PSSI_CR_ENABLE_Pos (14U)
12465#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos)
12466#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk
12467#define PSSI_CR_EDM_Pos (10U)
12468#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos)
12469#define PSSI_CR_EDM PSSI_CR_EDM_Msk
12470#define PSSI_CR_RDYPOL_Pos (8U)
12471#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos)
12472#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk
12473#define PSSI_CR_DEPOL_Pos (6U)
12474#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos)
12475#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk
12476#define PSSI_CR_CKPOL_Pos (5U)
12477#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos)
12478#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk
12479/******************** Bit definition for PSSI_SR register *******************/
12480#define PSSI_SR_RTT1B_Pos (3U)
12481#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos)
12482#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk
12483#define PSSI_SR_RTT4B_Pos (2U)
12484#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos)
12485#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk
12486/******************** Bit definition for PSSI_RIS register *******************/
12487#define PSSI_RIS_OVR_RIS_Pos (1U)
12488#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos)
12489#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk
12490/******************** Bit definition for PSSI_IER register *******************/
12491#define PSSI_IER_OVR_IE_Pos (1U)
12492#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos)
12493#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk
12494/******************** Bit definition for PSSI_MIS register *******************/
12495#define PSSI_MIS_OVR_MIS_Pos (1U)
12496#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos)
12497#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk
12498/******************** Bit definition for PSSI_ICR register *******************/
12499#define PSSI_ICR_OVR_ISC_Pos (1U)
12500#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos)
12501#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk
12502/******************** Bit definition for PSSI_DR register *******************/
12503#define PSSI_DR_DR_Pos (0U)
12504#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos)
12505#define PSSI_DR_DR PSSI_DR_DR_Msk
12507/******************************************************************************/
12508/* */
12509/* On The Fly Decryption */
12510/* */
12511/******************************************************************************/
12512/****************** Bit definition for OTFDEC_CR register ******************/
12513#define OTFDEC_CR_ENC_Pos (0U)
12514#define OTFDEC_CR_ENC_Msk (0x1UL << OTFDEC_CR_ENC_Pos)
12515#define OTFDEC_CR_ENC OTFDEC_CR_ENC_Msk
12517/****************** Bit definition for OTFDEC_PRIVCFGR register ************/
12518#define OTFDEC_PRIVCFGR_PRIV_Pos (0U)
12519#define OTFDEC_PRIVCFGR_PRIV_Msk (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)
12520#define OTFDEC_PRIVCFGR_PRIV OTFDEC_PRIVCFGR_PRIV_Msk
12522/****************** Bit definition for OTFDEC_REG_CONFIGR register *********/
12523#define OTFDEC_REG_CONFIGR_REG_EN_Pos (0U)
12524#define OTFDEC_REG_CONFIGR_REG_EN_Msk (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)
12525#define OTFDEC_REG_CONFIGR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk
12527#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos (1U)
12528#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)
12529#define OTFDEC_REG_CONFIGR_CONFIGLOCK OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk
12531#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos (2U)
12532#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)
12533#define OTFDEC_REG_CONFIGR_KEYLOCK OTFDEC_REG_CONFIGR_KEYLOCK_Msk
12535#define OTFDEC_REG_CONFIGR_MODE_Pos (4U)
12536#define OTFDEC_REG_CONFIGR_MODE_Msk (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)
12537#define OTFDEC_REG_CONFIGR_MODE OTFDEC_REG_CONFIGR_MODE_Msk
12538#define OTFDEC_REG_CONFIGR_MODE_0 (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)
12539#define OTFDEC_REG_CONFIGR_MODE_1 (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)
12541#define OTFDEC_REG_CONFIGR_KEYCRC_Pos (8U)
12542#define OTFDEC_REG_CONFIGR_KEYCRC_Msk (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)
12543#define OTFDEC_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk
12545#define OTFDEC_REG_CONFIGR_VERSION_Pos (16U)
12546#define OTFDEC_REG_CONFIGR_VERSION_Msk (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)
12547#define OTFDEC_REG_CONFIGR_VERSION OTFDEC_REG_CONFIGR_VERSION_Msk
12549/****************** Bit definition for OTFDEC_REG_START_ADDR register ******/
12550#define OTFDEC_REG_START_ADDR_Pos (0U)
12551#define OTFDEC_REG_START_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)
12552#define OTFDEC_REG_START_ADDR OTFDEC_REG_START_ADDR_Msk
12554/****************** Bit definition for OTFDEC_REG_END_ADDR register ********/
12555#define OTFDEC_REG_END_ADDR_Pos (0U)
12556#define OTFDEC_REG_END_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)
12557#define OTFDEC_REG_END_ADDR OTFDEC_REG_END_ADDR_Msk
12559/****************** Bit definition for OTFDEC_REG_NONCER0 register *********/
12560#define OTFDEC_REG_NONCER0_Pos (0U)
12561#define OTFDEC_REG_NONCER0_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)
12562#define OTFDEC_REG_NONCER0 OTFDEC_REG_NONCER0_Msk
12564/****************** Bit definition for OTFDEC_REG_NONCER1 register *********/
12565#define OTFDEC_REG_NONCER1_Pos (0U)
12566#define OTFDEC_REG_NONCER1_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)
12567#define OTFDEC_REG_NONCER1 OTFDEC_REG_NONCER1_Msk
12569/****************** Bit definition for OTFDEC_REG_KEYR0 register ***********/
12570#define OTFDEC_REG_KEYR0_Pos (0U)
12571#define OTFDEC_REG_KEYR0_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)
12572#define OTFDEC_REG_KEYR0 OTFDEC_REG_KEYR0_Msk
12574/****************** Bit definition for OTFDEC_REG_KEYR1 register ***********/
12575#define OTFDEC_REG_KEYR1_Pos (0U)
12576#define OTFDEC_REG_KEYR1_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)
12577#define OTFDEC_REG_KEYR1 OTFDEC_REG_KEYR1_Msk
12579/****************** Bit definition for OTFDEC_REG_KEYR2 register ***********/
12580#define OTFDEC_REG_KEYR2_Pos (0U)
12581#define OTFDEC_REG_KEYR2_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)
12582#define OTFDEC_REG_KEYR2 OTFDEC_REG_KEYR2_Msk
12584/****************** Bit definition for OTFDEC_REG_KEYR3 register ***********/
12585#define OTFDEC_REG_KEYR3_Pos (0U)
12586#define OTFDEC_REG_KEYR3_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)
12587#define OTFDEC_REG_KEYR3 OTFDEC_REG_KEYR3_Msk
12589/****************** Bit definition for OTFDEC_ISR register *****************/
12590#define OTFDEC_ISR_SEIF_Pos (0U)
12591#define OTFDEC_ISR_SEIF_Msk (0x1UL << OTFDEC_ISR_SEIF_Pos)
12592#define OTFDEC_ISR_SEIF OTFDEC_ISR_SEIF_Msk
12594#define OTFDEC_ISR_XONEIF_Pos (1U)
12595#define OTFDEC_ISR_XONEIF_Msk (0x1UL << OTFDEC_ISR_XONEIF_Pos)
12596#define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk
12598#define OTFDEC_ISR_KEIF_Pos (2U)
12599#define OTFDEC_ISR_KEIF_Msk (0x1UL << OTFDEC_ISR_KEIF_Pos)
12600#define OTFDEC_ISR_KEIF OTFDEC_ISR_KEIF_Msk
12602/****************** Bit definition for OTFDEC_ICR register *****************/
12603#define OTFDEC_ICR_SEIF_Pos (0U)
12604#define OTFDEC_ICR_SEIF_Msk (0x1UL << OTFDEC_ICR_SEIF_Pos)
12605#define OTFDEC_ICR_SEIF OTFDEC_ICR_SEIF_Msk
12607#define OTFDEC_ICR_XONEIF_Pos (1U)
12608#define OTFDEC_ICR_XONEIF_Msk (0x1UL << OTFDEC_ICR_XONEIF_Pos)
12609#define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk
12611#define OTFDEC_ICR_KEIF_Pos (2U)
12612#define OTFDEC_ICR_KEIF_Msk (0x1UL << OTFDEC_ICR_KEIF_Pos)
12613#define OTFDEC_ICR_KEIF OTFDEC_ICR_KEIF_Msk
12615/****************** Bit definition for OTFDEC_IER register *****************/
12616#define OTFDEC_IER_SEIE_Pos (0U)
12617#define OTFDEC_IER_SEIE_Msk (0x1UL << OTFDEC_IER_SEIE_Pos)
12618#define OTFDEC_IER_SEIE OTFDEC_IER_SEIE_Msk
12620#define OTFDEC_IER_XONEIE_Pos (1U)
12621#define OTFDEC_IER_XONEIE_Msk (0x1UL << OTFDEC_IER_XONEIE_Pos)
12622#define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk
12624#define OTFDEC_IER_KEIE_Pos (2U)
12625#define OTFDEC_IER_KEIE_Msk (0x1UL << OTFDEC_IER_KEIE_Pos)
12626#define OTFDEC_IER_KEIE OTFDEC_IER_KEIE_Msk
12627
12628/******************************************************************************/
12629/* */
12630/* Power Control */
12631/* */
12632/******************************************************************************/
12633/************************* NUMBER OF POWER DOMAINS **************************/
12634#define POWER_DOMAINS_NUMBER 2U
12636/******************** Bit definition for PWR_CR1 register *******************/
12637#define PWR_CR1_SRDRAMSO_Pos (27U)
12638#define PWR_CR1_SRDRAMSO_Msk (0x1UL << PWR_CR1_SRDRAMSO_Pos)
12639#define PWR_CR1_SRDRAMSO PWR_CR1_SRDRAMSO_Msk
12640#define PWR_CR1_HSITFSO_Pos (26U)
12641#define PWR_CR1_HSITFSO_Msk (0x1UL << PWR_CR1_HSITFSO_Pos)
12642#define PWR_CR1_HSITFSO PWR_CR1_HSITFSO_Msk
12643#define PWR_CR1_GFXSO_Pos (25U)
12644#define PWR_CR1_GFXSO_Msk (0x1UL << PWR_CR1_GFXSO_Pos)
12645#define PWR_CR1_GFXSO PWR_CR1_GFXSO_Msk
12646#define PWR_CR1_ITCMSO_Pos (24U)
12647#define PWR_CR1_ITCMSO_Msk (0x1UL << PWR_CR1_ITCMSO_Pos)
12648#define PWR_CR1_ITCMSO PWR_CR1_ITCMSO_Msk
12649#define PWR_CR1_AHBRAM2SO_Pos (23U)
12650#define PWR_CR1_AHBRAM2SO_Msk (0x1UL << PWR_CR1_AHBRAM2SO_Pos)
12651#define PWR_CR1_AHBRAM2SO PWR_CR1_AHBRAM2SO_Msk
12652#define PWR_CR1_AHBRAM1SO_Pos (22U)
12653#define PWR_CR1_AHBRAM1SO_Msk (0x1UL << PWR_CR1_AHBRAM1SO_Pos)
12654#define PWR_CR1_AHBRAM1SO PWR_CR1_AHBRAM1SO_Msk
12655#define PWR_CR1_AXIRAM3SO_Pos (21U)
12656#define PWR_CR1_AXIRAM3SO_Msk (0x1UL << PWR_CR1_AXIRAM3SO_Pos)
12657#define PWR_CR1_AXIRAM3SO PWR_CR1_AXIRAM3SO_Msk
12658#define PWR_CR1_AXIRAM2SO_Pos (20U)
12659#define PWR_CR1_AXIRAM2SO_Msk (0x1UL << PWR_CR1_AXIRAM2SO_Pos)
12660#define PWR_CR1_AXIRAM2SO PWR_CR1_AXIRAM2SO_Msk
12661#define PWR_CR1_AXIRAM1SO_Pos (19U)
12662#define PWR_CR1_AXIRAM1SO_Msk (0x1UL << PWR_CR1_AXIRAM1SO_Pos)
12663#define PWR_CR1_AXIRAM1SO PWR_CR1_AXIRAM1SO_Msk
12664#define PWR_CR1_ALS_Pos (17U)
12665#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos)
12666#define PWR_CR1_ALS PWR_CR1_ALS_Msk
12667#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos)
12668#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos)
12669#define PWR_CR1_AVDEN_Pos (16U)
12670#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos)
12671#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk
12672#define PWR_CR1_SVOS_Pos (14U)
12673#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos)
12674#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk
12675#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos)
12676#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos)
12677#define PWR_CR1_AVD_READY_Pos (13U)
12678#define PWR_CR1_AVD_READY_Msk (0x1UL << PWR_CR1_AVD_READY_Pos)
12679#define PWR_CR1_AVD_READY PWR_CR1_AVD_READY_Msk
12680#define PWR_CR1_BOOSTE_Pos (12U)
12681#define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos)
12682#define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk
12683#define PWR_CR1_FLPS_Pos (9U)
12684#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos)
12685#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk
12686#define PWR_CR1_DBP_Pos (8U)
12687#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
12688#define PWR_CR1_DBP PWR_CR1_DBP_Msk
12689#define PWR_CR1_PLS_Pos (5U)
12690#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
12691#define PWR_CR1_PLS PWR_CR1_PLS_Msk
12692#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
12693#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
12694#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
12695#define PWR_CR1_PVDEN_Pos (4U)
12696#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos)
12697#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk
12698#define PWR_CR1_LPDS_Pos (0U)
12699#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
12700#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
12703#define PWR_CR1_PLS_LEV0 (0UL)
12704#define PWR_CR1_PLS_LEV1_Pos (5U)
12705#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
12706#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
12707#define PWR_CR1_PLS_LEV2_Pos (6U)
12708#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
12709#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
12710#define PWR_CR1_PLS_LEV3_Pos (5U)
12711#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
12712#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
12713#define PWR_CR1_PLS_LEV4_Pos (7U)
12714#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
12715#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
12716#define PWR_CR1_PLS_LEV5_Pos (5U)
12717#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
12718#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
12719#define PWR_CR1_PLS_LEV6_Pos (6U)
12720#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
12721#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
12722#define PWR_CR1_PLS_LEV7_Pos (5U)
12723#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
12724#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
12727#define PWR_CR1_ALS_LEV0 (0UL)
12728#define PWR_CR1_ALS_LEV1_Pos (17U)
12729#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos)
12730#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk
12731#define PWR_CR1_ALS_LEV2_Pos (18U)
12732#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos)
12733#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk
12734#define PWR_CR1_ALS_LEV3_Pos (17U)
12735#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos)
12736#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk
12738/******************** Bit definition for PWR_CSR1 register ******************/
12739#define PWR_CSR1_MMCVDO_Pos (17U)
12740#define PWR_CSR1_MMCVDO_Msk (0x1UL << PWR_CSR1_MMCVDO_Pos)
12741#define PWR_CSR1_MMCVDO PWR_CSR1_MMCVDO_Msk
12742#define PWR_CSR1_AVDO_Pos (16U)
12743#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos)
12744#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk
12745#define PWR_CSR1_ACTVOS_Pos (14U)
12746#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos)
12747#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk
12748#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos)
12749#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos)
12750#define PWR_CSR1_ACTVOSRDY_Pos (13U)
12751#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
12752#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk
12753#define PWR_CSR1_PVDO_Pos (4U)
12754#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
12755#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
12757/******************** Bit definition for PWR_CR2 register *******************/
12758#define PWR_CR2_TEMPH_Pos (23U)
12759#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos)
12760#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk
12761#define PWR_CR2_TEMPL_Pos (22U)
12762#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos)
12763#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk
12764#define PWR_CR2_VBATH_Pos (21U)
12765#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos)
12766#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk
12767#define PWR_CR2_VBATL_Pos (20U)
12768#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos)
12769#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk
12770#define PWR_CR2_BRRDY_Pos (16U)
12771#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos)
12772#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk
12773#define PWR_CR2_MONEN_Pos (4U)
12774#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos)
12775#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk
12776#define PWR_CR2_BREN_Pos (0U)
12777#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos)
12778#define PWR_CR2_BREN PWR_CR2_BREN_Msk
12780/******************** Bit definition for PWR_CR3 register *******************/
12781#define PWR_CR3_USB33RDY_Pos (26U)
12782#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos)
12783#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk
12784#define PWR_CR3_USBREGEN_Pos (25U)
12785#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos)
12786#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk
12787#define PWR_CR3_USB33DEN_Pos (24U)
12788#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos)
12789#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk
12790#define PWR_CR3_SMPSEXTRDY_Pos (16U)
12791#define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)
12792#define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk
12793#define PWR_CR3_VBRS_Pos (9U)
12794#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos)
12795#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk
12796#define PWR_CR3_VBE_Pos (8U)
12797#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos)
12798#define PWR_CR3_VBE PWR_CR3_VBE_Msk
12799#define PWR_CR3_SMPSLEVEL_Pos (4U)
12800#define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos)
12801#define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk
12802#define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos)
12803#define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos)
12804#define PWR_CR3_SMPSEXTHP_Pos (3U)
12805#define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos)
12806#define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk
12807#define PWR_CR3_SMPSEN_Pos (2U)
12808#define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos)
12809#define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk
12810#define PWR_CR3_LDOEN_Pos (1U)
12811#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos)
12812#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk
12813#define PWR_CR3_BYPASS_Pos (0U)
12814#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos)
12815#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk
12817/******************** Bit definition for PWR_CPUCR register *****************/
12818#define PWR_CPUCR_RUN_SRD_Pos (11U)
12819#define PWR_CPUCR_RUN_SRD_Msk (0x1UL << PWR_CPUCR_RUN_SRD_Pos)
12820#define PWR_CPUCR_RUN_SRD PWR_CPUCR_RUN_SRD_Msk
12821#define PWR_CPUCR_CSSF_Pos (9U)
12822#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos)
12823#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk
12824#define PWR_CPUCR_SBF_Pos (6U)
12825#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos)
12826#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk
12827#define PWR_CPUCR_STOPF_Pos (5U)
12828#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos)
12829#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk
12830#define PWR_CPUCR_PDDS_SRD_Pos (2U)
12831#define PWR_CPUCR_PDDS_SRD_Msk (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)
12832#define PWR_CPUCR_PDDS_SRD PWR_CPUCR_PDDS_SRD_Msk
12833#define PWR_CPUCR_RETDS_CD_Pos (0U)
12834#define PWR_CPUCR_RETDS_CD_Msk (0x1UL << PWR_CPUCR_RETDS_CD_Pos)
12835#define PWR_CPUCR_RETDS_CD PWR_CPUCR_RETDS_CD_Msk
12836/******************** Bit definition for PWR_SRDCR register *****************/
12837#define PWR_SRDCR_VOS_Pos (14U)
12838#define PWR_SRDCR_VOS_Msk (0x3UL << PWR_SRDCR_VOS_Pos)
12839#define PWR_SRDCR_VOS PWR_SRDCR_VOS_Msk
12840#define PWR_SRDCR_VOS_0 (0x1UL << PWR_SRDCR_VOS_Pos)
12841#define PWR_SRDCR_VOS_1 (0x2UL << PWR_SRDCR_VOS_Pos)
12842#define PWR_SRDCR_VOSRDY_Pos (13U)
12843#define PWR_SRDCR_VOSRDY_Msk (0x1UL << PWR_SRDCR_VOSRDY_Pos)
12844#define PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY_Msk
12845/****************** Bit definition for PWR_WKUPCR register ******************/
12846#define PWR_WKUPCR_WKUPC6_Pos (5U)
12847#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
12848#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk
12849#define PWR_WKUPCR_WKUPC5_Pos (4U)
12850#define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos)
12851#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk
12852#define PWR_WKUPCR_WKUPC4_Pos (3U)
12853#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
12854#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk
12855#define PWR_WKUPCR_WKUPC3_Pos (2U)
12856#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos)
12857#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk
12858#define PWR_WKUPCR_WKUPC2_Pos (1U)
12859#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
12860#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk
12861#define PWR_WKUPCR_WKUPC1_Pos (0U)
12862#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
12863#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk
12865/******************** Bit definition for PWR_WKUPFR register ****************/
12866#define PWR_WKUPFR_WKUPF6_Pos (5U)
12867#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
12868#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk
12869#define PWR_WKUPFR_WKUPF5_Pos (4U)
12870#define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos)
12871#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk
12872#define PWR_WKUPFR_WKUPF4_Pos (3U)
12873#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
12874#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk
12875#define PWR_WKUPFR_WKUPF3_Pos (2U)
12876#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos)
12877#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk
12878#define PWR_WKUPFR_WKUPF2_Pos (1U)
12879#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
12880#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk
12881#define PWR_WKUPFR_WKUPF1_Pos (0U)
12882#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
12883#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk
12885/****************** Bit definition for PWR_WKUPEPR register *****************/
12886#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
12887#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
12888#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk
12889#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
12890#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
12891#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
12892#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
12893#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk
12894#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
12895#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
12896#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
12897#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
12898#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk
12899#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
12900#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
12901#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
12902#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
12903#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk
12904#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
12905#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
12906#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
12907#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
12908#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk
12909#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
12910#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
12911#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
12912#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
12913#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk
12914#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
12915#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
12916#define PWR_WKUPEPR_WKUPP6_Pos (13U)
12917#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
12918#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk
12919#define PWR_WKUPEPR_WKUPP5_Pos (12U)
12920#define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)
12921#define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk
12922#define PWR_WKUPEPR_WKUPP4_Pos (11U)
12923#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
12924#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk
12925#define PWR_WKUPEPR_WKUPP3_Pos (10U)
12926#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)
12927#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk
12928#define PWR_WKUPEPR_WKUPP2_Pos (9U)
12929#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
12930#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk
12931#define PWR_WKUPEPR_WKUPP1_Pos (8U)
12932#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
12933#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk
12934#define PWR_WKUPEPR_WKUPEN6_Pos (5U)
12935#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
12936#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk
12937#define PWR_WKUPEPR_WKUPEN5_Pos (4U)
12938#define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)
12939#define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk
12940#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
12941#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
12942#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk
12943#define PWR_WKUPEPR_WKUPEN3_Pos (2U)
12944#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)
12945#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk
12946#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
12947#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
12948#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk
12949#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
12950#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
12951#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk
12952#define PWR_WKUPEPR_WKUPEN_Pos (0U)
12953#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
12954#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk
12956/******************************************************************************/
12957/* */
12958/* Reset and Clock Control */
12959/* */
12960/******************************************************************************/
12961/******************************* RCC VERSION ********************************/
12962#define RCC_VER_2_0
12963
12964/******************** Bit definition for RCC_CR register ********************/
12965#define RCC_CR_HSION_Pos (0U)
12966#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
12967#define RCC_CR_HSION RCC_CR_HSION_Msk
12968#define RCC_CR_HSIKERON_Pos (1U)
12969#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
12970#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
12971#define RCC_CR_HSIRDY_Pos (2U)
12972#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
12973#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
12974#define RCC_CR_HSIDIV_Pos (3U)
12975#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos)
12976#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk
12977#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos)
12978#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos)
12979#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos)
12980#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos)
12982#define RCC_CR_HSIDIVF_Pos (5U)
12983#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
12984#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
12985#define RCC_CR_CSION_Pos (7U)
12986#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos)
12987#define RCC_CR_CSION RCC_CR_CSION_Msk
12988#define RCC_CR_CSIRDY_Pos (8U)
12989#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos)
12990#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk
12991#define RCC_CR_CSIKERON_Pos (9U)
12992#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos)
12993#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk
12994#define RCC_CR_HSI48ON_Pos (12U)
12995#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos)
12996#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk
12997#define RCC_CR_HSI48RDY_Pos (13U)
12998#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos)
12999#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk
13001#define RCC_CR_CPUCKRDY_Pos (14U)
13002#define RCC_CR_CPUCKRDY_Msk (0x1UL << RCC_CR_CPUCKRDY_Pos)
13003#define RCC_CR_CPUCKRDY RCC_CR_CPUCKRDY_Msk
13004#define RCC_CR_CDCKRDY_Pos (15U)
13005#define RCC_CR_CDCKRDY_Msk (0x1UL << RCC_CR_CDCKRDY_Pos)
13006#define RCC_CR_CDCKRDY RCC_CR_CDCKRDY_Msk
13008#define RCC_CR_HSEON_Pos (16U)
13009#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
13010#define RCC_CR_HSEON RCC_CR_HSEON_Msk
13011#define RCC_CR_HSERDY_Pos (17U)
13012#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
13013#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13014#define RCC_CR_HSEBYP_Pos (18U)
13015#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
13016#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13017#define RCC_CR_CSSHSEON_Pos (19U)
13018#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
13019#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
13021#define RCC_CR_HSEEXT_Pos (20U)
13022#define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos)
13023#define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk
13025#define RCC_CR_PLL1ON_Pos (24U)
13026#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos)
13027#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk
13028#define RCC_CR_PLL1RDY_Pos (25U)
13029#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos)
13030#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk
13031#define RCC_CR_PLL2ON_Pos (26U)
13032#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
13033#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
13034#define RCC_CR_PLL2RDY_Pos (27U)
13035#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
13036#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
13037#define RCC_CR_PLL3ON_Pos (28U)
13038#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
13039#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
13040#define RCC_CR_PLL3RDY_Pos (29U)
13041#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
13042#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
13044/*Legacy */
13045#define RCC_CR_PLLON_Pos (24U)
13046#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
13047#define RCC_CR_PLLON RCC_CR_PLLON_Msk
13048#define RCC_CR_PLLRDY_Pos (25U)
13049#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
13050#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13052/******************** Bit definition for RCC_HSICFGR register ***************/
13054#define RCC_HSICFGR_HSICAL_Pos (0U)
13055#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
13056#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk
13057#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos)
13058#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos)
13059#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos)
13060#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos)
13061#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos)
13062#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos)
13063#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos)
13064#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos)
13065#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos)
13066#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos)
13067#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos)
13068#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos)
13071#define RCC_HSICFGR_HSITRIM_Pos (24U)
13072#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
13073#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk
13074#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
13075#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
13076#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
13077#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
13078#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
13079#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
13080#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
13083/******************** Bit definition for RCC_CRRCR register *****************/
13084
13086#define RCC_CRRCR_HSI48CAL_Pos (0U)
13087#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
13088#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
13089#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
13090#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
13091#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
13092#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
13093#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
13094#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
13095#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
13096#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
13097#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
13098#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
13101/******************** Bit definition for RCC_CSICFGR register *****************/
13103#define RCC_CSICFGR_CSICAL_Pos (0U)
13104#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
13105#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk
13106#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos)
13107#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos)
13108#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos)
13109#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos)
13110#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos)
13111#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos)
13112#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos)
13113#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos)
13116#define RCC_CSICFGR_CSITRIM_Pos (24U)
13117#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
13118#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk
13119#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
13120#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
13121#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
13122#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
13123#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
13124#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
13126/******************** Bit definition for RCC_CFGR register ******************/
13128#define RCC_CFGR_SW_Pos (0U)
13129#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)
13130#define RCC_CFGR_SW RCC_CFGR_SW_Msk
13131#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
13132#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
13133#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)
13135#define RCC_CFGR_SW_HSI (0x00000000UL)
13136#define RCC_CFGR_SW_CSI (0x00000001UL)
13137#define RCC_CFGR_SW_HSE (0x00000002UL)
13138#define RCC_CFGR_SW_PLL1 (0x00000003UL)
13141#define RCC_CFGR_SWS_Pos (3U)
13142#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)
13143#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
13144#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
13145#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
13146#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)
13148#define RCC_CFGR_SWS_HSI (0x00000000UL)
13149#define RCC_CFGR_SWS_CSI (0x00000008UL)
13150#define RCC_CFGR_SWS_HSE (0x00000010UL)
13151#define RCC_CFGR_SWS_PLL1 (0x00000018UL)
13153#define RCC_CFGR_STOPWUCK_Pos (6U)
13154#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
13155#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
13157#define RCC_CFGR_STOPKERWUCK_Pos (7U)
13158#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
13159#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk
13162#define RCC_CFGR_RTCPRE_Pos (8U)
13163#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
13164#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13165#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos)
13166#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos)
13167#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos)
13168#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos)
13169#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
13170#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos)
13174#define RCC_CFGR_TIMPRE_Pos (15U)
13175#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
13176#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk
13179#define RCC_CFGR_MCO1_Pos (22U)
13180#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
13181#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13182#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
13183#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
13184#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos)
13186#define RCC_CFGR_MCO1PRE_Pos (18U)
13187#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
13188#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13189#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
13190#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
13191#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
13192#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos)
13194#define RCC_CFGR_MCO2PRE_Pos (25U)
13195#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
13196#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13197#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
13198#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
13199#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
13200#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos)
13202#define RCC_CFGR_MCO2_Pos (29U)
13203#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
13204#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
13205#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
13206#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
13207#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos)
13209/******************** Bit definition for RCC_D1CFGR register ******************/
13211#define RCC_CDCFGR1_HPRE_Pos (0U)
13212#define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos)
13213#define RCC_CDCFGR1_HPRE RCC_CDCFGR1_HPRE_Msk
13214#define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos)
13215#define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos)
13216#define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos)
13217#define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos)
13219#define RCC_CDCFGR1_HPRE_DIV1 (0U)
13220#define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
13221#define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)
13222#define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk
13223#define RCC_CDCFGR1_HPRE_DIV4_Pos (0U)
13224#define RCC_CDCFGR1_HPRE_DIV4_Msk (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)
13225#define RCC_CDCFGR1_HPRE_DIV4 RCC_CDCFGR1_HPRE_DIV4_Msk
13226#define RCC_CDCFGR1_HPRE_DIV8_Pos (1U)
13227#define RCC_CDCFGR1_HPRE_DIV8_Msk (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)
13228#define RCC_CDCFGR1_HPRE_DIV8 RCC_CDCFGR1_HPRE_DIV8_Msk
13229#define RCC_CDCFGR1_HPRE_DIV16_Pos (0U)
13230#define RCC_CDCFGR1_HPRE_DIV16_Msk (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)
13231#define RCC_CDCFGR1_HPRE_DIV16 RCC_CDCFGR1_HPRE_DIV16_Msk
13232#define RCC_CDCFGR1_HPRE_DIV64_Pos (2U)
13233#define RCC_CDCFGR1_HPRE_DIV64_Msk (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)
13234#define RCC_CDCFGR1_HPRE_DIV64 RCC_CDCFGR1_HPRE_DIV64_Msk
13235#define RCC_CDCFGR1_HPRE_DIV128_Pos (0U)
13236#define RCC_CDCFGR1_HPRE_DIV128_Msk (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos)
13237#define RCC_CDCFGR1_HPRE_DIV128 RCC_CDCFGR1_HPRE_DIV128_Msk
13238#define RCC_CDCFGR1_HPRE_DIV256_Pos (1U)
13239#define RCC_CDCFGR1_HPRE_DIV256_Msk (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos)
13240#define RCC_CDCFGR1_HPRE_DIV256 RCC_CDCFGR1_HPRE_DIV256_Msk
13241#define RCC_CDCFGR1_HPRE_DIV512_Pos (0U)
13242#define RCC_CDCFGR1_HPRE_DIV512_Msk (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos)
13243#define RCC_CDCFGR1_HPRE_DIV512 RCC_CDCFGR1_HPRE_DIV512_Msk
13246#define RCC_CDCFGR1_CDPPRE_Pos (4U)
13247#define RCC_CDCFGR1_CDPPRE_Msk (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)
13248#define RCC_CDCFGR1_CDPPRE RCC_CDCFGR1_CDPPRE_Msk
13249#define RCC_CDCFGR1_CDPPRE_0 (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)
13250#define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)
13251#define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)
13253#define RCC_CDCFGR1_CDPPRE_DIV1 (0U)
13254#define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
13255#define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos)
13256#define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk
13257#define RCC_CDCFGR1_CDPPRE_DIV4_Pos (4U)
13258#define RCC_CDCFGR1_CDPPRE_DIV4_Msk (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos)
13259#define RCC_CDCFGR1_CDPPRE_DIV4 RCC_CDCFGR1_CDPPRE_DIV4_Msk
13260#define RCC_CDCFGR1_CDPPRE_DIV8_Pos (5U)
13261#define RCC_CDCFGR1_CDPPRE_DIV8_Msk (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos)
13262#define RCC_CDCFGR1_CDPPRE_DIV8 RCC_CDCFGR1_CDPPRE_DIV8_Msk
13263#define RCC_CDCFGR1_CDPPRE_DIV16_Pos (4U)
13264#define RCC_CDCFGR1_CDPPRE_DIV16_Msk (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos)
13265#define RCC_CDCFGR1_CDPPRE_DIV16 RCC_CDCFGR1_CDPPRE_DIV16_Msk
13267#define RCC_CDCFGR1_CDCPRE_Pos (8U)
13268#define RCC_CDCFGR1_CDCPRE_Msk (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)
13269#define RCC_CDCFGR1_CDCPRE RCC_CDCFGR1_CDCPRE_Msk
13270#define RCC_CDCFGR1_CDCPRE_0 (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)
13271#define RCC_CDCFGR1_CDCPRE_1 (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)
13272#define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)
13273#define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)
13275#define RCC_CDCFGR1_CDCPRE_DIV1 (0U)
13276#define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
13277#define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)
13278#define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk
13279#define RCC_CDCFGR1_CDCPRE_DIV4_Pos (8U)
13280#define RCC_CDCFGR1_CDCPRE_DIV4_Msk (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)
13281#define RCC_CDCFGR1_CDCPRE_DIV4 RCC_CDCFGR1_CDCPRE_DIV4_Msk
13282#define RCC_CDCFGR1_CDCPRE_DIV8_Pos (9U)
13283#define RCC_CDCFGR1_CDCPRE_DIV8_Msk (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)
13284#define RCC_CDCFGR1_CDCPRE_DIV8 RCC_CDCFGR1_CDCPRE_DIV8_Msk
13285#define RCC_CDCFGR1_CDCPRE_DIV16_Pos (8U)
13286#define RCC_CDCFGR1_CDCPRE_DIV16_Msk (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos)
13287#define RCC_CDCFGR1_CDCPRE_DIV16 RCC_CDCFGR1_CDCPRE_DIV16_Msk
13288#define RCC_CDCFGR1_CDCPRE_DIV64_Pos (10U)
13289#define RCC_CDCFGR1_CDCPRE_DIV64_Msk (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos)
13290#define RCC_CDCFGR1_CDCPRE_DIV64 RCC_CDCFGR1_CDCPRE_DIV64_Msk
13291#define RCC_CDCFGR1_CDCPRE_DIV128_Pos (8U)
13292#define RCC_CDCFGR1_CDCPRE_DIV128_Msk (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)
13293#define RCC_CDCFGR1_CDCPRE_DIV128 RCC_CDCFGR1_CDCPRE_DIV128_Msk
13294#define RCC_CDCFGR1_CDCPRE_DIV256_Pos (9U)
13295#define RCC_CDCFGR1_CDCPRE_DIV256_Msk (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)
13296#define RCC_CDCFGR1_CDCPRE_DIV256 RCC_CDCFGR1_CDCPRE_DIV256_Msk
13297#define RCC_CDCFGR1_CDCPRE_DIV512_Pos (8U)
13298#define RCC_CDCFGR1_CDCPRE_DIV512_Msk (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)
13299#define RCC_CDCFGR1_CDCPRE_DIV512 RCC_CDCFGR1_CDCPRE_DIV512_Msk
13301/******************** Bit definition for RCC_CDCFGR2 register ******************/
13303#define RCC_CDCFGR2_CDPPRE1_Pos (4U)
13304#define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos)
13305#define RCC_CDCFGR2_CDPPRE1 RCC_CDCFGR2_CDPPRE1_Msk
13306#define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos)
13307#define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos)
13308#define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos)
13310#define RCC_CDCFGR2_CDPPRE1_DIV1 (0U)
13311#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
13312#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos)
13313#define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk
13314#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos (4U)
13315#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos)
13316#define RCC_CDCFGR2_CDPPRE1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4_Msk
13317#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos (5U)
13318#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos)
13319#define RCC_CDCFGR2_CDPPRE1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8_Msk
13320#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos (4U)
13321#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos)
13322#define RCC_CDCFGR2_CDPPRE1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16_Msk
13325#define RCC_CDCFGR2_CDPPRE2_Pos (8U)
13326#define RCC_CDCFGR2_CDPPRE2_Msk (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos)
13327#define RCC_CDCFGR2_CDPPRE2 RCC_CDCFGR2_CDPPRE2_Msk
13328#define RCC_CDCFGR2_CDPPRE2_0 (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos)
13329#define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos)
13330#define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos)
13332#define RCC_CDCFGR2_CDPPRE2_DIV1 (0U)
13333#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
13334#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos)
13335#define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk
13336#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos (8U)
13337#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos)
13338#define RCC_CDCFGR2_CDPPRE2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4_Msk
13339#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos (9U)
13340#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos)
13341#define RCC_CDCFGR2_CDPPRE2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8_Msk
13342#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos (8U)
13343#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos)
13344#define RCC_CDCFGR2_CDPPRE2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16_Msk
13346/******************** Bit definition for RCC_SRDCFGR register ******************/
13348#define RCC_SRDCFGR_SRDPPRE_Pos (4U)
13349#define RCC_SRDCFGR_SRDPPRE_Msk (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos)
13350#define RCC_SRDCFGR_SRDPPRE RCC_SRDCFGR_SRDPPRE_Msk
13351#define RCC_SRDCFGR_SRDPPRE_0 (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos)
13352#define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos)
13353#define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos)
13355#define RCC_SRDCFGR_SRDPPRE_DIV1 (0U)
13356#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
13357#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos)
13358#define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk
13359#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos (4U)
13360#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos)
13361#define RCC_SRDCFGR_SRDPPRE_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4_Msk
13362#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos (5U)
13363#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos)
13364#define RCC_SRDCFGR_SRDPPRE_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8_Msk
13365#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos (4U)
13366#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos)
13367#define RCC_SRDCFGR_SRDPPRE_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16_Msk
13369/******************** Bit definition for RCC_PLLCKSELR register *************/
13370
13371#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
13372#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
13373#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
13374
13375#define RCC_PLLCKSELR_PLLSRC_HSI (0U)
13376#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
13377#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
13378#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk
13379#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
13380#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
13381#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk
13382#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
13383#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
13384#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk
13386#define RCC_PLLCKSELR_DIVM1_Pos (4U)
13387#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
13388#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
13389#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
13390#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
13391#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
13392#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
13393#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
13394#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
13396#define RCC_PLLCKSELR_DIVM2_Pos (12U)
13397#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
13398#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
13399#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
13400#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
13401#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
13402#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
13403#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
13404#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
13406#define RCC_PLLCKSELR_DIVM3_Pos (20U)
13407#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
13408#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
13409#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
13410#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
13411#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
13412#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
13413#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
13414#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
13416/******************** Bit definition for RCC_PLLCFGR register ***************/
13417
13418#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
13419#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
13420#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
13421#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
13422#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
13423#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
13424#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
13425#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
13426#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
13427#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
13428#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
13429#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
13430#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
13432#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
13433#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
13434#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
13435#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
13436#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
13437#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
13438#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
13439#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
13440#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
13441#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
13442#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
13443#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
13444#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
13446#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
13447#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
13448#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
13449#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
13450#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
13451#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
13452#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
13453#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
13454#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
13455#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
13456#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
13457#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
13458#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
13460#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
13461#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
13462#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
13463#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
13464#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
13465#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
13466#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
13467#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
13468#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
13469
13470#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
13471#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
13472#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
13473#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
13474#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
13475#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
13476#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
13477#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
13478#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
13479
13480#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
13481#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
13482#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
13483#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
13484#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
13485#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
13486#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
13487#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
13488#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
13489
13490
13491/******************** Bit definition for RCC_PLL1DIVR register ***************/
13492#define RCC_PLL1DIVR_N1_Pos (0U)
13493#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
13494#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
13495#define RCC_PLL1DIVR_P1_Pos (9U)
13496#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos)
13497#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
13498#define RCC_PLL1DIVR_Q1_Pos (16U)
13499#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
13500#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
13501#define RCC_PLL1DIVR_R1_Pos (24U)
13502#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos)
13503#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
13504
13505/******************** Bit definition for RCC_PLL1FRACR register ***************/
13506#define RCC_PLL1FRACR_FRACN1_Pos (3U)
13507#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
13508#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
13509
13510/******************** Bit definition for RCC_PLL2DIVR register ***************/
13511#define RCC_PLL2DIVR_N2_Pos (0U)
13512#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
13513#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
13514#define RCC_PLL2DIVR_P2_Pos (9U)
13515#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos)
13516#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
13517#define RCC_PLL2DIVR_Q2_Pos (16U)
13518#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
13519#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
13520#define RCC_PLL2DIVR_R2_Pos (24U)
13521#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos)
13522#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
13523
13524/******************** Bit definition for RCC_PLL2FRACR register ***************/
13525#define RCC_PLL2FRACR_FRACN2_Pos (3U)
13526#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
13527#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
13528
13529/******************** Bit definition for RCC_PLL3DIVR register ***************/
13530#define RCC_PLL3DIVR_N3_Pos (0U)
13531#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
13532#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
13533#define RCC_PLL3DIVR_P3_Pos (9U)
13534#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos)
13535#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
13536#define RCC_PLL3DIVR_Q3_Pos (16U)
13537#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
13538#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
13539#define RCC_PLL3DIVR_R3_Pos (24U)
13540#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos)
13541#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
13542
13543/******************** Bit definition for RCC_PLL3FRACR register ***************/
13544#define RCC_PLL3FRACR_FRACN3_Pos (3U)
13545#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
13546#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
13547
13548/******************** Bit definition for RCC_CDCCIPR register ***************/
13549#define RCC_CDCCIPR_FMCSEL_Pos (0U)
13550#define RCC_CDCCIPR_FMCSEL_Msk (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)
13551#define RCC_CDCCIPR_FMCSEL RCC_CDCCIPR_FMCSEL_Msk
13552#define RCC_CDCCIPR_FMCSEL_0 (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)
13553#define RCC_CDCCIPR_FMCSEL_1 (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)
13554#define RCC_CDCCIPR_OCTOSPISEL_Pos (4U)
13555#define RCC_CDCCIPR_OCTOSPISEL_Msk (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos)
13556#define RCC_CDCCIPR_OCTOSPISEL RCC_CDCCIPR_OCTOSPISEL_Msk
13557#define RCC_CDCCIPR_OCTOSPISEL_0 (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos)
13558#define RCC_CDCCIPR_OCTOSPISEL_1 (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos)
13559#define RCC_CDCCIPR_SDMMCSEL_Pos (16U)
13560#define RCC_CDCCIPR_SDMMCSEL_Msk (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)
13561#define RCC_CDCCIPR_SDMMCSEL RCC_CDCCIPR_SDMMCSEL_Msk
13562#define RCC_CDCCIPR_CKPERSEL_Pos (28U)
13563#define RCC_CDCCIPR_CKPERSEL_Msk (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)
13564#define RCC_CDCCIPR_CKPERSEL RCC_CDCCIPR_CKPERSEL_Msk
13565#define RCC_CDCCIPR_CKPERSEL_0 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)
13566#define RCC_CDCCIPR_CKPERSEL_1 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)
13568/******************** Bit definition for RCC_CDCCIP1R register ***************/
13569#define RCC_CDCCIP1R_SAI1SEL_Pos (0U)
13570#define RCC_CDCCIP1R_SAI1SEL_Msk (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)
13571#define RCC_CDCCIP1R_SAI1SEL RCC_CDCCIP1R_SAI1SEL_Msk
13572#define RCC_CDCCIP1R_SAI1SEL_0 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)
13573#define RCC_CDCCIP1R_SAI1SEL_1 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)
13574#define RCC_CDCCIP1R_SAI1SEL_2 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)
13576#define RCC_CDCCIP1R_SAI2ASEL_Pos (6U)
13577#define RCC_CDCCIP1R_SAI2ASEL_Msk (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)
13578#define RCC_CDCCIP1R_SAI2ASEL RCC_CDCCIP1R_SAI2ASEL_Msk
13579#define RCC_CDCCIP1R_SAI2ASEL_0 (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)
13580#define RCC_CDCCIP1R_SAI2ASEL_1 (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)
13581#define RCC_CDCCIP1R_SAI2ASEL_2 (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)
13583#define RCC_CDCCIP1R_SAI2BSEL_Pos (9U)
13584#define RCC_CDCCIP1R_SAI2BSEL_Msk (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)
13585#define RCC_CDCCIP1R_SAI2BSEL RCC_CDCCIP1R_SAI2BSEL_Msk
13586#define RCC_CDCCIP1R_SAI2BSEL_0 (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)
13587#define RCC_CDCCIP1R_SAI2BSEL_1 (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)
13588#define RCC_CDCCIP1R_SAI2BSEL_2 (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)
13590#define RCC_CDCCIP1R_SPI123SEL_Pos (12U)
13591#define RCC_CDCCIP1R_SPI123SEL_Msk (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos)
13592#define RCC_CDCCIP1R_SPI123SEL RCC_CDCCIP1R_SPI123SEL_Msk
13593#define RCC_CDCCIP1R_SPI123SEL_0 (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos)
13594#define RCC_CDCCIP1R_SPI123SEL_1 (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos)
13595#define RCC_CDCCIP1R_SPI123SEL_2 (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos)
13597#define RCC_CDCCIP1R_SPI45SEL_Pos (16U)
13598#define RCC_CDCCIP1R_SPI45SEL_Msk (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)
13599#define RCC_CDCCIP1R_SPI45SEL RCC_CDCCIP1R_SPI45SEL_Msk
13600#define RCC_CDCCIP1R_SPI45SEL_0 (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)
13601#define RCC_CDCCIP1R_SPI45SEL_1 (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)
13602#define RCC_CDCCIP1R_SPI45SEL_2 (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)
13604#define RCC_CDCCIP1R_SPDIFSEL_Pos (20U)
13605#define RCC_CDCCIP1R_SPDIFSEL_Msk (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)
13606#define RCC_CDCCIP1R_SPDIFSEL RCC_CDCCIP1R_SPDIFSEL_Msk
13607#define RCC_CDCCIP1R_SPDIFSEL_0 (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)
13608#define RCC_CDCCIP1R_SPDIFSEL_1 (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)
13610#define RCC_CDCCIP1R_DFSDM1SEL_Pos (24U)
13611#define RCC_CDCCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos)
13612#define RCC_CDCCIP1R_DFSDM1SEL RCC_CDCCIP1R_DFSDM1SEL_Msk
13613
13614#define RCC_CDCCIP1R_FDCANSEL_Pos (28U)
13615#define RCC_CDCCIP1R_FDCANSEL_Msk (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)
13616#define RCC_CDCCIP1R_FDCANSEL RCC_CDCCIP1R_FDCANSEL_Msk
13617#define RCC_CDCCIP1R_FDCANSEL_0 (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)
13618#define RCC_CDCCIP1R_FDCANSEL_1 (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)
13620#define RCC_CDCCIP1R_SWPSEL_Pos (31U)
13621#define RCC_CDCCIP1R_SWPSEL_Msk (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)
13622#define RCC_CDCCIP1R_SWPSEL RCC_CDCCIP1R_SWPSEL_Msk
13623
13624/******************** Bit definition for RCC_CDCCIP2R register ***************/
13625#define RCC_CDCCIP2R_USART234578SEL_Pos (0U)
13626#define RCC_CDCCIP2R_USART234578SEL_Msk (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)
13627#define RCC_CDCCIP2R_USART234578SEL RCC_CDCCIP2R_USART234578SEL_Msk
13628#define RCC_CDCCIP2R_USART234578SEL_0 (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)
13629#define RCC_CDCCIP2R_USART234578SEL_1 (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)
13630#define RCC_CDCCIP2R_USART234578SEL_2 (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)
13632#define RCC_CDCCIP2R_USART16910SEL_Pos (3U)
13633#define RCC_CDCCIP2R_USART16910SEL_Msk (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)
13634#define RCC_CDCCIP2R_USART16910SEL RCC_CDCCIP2R_USART16910SEL_Msk
13635#define RCC_CDCCIP2R_USART16910SEL_0 (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)
13636#define RCC_CDCCIP2R_USART16910SEL_1 (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)
13637#define RCC_CDCCIP2R_USART16910SEL_2 (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)
13639#define RCC_CDCCIP2R_RNGSEL_Pos (8U)
13640#define RCC_CDCCIP2R_RNGSEL_Msk (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)
13641#define RCC_CDCCIP2R_RNGSEL RCC_CDCCIP2R_RNGSEL_Msk
13642#define RCC_CDCCIP2R_RNGSEL_0 (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)
13643#define RCC_CDCCIP2R_RNGSEL_1 (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)
13645#define RCC_CDCCIP2R_I2C123SEL_Pos (12U)
13646#define RCC_CDCCIP2R_I2C123SEL_Msk (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)
13647#define RCC_CDCCIP2R_I2C123SEL RCC_CDCCIP2R_I2C123SEL_Msk
13648#define RCC_CDCCIP2R_I2C123SEL_0 (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)
13649#define RCC_CDCCIP2R_I2C123SEL_1 (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)
13651#define RCC_CDCCIP2R_USBSEL_Pos (20U)
13652#define RCC_CDCCIP2R_USBSEL_Msk (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)
13653#define RCC_CDCCIP2R_USBSEL RCC_CDCCIP2R_USBSEL_Msk
13654#define RCC_CDCCIP2R_USBSEL_0 (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)
13655#define RCC_CDCCIP2R_USBSEL_1 (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)
13657#define RCC_CDCCIP2R_CECSEL_Pos (22U)
13658#define RCC_CDCCIP2R_CECSEL_Msk (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)
13659#define RCC_CDCCIP2R_CECSEL RCC_CDCCIP2R_CECSEL_Msk
13660#define RCC_CDCCIP2R_CECSEL_0 (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)
13661#define RCC_CDCCIP2R_CECSEL_1 (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)
13663#define RCC_CDCCIP2R_LPTIM1SEL_Pos (28U)
13664#define RCC_CDCCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)
13665#define RCC_CDCCIP2R_LPTIM1SEL RCC_CDCCIP2R_LPTIM1SEL_Msk
13666#define RCC_CDCCIP2R_LPTIM1SEL_0 (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)
13667#define RCC_CDCCIP2R_LPTIM1SEL_1 (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)
13668#define RCC_CDCCIP2R_LPTIM1SEL_2 (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)
13670/******************** Bit definition for RCC_SRDCCIPR register ***************/
13671#define RCC_SRDCCIPR_LPUART1SEL_Pos (0U)
13672#define RCC_SRDCCIPR_LPUART1SEL_Msk (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)
13673#define RCC_SRDCCIPR_LPUART1SEL RCC_SRDCCIPR_LPUART1SEL_Msk
13674#define RCC_SRDCCIPR_LPUART1SEL_0 (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)
13675#define RCC_SRDCCIPR_LPUART1SEL_1 (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)
13676#define RCC_SRDCCIPR_LPUART1SEL_2 (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)
13678#define RCC_SRDCCIPR_I2C4SEL_Pos (8U)
13679#define RCC_SRDCCIPR_I2C4SEL_Msk (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)
13680#define RCC_SRDCCIPR_I2C4SEL RCC_SRDCCIPR_I2C4SEL_Msk
13681#define RCC_SRDCCIPR_I2C4SEL_0 (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)
13682#define RCC_SRDCCIPR_I2C4SEL_1 (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)
13684#define RCC_SRDCCIPR_LPTIM2SEL_Pos (10U)
13685#define RCC_SRDCCIPR_LPTIM2SEL_Msk (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)
13686#define RCC_SRDCCIPR_LPTIM2SEL RCC_SRDCCIPR_LPTIM2SEL_Msk
13687#define RCC_SRDCCIPR_LPTIM2SEL_0 (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)
13688#define RCC_SRDCCIPR_LPTIM2SEL_1 (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)
13689#define RCC_SRDCCIPR_LPTIM2SEL_2 (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)
13691#define RCC_SRDCCIPR_LPTIM3SEL_Pos (13U)
13692#define RCC_SRDCCIPR_LPTIM3SEL_Msk (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)
13693#define RCC_SRDCCIPR_LPTIM3SEL RCC_SRDCCIPR_LPTIM3SEL_Msk
13694#define RCC_SRDCCIPR_LPTIM3SEL_0 (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)
13695#define RCC_SRDCCIPR_LPTIM3SEL_1 (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)
13696#define RCC_SRDCCIPR_LPTIM3SEL_2 (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)
13698#define RCC_SRDCCIPR_ADCSEL_Pos (16U)
13699#define RCC_SRDCCIPR_ADCSEL_Msk (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)
13700#define RCC_SRDCCIPR_ADCSEL RCC_SRDCCIPR_ADCSEL_Msk
13701#define RCC_SRDCCIPR_ADCSEL_0 (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)
13702#define RCC_SRDCCIPR_ADCSEL_1 (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)
13704#define RCC_SRDCCIPR_DFSDM2SEL_Pos (27U)
13705#define RCC_SRDCCIPR_DFSDM2SEL_Msk (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)
13706#define RCC_SRDCCIPR_DFSDM2SEL RCC_SRDCCIPR_DFSDM2SEL_Msk
13707
13708#define RCC_SRDCCIPR_SPI6SEL_Pos (28U)
13709#define RCC_SRDCCIPR_SPI6SEL_Msk (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)
13710#define RCC_SRDCCIPR_SPI6SEL RCC_SRDCCIPR_SPI6SEL_Msk
13711#define RCC_SRDCCIPR_SPI6SEL_0 (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)
13712#define RCC_SRDCCIPR_SPI6SEL_1 (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)
13713#define RCC_SRDCCIPR_SPI6SEL_2 (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)
13715/******************** Bit definition for RCC_CIER register ******************/
13716#define RCC_CIER_LSIRDYIE_Pos (0U)
13717#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
13718#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
13719#define RCC_CIER_LSERDYIE_Pos (1U)
13720#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
13721#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
13722#define RCC_CIER_HSIRDYIE_Pos (2U)
13723#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
13724#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
13725#define RCC_CIER_HSERDYIE_Pos (3U)
13726#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
13727#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
13728#define RCC_CIER_CSIRDYIE_Pos (4U)
13729#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos)
13730#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
13731#define RCC_CIER_HSI48RDYIE_Pos (5U)
13732#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
13733#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
13734#define RCC_CIER_PLL1RDYIE_Pos (6U)
13735#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
13736#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
13737#define RCC_CIER_PLL2RDYIE_Pos (7U)
13738#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
13739#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
13740#define RCC_CIER_PLL3RDYIE_Pos (8U)
13741#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
13742#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
13743#define RCC_CIER_LSECSSIE_Pos (9U)
13744#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
13745#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
13746
13747/******************** Bit definition for RCC_CIFR register ******************/
13748#define RCC_CIFR_LSIRDYF_Pos (0U)
13749#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
13750#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
13751#define RCC_CIFR_LSERDYF_Pos (1U)
13752#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
13753#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
13754#define RCC_CIFR_HSIRDYF_Pos (2U)
13755#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
13756#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
13757#define RCC_CIFR_HSERDYF_Pos (3U)
13758#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
13759#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
13760#define RCC_CIFR_CSIRDYF_Pos (4U)
13761#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos)
13762#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
13763#define RCC_CIFR_HSI48RDYF_Pos (5U)
13764#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
13765#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
13766#define RCC_CIFR_PLLRDYF_Pos (6U)
13767#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
13768#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
13769#define RCC_CIFR_PLL2RDYF_Pos (7U)
13770#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
13771#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
13772#define RCC_CIFR_PLL3RDYF_Pos (8U)
13773#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
13774#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
13775#define RCC_CIFR_LSECSSF_Pos (9U)
13776#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
13777#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
13778#define RCC_CIFR_HSECSSF_Pos (10U)
13779#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos)
13780#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
13781
13782/******************** Bit definition for RCC_CICR register ******************/
13783#define RCC_CICR_LSIRDYC_Pos (0U)
13784#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
13785#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
13786#define RCC_CICR_LSERDYC_Pos (1U)
13787#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
13788#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
13789#define RCC_CICR_HSIRDYC_Pos (2U)
13790#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
13791#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
13792#define RCC_CICR_HSERDYC_Pos (3U)
13793#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
13794#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
13795#define RCC_CICR_CSIRDYC_Pos (4U)
13796#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos)
13797#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
13798#define RCC_CICR_HSI48RDYC_Pos (5U)
13799#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
13800#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
13801#define RCC_CICR_PLLRDYC_Pos (6U)
13802#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
13803#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
13804#define RCC_CICR_PLL2RDYC_Pos (7U)
13805#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos)
13806#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
13807#define RCC_CICR_PLL3RDYC_Pos (8U)
13808#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos)
13809#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
13810#define RCC_CICR_LSECSSC_Pos (9U)
13811#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
13812#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
13813#define RCC_CICR_HSECSSC_Pos (10U)
13814#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos)
13815#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
13816
13817/******************** Bit definition for RCC_BDCR register ******************/
13818#define RCC_BDCR_LSEON_Pos (0U)
13819#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
13820#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
13821#define RCC_BDCR_LSERDY_Pos (1U)
13822#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
13823#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
13824#define RCC_BDCR_LSEBYP_Pos (2U)
13825#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
13826#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
13827
13828#define RCC_BDCR_LSEDRV_Pos (3U)
13829#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
13830#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
13831#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
13832#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
13834#define RCC_BDCR_LSECSSON_Pos (5U)
13835#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
13836#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
13837#define RCC_BDCR_LSECSSD_Pos (6U)
13838#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
13839#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
13840#define RCC_BDCR_LSEEXT_Pos (7U)
13841#define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos)
13842#define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk
13843
13844#define RCC_BDCR_RTCSEL_Pos (8U)
13845#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
13846#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
13847#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
13848#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
13850#define RCC_BDCR_RTCEN_Pos (15U)
13851#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
13852#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
13853#define RCC_BDCR_VSWRST_Pos (16U)
13854#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos)
13855#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk
13856/* Legacy define */
13857#define RCC_BDCR_BDRST_Pos RCC_BDCR_VSWRST_Pos
13858#define RCC_BDCR_BDRST_Msk RCC_BDCR_VSWRST_Msk
13859#define RCC_BDCR_BDRST RCC_BDCR_VSWRST
13860/******************** Bit definition for RCC_CSR register *******************/
13861#define RCC_CSR_LSION_Pos (0U)
13862#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
13863#define RCC_CSR_LSION RCC_CSR_LSION_Msk
13864#define RCC_CSR_LSIRDY_Pos (1U)
13865#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
13866#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
13867
13868
13869/******************** Bit definition for RCC_AHB3ENR register **************/
13870#define RCC_AHB3ENR_MDMAEN_Pos (0U)
13871#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
13872#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
13873#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
13874#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
13875#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
13876#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
13877#define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)
13878#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
13879#define RCC_AHB3ENR_FMCEN_Pos (12U)
13880#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
13881#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
13882#define RCC_AHB3ENR_OSPI1EN_Pos (14U)
13883#define RCC_AHB3ENR_OSPI1EN_Msk (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)
13884#define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
13885#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
13886#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
13887#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
13888#define RCC_AHB3ENR_OSPI2EN_Pos (19U)
13889#define RCC_AHB3ENR_OSPI2EN_Msk (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)
13890#define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
13891#define RCC_AHB3ENR_IOMNGREN_Pos (21U)
13892#define RCC_AHB3ENR_IOMNGREN_Msk (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)
13893#define RCC_AHB3ENR_IOMNGREN RCC_AHB3ENR_IOMNGREN_Msk
13894#define RCC_AHB3ENR_OTFDEC1EN_Pos (22U)
13895#define RCC_AHB3ENR_OTFDEC1EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)
13896#define RCC_AHB3ENR_OTFDEC1EN RCC_AHB3ENR_OTFDEC1EN_Msk
13897#define RCC_AHB3ENR_OTFDEC2EN_Pos (23U)
13898#define RCC_AHB3ENR_OTFDEC2EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)
13899#define RCC_AHB3ENR_OTFDEC2EN RCC_AHB3ENR_OTFDEC2EN_Msk
13900#define RCC_AHB3ENR_GFXMMUEN_Pos (24U)
13901#define RCC_AHB3ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)
13902#define RCC_AHB3ENR_GFXMMUEN RCC_AHB3ENR_GFXMMUEN_Msk
13903
13904/******************** Bit definition for RCC_AHB1ENR register ***************/
13905#define RCC_AHB1ENR_DMA1EN_Pos (0U)
13906#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
13907#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
13908#define RCC_AHB1ENR_DMA2EN_Pos (1U)
13909#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
13910#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
13911#define RCC_AHB1ENR_ADC12EN_Pos (5U)
13912#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
13913#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
13914#define RCC_AHB1ENR_CRCEN_Pos (9U)
13915#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
13916#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
13917#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
13918#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
13919#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
13920#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
13921#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
13922#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
13923
13924/******************** Bit definition for RCC_AHB2ENR register ***************/
13925#define RCC_AHB2ENR_DCMI_PSSIEN_Pos (0U)
13926#define RCC_AHB2ENR_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)
13927#define RCC_AHB2ENR_DCMI_PSSIEN RCC_AHB2ENR_DCMI_PSSIEN_Msk
13928#define RCC_AHB2ENR_HSEMEN_Pos (2U)
13929#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)
13930#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk
13931#define RCC_AHB2ENR_CRYPEN_Pos (4U)
13932#define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)
13933#define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
13934#define RCC_AHB2ENR_HASHEN_Pos (5U)
13935#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos)
13936#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
13937#define RCC_AHB2ENR_RNGEN_Pos (6U)
13938#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
13939#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
13940#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
13941#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
13942#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
13943#define RCC_AHB2ENR_BDMA1EN_Pos (11U)
13944#define RCC_AHB2ENR_BDMA1EN_Msk (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)
13945#define RCC_AHB2ENR_BDMA1EN RCC_AHB2ENR_BDMA1EN_Msk
13946#define RCC_AHB2ENR_AHBSRAM1EN_Pos (29U)
13947#define RCC_AHB2ENR_AHBSRAM1EN_Msk (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)
13948#define RCC_AHB2ENR_AHBSRAM1EN RCC_AHB2ENR_AHBSRAM1EN_Msk
13949#define RCC_AHB2ENR_AHBSRAM2EN_Pos (30U)
13950#define RCC_AHB2ENR_AHBSRAM2EN_Msk (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)
13951#define RCC_AHB2ENR_AHBSRAM2EN RCC_AHB2ENR_AHBSRAM2EN_Msk
13952
13953/* Legacy define */
13954#define RCC_AHB2ENR_DCMIEN_Pos RCC_AHB2ENR_DCMI_PSSIEN_Pos
13955#define RCC_AHB2ENR_DCMIEN_Msk RCC_AHB2ENR_DCMI_PSSIEN_Msk
13956#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMI_PSSIEN
13957
13958/******************** Bit definition for RCC_AHB4ENR register ******************/
13959#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
13960#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
13961#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
13962#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
13963#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
13964#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
13965#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
13966#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
13967#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
13968#define RCC_AHB4ENR_GPIODEN_Pos (3U)
13969#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
13970#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
13971#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
13972#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
13973#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
13974#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
13975#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
13976#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
13977#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
13978#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
13979#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
13980#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
13981#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
13982#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
13983#define RCC_AHB4ENR_GPIOIEN_Pos (8U)
13984#define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)
13985#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
13986#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
13987#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
13988#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
13989#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
13990#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
13991#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
13992#define RCC_AHB4ENR_BDMA2EN_Pos (21U)
13993#define RCC_AHB4ENR_BDMA2EN_Msk (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)
13994#define RCC_AHB4ENR_BDMA2EN RCC_AHB4ENR_BDMA2EN_Msk
13995#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
13996#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
13997#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
13998#define RCC_AHB4ENR_SRDSRAMEN_Pos (29U)
13999#define RCC_AHB4ENR_SRDSRAMEN_Msk (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)
14000#define RCC_AHB4ENR_SRDSRAMEN RCC_AHB4ENR_SRDSRAMEN_Msk
14001
14002/******************** Bit definition for RCC_APB3ENR register ******************/
14003#define RCC_APB3ENR_LTDCEN_Pos (3U)
14004#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos)
14005#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
14006#define RCC_APB3ENR_WWDGEN_Pos (6U)
14007#define RCC_APB3ENR_WWDGEN_Msk (0x1UL << RCC_APB3ENR_WWDGEN_Pos)
14008#define RCC_APB3ENR_WWDGEN RCC_APB3ENR_WWDGEN_Msk
14009
14010/* Legacy define */
14011#define RCC_APB3ENR_WWDG1EN_Pos RCC_APB3ENR_WWDGEN_Pos
14012#define RCC_APB3ENR_WWDG1EN_Msk RCC_APB3ENR_WWDGEN_Msk
14013#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDGEN
14014/******************** Bit definition for RCC_APB1LENR register ******************/
14015
14016#define RCC_APB1LENR_TIM2EN_Pos (0U)
14017#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
14018#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
14019#define RCC_APB1LENR_TIM3EN_Pos (1U)
14020#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
14021#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
14022#define RCC_APB1LENR_TIM4EN_Pos (2U)
14023#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
14024#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
14025#define RCC_APB1LENR_TIM5EN_Pos (3U)
14026#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
14027#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
14028#define RCC_APB1LENR_TIM6EN_Pos (4U)
14029#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
14030#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
14031#define RCC_APB1LENR_TIM7EN_Pos (5U)
14032#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
14033#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
14034#define RCC_APB1LENR_TIM12EN_Pos (6U)
14035#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
14036#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
14037#define RCC_APB1LENR_TIM13EN_Pos (7U)
14038#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
14039#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
14040#define RCC_APB1LENR_TIM14EN_Pos (8U)
14041#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
14042#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
14043#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
14044#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
14045#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
14046
14047
14048#define RCC_APB1LENR_SPI2EN_Pos (14U)
14049#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
14050#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
14051#define RCC_APB1LENR_SPI3EN_Pos (15U)
14052#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
14053#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
14054#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
14055#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
14056#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
14057#define RCC_APB1LENR_USART2EN_Pos (17U)
14058#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos)
14059#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
14060#define RCC_APB1LENR_USART3EN_Pos (18U)
14061#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos)
14062#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
14063#define RCC_APB1LENR_UART4EN_Pos (19U)
14064#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos)
14065#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
14066#define RCC_APB1LENR_UART5EN_Pos (20U)
14067#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos)
14068#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
14069#define RCC_APB1LENR_I2C1EN_Pos (21U)
14070#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
14071#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
14072#define RCC_APB1LENR_I2C2EN_Pos (22U)
14073#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
14074#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
14075#define RCC_APB1LENR_I2C3EN_Pos (23U)
14076#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
14077#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
14078#define RCC_APB1LENR_CECEN_Pos (27U)
14079#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos)
14080#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
14081#define RCC_APB1LENR_DAC12EN_Pos (29U)
14082#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
14083#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
14084#define RCC_APB1LENR_UART7EN_Pos (30U)
14085#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos)
14086#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
14087#define RCC_APB1LENR_UART8EN_Pos (31U)
14088#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos)
14089#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
14090
14091/* Legacy define */
14092#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
14093#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
14094#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
14095/******************** Bit definition for RCC_APB1HENR register ******************/
14096#define RCC_APB1HENR_CRSEN_Pos (1U)
14097#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos)
14098#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
14099#define RCC_APB1HENR_SWPMIEN_Pos (2U)
14100#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
14101#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
14102#define RCC_APB1HENR_OPAMPEN_Pos (4U)
14103#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
14104#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
14105#define RCC_APB1HENR_MDIOSEN_Pos (5U)
14106#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
14107#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
14108#define RCC_APB1HENR_FDCANEN_Pos (8U)
14109#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
14110#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
14111
14112/******************** Bit definition for RCC_APB2ENR register ******************/
14113#define RCC_APB2ENR_TIM1EN_Pos (0U)
14114#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
14115#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14116#define RCC_APB2ENR_TIM8EN_Pos (1U)
14117#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
14118#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14119#define RCC_APB2ENR_USART1EN_Pos (4U)
14120#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
14121#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14122#define RCC_APB2ENR_USART6EN_Pos (5U)
14123#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
14124#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14125#define RCC_APB2ENR_UART9EN_Pos (6U)
14126#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos)
14127#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
14128#define RCC_APB2ENR_USART10EN_Pos (7U)
14129#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos)
14130#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk
14131#define RCC_APB2ENR_SPI1EN_Pos (12U)
14132#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
14133#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14134#define RCC_APB2ENR_SPI4EN_Pos (13U)
14135#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
14136#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14137#define RCC_APB2ENR_TIM15EN_Pos (16U)
14138#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
14139#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
14140#define RCC_APB2ENR_TIM16EN_Pos (17U)
14141#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
14142#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
14143#define RCC_APB2ENR_TIM17EN_Pos (18U)
14144#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
14145#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
14146#define RCC_APB2ENR_SPI5EN_Pos (20U)
14147#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
14148#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14149#define RCC_APB2ENR_SAI1EN_Pos (22U)
14150#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
14151#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14152#define RCC_APB2ENR_SAI2EN_Pos (23U)
14153#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
14154#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
14155#define RCC_APB2ENR_DFSDM1EN_Pos (30U)
14156#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
14157#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
14158
14159/******************** Bit definition for RCC_APB4ENR register ******************/
14160#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
14161#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
14162#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
14163#define RCC_APB4ENR_LPUART1EN_Pos (3U)
14164#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
14165#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
14166#define RCC_APB4ENR_SPI6EN_Pos (5U)
14167#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
14168#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
14169#define RCC_APB4ENR_I2C4EN_Pos (7U)
14170#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
14171#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
14172#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
14173#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
14174#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
14175#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
14176#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
14177#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
14178#define RCC_APB4ENR_DAC2EN_Pos (13U)
14179#define RCC_APB4ENR_DAC2EN_Msk (0x1UL << RCC_APB4ENR_DAC2EN_Pos)
14180#define RCC_APB4ENR_DAC2EN RCC_APB4ENR_DAC2EN_Msk
14181#define RCC_APB4ENR_COMP12EN_Pos (14U)
14182#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
14183#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
14184#define RCC_APB4ENR_VREFEN_Pos (15U)
14185#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos)
14186#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
14187#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
14188#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
14189#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
14190
14191#define RCC_APB4ENR_DTSEN_Pos (26U)
14192#define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos)
14193#define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk
14194#define RCC_APB4ENR_DFSDM2EN_Pos (27U)
14195#define RCC_APB4ENR_DFSDM2EN_Msk (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos)
14196#define RCC_APB4ENR_DFSDM2EN RCC_APB4ENR_DFSDM2EN_Msk
14197
14198/******************** Bit definition for RCC_AHB3RSTR register ***************/
14199#define RCC_AHB3RSTR_MDMARST_Pos (0U)
14200#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
14201#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
14202#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
14203#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
14204#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
14205#define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
14206#define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)
14207#define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
14208#define RCC_AHB3RSTR_FMCRST_Pos (12U)
14209#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
14210#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14211#define RCC_AHB3RSTR_OSPI1RST_Pos (14U)
14212#define RCC_AHB3RSTR_OSPI1RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)
14213#define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
14214#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
14215#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
14216#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
14217#define RCC_AHB3RSTR_OSPI2RST_Pos (19U)
14218#define RCC_AHB3RSTR_OSPI2RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)
14219#define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
14220#define RCC_AHB3RSTR_IOMNGRRST_Pos (21U)
14221#define RCC_AHB3RSTR_IOMNGRRST_Msk (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)
14222#define RCC_AHB3RSTR_IOMNGRRST RCC_AHB3RSTR_IOMNGRRST_Msk
14223#define RCC_AHB3RSTR_OTFDEC1RST_Pos (22U)
14224#define RCC_AHB3RSTR_OTFDEC1RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)
14225#define RCC_AHB3RSTR_OTFDEC1RST RCC_AHB3RSTR_OTFDEC1RST_Msk
14226#define RCC_AHB3RSTR_OTFDEC2RST_Pos (23U)
14227#define RCC_AHB3RSTR_OTFDEC2RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)
14228#define RCC_AHB3RSTR_OTFDEC2RST RCC_AHB3RSTR_OTFDEC2RST_Msk
14229#define RCC_AHB3RSTR_GFXMMURST_Pos (24U)
14230#define RCC_AHB3RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)
14231#define RCC_AHB3RSTR_GFXMMURST RCC_AHB3RSTR_GFXMMURST_Msk
14232
14233
14234/******************** Bit definition for RCC_AHB1RSTR register ***************/
14235#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
14236#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
14237#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14238#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
14239#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
14240#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14241#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
14242#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
14243#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
14244#define RCC_AHB1RSTR_CRCRST_Pos (9U)
14245#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
14246#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
14247#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
14248#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
14249#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
14250
14251/******************** Bit definition for RCC_AHB2RSTR register ***************/
14252#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos (0U)
14253#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)
14254#define RCC_AHB2RSTR_DCMI_PSSIRST RCC_AHB2RSTR_DCMI_PSSIRST_Msk
14255#define RCC_AHB2RSTR_HSEMRST_Pos (2U)
14256#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)
14257#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk
14258#define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14259#define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)
14260#define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14261#define RCC_AHB2RSTR_HASHRST_Pos (5U)
14262#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)
14263#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
14264#define RCC_AHB2RSTR_RNGRST_Pos (6U)
14265#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
14266#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14267#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
14268#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
14269#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
14270#define RCC_AHB2RSTR_BDMA1RST_Pos (11U)
14271#define RCC_AHB2RSTR_BDMA1RST_Msk (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)
14272#define RCC_AHB2RSTR_BDMA1RST RCC_AHB2RSTR_BDMA1RST_Msk
14273
14274/* Legacy define */
14275#define RCC_AHB2RSTR_DCMIRST_Pos RCC_AHB2RSTR_DCMI_PSSIRST_Pos
14276#define RCC_AHB2RSTR_DCMIRST_Msk RCC_AHB2RSTR_DCMI_PSSIRST_Msk
14277#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMI_PSSIRST
14278/******************** Bit definition for RCC_AHB4RSTR register ******************/
14279#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
14280#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
14281#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
14282#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
14283#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
14284#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
14285#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
14286#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
14287#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
14288#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
14289#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
14290#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
14291#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
14292#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
14293#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
14294#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
14295#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
14296#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
14297#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
14298#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
14299#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
14300#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
14301#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
14302#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
14303#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
14304#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)
14305#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
14306#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
14307#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
14308#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
14309#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
14310#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
14311#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
14312#define RCC_AHB4RSTR_BDMA2RST_Pos (21U)
14313#define RCC_AHB4RSTR_BDMA2RST_Msk (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)
14314#define RCC_AHB4RSTR_BDMA2RST RCC_AHB4RSTR_BDMA2RST_Msk
14315
14316
14317/******************** Bit definition for RCC_APB3RSTR register ******************/
14318#define RCC_APB3RSTR_LTDCRST_Pos (3U)
14319#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos)
14320#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
14321
14322/******************** Bit definition for RCC_APB1LRSTR register ******************/
14323
14324#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
14325#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
14326#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
14327#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
14328#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
14329#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
14330#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
14331#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
14332#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
14333#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
14334#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
14335#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
14336#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
14337#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
14338#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
14339#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
14340#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
14341#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
14342#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
14343#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
14344#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
14345#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
14346#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
14347#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
14348#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
14349#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
14350#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
14351#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
14352#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
14353#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
14354#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
14355#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
14356#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
14357#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
14358#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
14359#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
14360#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
14361#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
14362#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
14363#define RCC_APB1LRSTR_USART2RST_Pos (17U)
14364#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
14365#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
14366#define RCC_APB1LRSTR_USART3RST_Pos (18U)
14367#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
14368#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
14369#define RCC_APB1LRSTR_UART4RST_Pos (19U)
14370#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
14371#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
14372#define RCC_APB1LRSTR_UART5RST_Pos (20U)
14373#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
14374#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
14375#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
14376#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
14377#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
14378#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
14379#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
14380#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
14381#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
14382#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
14383#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
14384#define RCC_APB1LRSTR_CECRST_Pos (27U)
14385#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
14386#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
14387#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
14388#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
14389#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
14390#define RCC_APB1LRSTR_UART7RST_Pos (30U)
14391#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
14392#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
14393#define RCC_APB1LRSTR_UART8RST_Pos (31U)
14394#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
14395#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
14396
14397/* Legacy define */
14398#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
14399#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
14400#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
14401/******************** Bit definition for RCC_APB1HRSTR register ******************/
14402#define RCC_APB1HRSTR_CRSRST_Pos (1U)
14403#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
14404#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
14405#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
14406#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
14407#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
14408#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
14409#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
14410#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
14411#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
14412#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
14413#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
14414#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
14415#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
14416#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
14417
14418/******************** Bit definition for RCC_APB2RSTR register ******************/
14419#define RCC_APB2RSTR_TIM1RST_Pos (0U)
14420#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
14421#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
14422#define RCC_APB2RSTR_TIM8RST_Pos (1U)
14423#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
14424#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
14425#define RCC_APB2RSTR_USART1RST_Pos (4U)
14426#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
14427#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
14428#define RCC_APB2RSTR_USART6RST_Pos (5U)
14429#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
14430#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
14431#define RCC_APB2RSTR_UART9RST_Pos (6U)
14432#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos)
14433#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
14434#define RCC_APB2RSTR_USART10RST_Pos (7U)
14435#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)
14436#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk
14437#define RCC_APB2RSTR_SPI1RST_Pos (12U)
14438#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
14439#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
14440#define RCC_APB2RSTR_SPI4RST_Pos (13U)
14441#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
14442#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
14443#define RCC_APB2RSTR_TIM15RST_Pos (16U)
14444#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
14445#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
14446#define RCC_APB2RSTR_TIM16RST_Pos (17U)
14447#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
14448#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
14449#define RCC_APB2RSTR_TIM17RST_Pos (18U)
14450#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
14451#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
14452#define RCC_APB2RSTR_SPI5RST_Pos (20U)
14453#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
14454#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
14455#define RCC_APB2RSTR_SAI1RST_Pos (22U)
14456#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
14457#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
14458#define RCC_APB2RSTR_SAI2RST_Pos (23U)
14459#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
14460#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
14461#define RCC_APB2RSTR_DFSDM1RST_Pos (30U)
14462#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
14463#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
14464
14465/******************** Bit definition for RCC_APB4RSTR register ******************/
14466#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
14467#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
14468#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
14469#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
14470#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
14471#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
14472#define RCC_APB4RSTR_SPI6RST_Pos (5U)
14473#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
14474#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
14475#define RCC_APB4RSTR_I2C4RST_Pos (7U)
14476#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
14477#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
14478#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
14479#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
14480#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
14481#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
14482#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
14483#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
14484#define RCC_APB4RSTR_DAC2RST_Pos (13U)
14485#define RCC_APB4RSTR_DAC2RST_Msk (0x1UL << RCC_APB4RSTR_DAC2RST_Pos)
14486#define RCC_APB4RSTR_DAC2RST RCC_APB4RSTR_DAC2RST_Msk
14487#define RCC_APB4RSTR_COMP12RST_Pos (14U)
14488#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
14489#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
14490#define RCC_APB4RSTR_VREFRST_Pos (15U)
14491#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
14492#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
14493
14494#define RCC_APB4RSTR_DTSRST_Pos (26U)
14495#define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos)
14496#define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk
14497#define RCC_APB4RSTR_DFSDM2RST_Pos (27U)
14498#define RCC_APB4RSTR_DFSDM2RST_Msk (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos)
14499#define RCC_APB4RSTR_DFSDM2RST RCC_APB4RSTR_DFSDM2RST_Msk
14500
14501
14502/******************** Bit definition for RCC_SRDAMR register ********************/
14503#define RCC_SRDAMR_BDMA2AMEN_Pos (0U)
14504#define RCC_SRDAMR_BDMA2AMEN_Msk (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos)
14505#define RCC_SRDAMR_BDMA2AMEN RCC_SRDAMR_BDMA2AMEN_Msk
14506#define RCC_SRDAMR_GPIOAMEN_Pos (1U)
14507#define RCC_SRDAMR_GPIOAMEN_Msk (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos)
14508#define RCC_SRDAMR_GPIOAMEN RCC_SRDAMR_GPIOAMEN_Msk
14509#define RCC_SRDAMR_LPUART1AMEN_Pos (3U)
14510#define RCC_SRDAMR_LPUART1AMEN_Msk (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos)
14511#define RCC_SRDAMR_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN_Msk
14512#define RCC_SRDAMR_SPI6AMEN_Pos (5U)
14513#define RCC_SRDAMR_SPI6AMEN_Msk (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos)
14514#define RCC_SRDAMR_SPI6AMEN RCC_SRDAMR_SPI6AMEN_Msk
14515#define RCC_SRDAMR_I2C4AMEN_Pos (7U)
14516#define RCC_SRDAMR_I2C4AMEN_Msk (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos)
14517#define RCC_SRDAMR_I2C4AMEN RCC_SRDAMR_I2C4AMEN_Msk
14518#define RCC_SRDAMR_LPTIM2AMEN_Pos (9U)
14519#define RCC_SRDAMR_LPTIM2AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos)
14520#define RCC_SRDAMR_LPTIM2AMEN RCC_SRDAMR_LPTIM2AMEN_Msk
14521#define RCC_SRDAMR_LPTIM3AMEN_Pos (10U)
14522#define RCC_SRDAMR_LPTIM3AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos)
14523#define RCC_SRDAMR_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN_Msk
14524#define RCC_SRDAMR_DAC2AMEN_Pos (13U)
14525#define RCC_SRDAMR_DAC2AMEN_Msk (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos)
14526#define RCC_SRDAMR_DAC2AMEN RCC_SRDAMR_DAC2AMEN_Msk
14527#define RCC_SRDAMR_COMP12AMEN_Pos (14U)
14528#define RCC_SRDAMR_COMP12AMEN_Msk (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos)
14529#define RCC_SRDAMR_COMP12AMEN RCC_SRDAMR_COMP12AMEN_Msk
14530#define RCC_SRDAMR_VREFAMEN_Pos (15U)
14531#define RCC_SRDAMR_VREFAMEN_Msk (0x1UL << RCC_SRDAMR_VREFAMEN_Pos)
14532#define RCC_SRDAMR_VREFAMEN RCC_SRDAMR_VREFAMEN_Msk
14533#define RCC_SRDAMR_RTCAMEN_Pos (16U)
14534#define RCC_SRDAMR_RTCAMEN_Msk (0x1UL << RCC_SRDAMR_RTCAMEN_Pos)
14535#define RCC_SRDAMR_RTCAMEN RCC_SRDAMR_RTCAMEN_Msk
14536#define RCC_SRDAMR_DTSAMEN_Pos (26U)
14537#define RCC_SRDAMR_DTSAMEN_Msk (0x1UL << RCC_SRDAMR_DTSAMEN_Pos)
14538#define RCC_SRDAMR_DTSAMEN RCC_SRDAMR_DTSAMEN_Msk
14539#define RCC_SRDAMR_DFSDM2AMEN_Pos (27U)
14540#define RCC_SRDAMR_DFSDM2AMEN_Msk (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos)
14541#define RCC_SRDAMR_DFSDM2AMEN RCC_SRDAMR_DFSDM2AMEN_Msk
14542#define RCC_SRDAMR_BKPRAMAMEN_Pos (28U)
14543#define RCC_SRDAMR_BKPRAMAMEN_Msk (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos)
14544#define RCC_SRDAMR_BKPRAMAMEN RCC_SRDAMR_BKPRAMAMEN_Msk
14545#define RCC_SRDAMR_SRDSRAMAMEN_Pos (29U)
14546#define RCC_SRDAMR_SRDSRAMAMEN_Msk (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos)
14547#define RCC_SRDAMR_SRDSRAMAMEN RCC_SRDAMR_SRDSRAMAMEN_Msk
14548/******************** Bit definition for RCC_CKGAENR register ********************/
14549#define RCC_CKGAENR_AXICKG_Pos (0U)
14550#define RCC_CKGAENR_AXICKG_Msk (0x1UL << RCC_CKGAENR_AXICKG_Pos)
14551#define RCC_CKGAENR_AXICKG RCC_CKGAENR_AXICKG_Msk
14552#define RCC_CKGAENR_AHBCKG_Pos (1U)
14553#define RCC_CKGAENR_AHBCKG_Msk (0x1UL << RCC_CKGAENR_AHBCKG_Pos)
14554#define RCC_CKGAENR_AHBCKG RCC_CKGAENR_AHBCKG_Msk
14555#define RCC_CKGAENR_CPUCKG_Pos (2U)
14556#define RCC_CKGAENR_CPUCKG_Msk (0x1UL << RCC_CKGAENR_CPUCKG_Pos)
14557#define RCC_CKGAENR_CPUCKG RCC_CKGAENR_CPUCKG_Msk
14558#define RCC_CKGAENR_SDMMCCKG_Pos (3U)
14559#define RCC_CKGAENR_SDMMCCKG_Msk (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos)
14560#define RCC_CKGAENR_SDMMCCKG RCC_CKGAENR_SDMMCCKG_Msk
14561#define RCC_CKGAENR_MDMACKG_Pos (4U)
14562#define RCC_CKGAENR_MDMACKG_Msk (0x1UL << RCC_CKGAENR_MDMACKG_Pos)
14563#define RCC_CKGAENR_MDMACKG RCC_CKGAENR_MDMACKG_Msk
14564#define RCC_CKGAENR_DMA2DCKG_Pos (5U)
14565#define RCC_CKGAENR_DMA2DCKG_Msk (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos)
14566#define RCC_CKGAENR_DMA2DCKG RCC_CKGAENR_DMA2DCKG_Msk
14567#define RCC_CKGAENR_LTDCCKG_Pos (6U)
14568#define RCC_CKGAENR_LTDCCKG_Msk (0x1UL << RCC_CKGAENR_LTDCCKG_Pos)
14569#define RCC_CKGAENR_LTDCCKG RCC_CKGAENR_LTDCCKG_Msk
14570#define RCC_CKGAENR_GFXMMUMCKG_Pos (7U)
14571#define RCC_CKGAENR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos)
14572#define RCC_CKGAENR_GFXMMUMCKG RCC_CKGAENR_GFXMMUMCKG_Msk
14573#define RCC_CKGAENR_AHB12CKG_Pos (8U)
14574#define RCC_CKGAENR_AHB12CKG_Msk (0x1UL << RCC_CKGAENR_AHB12CKG_Pos)
14575#define RCC_CKGAENR_AHB12CKG RCC_CKGAENR_AHB12CKG_Msk
14576#define RCC_CKGAENR_AHB34CKG_Pos (9U)
14577#define RCC_CKGAENR_AHB34CKG_Msk (0x1UL << RCC_CKGAENR_AHB34CKG_Pos)
14578#define RCC_CKGAENR_AHB34CKG RCC_CKGAENR_AHB34CKG_Msk
14579#define RCC_CKGAENR_FLIFTCKG_Pos (10U)
14580#define RCC_CKGAENR_FLIFTCKG_Msk (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos)
14581#define RCC_CKGAENR_FLIFTCKG RCC_CKGAENR_FLIFTCKG_Msk
14582#define RCC_CKGAENR_OCTOSPI2CKG_Pos (11U)
14583#define RCC_CKGAENR_OCTOSPI2CKG_Msk (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos)
14584#define RCC_CKGAENR_OCTOSPI2CKG RCC_CKGAENR_OCTOSPI2CKG_Msk
14585#define RCC_CKGAENR_FMCCKG_Pos (12U)
14586#define RCC_CKGAENR_FMCCKG_Msk (0x1UL << RCC_CKGAENR_FMCCKG_Pos)
14587#define RCC_CKGAENR_FMCCKG RCC_CKGAENR_FMCCKG_Msk
14588#define RCC_CKGAENR_OCTOSPI1CKG_Pos (13U)
14589#define RCC_CKGAENR_OCTOSPI1CKG_Msk (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos)
14590#define RCC_CKGAENR_OCTOSPI1CKG RCC_CKGAENR_OCTOSPI1CKG_Msk
14591#define RCC_CKGAENR_AXIRAM1CKG_Pos (14U)
14592#define RCC_CKGAENR_AXIRAM1CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos)
14593#define RCC_CKGAENR_AXIRAM1CKG RCC_CKGAENR_AXIRAM1CKG_Msk
14594#define RCC_CKGAENR_AXIRAM2CKG_Pos (15U)
14595#define RCC_CKGAENR_AXIRAM2CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos)
14596#define RCC_CKGAENR_AXIRAM2CKG RCC_CKGAENR_AXIRAM2CKG_Msk
14597#define RCC_CKGAENR_AXIRAM3CKG_Pos (16U)
14598#define RCC_CKGAENR_AXIRAM3CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos)
14599#define RCC_CKGAENR_AXIRAM3CKG RCC_CKGAENR_AXIRAM3CKG_Msk
14600#define RCC_CKGAENR_GFXMMUSCKG_Pos (17U)
14601#define RCC_CKGAENR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos)
14602#define RCC_CKGAENR_GFXMMUSCKG RCC_CKGAENR_GFXMMUSCKG_Msk
14603#define RCC_CKGAENR_ECCRAMCKG_Pos (29U)
14604#define RCC_CKGAENR_ECCRAMCKG_Msk (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos)
14605#define RCC_CKGAENR_ECCRAMCKG RCC_CKGAENR_ECCRAMCKG_Msk
14606#define RCC_CKGAENR_EXTICKG_Pos (30U)
14607#define RCC_CKGAENR_EXTICKG_Msk (0x1UL << RCC_CKGAENR_EXTICKG_Pos)
14608#define RCC_CKGAENR_EXTICKG RCC_CKGAENR_EXTICKG_Msk
14609#define RCC_CKGAENR_JTAGCKG_Pos (31U)
14610#define RCC_CKGAENR_JTAGCKG_Msk (0x1UL << RCC_CKGAENR_JTAGCKG_Pos)
14611#define RCC_CKGAENR_JTAGCKG RCC_CKGAENR_JTAGCKG_Msk
14612/******************** Bit definition for RCC_AHB3LPENR register **************/
14613#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
14614#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
14615#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
14616#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
14617#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
14618#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
14619#define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
14620#define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)
14621#define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
14622#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
14623#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
14624#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
14625#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
14626#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
14627#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14628#define RCC_AHB3LPENR_OSPI1LPEN_Pos (14U)
14629#define RCC_AHB3LPENR_OSPI1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)
14630#define RCC_AHB3LPENR_OSPI1LPEN RCC_AHB3LPENR_OSPI1LPEN_Msk
14631#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
14632#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
14633#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
14634#define RCC_AHB3LPENR_OSPI2LPEN_Pos (19U)
14635#define RCC_AHB3LPENR_OSPI2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)
14636#define RCC_AHB3LPENR_OSPI2LPEN RCC_AHB3LPENR_OSPI2LPEN_Msk
14637#define RCC_AHB3LPENR_IOMNGRLPEN_Pos (21U)
14638#define RCC_AHB3LPENR_IOMNGRLPEN_Msk (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)
14639#define RCC_AHB3LPENR_IOMNGRLPEN RCC_AHB3LPENR_IOMNGRLPEN_Msk
14640#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos (22U)
14641#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)
14642#define RCC_AHB3LPENR_OTFDEC1LPEN RCC_AHB3LPENR_OTFDEC1LPEN_Msk
14643#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos (23U)
14644#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)
14645#define RCC_AHB3LPENR_OTFDEC2LPEN RCC_AHB3LPENR_OTFDEC2LPEN_Msk
14646#define RCC_AHB3LPENR_GFXMMULPEN_Pos (24U)
14647#define RCC_AHB3LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)
14648#define RCC_AHB3LPENR_GFXMMULPEN RCC_AHB3LPENR_GFXMMULPEN_Msk
14649#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos (26U)
14650#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)
14651#define RCC_AHB3LPENR_AXISRAM2LPEN RCC_AHB3LPENR_AXISRAM2LPEN_Msk
14652#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos (27U)
14653#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)
14654#define RCC_AHB3LPENR_AXISRAM3LPEN RCC_AHB3LPENR_AXISRAM3LPEN_Msk
14655#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
14656#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
14657#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
14658#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
14659#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
14660#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
14661#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
14662#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
14663#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
14664#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos (31U)
14665#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)
14666#define RCC_AHB3LPENR_AXISRAM1LPEN RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14667
14668
14669/* Legacy define */
14670#define RCC_AHB3LPENR_AXISRAMLPEN_Pos RCC_AHB3LPENR_AXISRAM1LPEN_Pos
14671#define RCC_AHB3LPENR_AXISRAMLPEN_Msk RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14672#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAM1LPEN
14673/******************** Bit definition for RCC_AHB1LPENR register ***************/
14674#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
14675#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
14676#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14677#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
14678#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
14679#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14680#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
14681#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
14682#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
14683#define RCC_AHB1LPENR_CRCLPEN_Pos (9U)
14684#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
14685#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14686#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
14687#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
14688#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
14689#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
14690#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
14691#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
14692
14693/******************** Bit definition for RCC_AHB2LPENR register ***************/
14694#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
14695#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos)
14696#define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14697#define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
14698#define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos)
14699#define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
14700#define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
14701#define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos)
14702#define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
14703#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14704#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
14705#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14706#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
14707#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
14708#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
14709#define RCC_AHB2LPENR_BDMA1LPEN_Pos (11U)
14710#define RCC_AHB2LPENR_BDMA1LPEN_Msk (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)
14711#define RCC_AHB2LPENR_BDMA1LPEN RCC_AHB2LPENR_BDMA1LPEN_Msk
14712#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos (29U)
14713#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos)
14714#define RCC_AHB2LPENR_AHBSRAM1LPEN RCC_AHB2LPENR_AHBSRAM1LPEN_Msk
14715#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos (30U)
14716#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos)
14717#define RCC_AHB2LPENR_AHBSRAM2LPEN RCC_AHB2LPENR_AHBSRAM2LPEN_Msk
14718
14719/* Legacy define */
14720#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos RCC_AHB2LPENR_BDMA1LPEN_Pos
14721#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk RCC_AHB2LPENR_BDMA1LPEN_Msk
14722#define RCC_AHB2LPENR_DFSDMDMALPEN RCC_AHB2LPENR_BDMA1LPEN
14723#define RCC_AHB2LPENR_DCMILPEN_Pos RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
14724#define RCC_AHB2LPENR_DCMILPEN_Msk RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14725#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMI_PSSILPEN
14726
14727/******************** Bit definition for RCC_AHB4LPENR register ******************/
14728#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
14729#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
14730#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
14731#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
14732#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
14733#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
14734#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
14735#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
14736#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
14737#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
14738#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
14739#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
14740#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
14741#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
14742#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
14743#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
14744#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
14745#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
14746#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
14747#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
14748#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
14749#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
14750#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
14751#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
14752#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
14753#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos)
14754#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
14755#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
14756#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
14757#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
14758#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
14759#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
14760#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
14761#define RCC_AHB4LPENR_BDMA2LPEN_Pos (21U)
14762#define RCC_AHB4LPENR_BDMA2LPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos)
14763#define RCC_AHB4LPENR_BDMA2LPEN RCC_AHB4LPENR_BDMA2LPEN_Msk
14764#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
14765#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
14766#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
14767#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos (29U)
14768#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos)
14769#define RCC_AHB4LPENR_SRDSRAMLPEN RCC_AHB4LPENR_SRDSRAMLPEN_Msk
14770
14771/******************** Bit definition for RCC_APB3LPENR register ******************/
14772#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
14773#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos)
14774#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
14775#define RCC_APB3LPENR_WWDGLPEN_Pos (6U)
14776#define RCC_APB3LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)
14777#define RCC_APB3LPENR_WWDGLPEN RCC_APB3LPENR_WWDGLPEN_Msk
14778
14779/* Legacy define */
14780#define RCC_APB3LPENR_WWDG1LPEN_Pos RCC_APB3LPENR_WWDGLPEN_Pos
14781#define RCC_APB3LPENR_WWDG1LPEN_Msk RCC_APB3LPENR_WWDGLPEN_Msk
14782#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDGLPEN
14783/******************** Bit definition for RCC_APB1LLPENR register ******************/
14784
14785#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
14786#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
14787#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
14788#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
14789#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
14790#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
14791#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
14792#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
14793#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
14794#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
14795#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
14796#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
14797#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
14798#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
14799#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
14800#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
14801#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
14802#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
14803#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
14804#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
14805#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
14806#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
14807#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
14808#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
14809#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
14810#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
14811#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
14812#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
14813#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
14814#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
14815
14816
14817#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
14818#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
14819#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
14820#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
14821#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
14822#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
14823#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
14824#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
14825#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
14826#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
14827#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
14828#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
14829#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
14830#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
14831#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
14832#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
14833#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
14834#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
14835#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
14836#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
14837#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
14838#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
14839#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
14840#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
14841#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
14842#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
14843#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
14844#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
14845#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
14846#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
14847#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
14848#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
14849#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
14850#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
14851#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
14852#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
14853#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
14854#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
14855#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
14856#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
14857#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
14858#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
14859
14860/* Legacy define */
14861#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
14862#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
14863#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
14864/******************** Bit definition for RCC_APB1HLPENR register ******************/
14865#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
14866#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
14867#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
14868#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
14869#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
14870#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
14871#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
14872#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
14873#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
14874#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
14875#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
14876#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
14877#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
14878#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
14879#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
14880
14881/******************** Bit definition for RCC_APB2LPENR register ******************/
14882#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14883#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
14884#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14885#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14886#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
14887#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14888#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14889#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
14890#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14891#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14892#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
14893#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14894#define RCC_APB2LPENR_UART9LPEN_Pos (6U)
14895#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)
14896#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
14897#define RCC_APB2LPENR_USART10LPEN_Pos (7U)
14898#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos)
14899#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk
14900#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14901#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
14902#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14903#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14904#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
14905#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14906#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
14907#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
14908#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
14909#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
14910#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
14911#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
14912#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
14913#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
14914#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
14915#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14916#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
14917#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14918#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14919#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
14920#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14921#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
14922#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
14923#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
14924#define RCC_APB2LPENR_DFSDM1LPEN_Pos (30U)
14925#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
14926#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
14927
14928/******************** Bit definition for RCC_APB4LPENR register ******************/
14929#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
14930#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
14931#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
14932#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
14933#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
14934#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
14935#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
14936#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
14937#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
14938#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
14939#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
14940#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
14941#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
14942#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
14943#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
14944#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
14945#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
14946#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
14947#define RCC_APB4LPENR_DAC2LPEN_Pos (13U)
14948#define RCC_APB4LPENR_DAC2LPEN_Msk (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos)
14949#define RCC_APB4LPENR_DAC2LPEN RCC_APB4LPENR_DAC2LPEN_Msk
14950#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
14951#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
14952#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
14953#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
14954#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
14955#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
14956#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
14957#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
14958#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
14959
14960#define RCC_APB4LPENR_DTSLPEN_Pos (26U)
14961#define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos)
14962#define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk
14963#define RCC_APB4LPENR_DFSDM2LPEN_Pos (27U)
14964#define RCC_APB4LPENR_DFSDM2LPEN_Msk (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos)
14965#define RCC_APB4LPENR_DFSDM2LPEN RCC_APB4LPENR_DFSDM2LPEN_Msk
14966
14967/******************** Bit definition for RCC_RSR register *******************/
14968#define RCC_RSR_RMVF_Pos (16U)
14969#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos)
14970#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
14971#define RCC_RSR_CDRSTF_Pos (19U)
14972#define RCC_RSR_CDRSTF_Msk (0x1UL << RCC_RSR_CDRSTF_Pos)
14973#define RCC_RSR_CDRSTF RCC_RSR_CDRSTF_Msk
14974#define RCC_RSR_BORRSTF_Pos (21U)
14975#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos)
14976#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
14977#define RCC_RSR_PINRSTF_Pos (22U)
14978#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos)
14979#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
14980#define RCC_RSR_PORRSTF_Pos (23U)
14981#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos)
14982#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
14983#define RCC_RSR_SFTRSTF_Pos (24U)
14984#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos)
14985#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
14986#define RCC_RSR_IWDGRSTF_Pos (26U)
14987#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos)
14988#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk
14989#define RCC_RSR_WWDGRSTF_Pos (28U)
14990#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos)
14991#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk
14992
14993#define RCC_RSR_LPWRRSTF_Pos (30U)
14994#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos)
14995#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
14996
14997
14998/* Legacy define */
14999#define RCC_RSR_IWDG1RSTF_Pos RCC_RSR_IWDGRSTF_Pos
15000#define RCC_RSR_IWDG1RSTF_Msk RCC_RSR_IWDGRSTF_Msk
15001#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDGRSTF
15002#define RCC_RSR_WWDG1RSTF_Pos RCC_RSR_WWDGRSTF_Pos
15003#define RCC_RSR_WWDG1RSTF_Msk RCC_RSR_WWDGRSTF_Msk
15004#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDGRSTF
15005/******************************************************************************/
15006/* */
15007/* RNG */
15008/* */
15009/******************************************************************************/
15010/*************************** RNG VER **************************************/
15011#define RNG_VER_3_1
15012/******************** Bits definition for RNG_CR register *******************/
15013#define RNG_CR_RNGEN_Pos (2U)
15014#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
15015#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
15016#define RNG_CR_IE_Pos (3U)
15017#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
15018#define RNG_CR_IE RNG_CR_IE_Msk
15019#define RNG_CR_CED_Pos (5U)
15020#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)
15021#define RNG_CR_CED RNG_CR_CED_Msk
15022#define RNG_CR_RNG_CONFIG3_Pos (8U)
15023#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
15024#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
15025#define RNG_CR_NISTC_Pos (12U)
15026#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
15027#define RNG_CR_NISTC RNG_CR_NISTC_Msk
15028#define RNG_CR_RNG_CONFIG2_Pos (13U)
15029#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
15030#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
15031#define RNG_CR_CLKDIV_Pos (16U)
15032#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
15033#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
15034#define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos)
15035#define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos)
15036#define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos)
15037#define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos)
15038#define RNG_CR_RNG_CONFIG1_Pos (20U)
15039#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
15040#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
15041#define RNG_CR_CONDRST_Pos (30U)
15042#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
15043#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
15044#define RNG_CR_CONFIGLOCK_Pos (31U)
15045#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
15046#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
15047
15048/******************** Bits definition for RNG_SR register *******************/
15049#define RNG_SR_DRDY_Pos (0U)
15050#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
15051#define RNG_SR_DRDY RNG_SR_DRDY_Msk
15052#define RNG_SR_CECS_Pos (1U)
15053#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
15054#define RNG_SR_CECS RNG_SR_CECS_Msk
15055#define RNG_SR_SECS_Pos (2U)
15056#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
15057#define RNG_SR_SECS RNG_SR_SECS_Msk
15058#define RNG_SR_CEIS_Pos (5U)
15059#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
15060#define RNG_SR_CEIS RNG_SR_CEIS_Msk
15061#define RNG_SR_SEIS_Pos (6U)
15062#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
15063#define RNG_SR_SEIS RNG_SR_SEIS_Msk
15064
15065/******************************************************************************/
15066/* */
15067/* Real-Time Clock (RTC) */
15068/* */
15069/******************************************************************************/
15070/******************** Bits definition for RTC_TR register *******************/
15071#define RTC_TR_PM_Pos (22U)
15072#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
15073#define RTC_TR_PM RTC_TR_PM_Msk
15074#define RTC_TR_HT_Pos (20U)
15075#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
15076#define RTC_TR_HT RTC_TR_HT_Msk
15077#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
15078#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
15079#define RTC_TR_HU_Pos (16U)
15080#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
15081#define RTC_TR_HU RTC_TR_HU_Msk
15082#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
15083#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
15084#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
15085#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
15086#define RTC_TR_MNT_Pos (12U)
15087#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
15088#define RTC_TR_MNT RTC_TR_MNT_Msk
15089#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
15090#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
15091#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
15092#define RTC_TR_MNU_Pos (8U)
15093#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
15094#define RTC_TR_MNU RTC_TR_MNU_Msk
15095#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
15096#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
15097#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
15098#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
15099#define RTC_TR_ST_Pos (4U)
15100#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
15101#define RTC_TR_ST RTC_TR_ST_Msk
15102#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
15103#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
15104#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
15105#define RTC_TR_SU_Pos (0U)
15106#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
15107#define RTC_TR_SU RTC_TR_SU_Msk
15108#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
15109#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
15110#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
15111#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
15113/******************** Bits definition for RTC_DR register *******************/
15114#define RTC_DR_YT_Pos (20U)
15115#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
15116#define RTC_DR_YT RTC_DR_YT_Msk
15117#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
15118#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
15119#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
15120#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
15121#define RTC_DR_YU_Pos (16U)
15122#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
15123#define RTC_DR_YU RTC_DR_YU_Msk
15124#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
15125#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
15126#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
15127#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
15128#define RTC_DR_WDU_Pos (13U)
15129#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
15130#define RTC_DR_WDU RTC_DR_WDU_Msk
15131#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
15132#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
15133#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
15134#define RTC_DR_MT_Pos (12U)
15135#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
15136#define RTC_DR_MT RTC_DR_MT_Msk
15137#define RTC_DR_MU_Pos (8U)
15138#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
15139#define RTC_DR_MU RTC_DR_MU_Msk
15140#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
15141#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
15142#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
15143#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
15144#define RTC_DR_DT_Pos (4U)
15145#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
15146#define RTC_DR_DT RTC_DR_DT_Msk
15147#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
15148#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
15149#define RTC_DR_DU_Pos (0U)
15150#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
15151#define RTC_DR_DU RTC_DR_DU_Msk
15152#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
15153#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
15154#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
15155#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
15157/******************** Bits definition for RTC_CR register *******************/
15158#define RTC_CR_OUT2EN_Pos (31U)
15159#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos)
15160#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk
15161#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
15162#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)
15163#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk
15164#define RTC_CR_TAMPALRM_PU_Pos (29U)
15165#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos)
15166#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk
15167#define RTC_CR_TAMPOE_Pos (26U)
15168#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos)
15169#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk
15170#define RTC_CR_TAMPTS_Pos (25U)
15171#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos)
15172#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk
15173#define RTC_CR_ITSE_Pos (24U)
15174#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
15175#define RTC_CR_ITSE RTC_CR_ITSE_Msk
15176#define RTC_CR_COE_Pos (23U)
15177#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
15178#define RTC_CR_COE RTC_CR_COE_Msk
15179#define RTC_CR_OSEL_Pos (21U)
15180#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
15181#define RTC_CR_OSEL RTC_CR_OSEL_Msk
15182#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
15183#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
15184#define RTC_CR_POL_Pos (20U)
15185#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
15186#define RTC_CR_POL RTC_CR_POL_Msk
15187#define RTC_CR_COSEL_Pos (19U)
15188#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
15189#define RTC_CR_COSEL RTC_CR_COSEL_Msk
15190#define RTC_CR_BKP_Pos (18U)
15191#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
15192#define RTC_CR_BKP RTC_CR_BKP_Msk
15193#define RTC_CR_SUB1H_Pos (17U)
15194#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
15195#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15196#define RTC_CR_ADD1H_Pos (16U)
15197#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
15198#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15199#define RTC_CR_TSIE_Pos (15U)
15200#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
15201#define RTC_CR_TSIE RTC_CR_TSIE_Msk
15202#define RTC_CR_WUTIE_Pos (14U)
15203#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
15204#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15205#define RTC_CR_ALRBIE_Pos (13U)
15206#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
15207#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15208#define RTC_CR_ALRAIE_Pos (12U)
15209#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
15210#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15211#define RTC_CR_TSE_Pos (11U)
15212#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
15213#define RTC_CR_TSE RTC_CR_TSE_Msk
15214#define RTC_CR_WUTE_Pos (10U)
15215#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
15216#define RTC_CR_WUTE RTC_CR_WUTE_Msk
15217#define RTC_CR_ALRBE_Pos (9U)
15218#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
15219#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15220#define RTC_CR_ALRAE_Pos (8U)
15221#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
15222#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15223#define RTC_CR_FMT_Pos (6U)
15224#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
15225#define RTC_CR_FMT RTC_CR_FMT_Msk
15226#define RTC_CR_BYPSHAD_Pos (5U)
15227#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
15228#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15229#define RTC_CR_REFCKON_Pos (4U)
15230#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
15231#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15232#define RTC_CR_TSEDGE_Pos (3U)
15233#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
15234#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15235#define RTC_CR_WUCKSEL_Pos (0U)
15236#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
15237#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15238#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
15239#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
15240#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
15242/******************** Bits definition for RTC_ICSR register ******************/
15243#define RTC_ICSR_RECALPF_Pos (16U)
15244#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos)
15245#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
15246#define RTC_ICSR_INIT_Pos (7U)
15247#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos)
15248#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
15249#define RTC_ICSR_INITF_Pos (6U)
15250#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos)
15251#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
15252#define RTC_ICSR_RSF_Pos (5U)
15253#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos)
15254#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
15255#define RTC_ICSR_INITS_Pos (4U)
15256#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos)
15257#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
15258#define RTC_ICSR_SHPF_Pos (3U)
15259#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos)
15260#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
15261#define RTC_ICSR_WUTWF_Pos (2U)
15262#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos)
15263#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
15264#define RTC_ICSR_ALRBWF_Pos (1U)
15265#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos)
15266#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
15267#define RTC_ICSR_ALRAWF_Pos (0U)
15268#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos)
15269#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
15270
15271/******************** Bits definition for RTC_PRER register *****************/
15272#define RTC_PRER_PREDIV_A_Pos (16U)
15273#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
15274#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15275#define RTC_PRER_PREDIV_S_Pos (0U)
15276#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
15277#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15278
15279/******************** Bits definition for RTC_WUTR register *****************/
15280#define RTC_WUTR_WUT_Pos (0U)
15281#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
15282#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15283
15284/******************** Bits definition for RTC_ALRMAR register ***************/
15285#define RTC_ALRMAR_MSK4_Pos (31U)
15286#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
15287#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15288#define RTC_ALRMAR_WDSEL_Pos (30U)
15289#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
15290#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15291#define RTC_ALRMAR_DT_Pos (28U)
15292#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
15293#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15294#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
15295#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
15296#define RTC_ALRMAR_DU_Pos (24U)
15297#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
15298#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15299#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
15300#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
15301#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
15302#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
15303#define RTC_ALRMAR_MSK3_Pos (23U)
15304#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
15305#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15306#define RTC_ALRMAR_PM_Pos (22U)
15307#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
15308#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15309#define RTC_ALRMAR_HT_Pos (20U)
15310#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
15311#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15312#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
15313#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
15314#define RTC_ALRMAR_HU_Pos (16U)
15315#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
15316#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15317#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
15318#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
15319#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
15320#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
15321#define RTC_ALRMAR_MSK2_Pos (15U)
15322#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
15323#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15324#define RTC_ALRMAR_MNT_Pos (12U)
15325#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
15326#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15327#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
15328#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
15329#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
15330#define RTC_ALRMAR_MNU_Pos (8U)
15331#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
15332#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15333#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
15334#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
15335#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
15336#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
15337#define RTC_ALRMAR_MSK1_Pos (7U)
15338#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
15339#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15340#define RTC_ALRMAR_ST_Pos (4U)
15341#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
15342#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15343#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
15344#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
15345#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
15346#define RTC_ALRMAR_SU_Pos (0U)
15347#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
15348#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15349#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
15350#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
15351#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
15352#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
15354/******************** Bits definition for RTC_ALRMBR register ***************/
15355#define RTC_ALRMBR_MSK4_Pos (31U)
15356#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
15357#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15358#define RTC_ALRMBR_WDSEL_Pos (30U)
15359#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
15360#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15361#define RTC_ALRMBR_DT_Pos (28U)
15362#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
15363#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15364#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
15365#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
15366#define RTC_ALRMBR_DU_Pos (24U)
15367#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
15368#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15369#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
15370#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
15371#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
15372#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
15373#define RTC_ALRMBR_MSK3_Pos (23U)
15374#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
15375#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15376#define RTC_ALRMBR_PM_Pos (22U)
15377#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
15378#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15379#define RTC_ALRMBR_HT_Pos (20U)
15380#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
15381#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15382#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
15383#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
15384#define RTC_ALRMBR_HU_Pos (16U)
15385#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
15386#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15387#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
15388#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
15389#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
15390#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
15391#define RTC_ALRMBR_MSK2_Pos (15U)
15392#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
15393#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15394#define RTC_ALRMBR_MNT_Pos (12U)
15395#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
15396#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15397#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
15398#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
15399#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
15400#define RTC_ALRMBR_MNU_Pos (8U)
15401#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
15402#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15403#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
15404#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
15405#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
15406#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
15407#define RTC_ALRMBR_MSK1_Pos (7U)
15408#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
15409#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15410#define RTC_ALRMBR_ST_Pos (4U)
15411#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
15412#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15413#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
15414#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
15415#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
15416#define RTC_ALRMBR_SU_Pos (0U)
15417#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
15418#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15419#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
15420#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
15421#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
15422#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
15424/******************** Bits definition for RTC_WPR register ******************/
15425#define RTC_WPR_KEY_Pos (0U)
15426#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
15427#define RTC_WPR_KEY RTC_WPR_KEY_Msk
15428
15429/******************** Bits definition for RTC_SSR register ******************/
15430#define RTC_SSR_SS_Pos (0U)
15431#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
15432#define RTC_SSR_SS RTC_SSR_SS_Msk
15433
15434/******************** Bits definition for RTC_SHIFTR register ***************/
15435#define RTC_SHIFTR_SUBFS_Pos (0U)
15436#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
15437#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15438#define RTC_SHIFTR_ADD1S_Pos (31U)
15439#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
15440#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15441
15442/******************** Bits definition for RTC_TSTR register *****************/
15443#define RTC_TSTR_PM_Pos (22U)
15444#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
15445#define RTC_TSTR_PM RTC_TSTR_PM_Msk
15446#define RTC_TSTR_HT_Pos (20U)
15447#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
15448#define RTC_TSTR_HT RTC_TSTR_HT_Msk
15449#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
15450#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
15451#define RTC_TSTR_HU_Pos (16U)
15452#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
15453#define RTC_TSTR_HU RTC_TSTR_HU_Msk
15454#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
15455#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
15456#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
15457#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
15458#define RTC_TSTR_MNT_Pos (12U)
15459#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
15460#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15461#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
15462#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
15463#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
15464#define RTC_TSTR_MNU_Pos (8U)
15465#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
15466#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15467#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
15468#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
15469#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
15470#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
15471#define RTC_TSTR_ST_Pos (4U)
15472#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
15473#define RTC_TSTR_ST RTC_TSTR_ST_Msk
15474#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
15475#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
15476#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
15477#define RTC_TSTR_SU_Pos (0U)
15478#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
15479#define RTC_TSTR_SU RTC_TSTR_SU_Msk
15480#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
15481#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
15482#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
15483#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
15485/******************** Bits definition for RTC_TSDR register *****************/
15486#define RTC_TSDR_WDU_Pos (13U)
15487#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
15488#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15489#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
15490#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
15491#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
15492#define RTC_TSDR_MT_Pos (12U)
15493#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
15494#define RTC_TSDR_MT RTC_TSDR_MT_Msk
15495#define RTC_TSDR_MU_Pos (8U)
15496#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
15497#define RTC_TSDR_MU RTC_TSDR_MU_Msk
15498#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
15499#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
15500#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
15501#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
15502#define RTC_TSDR_DT_Pos (4U)
15503#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
15504#define RTC_TSDR_DT RTC_TSDR_DT_Msk
15505#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
15506#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
15507#define RTC_TSDR_DU_Pos (0U)
15508#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
15509#define RTC_TSDR_DU RTC_TSDR_DU_Msk
15510#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
15511#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
15512#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
15513#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
15515/******************** Bits definition for RTC_TSSSR register ****************/
15516#define RTC_TSSSR_SS_Pos (0U)
15517#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
15518#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15519
15520/******************** Bits definition for RTC_CALR register *****************/
15521#define RTC_CALR_CALP_Pos (15U)
15522#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
15523#define RTC_CALR_CALP RTC_CALR_CALP_Msk
15524#define RTC_CALR_CALW8_Pos (14U)
15525#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
15526#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15527#define RTC_CALR_CALW16_Pos (13U)
15528#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
15529#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15530#define RTC_CALR_CALM_Pos (0U)
15531#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
15532#define RTC_CALR_CALM RTC_CALR_CALM_Msk
15533#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
15534#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
15535#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
15536#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
15537#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
15538#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
15539#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
15540#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
15541#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
15544/******************** Bits definition for RTC_ALRMASSR register *************/
15545#define RTC_ALRMASSR_MASKSS_Pos (24U)
15546#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
15547#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15548#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
15549#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
15550#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
15551#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
15552#define RTC_ALRMASSR_SS_Pos (0U)
15553#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
15554#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15555
15556/******************** Bits definition for RTC_ALRMBSSR register *************/
15557#define RTC_ALRMBSSR_MASKSS_Pos (24U)
15558#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
15559#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15560#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
15561#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
15562#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
15563#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
15564#define RTC_ALRMBSSR_SS_Pos (0U)
15565#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
15566#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15567
15568
15569/******************** Bits definition for RTC_SR register *******************/
15570#define RTC_SR_ITSF_Pos (5U)
15571#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos)
15572#define RTC_SR_ITSF RTC_SR_ITSF_Msk
15573#define RTC_SR_TSOVF_Pos (4U)
15574#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos)
15575#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
15576#define RTC_SR_TSF_Pos (3U)
15577#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos)
15578#define RTC_SR_TSF RTC_SR_TSF_Msk
15579#define RTC_SR_WUTF_Pos (2U)
15580#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos)
15581#define RTC_SR_WUTF RTC_SR_WUTF_Msk
15582#define RTC_SR_ALRBF_Pos (1U)
15583#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos)
15584#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
15585#define RTC_SR_ALRAF_Pos (0U)
15586#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos)
15587#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
15588
15589/******************** Bits definition for RTC_MISR register *****************/
15590#define RTC_MISR_ITSMF_Pos (5U)
15591#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos)
15592#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
15593#define RTC_MISR_TSOVMF_Pos (4U)
15594#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos)
15595#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
15596#define RTC_MISR_TSMF_Pos (3U)
15597#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos)
15598#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
15599#define RTC_MISR_WUTMF_Pos (2U)
15600#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos)
15601#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
15602#define RTC_MISR_ALRBMF_Pos (1U)
15603#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos)
15604#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
15605#define RTC_MISR_ALRAMF_Pos (0U)
15606#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos)
15607#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
15608
15609/******************** Bits definition for RTC_SCR register ******************/
15610#define RTC_SCR_CITSF_Pos (5U)
15611#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos)
15612#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
15613#define RTC_SCR_CTSOVF_Pos (4U)
15614#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos)
15615#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
15616#define RTC_SCR_CTSF_Pos (3U)
15617#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos)
15618#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
15619#define RTC_SCR_CWUTF_Pos (2U)
15620#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos)
15621#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
15622#define RTC_SCR_CALRBF_Pos (1U)
15623#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos)
15624#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
15625#define RTC_SCR_CALRAF_Pos (0U)
15626#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos)
15627#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
15628
15629/******************************************************************************/
15630/* */
15631/* Tamper and backup register (TAMP) */
15632/* */
15633/******************************************************************************/
15634/******************** Bits definition for TAMP_CR1 register *****************/
15635#define TAMP_CR1_TAMP1E_Pos (0U)
15636#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos)
15637#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
15638#define TAMP_CR1_TAMP2E_Pos (1U)
15639#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos)
15640#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
15641#define TAMP_CR1_TAMP3E_Pos (2U)
15642#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos)
15643#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
15644#define TAMP_CR1_ITAMP1E_Pos (16U)
15645#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos)
15646#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
15647#define TAMP_CR1_ITAMP2E_Pos (17U)
15648#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos)
15649#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
15650#define TAMP_CR1_ITAMP3E_Pos (18U)
15651#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos)
15652#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
15653#define TAMP_CR1_ITAMP4E_Pos (19U)
15654#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos)
15655#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
15656#define TAMP_CR1_ITAMP5E_Pos (20U)
15657#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos)
15658#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
15659#define TAMP_CR1_ITAMP6E_Pos (21U)
15660#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos)
15661#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
15662#define TAMP_CR1_ITAMP8E_Pos (23U)
15663#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos)
15664#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
15665
15666/******************** Bits definition for TAMP_CR2 register *****************/
15667#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
15668#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)
15669#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
15670#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
15671#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)
15672#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
15673#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
15674#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)
15675#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
15676#define TAMP_CR2_TAMP1MSK_Pos (16U)
15677#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos)
15678#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
15679#define TAMP_CR2_TAMP2MSK_Pos (17U)
15680#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos)
15681#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
15682#define TAMP_CR2_TAMP3MSK_Pos (18U)
15683#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos)
15684#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
15685#define TAMP_CR2_TAMP1TRG_Pos (24U)
15686#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos)
15687#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
15688#define TAMP_CR2_TAMP2TRG_Pos (25U)
15689#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos)
15690#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
15691#define TAMP_CR2_TAMP3TRG_Pos (26U)
15692#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos)
15693#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
15694
15695/******************** Bits definition for TAMP_FLTCR register ***************/
15696#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
15697#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)
15698#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
15699#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)
15700#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)
15701#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)
15702#define TAMP_FLTCR_TAMPFLT_Pos (3U)
15703#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)
15704#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
15705#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)
15706#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)
15707#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
15708#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)
15709#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
15710#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)
15711#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)
15712#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
15713#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)
15714#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
15715
15716/******************* Bits definition for TAMP_ATCR1 register ****************/
15717#define TAMP_ATCR1_TAMP1AM_Pos (0U)
15718#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)
15719#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
15720#define TAMP_ATCR1_TAMP2AM_Pos (1U)
15721#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)
15722#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
15723#define TAMP_ATCR1_TAMP3AM_Pos (2U)
15724#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)
15725#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
15726#define TAMP_ATCR1_ATOSEL1_Pos (8U)
15727#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)
15728#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
15729#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)
15730#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)
15731#define TAMP_ATCR1_ATOSEL2_Pos (10U)
15732#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)
15733#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
15734#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)
15735#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)
15736#define TAMP_ATCR1_ATOSEL3_Pos (12U)
15737#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)
15738#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
15739#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)
15740#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)
15741#define TAMP_ATCR1_ATOSEL4_Pos (14U)
15742#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)
15743#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
15744#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)
15745#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)
15746#define TAMP_ATCR1_ATCKSEL_Pos (16U)
15747#define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)
15748#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
15749#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)
15750#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)
15751#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)
15752#define TAMP_ATCR1_ATPER_Pos (24U)
15753#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos)
15754#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
15755#define TAMP_ATCR1_ATOSHARE_Pos (30U)
15756#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)
15757#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
15758#define TAMP_ATCR1_FLTEN_Pos (31U)
15759#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos)
15760#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
15761
15762/******************** Bits definition for TAMP_ATSEEDR register *************/
15763#define TAMP_ATSEEDR_SEED_Pos (0U)
15764#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)
15765#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
15766
15767/******************** Bits definition for TAMP_ATOR register ****************/
15768#define TAMP_ATOR_PRNG_Pos (0U)
15769#define TAMP_ATOR_PRNG_Msk (0x000000FFUL << TAMP_ATOR_PRNG_Pos)
15770#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
15771#define TAMP_ATOR_SEEDF_Pos (14U)
15772#define TAMP_ATOR_SEEDF_Msk (0x01UL << TAMP_ATOR_SEEDF_Pos)
15773#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
15774#define TAMP_ATOR_INITS_Pos (15U)
15775#define TAMP_ATOR_INITS_Msk (0x01UL << TAMP_ATOR_INITS_Pos)
15776#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
15777
15778/******************** Bits definition for TAMP_IER register *****************/
15779#define TAMP_IER_TAMP1IE_Pos (0U)
15780#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos)
15781#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
15782#define TAMP_IER_TAMP2IE_Pos (1U)
15783#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos)
15784#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
15785#define TAMP_IER_TAMP3IE_Pos (2U)
15786#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos)
15787#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
15788#define TAMP_IER_ITAMP1IE_Pos (16U)
15789#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos)
15790#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
15791#define TAMP_IER_ITAMP2IE_Pos (17U)
15792#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos)
15793#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
15794#define TAMP_IER_ITAMP3IE_Pos (18U)
15795#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos)
15796#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
15797#define TAMP_IER_ITAMP4IE_Pos (19U)
15798#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos)
15799#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
15800#define TAMP_IER_ITAMP5IE_Pos (20U)
15801#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos)
15802#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
15803#define TAMP_IER_ITAMP6IE_Pos (21U)
15804#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos)
15805#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
15806#define TAMP_IER_ITAMP8IE_Pos (23U)
15807#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos)
15808#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
15809
15810/******************** Bits definition for TAMP_SR register *****************/
15811#define TAMP_SR_TAMP1F_Pos (0U)
15812#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos)
15813#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
15814#define TAMP_SR_TAMP2F_Pos (1U)
15815#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos)
15816#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
15817#define TAMP_SR_TAMP3F_Pos (2U)
15818#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos)
15819#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
15820#define TAMP_SR_ITAMP1F_Pos (16U)
15821#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos)
15822#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
15823#define TAMP_SR_ITAMP2F_Pos (17U)
15824#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos)
15825#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
15826#define TAMP_SR_ITAMP3F_Pos (18U)
15827#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos)
15828#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
15829#define TAMP_SR_ITAMP4F_Pos (19U)
15830#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos)
15831#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
15832#define TAMP_SR_ITAMP5F_Pos (20U)
15833#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos)
15834#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
15835#define TAMP_SR_ITAMP6F_Pos (21U)
15836#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos)
15837#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
15838#define TAMP_SR_ITAMP8F_Pos (23U)
15839#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos)
15840#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
15841
15842/******************** Bits definition for TAMP_MISR register ************ *****/
15843#define TAMP_MISR_TAMP1MF_Pos (0U)
15844#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos)
15845#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
15846#define TAMP_MISR_TAMP2MF_Pos (1U)
15847#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos)
15848#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
15849#define TAMP_MISR_TAMP3MF_Pos (2U)
15850#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos)
15851#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
15852#define TAMP_MISR_ITAMP1MF_Pos (16U)
15853#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos)
15854#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
15855#define TAMP_MISR_ITAMP2MF_Pos (17U)
15856#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos)
15857#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
15858#define TAMP_MISR_ITAMP3MF_Pos (18U)
15859#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos)
15860#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
15861#define TAMP_MISR_ITAMP4MF_Pos (19U)
15862#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos)
15863#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
15864#define TAMP_MISR_ITAMP5MF_Pos (20U)
15865#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos)
15866#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
15867#define TAMP_MISR_ITAMP6MF_Pos (21U)
15868#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos)
15869#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
15870#define TAMP_MISR_ITAMP8MF_Pos (23U)
15871#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos)
15872#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
15873
15874/******************** Bits definition for TAMP_SCR register *****************/
15875#define TAMP_SCR_CTAMP1F_Pos (0U)
15876#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos)
15877#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
15878#define TAMP_SCR_CTAMP2F_Pos (1U)
15879#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos)
15880#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
15881#define TAMP_SCR_CTAMP3F_Pos (2U)
15882#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos)
15883#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
15884#define TAMP_SCR_CITAMP1F_Pos (16U)
15885#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos)
15886#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
15887#define TAMP_SCR_CITAMP2F_Pos (17U)
15888#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos)
15889#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
15890#define TAMP_SCR_CITAMP3F_Pos (18U)
15891#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos)
15892#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
15893#define TAMP_SCR_CITAMP4F_Pos (19U)
15894#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos)
15895#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
15896#define TAMP_SCR_CITAMP5F_Pos (20U)
15897#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos)
15898#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
15899#define TAMP_SCR_CITAMP6F_Pos (21U)
15900#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos)
15901#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
15902#define TAMP_SCR_CITAMP8F_Pos (23U)
15903#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos)
15904#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
15905
15906/******************** Bits definition for TAMP_COUNTR register **************/
15907#define TAMP_COUNTR_Pos (16U)
15908#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos)
15909#define TAMP_COUNTR TAMP_COUNTR_Msk
15910
15911/******************** Bits definition for TAMP_OR register ******************/
15912#define TAMP_OR_OUT3_RMP_Pos (0U)
15913#define TAMP_OR_OUT3_RMP_Msk (0x1UL << TAMP_OR_OUT3_RMP_Pos)
15914#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk
15915
15916/******************** Bits definition for TAMP_BKP0R register ***************/
15917#define TAMP_BKP0R_Pos (0U)
15918#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos)
15919#define TAMP_BKP0R TAMP_BKP0R_Msk
15920
15921/******************** Bits definition for TAMP_BKP1R register ****************/
15922#define TAMP_BKP1R_Pos (0U)
15923#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos)
15924#define TAMP_BKP1R TAMP_BKP1R_Msk
15925
15926/******************** Bits definition for TAMP_BKP2R register ****************/
15927#define TAMP_BKP2R_Pos (0U)
15928#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos)
15929#define TAMP_BKP2R TAMP_BKP2R_Msk
15930
15931/******************** Bits definition for TAMP_BKP3R register ****************/
15932#define TAMP_BKP3R_Pos (0U)
15933#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos)
15934#define TAMP_BKP3R TAMP_BKP3R_Msk
15935
15936/******************** Bits definition for TAMP_BKP4R register ****************/
15937#define TAMP_BKP4R_Pos (0U)
15938#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos)
15939#define TAMP_BKP4R TAMP_BKP4R_Msk
15940
15941/******************** Bits definition for TAMP_BKP5R register ****************/
15942#define TAMP_BKP5R_Pos (0U)
15943#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos)
15944#define TAMP_BKP5R TAMP_BKP5R_Msk
15945
15946/******************** Bits definition for TAMP_BKP6R register ****************/
15947#define TAMP_BKP6R_Pos (0U)
15948#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos)
15949#define TAMP_BKP6R TAMP_BKP6R_Msk
15950
15951/******************** Bits definition for TAMP_BKP7R register ****************/
15952#define TAMP_BKP7R_Pos (0U)
15953#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos)
15954#define TAMP_BKP7R TAMP_BKP7R_Msk
15955
15956/******************** Bits definition for TAMP_BKP8R register ****************/
15957#define TAMP_BKP8R_Pos (0U)
15958#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos)
15959#define TAMP_BKP8R TAMP_BKP8R_Msk
15960
15961/******************** Bits definition for TAMP_BKP9R register ****************/
15962#define TAMP_BKP9R_Pos (0U)
15963#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos)
15964#define TAMP_BKP9R TAMP_BKP9R_Msk
15965
15966/******************** Bits definition for TAMP_BKP10R register ***************/
15967#define TAMP_BKP10R_Pos (0U)
15968#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos)
15969#define TAMP_BKP10R TAMP_BKP10R_Msk
15970
15971/******************** Bits definition for TAMP_BKP11R register ***************/
15972#define TAMP_BKP11R_Pos (0U)
15973#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos)
15974#define TAMP_BKP11R TAMP_BKP11R_Msk
15975
15976/******************** Bits definition for TAMP_BKP12R register ***************/
15977#define TAMP_BKP12R_Pos (0U)
15978#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos)
15979#define TAMP_BKP12R TAMP_BKP12R_Msk
15980
15981/******************** Bits definition for TAMP_BKP13R register ***************/
15982#define TAMP_BKP13R_Pos (0U)
15983#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos)
15984#define TAMP_BKP13R TAMP_BKP13R_Msk
15985
15986/******************** Bits definition for TAMP_BKP14R register ***************/
15987#define TAMP_BKP14R_Pos (0U)
15988#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos)
15989#define TAMP_BKP14R TAMP_BKP14R_Msk
15990
15991/******************** Bits definition for TAMP_BKP15R register ***************/
15992#define TAMP_BKP15R_Pos (0U)
15993#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos)
15994#define TAMP_BKP15R TAMP_BKP15R_Msk
15995
15996/******************** Bits definition for TAMP_BKP16R register ***************/
15997#define TAMP_BKP16R_Pos (0U)
15998#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos)
15999#define TAMP_BKP16R TAMP_BKP16R_Msk
16000
16001/******************** Bits definition for TAMP_BKP17R register ***************/
16002#define TAMP_BKP17R_Pos (0U)
16003#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos)
16004#define TAMP_BKP17R TAMP_BKP17R_Msk
16005
16006/******************** Bits definition for TAMP_BKP18R register ***************/
16007#define TAMP_BKP18R_Pos (0U)
16008#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos)
16009#define TAMP_BKP18R TAMP_BKP18R_Msk
16010
16011/******************** Bits definition for TAMP_BKP19R register ***************/
16012#define TAMP_BKP19R_Pos (0U)
16013#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos)
16014#define TAMP_BKP19R TAMP_BKP19R_Msk
16015
16016/******************** Bits definition for TAMP_BKP20R register ***************/
16017#define TAMP_BKP20R_Pos (0U)
16018#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos)
16019#define TAMP_BKP20R TAMP_BKP20R_Msk
16020
16021/******************** Bits definition for TAMP_BKP21R register ***************/
16022#define TAMP_BKP21R_Pos (0U)
16023#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos)
16024#define TAMP_BKP21R TAMP_BKP21R_Msk
16025
16026/******************** Bits definition for TAMP_BKP22R register ***************/
16027#define TAMP_BKP22R_Pos (0U)
16028#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos)
16029#define TAMP_BKP22R TAMP_BKP22R_Msk
16030
16031/******************** Bits definition for TAMP_BKP23R register ***************/
16032#define TAMP_BKP23R_Pos (0U)
16033#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos)
16034#define TAMP_BKP23R TAMP_BKP23R_Msk
16035
16036/******************** Bits definition for TAMP_BKP24R register ***************/
16037#define TAMP_BKP24R_Pos (0U)
16038#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos)
16039#define TAMP_BKP24R TAMP_BKP24R_Msk
16040
16041/******************** Bits definition for TAMP_BKP25R register ***************/
16042#define TAMP_BKP25R_Pos (0U)
16043#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos)
16044#define TAMP_BKP25R TAMP_BKP25R_Msk
16045
16046/******************** Bits definition for TAMP_BKP26R register ***************/
16047#define TAMP_BKP26R_Pos (0U)
16048#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos)
16049#define TAMP_BKP26R TAMP_BKP26R_Msk
16050
16051/******************** Bits definition for TAMP_BKP27R register ***************/
16052#define TAMP_BKP27R_Pos (0U)
16053#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos)
16054#define TAMP_BKP27R TAMP_BKP27R_Msk
16055
16056/******************** Bits definition for TAMP_BKP28R register ***************/
16057#define TAMP_BKP28R_Pos (0U)
16058#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos)
16059#define TAMP_BKP28R TAMP_BKP28R_Msk
16060
16061/******************** Bits definition for TAMP_BKP29R register ***************/
16062#define TAMP_BKP29R_Pos (0U)
16063#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos)
16064#define TAMP_BKP29R TAMP_BKP29R_Msk
16065
16066/******************** Bits definition for TAMP_BKP30R register ***************/
16067#define TAMP_BKP30R_Pos (0U)
16068#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos)
16069#define TAMP_BKP30R TAMP_BKP30R_Msk
16070
16071/******************** Bits definition for TAMP_BKP31R register ***************/
16072#define TAMP_BKP31R_Pos (0U)
16073#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos)
16074#define TAMP_BKP31R TAMP_BKP31R_Msk
16075
16076/******************** Number of backup registers ******************************/
16077#define TAMP_BKP_NUMBER_Pos (5U)
16078#define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos)
16079#define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk
16081/******************************************************************************/
16082/* */
16083/* SPDIF-RX Interface */
16084/* */
16085/******************************************************************************/
16086/******************** Bit definition for SPDIF_CR register ******************/
16087#define SPDIFRX_CR_SPDIFEN_Pos (0U)
16088#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
16089#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
16090#define SPDIFRX_CR_RXDMAEN_Pos (2U)
16091#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
16092#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
16093#define SPDIFRX_CR_RXSTEO_Pos (3U)
16094#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
16095#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
16096#define SPDIFRX_CR_DRFMT_Pos (4U)
16097#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
16098#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
16099#define SPDIFRX_CR_PMSK_Pos (6U)
16100#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
16101#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
16102#define SPDIFRX_CR_VMSK_Pos (7U)
16103#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
16104#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
16105#define SPDIFRX_CR_CUMSK_Pos (8U)
16106#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
16107#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
16108#define SPDIFRX_CR_PTMSK_Pos (9U)
16109#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
16110#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
16111#define SPDIFRX_CR_CBDMAEN_Pos (10U)
16112#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
16113#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
16114#define SPDIFRX_CR_CHSEL_Pos (11U)
16115#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
16116#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
16117#define SPDIFRX_CR_NBTR_Pos (12U)
16118#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
16119#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
16120#define SPDIFRX_CR_WFA_Pos (14U)
16121#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
16122#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
16123#define SPDIFRX_CR_INSEL_Pos (16U)
16124#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
16125#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
16126#define SPDIFRX_CR_CKSEN_Pos (20U)
16127#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos)
16128#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk
16129#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
16130#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
16131#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk
16133/******************* Bit definition for SPDIFRX_IMR register *******************/
16134#define SPDIFRX_IMR_RXNEIE_Pos (0U)
16135#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
16136#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
16137#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
16138#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
16139#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
16140#define SPDIFRX_IMR_PERRIE_Pos (2U)
16141#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
16142#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
16143#define SPDIFRX_IMR_OVRIE_Pos (3U)
16144#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
16145#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
16146#define SPDIFRX_IMR_SBLKIE_Pos (4U)
16147#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
16148#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
16149#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
16150#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
16151#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
16152#define SPDIFRX_IMR_IFEIE_Pos (6U)
16153#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
16154#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
16156/******************* Bit definition for SPDIFRX_SR register *******************/
16157#define SPDIFRX_SR_RXNE_Pos (0U)
16158#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
16159#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
16160#define SPDIFRX_SR_CSRNE_Pos (1U)
16161#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
16162#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
16163#define SPDIFRX_SR_PERR_Pos (2U)
16164#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
16165#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
16166#define SPDIFRX_SR_OVR_Pos (3U)
16167#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
16168#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
16169#define SPDIFRX_SR_SBD_Pos (4U)
16170#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
16171#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
16172#define SPDIFRX_SR_SYNCD_Pos (5U)
16173#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
16174#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
16175#define SPDIFRX_SR_FERR_Pos (6U)
16176#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
16177#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
16178#define SPDIFRX_SR_SERR_Pos (7U)
16179#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
16180#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
16181#define SPDIFRX_SR_TERR_Pos (8U)
16182#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
16183#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
16184#define SPDIFRX_SR_WIDTH5_Pos (16U)
16185#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
16186#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
16188/******************* Bit definition for SPDIFRX_IFCR register *******************/
16189#define SPDIFRX_IFCR_PERRCF_Pos (2U)
16190#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
16191#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
16192#define SPDIFRX_IFCR_OVRCF_Pos (3U)
16193#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
16194#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
16195#define SPDIFRX_IFCR_SBDCF_Pos (4U)
16196#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
16197#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
16198#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
16199#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
16200#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
16202/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
16203#define SPDIFRX_DR0_DR_Pos (0U)
16204#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
16205#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
16206#define SPDIFRX_DR0_PE_Pos (24U)
16207#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
16208#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
16209#define SPDIFRX_DR0_V_Pos (25U)
16210#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
16211#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
16212#define SPDIFRX_DR0_U_Pos (26U)
16213#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
16214#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
16215#define SPDIFRX_DR0_C_Pos (27U)
16216#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
16217#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
16218#define SPDIFRX_DR0_PT_Pos (28U)
16219#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
16220#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
16222/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
16223#define SPDIFRX_DR1_DR_Pos (8U)
16224#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
16225#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
16226#define SPDIFRX_DR1_PT_Pos (4U)
16227#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
16228#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
16229#define SPDIFRX_DR1_C_Pos (3U)
16230#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
16231#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
16232#define SPDIFRX_DR1_U_Pos (2U)
16233#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
16234#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
16235#define SPDIFRX_DR1_V_Pos (1U)
16236#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
16237#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
16238#define SPDIFRX_DR1_PE_Pos (0U)
16239#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
16240#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
16242/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
16243#define SPDIFRX_DR1_DRNL1_Pos (16U)
16244#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
16245#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
16246#define SPDIFRX_DR1_DRNL2_Pos (0U)
16247#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
16248#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
16250/******************* Bit definition for SPDIFRX_CSR register *******************/
16251#define SPDIFRX_CSR_USR_Pos (0U)
16252#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
16253#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
16254#define SPDIFRX_CSR_CS_Pos (16U)
16255#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
16256#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
16257#define SPDIFRX_CSR_SOB_Pos (24U)
16258#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
16259#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
16261/******************* Bit definition for SPDIFRX_DIR register *******************/
16262#define SPDIFRX_DIR_THI_Pos (0U)
16263#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
16264#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
16265#define SPDIFRX_DIR_TLO_Pos (16U)
16266#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
16267#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
16269/******************* Bit definition for SPDIFRX_VERR register *******************/
16270#define SPDIFRX_VERR_MINREV_Pos (0U)
16271#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos)
16272#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk
16273#define SPDIFRX_VERR_MAJREV_Pos (4U)
16274#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
16275#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk
16277/******************* Bit definition for SPDIFRX_IDR register *******************/
16278#define SPDIFRX_IDR_ID_Pos (0U)
16279#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
16280#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk
16282/******************* Bit definition for SPDIFRX_SIDR register *******************/
16283#define SPDIFRX_SIDR_SID_Pos (0U)
16284#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
16285#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk
16287/******************************************************************************/
16288/* */
16289/* Serial Audio Interface */
16290/* */
16291/******************************************************************************/
16292/******************************* SAI VERSION ********************************/
16293#define SAI_VER_V2_1
16294
16295/******************** Bit definition for SAI_GCR register *******************/
16296#define SAI_GCR_SYNCIN_Pos (0U)
16297#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
16298#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
16299#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
16300#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
16302#define SAI_GCR_SYNCOUT_Pos (4U)
16303#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
16304#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
16305#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
16306#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
16308/******************* Bit definition for SAI_xCR1 register *******************/
16309#define SAI_xCR1_MODE_Pos (0U)
16310#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
16311#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
16312#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
16313#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
16315#define SAI_xCR1_PRTCFG_Pos (2U)
16316#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
16317#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
16318#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
16319#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
16321#define SAI_xCR1_DS_Pos (5U)
16322#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
16323#define SAI_xCR1_DS SAI_xCR1_DS_Msk
16324#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
16325#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
16326#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
16328#define SAI_xCR1_LSBFIRST_Pos (8U)
16329#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
16330#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
16331#define SAI_xCR1_CKSTR_Pos (9U)
16332#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
16333#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
16335#define SAI_xCR1_SYNCEN_Pos (10U)
16336#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
16337#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
16338#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
16339#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
16341#define SAI_xCR1_MONO_Pos (12U)
16342#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
16343#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
16344#define SAI_xCR1_OUTDRIV_Pos (13U)
16345#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
16346#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
16347#define SAI_xCR1_SAIEN_Pos (16U)
16348#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
16349#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
16350#define SAI_xCR1_DMAEN_Pos (17U)
16351#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
16352#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
16353#define SAI_xCR1_NODIV_Pos (19U)
16354#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
16355#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
16357#define SAI_xCR1_MCKDIV_Pos (20U)
16358#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
16359#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
16360#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos)
16361#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos)
16362#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos)
16363#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos)
16364#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos)
16365#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos)
16367#define SAI_xCR1_MCKEN_Pos (27U)
16368#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
16369#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
16371#define SAI_xCR1_OSR_Pos (26U)
16372#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
16373#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
16375/* Legacy define */
16376#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
16377
16378/******************* Bit definition for SAI_xCR2 register *******************/
16379#define SAI_xCR2_FTH_Pos (0U)
16380#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
16381#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
16382#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
16383#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
16384#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
16386#define SAI_xCR2_FFLUSH_Pos (3U)
16387#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
16388#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
16389#define SAI_xCR2_TRIS_Pos (4U)
16390#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
16391#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
16392#define SAI_xCR2_MUTE_Pos (5U)
16393#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
16394#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
16395#define SAI_xCR2_MUTEVAL_Pos (6U)
16396#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
16397#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
16399#define SAI_xCR2_MUTECNT_Pos (7U)
16400#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
16401#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
16402#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
16403#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
16404#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
16405#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
16406#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
16407#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
16409#define SAI_xCR2_CPL_Pos (13U)
16410#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
16411#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
16413#define SAI_xCR2_COMP_Pos (14U)
16414#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
16415#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
16416#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
16417#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
16419/****************** Bit definition for SAI_xFRCR register *******************/
16420#define SAI_xFRCR_FRL_Pos (0U)
16421#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
16422#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
16423#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
16424#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
16425#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
16426#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
16427#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
16428#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
16429#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
16430#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
16432#define SAI_xFRCR_FSALL_Pos (8U)
16433#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
16434#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
16435#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
16436#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
16437#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
16438#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
16439#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
16440#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
16441#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
16443#define SAI_xFRCR_FSDEF_Pos (16U)
16444#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
16445#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
16446#define SAI_xFRCR_FSPOL_Pos (17U)
16447#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
16448#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
16449#define SAI_xFRCR_FSOFF_Pos (18U)
16450#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
16451#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
16453/* Legacy define */
16454#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
16455
16456/****************** Bit definition for SAI_xSLOTR register *******************/
16457#define SAI_xSLOTR_FBOFF_Pos (0U)
16458#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
16459#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
16460#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
16461#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
16462#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
16463#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
16464#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
16466#define SAI_xSLOTR_SLOTSZ_Pos (6U)
16467#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
16468#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
16469#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
16470#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
16472#define SAI_xSLOTR_NBSLOT_Pos (8U)
16473#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
16474#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
16475#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
16476#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
16477#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
16478#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
16480#define SAI_xSLOTR_SLOTEN_Pos (16U)
16481#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
16482#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
16484/******************* Bit definition for SAI_xIMR register *******************/
16485#define SAI_xIMR_OVRUDRIE_Pos (0U)
16486#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
16487#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
16488#define SAI_xIMR_MUTEDETIE_Pos (1U)
16489#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
16490#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
16491#define SAI_xIMR_WCKCFGIE_Pos (2U)
16492#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
16493#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
16494#define SAI_xIMR_FREQIE_Pos (3U)
16495#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
16496#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
16497#define SAI_xIMR_CNRDYIE_Pos (4U)
16498#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
16499#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
16500#define SAI_xIMR_AFSDETIE_Pos (5U)
16501#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
16502#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
16503#define SAI_xIMR_LFSDETIE_Pos (6U)
16504#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
16505#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
16507/******************** Bit definition for SAI_xSR register *******************/
16508#define SAI_xSR_OVRUDR_Pos (0U)
16509#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
16510#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
16511#define SAI_xSR_MUTEDET_Pos (1U)
16512#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
16513#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
16514#define SAI_xSR_WCKCFG_Pos (2U)
16515#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
16516#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
16517#define SAI_xSR_FREQ_Pos (3U)
16518#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
16519#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
16520#define SAI_xSR_CNRDY_Pos (4U)
16521#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
16522#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
16523#define SAI_xSR_AFSDET_Pos (5U)
16524#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
16525#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
16526#define SAI_xSR_LFSDET_Pos (6U)
16527#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
16528#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
16530#define SAI_xSR_FLVL_Pos (16U)
16531#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
16532#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
16533#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
16534#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
16535#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
16537/****************** Bit definition for SAI_xCLRFR register ******************/
16538#define SAI_xCLRFR_COVRUDR_Pos (0U)
16539#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
16540#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
16541#define SAI_xCLRFR_CMUTEDET_Pos (1U)
16542#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
16543#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
16544#define SAI_xCLRFR_CWCKCFG_Pos (2U)
16545#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
16546#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
16547#define SAI_xCLRFR_CFREQ_Pos (3U)
16548#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
16549#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
16550#define SAI_xCLRFR_CCNRDY_Pos (4U)
16551#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
16552#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
16553#define SAI_xCLRFR_CAFSDET_Pos (5U)
16554#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
16555#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
16556#define SAI_xCLRFR_CLFSDET_Pos (6U)
16557#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
16558#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
16560/****************** Bit definition for SAI_xDR register *********************/
16561#define SAI_xDR_DATA_Pos (0U)
16562#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
16563#define SAI_xDR_DATA SAI_xDR_DATA_Msk
16564
16565/******************* Bit definition for SAI_PDMCR register ******************/
16566#define SAI_PDMCR_PDMEN_Pos (0U)
16567#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
16568#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
16570#define SAI_PDMCR_MICNBR_Pos (4U)
16571#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
16572#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
16573#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
16574#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
16576#define SAI_PDMCR_CKEN1_Pos (8U)
16577#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
16578#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
16579#define SAI_PDMCR_CKEN2_Pos (9U)
16580#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
16581#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
16582#define SAI_PDMCR_CKEN3_Pos (10U)
16583#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
16584#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
16585#define SAI_PDMCR_CKEN4_Pos (11U)
16586#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
16587#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
16589/****************** Bit definition for SAI_PDMDLY register ******************/
16590#define SAI_PDMDLY_DLYM1L_Pos (0U)
16591#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
16592#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
16593#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
16594#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
16595#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
16597#define SAI_PDMDLY_DLYM1R_Pos (4U)
16598#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
16599#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
16600#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
16601#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
16602#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
16604#define SAI_PDMDLY_DLYM2L_Pos (8U)
16605#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
16606#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
16607#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
16608#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
16609#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
16611#define SAI_PDMDLY_DLYM2R_Pos (12U)
16612#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
16613#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
16614#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
16615#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
16616#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
16618#define SAI_PDMDLY_DLYM3L_Pos (16U)
16619#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
16620#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
16621#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
16622#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
16623#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
16625#define SAI_PDMDLY_DLYM3R_Pos (20U)
16626#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
16627#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
16628#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
16629#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
16630#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
16632#define SAI_PDMDLY_DLYM4L_Pos (24U)
16633#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
16634#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
16635#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
16636#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
16637#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
16639#define SAI_PDMDLY_DLYM4R_Pos (28U)
16640#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
16641#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
16642#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
16643#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
16644#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
16646/******************************************************************************/
16647/* */
16648/* SDMMC Interface */
16649/* */
16650/******************************************************************************/
16651/****************** Bit definition for SDMMC_POWER register ******************/
16652#define SDMMC_POWER_PWRCTRL_Pos (0U)
16653#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
16654#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
16655#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
16656#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
16657#define SDMMC_POWER_VSWITCH_Pos (2U)
16658#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos)
16659#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk
16660#define SDMMC_POWER_VSWITCHEN_Pos (3U)
16661#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
16662#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk
16663#define SDMMC_POWER_DIRPOL_Pos (4U)
16664#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos)
16665#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk
16667/****************** Bit definition for SDMMC_CLKCR register ******************/
16668#define SDMMC_CLKCR_CLKDIV_Pos (0U)
16669#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
16670#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
16671#define SDMMC_CLKCR_PWRSAV_Pos (12U)
16672#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
16673#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
16675#define SDMMC_CLKCR_WIDBUS_Pos (14U)
16676#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
16677#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
16678#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
16679#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
16681#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
16682#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
16683#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
16684#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
16685#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
16686#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
16687#define SDMMC_CLKCR_DDR_Pos (18U)
16688#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos)
16689#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk
16690#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
16691#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
16692#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk
16693#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
16694#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
16695#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk
16696#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
16697#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
16699/******************* Bit definition for SDMMC_ARG register *******************/
16700#define SDMMC_ARG_CMDARG_Pos (0U)
16701#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
16702#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
16704/******************* Bit definition for SDMMC_CMD register *******************/
16705#define SDMMC_CMD_CMDINDEX_Pos (0U)
16706#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
16707#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
16708#define SDMMC_CMD_CMDTRANS_Pos (6U)
16709#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
16710#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk
16711#define SDMMC_CMD_CMDSTOP_Pos (7U)
16712#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
16713#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk
16715#define SDMMC_CMD_WAITRESP_Pos (8U)
16716#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
16717#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
16718#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
16719#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
16721#define SDMMC_CMD_WAITINT_Pos (10U)
16722#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
16723#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
16724#define SDMMC_CMD_WAITPEND_Pos (11U)
16725#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
16726#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
16727#define SDMMC_CMD_CPSMEN_Pos (12U)
16728#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
16729#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
16730#define SDMMC_CMD_DTHOLD_Pos (13U)
16731#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos)
16732#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk
16733#define SDMMC_CMD_BOOTMODE_Pos (14U)
16734#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
16735#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk
16736#define SDMMC_CMD_BOOTEN_Pos (15U)
16737#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos)
16738#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk
16739#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
16740#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
16741#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk
16743/***************** Bit definition for SDMMC_RESPCMD register *****************/
16744#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
16745#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
16746#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
16748/****************** Bit definition for SDMMC_RESP0 register ******************/
16749#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
16750#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
16751#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
16753/****************** Bit definition for SDMMC_RESP1 register ******************/
16754#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
16755#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
16756#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
16758/****************** Bit definition for SDMMC_RESP2 register ******************/
16759#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
16760#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
16761#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
16763/****************** Bit definition for SDMMC_RESP3 register ******************/
16764#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
16765#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
16766#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
16768/****************** Bit definition for SDMMC_RESP4 register ******************/
16769#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
16770#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
16771#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
16773/****************** Bit definition for SDMMC_DTIMER register *****************/
16774#define SDMMC_DTIMER_DATATIME_Pos (0U)
16775#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
16776#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
16778/****************** Bit definition for SDMMC_DLEN register *******************/
16779#define SDMMC_DLEN_DATALENGTH_Pos (0U)
16780#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
16781#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
16783/****************** Bit definition for SDMMC_DCTRL register ******************/
16784#define SDMMC_DCTRL_DTEN_Pos (0U)
16785#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
16786#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
16787#define SDMMC_DCTRL_DTDIR_Pos (1U)
16788#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
16789#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
16790#define SDMMC_DCTRL_DTMODE_Pos (2U)
16791#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
16792#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
16793#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
16794#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
16796#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
16797#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
16798#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
16799#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
16800#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
16801#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
16802#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
16804#define SDMMC_DCTRL_RWSTART_Pos (8U)
16805#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
16806#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
16807#define SDMMC_DCTRL_RWSTOP_Pos (9U)
16808#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
16809#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
16810#define SDMMC_DCTRL_RWMOD_Pos (10U)
16811#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
16812#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
16813#define SDMMC_DCTRL_SDIOEN_Pos (11U)
16814#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
16815#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
16816#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
16817#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
16818#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk
16819#define SDMMC_DCTRL_FIFORST_Pos (13U)
16820#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
16821#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk
16823/****************** Bit definition for SDMMC_DCOUNT register *****************/
16824#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
16825#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
16826#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
16828/****************** Bit definition for SDMMC_STA register ********************/
16829#define SDMMC_STA_CCRCFAIL_Pos (0U)
16830#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
16831#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
16832#define SDMMC_STA_DCRCFAIL_Pos (1U)
16833#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
16834#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
16835#define SDMMC_STA_CTIMEOUT_Pos (2U)
16836#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
16837#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
16838#define SDMMC_STA_DTIMEOUT_Pos (3U)
16839#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
16840#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
16841#define SDMMC_STA_TXUNDERR_Pos (4U)
16842#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
16843#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
16844#define SDMMC_STA_RXOVERR_Pos (5U)
16845#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
16846#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
16847#define SDMMC_STA_CMDREND_Pos (6U)
16848#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
16849#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
16850#define SDMMC_STA_CMDSENT_Pos (7U)
16851#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
16852#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
16853#define SDMMC_STA_DATAEND_Pos (8U)
16854#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
16855#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
16856#define SDMMC_STA_DHOLD_Pos (9U)
16857#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos)
16858#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk
16859#define SDMMC_STA_DBCKEND_Pos (10U)
16860#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
16861#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
16862#define SDMMC_STA_DABORT_Pos (11U)
16863#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos)
16864#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk
16865#define SDMMC_STA_DPSMACT_Pos (12U)
16866#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos)
16867#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk
16868#define SDMMC_STA_CPSMACT_Pos (13U)
16869#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos)
16870#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk
16871#define SDMMC_STA_TXFIFOHE_Pos (14U)
16872#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
16873#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
16874#define SDMMC_STA_RXFIFOHF_Pos (15U)
16875#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
16876#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
16877#define SDMMC_STA_TXFIFOF_Pos (16U)
16878#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
16879#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
16880#define SDMMC_STA_RXFIFOF_Pos (17U)
16881#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
16882#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
16883#define SDMMC_STA_TXFIFOE_Pos (18U)
16884#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
16885#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
16886#define SDMMC_STA_RXFIFOE_Pos (19U)
16887#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
16888#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
16889#define SDMMC_STA_BUSYD0_Pos (20U)
16890#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos)
16891#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk
16892#define SDMMC_STA_BUSYD0END_Pos (21U)
16893#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos)
16894#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk
16895#define SDMMC_STA_SDIOIT_Pos (22U)
16896#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
16897#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
16898#define SDMMC_STA_ACKFAIL_Pos (23U)
16899#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos)
16900#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk
16901#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
16902#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
16903#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk
16904#define SDMMC_STA_VSWEND_Pos (25U)
16905#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos)
16906#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk
16907#define SDMMC_STA_CKSTOP_Pos (26U)
16908#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos)
16909#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk
16910#define SDMMC_STA_IDMATE_Pos (27U)
16911#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos)
16912#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk
16913#define SDMMC_STA_IDMABTC_Pos (28U)
16914#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos)
16915#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk
16917/******************* Bit definition for SDMMC_ICR register *******************/
16918#define SDMMC_ICR_CCRCFAILC_Pos (0U)
16919#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
16920#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
16921#define SDMMC_ICR_DCRCFAILC_Pos (1U)
16922#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
16923#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
16924#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
16925#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
16926#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
16927#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
16928#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
16929#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
16930#define SDMMC_ICR_TXUNDERRC_Pos (4U)
16931#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
16932#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
16933#define SDMMC_ICR_RXOVERRC_Pos (5U)
16934#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
16935#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
16936#define SDMMC_ICR_CMDRENDC_Pos (6U)
16937#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
16938#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
16939#define SDMMC_ICR_CMDSENTC_Pos (7U)
16940#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
16941#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
16942#define SDMMC_ICR_DATAENDC_Pos (8U)
16943#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
16944#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
16945#define SDMMC_ICR_DHOLDC_Pos (9U)
16946#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos)
16947#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk
16948#define SDMMC_ICR_DBCKENDC_Pos (10U)
16949#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
16950#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
16951#define SDMMC_ICR_DABORTC_Pos (11U)
16952#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos)
16953#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk
16954#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
16955#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
16956#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk
16957#define SDMMC_ICR_SDIOITC_Pos (22U)
16958#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
16959#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
16960#define SDMMC_ICR_ACKFAILC_Pos (23U)
16961#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
16962#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk
16963#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
16964#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
16965#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk
16966#define SDMMC_ICR_VSWENDC_Pos (25U)
16967#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos)
16968#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk
16969#define SDMMC_ICR_CKSTOPC_Pos (26U)
16970#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
16971#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk
16972#define SDMMC_ICR_IDMATEC_Pos (27U)
16973#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos)
16974#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk
16975#define SDMMC_ICR_IDMABTCC_Pos (28U)
16976#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
16977#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk
16979/****************** Bit definition for SDMMC_MASK register *******************/
16980#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
16981#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
16982#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
16983#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
16984#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
16985#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
16986#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
16987#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
16988#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
16989#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
16990#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
16991#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
16992#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
16993#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
16994#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
16995#define SDMMC_MASK_RXOVERRIE_Pos (5U)
16996#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
16997#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
16998#define SDMMC_MASK_CMDRENDIE_Pos (6U)
16999#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
17000#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
17001#define SDMMC_MASK_CMDSENTIE_Pos (7U)
17002#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
17003#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
17004#define SDMMC_MASK_DATAENDIE_Pos (8U)
17005#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
17006#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
17007#define SDMMC_MASK_DHOLDIE_Pos (9U)
17008#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
17009#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk
17010#define SDMMC_MASK_DBCKENDIE_Pos (10U)
17011#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
17012#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
17013#define SDMMC_MASK_DABORTIE_Pos (11U)
17014#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos)
17015#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk
17017#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
17018#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
17019#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
17020#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
17021#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
17022#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
17024#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
17025#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
17026#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
17027#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
17028#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
17029#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
17031#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
17032#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
17033#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk
17034#define SDMMC_MASK_SDIOITIE_Pos (22U)
17035#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
17036#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
17037#define SDMMC_MASK_ACKFAILIE_Pos (23U)
17038#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
17039#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk
17040#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
17041#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
17042#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk
17043#define SDMMC_MASK_VSWENDIE_Pos (25U)
17044#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
17045#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk
17046#define SDMMC_MASK_CKSTOPIE_Pos (26U)
17047#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
17048#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk
17049#define SDMMC_MASK_IDMABTCIE_Pos (28U)
17050#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
17051#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk
17053/***************** Bit definition for SDMMC_ACKTIME register *****************/
17054#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
17055#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
17056#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk
17058/****************** Bit definition for SDMMC_FIFO register *******************/
17059#define SDMMC_FIFO_FIFODATA_Pos (0U)
17060#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
17061#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
17063/****************** Bit definition for SDMMC_IDMACTRL register ****************/
17064#define SDMMC_IDMA_IDMAEN_Pos (0U)
17065#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
17066#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk
17067#define SDMMC_IDMA_IDMABMODE_Pos (1U)
17068#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
17069#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk
17070#define SDMMC_IDMA_IDMABACT_Pos (2U)
17071#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
17072#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk
17074/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
17075#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
17076#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
17077#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk
17079/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
17080#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU)
17082/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
17083#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU)
17085/******************************************************************************/
17086/* */
17087/* Delay Block Interface (DLYB) */
17088/* */
17089/******************************************************************************/
17090/******************* Bit definition for DLYB_CR register ********************/
17091#define DLYB_CR_DEN_Pos (0U)
17092#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos)
17093#define DLYB_CR_DEN DLYB_CR_DEN_Msk
17094#define DLYB_CR_SEN_Pos (1U)
17095#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos)
17096#define DLYB_CR_SEN DLYB_CR_SEN_Msk
17099/******************* Bit definition for DLYB_CFGR register ********************/
17100#define DLYB_CFGR_SEL_Pos (0U)
17101#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos)
17102#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk
17103#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos)
17104#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos)
17105#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos)
17106#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos)
17108#define DLYB_CFGR_UNIT_Pos (8U)
17109#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos)
17110#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk
17111#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos)
17112#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos)
17113#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos)
17114#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos)
17115#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos)
17116#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos)
17117#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos)
17119#define DLYB_CFGR_LNG_Pos (16U)
17120#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos)
17121#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk
17122#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos)
17123#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos)
17124#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos)
17125#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos)
17126#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos)
17127#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos)
17128#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos)
17129#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos)
17130#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos)
17131#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos)
17132#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos)
17133#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos)
17135#define DLYB_CFGR_LNGF_Pos (31U)
17136#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos)
17137#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk
17139/******************************************************************************/
17140/* */
17141/* Serial Peripheral Interface (SPI/I2S) */
17142/* */
17143/******************************************************************************/
17144#define SPI_SPI6I2S_SUPPORT
17145/******************* Bit definition for SPI_CR1 register ********************/
17146#define SPI_CR1_SPE_Pos (0U)
17147#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
17148#define SPI_CR1_SPE SPI_CR1_SPE_Msk
17149#define SPI_CR1_MASRX_Pos (8U)
17150#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos)
17151#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk
17152#define SPI_CR1_CSTART_Pos (9U)
17153#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos)
17154#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk
17155#define SPI_CR1_CSUSP_Pos (10U)
17156#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos)
17157#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk
17158#define SPI_CR1_HDDIR_Pos (11U)
17159#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos)
17160#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk
17161#define SPI_CR1_SSI_Pos (12U)
17162#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
17163#define SPI_CR1_SSI SPI_CR1_SSI_Msk
17164#define SPI_CR1_CRC33_17_Pos (13U)
17165#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos)
17166#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk
17167#define SPI_CR1_RCRCINI_Pos (14U)
17168#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos)
17169#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk
17170#define SPI_CR1_TCRCINI_Pos (15U)
17171#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos)
17172#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk
17173#define SPI_CR1_IOLOCK_Pos (16U)
17174#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos)
17175#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk
17177/******************* Bit definition for SPI_CR2 register ********************/
17178#define SPI_CR2_TSER_Pos (16U)
17179#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos)
17180#define SPI_CR2_TSER SPI_CR2_TSER_Msk
17181#define SPI_CR2_TSIZE_Pos (0U)
17182#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos)
17183#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk
17185/******************* Bit definition for SPI_CFG1 register ********************/
17186#define SPI_CFG1_DSIZE_Pos (0U)
17187#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos)
17188#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk
17189#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos)
17190#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos)
17191#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos)
17192#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos)
17193#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos)
17195#define SPI_CFG1_FTHLV_Pos (5U)
17196#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos)
17197#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk
17198#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos)
17199#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos)
17200#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos)
17201#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos)
17203#define SPI_CFG1_UDRCFG_Pos (9U)
17204#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos)
17205#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk
17206#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos)
17207#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos)
17210#define SPI_CFG1_UDRDET_Pos (11U)
17211#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
17212#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk
17213#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos)
17214#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos)
17216#define SPI_CFG1_RXDMAEN_Pos (14U)
17217#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos)
17218#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk
17219#define SPI_CFG1_TXDMAEN_Pos (15U)
17220#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos)
17221#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk
17223#define SPI_CFG1_CRCSIZE_Pos (16U)
17224#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
17225#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk
17226#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos)
17227#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos)
17228#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos)
17229#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos)
17230#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos)
17232#define SPI_CFG1_CRCEN_Pos (22U)
17233#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos)
17234#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk
17236#define SPI_CFG1_MBR_Pos (28U)
17237#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos)
17238#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk
17239#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos)
17240#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos)
17241#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos)
17243/******************* Bit definition for SPI_CFG2 register ********************/
17244#define SPI_CFG2_MSSI_Pos (0U)
17245#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos)
17246#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk
17247#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos)
17248#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos)
17249#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos)
17250#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos)
17252#define SPI_CFG2_MIDI_Pos (4U)
17253#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos)
17254#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk
17255#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos)
17256#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos)
17257#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos)
17258#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos)
17260#define SPI_CFG2_IOSWP_Pos (15U)
17261#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos)
17262#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk
17264#define SPI_CFG2_COMM_Pos (17U)
17265#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos)
17266#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk
17267#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos)
17268#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos)
17270#define SPI_CFG2_SP_Pos (19U)
17271#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos)
17272#define SPI_CFG2_SP SPI_CFG2_SP_Msk
17273#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos)
17274#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos)
17275#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos)
17277#define SPI_CFG2_MASTER_Pos (22U)
17278#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos)
17279#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk
17280#define SPI_CFG2_LSBFRST_Pos (23U)
17281#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos)
17282#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk
17283#define SPI_CFG2_CPHA_Pos (24U)
17284#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos)
17285#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk
17286#define SPI_CFG2_CPOL_Pos (25U)
17287#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos)
17288#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk
17289#define SPI_CFG2_SSM_Pos (26U)
17290#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos)
17291#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk
17293#define SPI_CFG2_SSIOP_Pos (28U)
17294#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos)
17295#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk
17296#define SPI_CFG2_SSOE_Pos (29U)
17297#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos)
17298#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk
17299#define SPI_CFG2_SSOM_Pos (30U)
17300#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos)
17301#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk
17303#define SPI_CFG2_AFCNTR_Pos (31U)
17304#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos)
17305#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk
17307/******************* Bit definition for SPI_IER register ********************/
17308#define SPI_IER_RXPIE_Pos (0U)
17309#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos)
17310#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk
17311#define SPI_IER_TXPIE_Pos (1U)
17312#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos)
17313#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk
17314#define SPI_IER_DXPIE_Pos (2U)
17315#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos)
17316#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk
17317#define SPI_IER_EOTIE_Pos (3U)
17318#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos)
17319#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk
17320#define SPI_IER_TXTFIE_Pos (4U)
17321#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos)
17322#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk
17323#define SPI_IER_UDRIE_Pos (5U)
17324#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos)
17325#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk
17326#define SPI_IER_OVRIE_Pos (6U)
17327#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos)
17328#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk
17329#define SPI_IER_CRCEIE_Pos (7U)
17330#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos)
17331#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk
17332#define SPI_IER_TIFREIE_Pos (8U)
17333#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos)
17334#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk
17335#define SPI_IER_MODFIE_Pos (9U)
17336#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos)
17337#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk
17338#define SPI_IER_TSERFIE_Pos (10U)
17339#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
17340#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk
17342/******************* Bit definition for SPI_SR register ********************/
17343#define SPI_SR_RXP_Pos (0U)
17344#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos)
17345#define SPI_SR_RXP SPI_SR_RXP_Msk
17346#define SPI_SR_TXP_Pos (1U)
17347#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos)
17348#define SPI_SR_TXP SPI_SR_TXP_Msk
17349#define SPI_SR_DXP_Pos (2U)
17350#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos)
17351#define SPI_SR_DXP SPI_SR_DXP_Msk
17352#define SPI_SR_EOT_Pos (3U)
17353#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos)
17354#define SPI_SR_EOT SPI_SR_EOT_Msk
17355#define SPI_SR_TXTF_Pos (4U)
17356#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos)
17357#define SPI_SR_TXTF SPI_SR_TXTF_Msk
17358#define SPI_SR_UDR_Pos (5U)
17359#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
17360#define SPI_SR_UDR SPI_SR_UDR_Msk
17361#define SPI_SR_OVR_Pos (6U)
17362#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
17363#define SPI_SR_OVR SPI_SR_OVR_Msk
17364#define SPI_SR_CRCE_Pos (7U)
17365#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos)
17366#define SPI_SR_CRCE SPI_SR_CRCE_Msk
17367#define SPI_SR_TIFRE_Pos (8U)
17368#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos)
17369#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk
17370#define SPI_SR_MODF_Pos (9U)
17371#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
17372#define SPI_SR_MODF SPI_SR_MODF_Msk
17373#define SPI_SR_TSERF_Pos (10U)
17374#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos)
17375#define SPI_SR_TSERF SPI_SR_TSERF_Msk
17376#define SPI_SR_SUSP_Pos (11U)
17377#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos)
17378#define SPI_SR_SUSP SPI_SR_SUSP_Msk
17379#define SPI_SR_TXC_Pos (12U)
17380#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos)
17381#define SPI_SR_TXC SPI_SR_TXC_Msk
17382#define SPI_SR_RXPLVL_Pos (13U)
17383#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos)
17384#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk
17385#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos)
17386#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos)
17387#define SPI_SR_RXWNE_Pos (15U)
17388#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos)
17389#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk
17390#define SPI_SR_CTSIZE_Pos (16U)
17391#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos)
17392#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk
17394/******************* Bit definition for SPI_IFCR register ********************/
17395#define SPI_IFCR_EOTC_Pos (3U)
17396#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos)
17397#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk
17398#define SPI_IFCR_TXTFC_Pos (4U)
17399#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos)
17400#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk
17401#define SPI_IFCR_UDRC_Pos (5U)
17402#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos)
17403#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk
17404#define SPI_IFCR_OVRC_Pos (6U)
17405#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos)
17406#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk
17407#define SPI_IFCR_CRCEC_Pos (7U)
17408#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos)
17409#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk
17410#define SPI_IFCR_TIFREC_Pos (8U)
17411#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos)
17412#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk
17413#define SPI_IFCR_MODFC_Pos (9U)
17414#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos)
17415#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk
17416#define SPI_IFCR_TSERFC_Pos (10U)
17417#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos)
17418#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk
17419#define SPI_IFCR_SUSPC_Pos (11U)
17420#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos)
17421#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk
17423/******************* Bit definition for SPI_TXDR register ********************/
17424#define SPI_TXDR_TXDR_Pos (0U)
17425#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
17426#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
17427
17428/******************* Bit definition for SPI_RXDR register ********************/
17429#define SPI_RXDR_RXDR_Pos (0U)
17430#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
17431#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
17432
17433/******************* Bit definition for SPI_CRCPOLY register ********************/
17434#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
17435#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
17436#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
17437
17438/******************* Bit definition for SPI_TXCRC register ********************/
17439#define SPI_TXCRC_TXCRC_Pos (0U)
17440#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
17441#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
17442
17443/******************* Bit definition for SPI_RXCRC register ********************/
17444#define SPI_RXCRC_RXCRC_Pos (0U)
17445#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
17446#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
17447
17448/******************* Bit definition for SPI_UDRDR register ********************/
17449#define SPI_UDRDR_UDRDR_Pos (0U)
17450#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
17451#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
17452
17453/****************** Bit definition for SPI_I2SCFGR register *****************/
17454#define SPI_I2SCFGR_I2SMOD_Pos (0U)
17455#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
17456#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
17457#define SPI_I2SCFGR_I2SCFG_Pos (1U)
17458#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
17459#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
17460#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
17461#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
17462#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
17463#define SPI_I2SCFGR_I2SSTD_Pos (4U)
17464#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
17465#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
17466#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
17467#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
17468#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
17469#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
17470#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
17471#define SPI_I2SCFGR_DATLEN_Pos (8U)
17472#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
17473#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
17474#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
17475#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
17476#define SPI_I2SCFGR_CHLEN_Pos (10U)
17477#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
17478#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
17479#define SPI_I2SCFGR_CKPOL_Pos (11U)
17480#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
17481#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
17482#define SPI_I2SCFGR_FIXCH_Pos (12U)
17483#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
17484#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk
17485#define SPI_I2SCFGR_WSINV_Pos (13U)
17486#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos)
17487#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk
17488#define SPI_I2SCFGR_DATFMT_Pos (14U)
17489#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
17490#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk
17491#define SPI_I2SCFGR_I2SDIV_Pos (16U)
17492#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
17493#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk
17494#define SPI_I2SCFGR_ODD_Pos (24U)
17495#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos)
17496#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk
17497#define SPI_I2SCFGR_MCKOE_Pos (25U)
17498#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
17499#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk
17503/******************************************************************************/
17504/* */
17505/* SYSCFG */
17506/* */
17507/******************************************************************************/
17508
17509/****************** Bit definition for SYSCFG_PMCR register ******************/
17510#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
17511#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
17512#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk
17513#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
17514#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
17515#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk
17516#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
17517#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
17518#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk
17519#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
17520#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
17521#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk
17522#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
17523#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
17524#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk
17525#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
17526#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
17527#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk
17528#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
17529#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
17530#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk
17531#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
17532#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
17533#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk
17534#define SYSCFG_PMCR_PA0SO_Pos (24U)
17535#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
17536#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk
17537#define SYSCFG_PMCR_PA1SO_Pos (25U)
17538#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
17539#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk
17540#define SYSCFG_PMCR_PC2SO_Pos (26U)
17541#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
17542#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk
17543#define SYSCFG_PMCR_PC3SO_Pos (27U)
17544#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
17545#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk
17547/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
17548#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
17549#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
17550#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
17551#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
17552#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
17553#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
17554#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
17555#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
17556#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
17557#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
17558#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
17559#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
17563#define SYSCFG_EXTICR1_EXTI0_PA (0U)
17564#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
17565#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
17566#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
17567#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
17568#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
17569#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
17570#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
17571#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U)
17572#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U)
17573#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU)
17578#define SYSCFG_EXTICR1_EXTI1_PA (0U)
17579#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
17580#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
17581#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
17582#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
17583#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
17584#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
17585#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
17586#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U)
17587#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U)
17588#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U)
17592#define SYSCFG_EXTICR1_EXTI2_PA (0U)
17593#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
17594#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
17595#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
17596#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
17597#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
17598#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
17599#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U)
17600#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U)
17601#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U)
17602#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U)
17607#define SYSCFG_EXTICR1_EXTI3_PA (0U)
17608#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
17609#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
17610#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
17611#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
17612#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
17613#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
17614#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U)
17615#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U)
17616#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U)
17617#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U)
17619/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
17620#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
17621#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
17622#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
17623#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
17624#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
17625#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
17626#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
17627#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
17628#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
17629#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
17630#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
17631#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
17635#define SYSCFG_EXTICR2_EXTI4_PA (0U)
17636#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
17637#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
17638#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
17639#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
17640#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
17641#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
17642#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
17643#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U)
17644#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U)
17645#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU)
17649#define SYSCFG_EXTICR2_EXTI5_PA (0U)
17650#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
17651#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
17652#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
17653#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
17654#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
17655#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
17656#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U)
17657#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U)
17658#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U)
17659#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U)
17663#define SYSCFG_EXTICR2_EXTI6_PA (0U)
17664#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
17665#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
17666#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
17667#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
17668#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
17669#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
17670#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U)
17671#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U)
17672#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U)
17673#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U)
17678#define SYSCFG_EXTICR2_EXTI7_PA (0U)
17679#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
17680#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
17681#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
17682#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
17683#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
17684#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
17685#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U)
17686#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U)
17687#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U)
17688#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U)
17690/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
17691#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
17692#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
17693#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
17694#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
17695#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
17696#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
17697#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
17698#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
17699#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
17700#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
17701#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
17702#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
17707#define SYSCFG_EXTICR3_EXTI8_PA (0U)
17708#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
17709#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
17710#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
17711#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
17712#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
17713#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
17714#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U)
17715#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U)
17716#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U)
17717#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU)
17722#define SYSCFG_EXTICR3_EXTI9_PA (0U)
17723#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
17724#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
17725#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
17726#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
17727#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
17728#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
17729#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U)
17730#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U)
17731#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U)
17732#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U)
17737#define SYSCFG_EXTICR3_EXTI10_PA (0U)
17738#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
17739#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
17740#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
17741#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
17742#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
17743#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
17744#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U)
17745#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U)
17746#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U)
17747#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U)
17752#define SYSCFG_EXTICR3_EXTI11_PA (0U)
17753#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
17754#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
17755#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
17756#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
17757#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
17758#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)
17759#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U)
17760#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U)
17761#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U)
17762#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U)
17764/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
17765#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
17766#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
17767#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
17768#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
17769#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
17770#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
17771#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
17772#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
17773#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
17774#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
17775#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
17776#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
17780#define SYSCFG_EXTICR4_EXTI12_PA (0U)
17781#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
17782#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
17783#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
17784#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
17785#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
17786#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
17787#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U)
17788#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U)
17789#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U)
17790#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU)
17794#define SYSCFG_EXTICR4_EXTI13_PA (0U)
17795#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
17796#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
17797#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
17798#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
17799#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
17800#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
17801#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U)
17802#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U)
17803#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U)
17804#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U)
17808#define SYSCFG_EXTICR4_EXTI14_PA (0U)
17809#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
17810#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
17811#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
17812#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
17813#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
17814#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
17815#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U)
17816#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U)
17817#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U)
17818#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U)
17822#define SYSCFG_EXTICR4_EXTI15_PA (0U)
17823#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
17824#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
17825#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
17826#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
17827#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
17828#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)
17829#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U)
17830#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U)
17831#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U)
17832#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U)
17834/****************** Bit definition for SYSCFG_CFGR register ******************/
17835#define SYSCFG_CFGR_PVDL_Pos (2U)
17836#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos)
17837#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk
17838#define SYSCFG_CFGR_FLASHL_Pos (3U)
17839#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
17840#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk
17841#define SYSCFG_CFGR_CM7L_Pos (6U)
17842#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos)
17843#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk
17844#define SYSCFG_CFGR_DTCML_Pos (13U)
17845#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos)
17846#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk
17847#define SYSCFG_CFGR_ITCML_Pos (14U)
17848#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos)
17849#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk
17850/****************** Bit definition for SYSCFG_CCCSR register ******************/
17851#define SYSCFG_CCCSR_EN_Pos (0U)
17852#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos)
17853#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk
17854#define SYSCFG_CCCSR_CS_Pos (1U)
17855#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos)
17856#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk
17857#define SYSCFG_CCCSR_CS_MMC_Pos (3U)
17858#define SYSCFG_CCCSR_CS_MMC_Msk (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)
17859#define SYSCFG_CCCSR_CS_MMC SYSCFG_CCCSR_CS_MMC_Msk
17860#define SYSCFG_CCCSR_READY_Pos (8U)
17861#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos)
17862#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk
17863#define SYSCFG_CCCSR_HSLV0_Pos (16U)
17864#define SYSCFG_CCCSR_HSLV0_Msk (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)
17865#define SYSCFG_CCCSR_HSLV0 SYSCFG_CCCSR_HSLV0_Msk
17866#define SYSCFG_CCCSR_HSLV1_Pos (17U)
17867#define SYSCFG_CCCSR_HSLV1_Msk (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)
17868#define SYSCFG_CCCSR_HSLV1 SYSCFG_CCCSR_HSLV1_Msk
17869#define SYSCFG_CCCSR_HSLV2_Pos (18U)
17870#define SYSCFG_CCCSR_HSLV2_Msk (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)
17871#define SYSCFG_CCCSR_HSLV2 SYSCFG_CCCSR_HSLV2_Msk
17872#define SYSCFG_CCCSR_HSLV3_Pos (19U)
17873#define SYSCFG_CCCSR_HSLV3_Msk (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)
17874#define SYSCFG_CCCSR_HSLV3 SYSCFG_CCCSR_HSLV3_Msk
17875/****************** Bit definition for SYSCFG_CCVR register *******************/
17876#define SYSCFG_CCVR_NCV_Pos (0U)
17877#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos)
17878#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk
17879#define SYSCFG_CCVR_PCV_Pos (4U)
17880#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos)
17881#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk
17883/****************** Bit definition for SYSCFG_CCCR register *******************/
17884#define SYSCFG_CCCR_NCC_Pos (0U)
17885#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos)
17886#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk
17887#define SYSCFG_CCCR_PCC_Pos (4U)
17888#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos)
17889#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk
17890#define SYSCFG_CCCR_NCC_MMC_Pos (8U)
17891#define SYSCFG_CCCR_NCC_MMC_Msk (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)
17892#define SYSCFG_CCCR_NCC_MMC SYSCFG_CCCR_NCC_MMC_Msk
17893#define SYSCFG_CCCR_PCC_MMC_Pos (12U)
17894#define SYSCFG_CCCR_PCC_MMC_Msk (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)
17895#define SYSCFG_CCCR_PCC_MMC SYSCFG_CCCR_PCC_MMC_Msk
17896/******************************************************************************/
17897/* */
17898/* Digital Temperature Sensor (DTS) */
17899/* */
17900/******************************************************************************/
17901
17902/****************** Bit definition for DTS_CFGR1 register ******************/
17903#define DTS_CFGR1_TS1_EN_Pos (0U)
17904#define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos)
17905#define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk
17906#define DTS_CFGR1_TS1_START_Pos (4U)
17907#define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos)
17908#define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk
17909#define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
17910#define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
17911#define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk
17912#define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
17913#define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
17914#define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
17915#define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos)
17916#define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
17917#define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos)
17918#define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk
17919#define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
17920#define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
17921#define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
17922#define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos)
17923#define DTS_CFGR1_REFCLK_SEL_Pos (20U)
17924#define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos)
17925#define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk
17926#define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
17927#define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos)
17928#define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk
17929#define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
17930#define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos)
17931#define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk
17933/****************** Bit definition for DTS_T0VALR1 register ******************/
17934#define DTS_T0VALR1_TS1_FMT0_Pos (0U)
17935#define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos)
17936#define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk
17937#define DTS_T0VALR1_TS1_T0_Pos (16U)
17938#define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos)
17939#define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk
17941/****************** Bit definition for DTS_RAMPVALR register ******************/
17942#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
17943#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos)
17944#define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk
17946/****************** Bit definition for DTS_ITR1 register ******************/
17947#define DTS_ITR1_TS1_LITTHD_Pos (0U)
17948#define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos)
17949#define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk
17950#define DTS_ITR1_TS1_HITTHD_Pos (16U)
17951#define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos)
17952#define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk
17954/****************** Bit definition for DTS_DR register ******************/
17955#define DTS_DR_TS1_MFREQ_Pos (0U)
17956#define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos)
17957#define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk
17959/****************** Bit definition for DTS_SR register ******************/
17960#define DTS_SR_TS1_ITEF_Pos (0U)
17961#define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos)
17962#define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk
17963#define DTS_SR_TS1_ITLF_Pos (1U)
17964#define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos)
17965#define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk
17966#define DTS_SR_TS1_ITHF_Pos (2U)
17967#define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos)
17968#define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk
17969#define DTS_SR_TS1_AITEF_Pos (4U)
17970#define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos)
17971#define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk
17972#define DTS_SR_TS1_AITLF_Pos (5U)
17973#define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos)
17974#define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk
17975#define DTS_SR_TS1_AITHF_Pos (6U)
17976#define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos)
17977#define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk
17978#define DTS_SR_TS1_RDY_Pos (15U)
17979#define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos)
17980#define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk
17982/****************** Bit definition for DTS_ITENR register ******************/
17983#define DTS_ITENR_TS1_ITEEN_Pos (0U)
17984#define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos)
17985#define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk
17986#define DTS_ITENR_TS1_ITLEN_Pos (1U)
17987#define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos)
17988#define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk
17989#define DTS_ITENR_TS1_ITHEN_Pos (2U)
17990#define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos)
17991#define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk
17992#define DTS_ITENR_TS1_AITEEN_Pos (4U)
17993#define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos)
17994#define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk
17995#define DTS_ITENR_TS1_AITLEN_Pos (5U)
17996#define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos)
17997#define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk
17998#define DTS_ITENR_TS1_AITHEN_Pos (6U)
17999#define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos)
18000#define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk
18002/****************** Bit definition for DTS_ICIFR register ******************/
18003#define DTS_ICIFR_TS1_CITEF_Pos (0U)
18004#define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos)
18005#define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk
18006#define DTS_ICIFR_TS1_CITLF_Pos (1U)
18007#define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos)
18008#define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk
18009#define DTS_ICIFR_TS1_CITHF_Pos (2U)
18010#define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos)
18011#define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk
18012#define DTS_ICIFR_TS1_CAITEF_Pos (4U)
18013#define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos)
18014#define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk
18015#define DTS_ICIFR_TS1_CAITLF_Pos (5U)
18016#define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos)
18017#define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk
18018#define DTS_ICIFR_TS1_CAITHF_Pos (6U)
18019#define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos)
18020#define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk
18023/******************************************************************************/
18024/* */
18025/* TIM */
18026/* */
18027/******************************************************************************/
18028#define TIM_BREAK_INPUT_SUPPORT
18030/******************* Bit definition for TIM_CR1 register ********************/
18031#define TIM_CR1_CEN_Pos (0U)
18032#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
18033#define TIM_CR1_CEN TIM_CR1_CEN_Msk
18034#define TIM_CR1_UDIS_Pos (1U)
18035#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
18036#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
18037#define TIM_CR1_URS_Pos (2U)
18038#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
18039#define TIM_CR1_URS TIM_CR1_URS_Msk
18040#define TIM_CR1_OPM_Pos (3U)
18041#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
18042#define TIM_CR1_OPM TIM_CR1_OPM_Msk
18043#define TIM_CR1_DIR_Pos (4U)
18044#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
18045#define TIM_CR1_DIR TIM_CR1_DIR_Msk
18047#define TIM_CR1_CMS_Pos (5U)
18048#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
18049#define TIM_CR1_CMS TIM_CR1_CMS_Msk
18050#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
18051#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
18053#define TIM_CR1_ARPE_Pos (7U)
18054#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
18055#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
18057#define TIM_CR1_CKD_Pos (8U)
18058#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
18059#define TIM_CR1_CKD TIM_CR1_CKD_Msk
18060#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
18061#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
18063#define TIM_CR1_UIFREMAP_Pos (11U)
18064#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
18065#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
18067/******************* Bit definition for TIM_CR2 register ********************/
18068#define TIM_CR2_CCPC_Pos (0U)
18069#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
18070#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
18071#define TIM_CR2_CCUS_Pos (2U)
18072#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
18073#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
18074#define TIM_CR2_CCDS_Pos (3U)
18075#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
18076#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
18078#define TIM_CR2_MMS_Pos (4U)
18079#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
18080#define TIM_CR2_MMS TIM_CR2_MMS_Msk
18081#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
18082#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
18083#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
18085#define TIM_CR2_TI1S_Pos (7U)
18086#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
18087#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
18088#define TIM_CR2_OIS1_Pos (8U)
18089#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
18090#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
18091#define TIM_CR2_OIS1N_Pos (9U)
18092#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
18093#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
18094#define TIM_CR2_OIS2_Pos (10U)
18095#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
18096#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
18097#define TIM_CR2_OIS2N_Pos (11U)
18098#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
18099#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
18100#define TIM_CR2_OIS3_Pos (12U)
18101#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
18102#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
18103#define TIM_CR2_OIS3N_Pos (13U)
18104#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
18105#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
18106#define TIM_CR2_OIS4_Pos (14U)
18107#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
18108#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
18109#define TIM_CR2_OIS5_Pos (16U)
18110#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
18111#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
18112#define TIM_CR2_OIS6_Pos (18U)
18113#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
18114#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
18116#define TIM_CR2_MMS2_Pos (20U)
18117#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
18118#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
18119#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
18120#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
18121#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
18122#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
18124/******************* Bit definition for TIM_SMCR register *******************/
18125#define TIM_SMCR_SMS_Pos (0U)
18126#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
18127#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
18128#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
18129#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
18130#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
18131#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
18133#define TIM_SMCR_TS_Pos (4U)
18134#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
18135#define TIM_SMCR_TS TIM_SMCR_TS_Msk
18136#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
18137#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
18138#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
18139#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
18140#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
18142#define TIM_SMCR_MSM_Pos (7U)
18143#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
18144#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
18146#define TIM_SMCR_ETF_Pos (8U)
18147#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
18148#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
18149#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
18150#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
18151#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
18152#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
18154#define TIM_SMCR_ETPS_Pos (12U)
18155#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
18156#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
18157#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
18158#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
18160#define TIM_SMCR_ECE_Pos (14U)
18161#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
18162#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
18163#define TIM_SMCR_ETP_Pos (15U)
18164#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
18165#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
18167/******************* Bit definition for TIM_DIER register *******************/
18168#define TIM_DIER_UIE_Pos (0U)
18169#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
18170#define TIM_DIER_UIE TIM_DIER_UIE_Msk
18171#define TIM_DIER_CC1IE_Pos (1U)
18172#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
18173#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
18174#define TIM_DIER_CC2IE_Pos (2U)
18175#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
18176#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
18177#define TIM_DIER_CC3IE_Pos (3U)
18178#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
18179#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
18180#define TIM_DIER_CC4IE_Pos (4U)
18181#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
18182#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
18183#define TIM_DIER_COMIE_Pos (5U)
18184#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
18185#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
18186#define TIM_DIER_TIE_Pos (6U)
18187#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
18188#define TIM_DIER_TIE TIM_DIER_TIE_Msk
18189#define TIM_DIER_BIE_Pos (7U)
18190#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
18191#define TIM_DIER_BIE TIM_DIER_BIE_Msk
18192#define TIM_DIER_UDE_Pos (8U)
18193#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
18194#define TIM_DIER_UDE TIM_DIER_UDE_Msk
18195#define TIM_DIER_CC1DE_Pos (9U)
18196#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
18197#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
18198#define TIM_DIER_CC2DE_Pos (10U)
18199#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
18200#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
18201#define TIM_DIER_CC3DE_Pos (11U)
18202#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
18203#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
18204#define TIM_DIER_CC4DE_Pos (12U)
18205#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
18206#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
18207#define TIM_DIER_COMDE_Pos (13U)
18208#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
18209#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
18210#define TIM_DIER_TDE_Pos (14U)
18211#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
18212#define TIM_DIER_TDE TIM_DIER_TDE_Msk
18214/******************** Bit definition for TIM_SR register ********************/
18215#define TIM_SR_UIF_Pos (0U)
18216#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
18217#define TIM_SR_UIF TIM_SR_UIF_Msk
18218#define TIM_SR_CC1IF_Pos (1U)
18219#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
18220#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
18221#define TIM_SR_CC2IF_Pos (2U)
18222#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
18223#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
18224#define TIM_SR_CC3IF_Pos (3U)
18225#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
18226#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
18227#define TIM_SR_CC4IF_Pos (4U)
18228#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
18229#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
18230#define TIM_SR_COMIF_Pos (5U)
18231#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
18232#define TIM_SR_COMIF TIM_SR_COMIF_Msk
18233#define TIM_SR_TIF_Pos (6U)
18234#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
18235#define TIM_SR_TIF TIM_SR_TIF_Msk
18236#define TIM_SR_BIF_Pos (7U)
18237#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
18238#define TIM_SR_BIF TIM_SR_BIF_Msk
18239#define TIM_SR_B2IF_Pos (8U)
18240#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
18241#define TIM_SR_B2IF TIM_SR_B2IF_Msk
18242#define TIM_SR_CC1OF_Pos (9U)
18243#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
18244#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
18245#define TIM_SR_CC2OF_Pos (10U)
18246#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
18247#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
18248#define TIM_SR_CC3OF_Pos (11U)
18249#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
18250#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
18251#define TIM_SR_CC4OF_Pos (12U)
18252#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
18253#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
18254#define TIM_SR_CC5IF_Pos (16U)
18255#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
18256#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
18257#define TIM_SR_CC6IF_Pos (17U)
18258#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
18259#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
18260#define TIM_SR_SBIF_Pos (13U)
18261#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
18262#define TIM_SR_SBIF TIM_SR_SBIF_Msk
18264/******************* Bit definition for TIM_EGR register ********************/
18265#define TIM_EGR_UG_Pos (0U)
18266#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
18267#define TIM_EGR_UG TIM_EGR_UG_Msk
18268#define TIM_EGR_CC1G_Pos (1U)
18269#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
18270#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
18271#define TIM_EGR_CC2G_Pos (2U)
18272#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
18273#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
18274#define TIM_EGR_CC3G_Pos (3U)
18275#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
18276#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
18277#define TIM_EGR_CC4G_Pos (4U)
18278#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
18279#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
18280#define TIM_EGR_COMG_Pos (5U)
18281#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
18282#define TIM_EGR_COMG TIM_EGR_COMG_Msk
18283#define TIM_EGR_TG_Pos (6U)
18284#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
18285#define TIM_EGR_TG TIM_EGR_TG_Msk
18286#define TIM_EGR_BG_Pos (7U)
18287#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
18288#define TIM_EGR_BG TIM_EGR_BG_Msk
18289#define TIM_EGR_B2G_Pos (8U)
18290#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
18291#define TIM_EGR_B2G TIM_EGR_B2G_Msk
18294/****************** Bit definition for TIM_CCMR1 register *******************/
18295#define TIM_CCMR1_CC1S_Pos (0U)
18296#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
18297#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
18298#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
18299#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
18301#define TIM_CCMR1_OC1FE_Pos (2U)
18302#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
18303#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
18304#define TIM_CCMR1_OC1PE_Pos (3U)
18305#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
18306#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
18308#define TIM_CCMR1_OC1M_Pos (4U)
18309#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
18310#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
18311#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
18312#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
18313#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
18314#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
18316#define TIM_CCMR1_OC1CE_Pos (7U)
18317#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
18318#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
18320#define TIM_CCMR1_CC2S_Pos (8U)
18321#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
18322#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
18323#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
18324#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
18326#define TIM_CCMR1_OC2FE_Pos (10U)
18327#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
18328#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
18329#define TIM_CCMR1_OC2PE_Pos (11U)
18330#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
18331#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
18333#define TIM_CCMR1_OC2M_Pos (12U)
18334#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
18335#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
18336#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
18337#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
18338#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
18339#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
18341#define TIM_CCMR1_OC2CE_Pos (15U)
18342#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
18343#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
18345/*----------------------------------------------------------------------------*/
18346
18347#define TIM_CCMR1_IC1PSC_Pos (2U)
18348#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
18349#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
18350#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
18351#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
18353#define TIM_CCMR1_IC1F_Pos (4U)
18354#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
18355#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
18356#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
18357#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
18358#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
18359#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
18361#define TIM_CCMR1_IC2PSC_Pos (10U)
18362#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
18363#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
18364#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
18365#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
18367#define TIM_CCMR1_IC2F_Pos (12U)
18368#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
18369#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
18370#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
18371#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
18372#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
18373#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
18375/****************** Bit definition for TIM_CCMR2 register *******************/
18376#define TIM_CCMR2_CC3S_Pos (0U)
18377#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
18378#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
18379#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
18380#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
18382#define TIM_CCMR2_OC3FE_Pos (2U)
18383#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
18384#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
18385#define TIM_CCMR2_OC3PE_Pos (3U)
18386#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
18387#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
18389#define TIM_CCMR2_OC3M_Pos (4U)
18390#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
18391#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
18392#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
18393#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
18394#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
18395#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
18397#define TIM_CCMR2_OC3CE_Pos (7U)
18398#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
18399#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
18401#define TIM_CCMR2_CC4S_Pos (8U)
18402#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
18403#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
18404#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
18405#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
18407#define TIM_CCMR2_OC4FE_Pos (10U)
18408#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
18409#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
18410#define TIM_CCMR2_OC4PE_Pos (11U)
18411#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
18412#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
18414#define TIM_CCMR2_OC4M_Pos (12U)
18415#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
18416#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
18417#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
18418#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
18419#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
18420#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
18422#define TIM_CCMR2_OC4CE_Pos (15U)
18423#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
18424#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
18426/*----------------------------------------------------------------------------*/
18427
18428#define TIM_CCMR2_IC3PSC_Pos (2U)
18429#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
18430#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
18431#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
18432#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
18434#define TIM_CCMR2_IC3F_Pos (4U)
18435#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
18436#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
18437#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
18438#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
18439#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
18440#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
18442#define TIM_CCMR2_IC4PSC_Pos (10U)
18443#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
18444#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
18445#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
18446#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
18448#define TIM_CCMR2_IC4F_Pos (12U)
18449#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
18450#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
18451#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
18452#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
18453#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
18454#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
18456/******************* Bit definition for TIM_CCER register *******************/
18457#define TIM_CCER_CC1E_Pos (0U)
18458#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
18459#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
18460#define TIM_CCER_CC1P_Pos (1U)
18461#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
18462#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
18463#define TIM_CCER_CC1NE_Pos (2U)
18464#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
18465#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
18466#define TIM_CCER_CC1NP_Pos (3U)
18467#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
18468#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
18469#define TIM_CCER_CC2E_Pos (4U)
18470#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
18471#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
18472#define TIM_CCER_CC2P_Pos (5U)
18473#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
18474#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
18475#define TIM_CCER_CC2NE_Pos (6U)
18476#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
18477#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
18478#define TIM_CCER_CC2NP_Pos (7U)
18479#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
18480#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
18481#define TIM_CCER_CC3E_Pos (8U)
18482#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
18483#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
18484#define TIM_CCER_CC3P_Pos (9U)
18485#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
18486#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
18487#define TIM_CCER_CC3NE_Pos (10U)
18488#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
18489#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
18490#define TIM_CCER_CC3NP_Pos (11U)
18491#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
18492#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
18493#define TIM_CCER_CC4E_Pos (12U)
18494#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
18495#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
18496#define TIM_CCER_CC4P_Pos (13U)
18497#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
18498#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
18499#define TIM_CCER_CC4NP_Pos (15U)
18500#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
18501#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
18502#define TIM_CCER_CC5E_Pos (16U)
18503#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
18504#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
18505#define TIM_CCER_CC5P_Pos (17U)
18506#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
18507#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
18508#define TIM_CCER_CC6E_Pos (20U)
18509#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
18510#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
18511#define TIM_CCER_CC6P_Pos (21U)
18512#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
18513#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
18514/******************* Bit definition for TIM_CNT register ********************/
18515#define TIM_CNT_CNT_Pos (0U)
18516#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
18517#define TIM_CNT_CNT TIM_CNT_CNT_Msk
18518#define TIM_CNT_UIFCPY_Pos (31U)
18519#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
18520#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
18521/******************* Bit definition for TIM_PSC register ********************/
18522#define TIM_PSC_PSC_Pos (0U)
18523#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
18524#define TIM_PSC_PSC TIM_PSC_PSC_Msk
18526/******************* Bit definition for TIM_ARR register ********************/
18527#define TIM_ARR_ARR_Pos (0U)
18528#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
18529#define TIM_ARR_ARR TIM_ARR_ARR_Msk
18531/******************* Bit definition for TIM_RCR register ********************/
18532#define TIM_RCR_REP_Pos (0U)
18533#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
18534#define TIM_RCR_REP TIM_RCR_REP_Msk
18536/******************* Bit definition for TIM_CCR1 register *******************/
18537#define TIM_CCR1_CCR1_Pos (0U)
18538#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
18539#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
18541/******************* Bit definition for TIM_CCR2 register *******************/
18542#define TIM_CCR2_CCR2_Pos (0U)
18543#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
18544#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
18546/******************* Bit definition for TIM_CCR3 register *******************/
18547#define TIM_CCR3_CCR3_Pos (0U)
18548#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
18549#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
18551/******************* Bit definition for TIM_CCR4 register *******************/
18552#define TIM_CCR4_CCR4_Pos (0U)
18553#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
18554#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
18556/******************* Bit definition for TIM_CCR5 register *******************/
18557#define TIM_CCR5_CCR5_Pos (0U)
18558#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
18559#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
18560#define TIM_CCR5_GC5C1_Pos (29U)
18561#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
18562#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
18563#define TIM_CCR5_GC5C2_Pos (30U)
18564#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
18565#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
18566#define TIM_CCR5_GC5C3_Pos (31U)
18567#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
18568#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
18570/******************* Bit definition for TIM_CCR6 register *******************/
18571#define TIM_CCR6_CCR6_Pos (0U)
18572#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
18573#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
18575/******************* Bit definition for TIM_BDTR register *******************/
18576#define TIM_BDTR_DTG_Pos (0U)
18577#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
18578#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
18579#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
18580#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
18581#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
18582#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
18583#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
18584#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
18585#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
18586#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
18588#define TIM_BDTR_LOCK_Pos (8U)
18589#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
18590#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
18591#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
18592#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
18594#define TIM_BDTR_OSSI_Pos (10U)
18595#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
18596#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
18597#define TIM_BDTR_OSSR_Pos (11U)
18598#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
18599#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
18600#define TIM_BDTR_BKE_Pos (12U)
18601#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
18602#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
18603#define TIM_BDTR_BKP_Pos (13U)
18604#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
18605#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
18606#define TIM_BDTR_AOE_Pos (14U)
18607#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
18608#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
18609#define TIM_BDTR_MOE_Pos (15U)
18610#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
18611#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
18613#define TIM_BDTR_BKF_Pos (16U)
18614#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
18615#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
18616#define TIM_BDTR_BK2F_Pos (20U)
18617#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
18618#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
18620#define TIM_BDTR_BK2E_Pos (24U)
18621#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
18622#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
18623#define TIM_BDTR_BK2P_Pos (25U)
18624#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
18625#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
18626#define TIM_BDTR_BKDSRM_Pos (26U)
18627#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos)
18628#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk
18629#define TIM_BDTR_BK2DSRM_Pos (27U)
18630#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos)
18631#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk
18632#define TIM_BDTR_BKBID_Pos (28U)
18633#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos)
18634#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk
18635#define TIM_BDTR_BK2BID_Pos (29U)
18636#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos)
18637#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk
18639/******************* Bit definition for TIM_DCR register ********************/
18640#define TIM_DCR_DBA_Pos (0U)
18641#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
18642#define TIM_DCR_DBA TIM_DCR_DBA_Msk
18643#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
18644#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
18645#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
18646#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
18647#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
18649#define TIM_DCR_DBL_Pos (8U)
18650#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
18651#define TIM_DCR_DBL TIM_DCR_DBL_Msk
18652#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
18653#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
18654#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
18655#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
18656#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
18658/******************* Bit definition for TIM_DMAR register *******************/
18659#define TIM_DMAR_DMAB_Pos (0U)
18660#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
18661#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
18663/****************** Bit definition for TIM_CCMR3 register *******************/
18664#define TIM_CCMR3_OC5FE_Pos (2U)
18665#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
18666#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
18667#define TIM_CCMR3_OC5PE_Pos (3U)
18668#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
18669#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
18671#define TIM_CCMR3_OC5M_Pos (4U)
18672#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
18673#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
18674#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos)
18675#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos)
18676#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos)
18677#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
18679#define TIM_CCMR3_OC5CE_Pos (7U)
18680#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
18681#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
18683#define TIM_CCMR3_OC6FE_Pos (10U)
18684#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
18685#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
18686#define TIM_CCMR3_OC6PE_Pos (11U)
18687#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
18688#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
18690#define TIM_CCMR3_OC6M_Pos (12U)
18691#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
18692#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
18693#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos)
18694#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos)
18695#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos)
18696#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
18698#define TIM_CCMR3_OC6CE_Pos (15U)
18699#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
18700#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
18701/******************* Bit definition for TIM1_AF1 register *********************/
18702#define TIM1_AF1_BKINE_Pos (0U)
18703#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
18704#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
18705#define TIM1_AF1_BKCMP1E_Pos (1U)
18706#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
18707#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
18708#define TIM1_AF1_BKCMP2E_Pos (2U)
18709#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
18710#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
18711#define TIM1_AF1_BKDF1BK0E_Pos (8U)
18712#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
18713#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk
18714#define TIM1_AF1_BKINP_Pos (9U)
18715#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
18716#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
18717#define TIM1_AF1_BKCMP1P_Pos (10U)
18718#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
18719#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
18720#define TIM1_AF1_BKCMP2P_Pos (11U)
18721#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
18722#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
18724#define TIM1_AF1_ETRSEL_Pos (14U)
18725#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
18726#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
18727#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
18728#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
18729#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
18730#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
18732/******************* Bit definition for TIM1_AF2 register *********************/
18733#define TIM1_AF2_BK2INE_Pos (0U)
18734#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
18735#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
18736#define TIM1_AF2_BK2CMP1E_Pos (1U)
18737#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
18738#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
18739#define TIM1_AF2_BK2CMP2E_Pos (2U)
18740#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
18741#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
18742#define TIM1_AF2_BK2DFBK1E_Pos (8U)
18743#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
18744#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk
18745#define TIM1_AF2_BK2INP_Pos (9U)
18746#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
18747#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
18748#define TIM1_AF2_BK2CMP1P_Pos (10U)
18749#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
18750#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
18751#define TIM1_AF2_BK2CMP2P_Pos (11U)
18752#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
18753#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
18755/******************* Bit definition for TIM_TISEL register *********************/
18756#define TIM_TISEL_TI1SEL_Pos (0U)
18757#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
18758#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
18759#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
18760#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
18761#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
18762#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
18764#define TIM_TISEL_TI2SEL_Pos (8U)
18765#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
18766#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
18767#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
18768#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
18769#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
18770#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
18772#define TIM_TISEL_TI3SEL_Pos (16U)
18773#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
18774#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
18775#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
18776#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
18777#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
18778#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
18780#define TIM_TISEL_TI4SEL_Pos (24U)
18781#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
18782#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
18783#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
18784#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
18785#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
18786#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
18788/******************* Bit definition for TIM8_AF1 register *********************/
18789#define TIM8_AF1_BKINE_Pos (0U)
18790#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
18791#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
18792#define TIM8_AF1_BKCMP1E_Pos (1U)
18793#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos)
18794#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk
18795#define TIM8_AF1_BKCMP2E_Pos (2U)
18796#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos)
18797#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk
18798#define TIM8_AF1_BKDFBK2E_Pos (8U)
18799#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
18800#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk
18801#define TIM8_AF1_BKINP_Pos (9U)
18802#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
18803#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
18804#define TIM8_AF1_BKCMP1P_Pos (10U)
18805#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos)
18806#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk
18807#define TIM8_AF1_BKCMP2P_Pos (11U)
18808#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos)
18809#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk
18811#define TIM8_AF1_ETRSEL_Pos (14U)
18812#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos)
18813#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk
18814#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos)
18815#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos)
18816#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos)
18817#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos)
18818/******************* Bit definition for TIM8_AF2 register *********************/
18819#define TIM8_AF2_BK2INE_Pos (0U)
18820#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
18821#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
18822#define TIM8_AF2_BK2CMP1E_Pos (1U)
18823#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
18824#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk
18825#define TIM8_AF2_BK2CMP2E_Pos (2U)
18826#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
18827#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk
18828#define TIM8_AF2_BK2DFBK3E_Pos (8U)
18829#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
18830#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk
18831#define TIM8_AF2_BK2INP_Pos (9U)
18832#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
18833#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
18834#define TIM8_AF2_BK2CMP1P_Pos (10U)
18835#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
18836#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk
18837#define TIM8_AF2_BK2CMP2P_Pos (11U)
18838#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
18839#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk
18841/******************* Bit definition for TIM2_AF1 register *********************/
18842#define TIM2_AF1_ETRSEL_Pos (14U)
18843#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)
18844#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk
18845#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos)
18846#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos)
18847#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos)
18848#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos)
18850/******************* Bit definition for TIM3_AF1 register *********************/
18851#define TIM3_AF1_ETRSEL_Pos (14U)
18852#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)
18853#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk
18854#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)
18855#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)
18856#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)
18857#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)
18859/******************* Bit definition for TIM5_AF1 register *********************/
18860#define TIM5_AF1_ETRSEL_Pos (14U)
18861#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos)
18862#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk
18863#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos)
18864#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos)
18865#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos)
18866#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos)
18868/******************* Bit definition for TIM15_AF1 register *********************/
18869#define TIM15_AF1_BKINE_Pos (0U)
18870#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos)
18871#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk
18872#define TIM15_AF1_BKCMP1E_Pos (1U)
18873#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos)
18874#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk
18875#define TIM15_AF1_BKCMP2E_Pos (2U)
18876#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos)
18877#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk
18878#define TIM15_AF1_BKDF1BK2E_Pos (8U)
18879#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
18880#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk
18881#define TIM15_AF1_BKINP_Pos (9U)
18882#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos)
18883#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk
18884#define TIM15_AF1_BKCMP1P_Pos (10U)
18885#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos)
18886#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk
18887#define TIM15_AF1_BKCMP2P_Pos (11U)
18888#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
18889#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk
18891/******************* Bit definition for TIM16_ register *********************/
18892#define TIM16_AF1_BKINE_Pos (0U)
18893#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)
18894#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk
18895#define TIM16_AF1_BKCMP1E_Pos (1U)
18896#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)
18897#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk
18898#define TIM16_AF1_BKCMP2E_Pos (2U)
18899#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)
18900#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk
18901#define TIM16_AF1_BKDF1BK2E_Pos (8U)
18902#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
18903#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk
18904#define TIM16_AF1_BKINP_Pos (9U)
18905#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)
18906#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk
18907#define TIM16_AF1_BKCMP1P_Pos (10U)
18908#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)
18909#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk
18910#define TIM16_AF1_BKCMP2P_Pos (11U)
18911#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)
18912#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk
18914/******************* Bit definition for TIM17_AF1 register *********************/
18915#define TIM17_AF1_BKINE_Pos (0U)
18916#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)
18917#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk
18918#define TIM17_AF1_BKCMP1E_Pos (1U)
18919#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)
18920#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk
18921#define TIM17_AF1_BKCMP2E_Pos (2U)
18922#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)
18923#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk
18924#define TIM17_AF1_BKDF1BK2E_Pos (8U)
18925#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
18926#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk
18927#define TIM17_AF1_BKINP_Pos (9U)
18928#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)
18929#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk
18930#define TIM17_AF1_BKCMP1P_Pos (10U)
18931#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)
18932#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk
18933#define TIM17_AF1_BKCMP2P_Pos (11U)
18934#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)
18935#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk
18937/******************************************************************************/
18938/* */
18939/* Low Power Timer (LPTTIM) */
18940/* */
18941/******************************************************************************/
18942/****************** Bit definition for LPTIM_ISR register *******************/
18943#define LPTIM_ISR_CMPM_Pos (0U)
18944#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
18945#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
18946#define LPTIM_ISR_ARRM_Pos (1U)
18947#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
18948#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
18949#define LPTIM_ISR_EXTTRIG_Pos (2U)
18950#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
18951#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
18952#define LPTIM_ISR_CMPOK_Pos (3U)
18953#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
18954#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
18955#define LPTIM_ISR_ARROK_Pos (4U)
18956#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
18957#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
18958#define LPTIM_ISR_UP_Pos (5U)
18959#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
18960#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
18961#define LPTIM_ISR_DOWN_Pos (6U)
18962#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
18963#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
18965/****************** Bit definition for LPTIM_ICR register *******************/
18966#define LPTIM_ICR_CMPMCF_Pos (0U)
18967#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
18968#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
18969#define LPTIM_ICR_ARRMCF_Pos (1U)
18970#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
18971#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
18972#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
18973#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
18974#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
18975#define LPTIM_ICR_CMPOKCF_Pos (3U)
18976#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
18977#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
18978#define LPTIM_ICR_ARROKCF_Pos (4U)
18979#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
18980#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
18981#define LPTIM_ICR_UPCF_Pos (5U)
18982#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
18983#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
18984#define LPTIM_ICR_DOWNCF_Pos (6U)
18985#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
18986#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
18988/****************** Bit definition for LPTIM_IER register ********************/
18989#define LPTIM_IER_CMPMIE_Pos (0U)
18990#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
18991#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
18992#define LPTIM_IER_ARRMIE_Pos (1U)
18993#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
18994#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
18995#define LPTIM_IER_EXTTRIGIE_Pos (2U)
18996#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
18997#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
18998#define LPTIM_IER_CMPOKIE_Pos (3U)
18999#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
19000#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
19001#define LPTIM_IER_ARROKIE_Pos (4U)
19002#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
19003#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
19004#define LPTIM_IER_UPIE_Pos (5U)
19005#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
19006#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
19007#define LPTIM_IER_DOWNIE_Pos (6U)
19008#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
19009#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
19011/****************** Bit definition for LPTIM_CFGR register *******************/
19012#define LPTIM_CFGR_CKSEL_Pos (0U)
19013#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
19014#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
19016#define LPTIM_CFGR_CKPOL_Pos (1U)
19017#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
19018#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
19019#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
19020#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
19022#define LPTIM_CFGR_CKFLT_Pos (3U)
19023#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
19024#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
19025#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
19026#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
19028#define LPTIM_CFGR_TRGFLT_Pos (6U)
19029#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
19030#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
19031#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
19032#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
19034#define LPTIM_CFGR_PRESC_Pos (9U)
19035#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
19036#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
19037#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
19038#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
19039#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
19041#define LPTIM_CFGR_TRIGSEL_Pos (13U)
19042#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
19043#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
19044#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
19045#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
19046#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
19048#define LPTIM_CFGR_TRIGEN_Pos (17U)
19049#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
19050#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
19051#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
19052#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
19054#define LPTIM_CFGR_TIMOUT_Pos (19U)
19055#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
19056#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
19057#define LPTIM_CFGR_WAVE_Pos (20U)
19058#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
19059#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
19060#define LPTIM_CFGR_WAVPOL_Pos (21U)
19061#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
19062#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
19063#define LPTIM_CFGR_PRELOAD_Pos (22U)
19064#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
19065#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
19066#define LPTIM_CFGR_COUNTMODE_Pos (23U)
19067#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
19068#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
19069#define LPTIM_CFGR_ENC_Pos (24U)
19070#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
19071#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
19073/****************** Bit definition for LPTIM_CR register ********************/
19074#define LPTIM_CR_ENABLE_Pos (0U)
19075#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
19076#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
19077#define LPTIM_CR_SNGSTRT_Pos (1U)
19078#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
19079#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
19080#define LPTIM_CR_CNTSTRT_Pos (2U)
19081#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
19082#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
19083#define LPTIM_CR_COUNTRST_Pos (3U)
19084#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
19085#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
19086#define LPTIM_CR_RSTARE_Pos (4U)
19087#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
19088#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
19091/****************** Bit definition for LPTIM_CMP register *******************/
19092#define LPTIM_CMP_CMP_Pos (0U)
19093#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
19094#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
19096/****************** Bit definition for LPTIM_ARR register *******************/
19097#define LPTIM_ARR_ARR_Pos (0U)
19098#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
19099#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
19101/****************** Bit definition for LPTIM_CNT register *******************/
19102#define LPTIM_CNT_CNT_Pos (0U)
19103#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
19104#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
19106/****************** Bit definition for LPTIM_CFGR2 register *****************/
19107#define LPTIM_CFGR2_IN1SEL_Pos (0U)
19108#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
19109#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk
19110#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
19111#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
19112#define LPTIM_CFGR2_IN2SEL_Pos (4U)
19113#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
19114#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk
19115#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
19116#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
19118/******************************************************************************/
19119/* */
19120/* OCTOSPI */
19121/* */
19122/******************************************************************************/
19123/***************** Bit definition for OCTOSPI_CR register *******************/
19124#define OCTOSPI_CR_EN_Pos (0U)
19125#define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos)
19126#define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk
19127#define OCTOSPI_CR_ABORT_Pos (1U)
19128#define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos)
19129#define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk
19130#define OCTOSPI_CR_DMAEN_Pos (2U)
19131#define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos)
19132#define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk
19133#define OCTOSPI_CR_TCEN_Pos (3U)
19134#define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos)
19135#define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk
19136#define OCTOSPI_CR_DQM_Pos (6U)
19137#define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos)
19138#define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk
19139#define OCTOSPI_CR_FSEL_Pos (7U)
19140#define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos)
19141#define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk
19142#define OCTOSPI_CR_FTHRES_Pos (8U)
19143#define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos)
19144#define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk
19145#define OCTOSPI_CR_TEIE_Pos (16U)
19146#define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos)
19147#define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk
19148#define OCTOSPI_CR_TCIE_Pos (17U)
19149#define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos)
19150#define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk
19151#define OCTOSPI_CR_FTIE_Pos (18U)
19152#define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos)
19153#define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk
19154#define OCTOSPI_CR_SMIE_Pos (19U)
19155#define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos)
19156#define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk
19157#define OCTOSPI_CR_TOIE_Pos (20U)
19158#define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos)
19159#define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk
19160#define OCTOSPI_CR_APMS_Pos (22U)
19161#define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos)
19162#define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk
19163#define OCTOSPI_CR_PMM_Pos (23U)
19164#define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos)
19165#define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk
19166#define OCTOSPI_CR_FMODE_Pos (28U)
19167#define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos)
19168#define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk
19169#define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos)
19170#define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos)
19172/**************** Bit definition for OCTOSPI_DCR1 register ******************/
19173#define OCTOSPI_DCR1_CKMODE_Pos (0U)
19174#define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)
19175#define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk
19176#define OCTOSPI_DCR1_FRCK_Pos (1U)
19177#define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos)
19178#define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk
19179#define OCTOSPI_DCR1_DLYBYP_Pos (3U)
19180#define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)
19181#define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk
19182#define OCTOSPI_DCR1_CSHT_Pos (8U)
19183#define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos)
19184#define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk
19185#define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
19186#define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)
19187#define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk
19188#define OCTOSPI_DCR1_MTYP_Pos (24U)
19189#define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos)
19190#define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk
19191#define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos)
19192#define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos)
19193#define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos)
19195/* Legacy define */
19196#define OCTOSPI_DCR1_CKCSHT_Pos (4U)
19197#define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)
19198#define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk
19200/**************** Bit definition for OCTOSPI_DCR2 register ******************/
19201#define OCTOSPI_DCR2_PRESCALER_Pos (0U)
19202#define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)
19203#define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk
19204#define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
19205#define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
19206#define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk
19207#define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
19208#define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
19209#define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)
19211/**************** Bit definition for OCTOSPI_DCR3 register ******************/
19212#define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
19213#define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)
19214#define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk
19215#define OCTOSPI_DCR3_CSBOUND_Pos (16U)
19216#define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)
19217#define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk
19219/**************** Bit definition for OCTOSPI_DCR4 register ******************/
19220#define OCTOSPI_DCR4_REFRESH_Pos (0U)
19221#define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos)
19222#define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk
19224/***************** Bit definition for OCTOSPI_SR register *******************/
19225#define OCTOSPI_SR_TEF_Pos (0U)
19226#define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos)
19227#define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk
19228#define OCTOSPI_SR_TCF_Pos (1U)
19229#define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos)
19230#define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk
19231#define OCTOSPI_SR_FTF_Pos (2U)
19232#define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos)
19233#define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk
19234#define OCTOSPI_SR_SMF_Pos (3U)
19235#define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos)
19236#define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk
19237#define OCTOSPI_SR_TOF_Pos (4U)
19238#define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos)
19239#define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk
19240#define OCTOSPI_SR_BUSY_Pos (5U)
19241#define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos)
19242#define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk
19243#define OCTOSPI_SR_FLEVEL_Pos (8U)
19244#define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)
19245#define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk
19247/**************** Bit definition for OCTOSPI_FCR register *******************/
19248#define OCTOSPI_FCR_CTEF_Pos (0U)
19249#define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos)
19250#define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk
19251#define OCTOSPI_FCR_CTCF_Pos (1U)
19252#define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos)
19253#define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk
19254#define OCTOSPI_FCR_CSMF_Pos (3U)
19255#define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos)
19256#define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk
19257#define OCTOSPI_FCR_CTOF_Pos (4U)
19258#define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos)
19259#define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk
19261/**************** Bit definition for OCTOSPI_DLR register *******************/
19262#define OCTOSPI_DLR_DL_Pos (0U)
19263#define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)
19264#define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk
19266/***************** Bit definition for OCTOSPI_AR register *******************/
19267#define OCTOSPI_AR_ADDRESS_Pos (0U)
19268#define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos)
19269#define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk
19271/***************** Bit definition for OCTOSPI_DR register *******************/
19272#define OCTOSPI_DR_DATA_Pos (0U)
19273#define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)
19274#define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk
19276/*************** Bit definition for OCTOSPI_PSMKR register ******************/
19277#define OCTOSPI_PSMKR_MASK_Pos (0U)
19278#define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos)
19279#define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk
19281/*************** Bit definition for OCTOSPI_PSMAR register ******************/
19282#define OCTOSPI_PSMAR_MATCH_Pos (0U)
19283#define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos)
19284#define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk
19286/**************** Bit definition for OCTOSPI_PIR register *******************/
19287#define OCTOSPI_PIR_INTERVAL_Pos (0U)
19288#define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)
19289#define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk
19291/**************** Bit definition for OCTOSPI_CCR register *******************/
19292#define OCTOSPI_CCR_IMODE_Pos (0U)
19293#define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos)
19294#define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk
19295#define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos)
19296#define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos)
19297#define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos)
19298#define OCTOSPI_CCR_IDTR_Pos (3U)
19299#define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos)
19300#define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk
19301#define OCTOSPI_CCR_ISIZE_Pos (4U)
19302#define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos)
19303#define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk
19304#define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos)
19305#define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos)
19306#define OCTOSPI_CCR_ADMODE_Pos (8U)
19307#define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos)
19308#define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk
19309#define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos)
19310#define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos)
19311#define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos)
19312#define OCTOSPI_CCR_ADDTR_Pos (11U)
19313#define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos)
19314#define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk
19315#define OCTOSPI_CCR_ADSIZE_Pos (12U)
19316#define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)
19317#define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk
19318#define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)
19319#define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)
19320#define OCTOSPI_CCR_ABMODE_Pos (16U)
19321#define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos)
19322#define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk
19323#define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos)
19324#define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos)
19325#define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos)
19326#define OCTOSPI_CCR_ABDTR_Pos (19U)
19327#define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos)
19328#define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk
19329#define OCTOSPI_CCR_ABSIZE_Pos (20U)
19330#define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)
19331#define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk
19332#define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)
19333#define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)
19334#define OCTOSPI_CCR_DMODE_Pos (24U)
19335#define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos)
19336#define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk
19337#define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos)
19338#define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos)
19339#define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos)
19340#define OCTOSPI_CCR_DDTR_Pos (27U)
19341#define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos)
19342#define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk
19343#define OCTOSPI_CCR_DQSE_Pos (29U)
19344#define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos)
19345#define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk
19346#define OCTOSPI_CCR_SIOO_Pos (31U)
19347#define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos)
19348#define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk
19350/**************** Bit definition for OCTOSPI_TCR register *******************/
19351#define OCTOSPI_TCR_DCYC_Pos (0U)
19352#define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos)
19353#define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk
19354#define OCTOSPI_TCR_DHQC_Pos (28U)
19355#define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos)
19356#define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk
19357#define OCTOSPI_TCR_SSHIFT_Pos (30U)
19358#define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)
19359#define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk
19361/***************** Bit definition for OCTOSPI_IR register *******************/
19362#define OCTOSPI_IR_INSTRUCTION_Pos (0U)
19363#define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos)
19364#define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk
19366/**************** Bit definition for OCTOSPI_ABR register *******************/
19367#define OCTOSPI_ABR_ALTERNATE_Pos (0U)
19368#define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos)
19369#define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk
19371/**************** Bit definition for OCTOSPI_LPTR register ******************/
19372#define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
19373#define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)
19374#define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk
19376/**************** Bit definition for OCTOSPI_WPCCR register *******************/
19377#define OCTOSPI_WPCCR_IMODE_Pos (0U)
19378#define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)
19379#define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk
19380#define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)
19381#define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)
19382#define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)
19383#define OCTOSPI_WPCCR_IDTR_Pos (3U)
19384#define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)
19385#define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk
19386#define OCTOSPI_WPCCR_ISIZE_Pos (4U)
19387#define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)
19388#define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk
19389#define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)
19390#define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)
19391#define OCTOSPI_WPCCR_ADMODE_Pos (8U)
19392#define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)
19393#define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk
19394#define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)
19395#define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)
19396#define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)
19397#define OCTOSPI_WPCCR_ADDTR_Pos (11U)
19398#define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)
19399#define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk
19400#define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
19401#define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)
19402#define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk
19403#define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)
19404#define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)
19405#define OCTOSPI_WPCCR_ABMODE_Pos (16U)
19406#define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)
19407#define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk
19408#define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)
19409#define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)
19410#define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)
19411#define OCTOSPI_WPCCR_ABDTR_Pos (19U)
19412#define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)
19413#define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk
19414#define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
19415#define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)
19416#define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk
19417#define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)
19418#define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)
19419#define OCTOSPI_WPCCR_DMODE_Pos (24U)
19420#define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)
19421#define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk
19422#define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)
19423#define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)
19424#define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)
19425#define OCTOSPI_WPCCR_DDTR_Pos (27U)
19426#define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)
19427#define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk
19428#define OCTOSPI_WPCCR_DQSE_Pos (29U)
19429#define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)
19430#define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk
19431#define OCTOSPI_WPCCR_SIOO_Pos (31U)
19432#define OCTOSPI_WPCCR_SIOO_Msk (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)
19433#define OCTOSPI_WPCCR_SIOO OCTOSPI_WPCCR_SIOO_Msk
19435/**************** Bit definition for OCTOSPI_WPTCR register *******************/
19436#define OCTOSPI_WPTCR_DCYC_Pos (0U)
19437#define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)
19438#define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk
19439#define OCTOSPI_WPTCR_DHQC_Pos (28U)
19440#define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)
19441#define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk
19442#define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
19443#define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)
19444#define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk
19446/***************** Bit definition for OCTOSPI_WPIR register *******************/
19447#define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
19448#define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos)
19449#define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk
19451/**************** Bit definition for OCTOSPI_WPABR register *******************/
19452#define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
19453#define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos)
19454#define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk
19456/**************** Bit definition for OCTOSPI_WCCR register ******************/
19457#define OCTOSPI_WCCR_IMODE_Pos (0U)
19458#define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos)
19459#define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk
19460#define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos)
19461#define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos)
19462#define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos)
19463#define OCTOSPI_WCCR_IDTR_Pos (3U)
19464#define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos)
19465#define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk
19466#define OCTOSPI_WCCR_ISIZE_Pos (4U)
19467#define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)
19468#define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk
19469#define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)
19470#define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)
19471#define OCTOSPI_WCCR_ADMODE_Pos (8U)
19472#define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)
19473#define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk
19474#define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)
19475#define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)
19476#define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)
19477#define OCTOSPI_WCCR_ADDTR_Pos (11U)
19478#define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)
19479#define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk
19480#define OCTOSPI_WCCR_ADSIZE_Pos (12U)
19481#define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)
19482#define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk
19483#define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)
19484#define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)
19485#define OCTOSPI_WCCR_ABMODE_Pos (16U)
19486#define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)
19487#define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk
19488#define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)
19489#define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)
19490#define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)
19491#define OCTOSPI_WCCR_ABDTR_Pos (19U)
19492#define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)
19493#define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk
19494#define OCTOSPI_WCCR_ABSIZE_Pos (20U)
19495#define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)
19496#define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk
19497#define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)
19498#define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)
19499#define OCTOSPI_WCCR_DMODE_Pos (24U)
19500#define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos)
19501#define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk
19502#define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos)
19503#define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos)
19504#define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos)
19505#define OCTOSPI_WCCR_DDTR_Pos (27U)
19506#define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos)
19507#define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk
19508#define OCTOSPI_WCCR_DQSE_Pos (29U)
19509#define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos)
19510#define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk
19511#define OCTOSPI_WCCR_SIOO_Pos (31U)
19512#define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos)
19513#define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk
19515/**************** Bit definition for OCTOSPI_WTCR register ******************/
19516#define OCTOSPI_WTCR_DCYC_Pos (0U)
19517#define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)
19518#define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk
19520/**************** Bit definition for OCTOSPI_WIR register *******************/
19521#define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
19522#define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos)
19523#define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk
19525/**************** Bit definition for OCTOSPI_WABR register ******************/
19526#define OCTOSPI_WABR_ALTERNATE_Pos (0U)
19527#define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos)
19528#define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk
19530/**************** Bit definition for OCTOSPI_HLCR register ******************/
19531#define OCTOSPI_HLCR_LM_Pos (0U)
19532#define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos)
19533#define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk
19534#define OCTOSPI_HLCR_WZL_Pos (1U)
19535#define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos)
19536#define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk
19537#define OCTOSPI_HLCR_TACC_Pos (8U)
19538#define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos)
19539#define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk
19540#define OCTOSPI_HLCR_TRWR_Pos (16U)
19541#define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)
19542#define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk
19544/**************** Bit definition for OCTOSPI_VER register *******************/
19545#define OCTOSPI_VER_VER_Pos (0U)
19546#define OCTOSPI_VER_VER_Msk (0xFFUL << OCTOSPI_VER_VER_Pos)
19547#define OCTOSPI_VER_VER OCTOSPI_VER_VER_Msk
19549/***************** Bit definition for OCTOSPI_ID register *******************/
19550#define OCTOSPI_ID_ID_Pos (0U)
19551#define OCTOSPI_ID_ID_Msk (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)
19552#define OCTOSPI_ID_ID OCTOSPI_ID_ID_Msk
19554/**************** Bit definition for OCTOSPI_MID register *******************/
19555#define OCTOSPI_MID_MID_Pos (0U)
19556#define OCTOSPI_MID_MID_Msk (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)
19557#define OCTOSPI_MID_MID OCTOSPI_MID_MID_Msk
19559/******************************************************************************/
19560/* */
19561/* OCTOSPIM */
19562/* */
19563/******************************************************************************/
19564
19565/*************** Bit definition for OCTOSPIM_CR register ********************/
19566#define OCTOSPIM_CR_MUXEN_Pos (0U)
19567#define OCTOSPIM_CR_MUXEN_Msk (0x1UL << OCTOSPIM_CR_MUXEN_Pos)
19568#define OCTOSPIM_CR_MUXEN OCTOSPIM_CR_MUXEN_Msk
19569#define OCTOSPIM_CR_REQ2ACK_TIME_Pos (16U)
19570#define OCTOSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)
19571#define OCTOSPIM_CR_REQ2ACK_TIME OCTOSPIM_CR_REQ2ACK_TIME_Msk
19573/*************** Bit definition for OCTOSPIM_PCR register *******************/
19574#define OCTOSPIM_PCR_CLKEN_Pos (0U)
19575#define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)
19576#define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk
19577#define OCTOSPIM_PCR_CLKSRC_Pos (1U)
19578#define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)
19579#define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk
19580#define OCTOSPIM_PCR_DQSEN_Pos (4U)
19581#define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)
19582#define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk
19583#define OCTOSPIM_PCR_DQSSRC_Pos (5U)
19584#define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)
19585#define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk
19586#define OCTOSPIM_PCR_NCSEN_Pos (8U)
19587#define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)
19588#define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk
19589#define OCTOSPIM_PCR_NCSSRC_Pos (9U)
19590#define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)
19591#define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk
19592#define OCTOSPIM_PCR_IOLEN_Pos (16U)
19593#define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)
19594#define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk
19595#define OCTOSPIM_PCR_IOLSRC_Pos (17U)
19596#define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)
19597#define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk
19598#define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)
19599#define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)
19600#define OCTOSPIM_PCR_IOHEN_Pos (24U)
19601#define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)
19602#define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk
19603#define OCTOSPIM_PCR_IOHSRC_Pos (25U)
19604#define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)
19605#define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk
19606#define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)
19607#define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)
19608/******************************************************************************/
19609/* */
19610/* Analog Comparators (COMP) */
19611/* */
19612/******************************************************************************/
19613
19614/******************* Bit definition for COMP_SR register ********************/
19615#define COMP_SR_C1VAL_Pos (0U)
19616#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos)
19617#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
19618#define COMP_SR_C2VAL_Pos (1U)
19619#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos)
19620#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
19621#define COMP_SR_C1IF_Pos (16U)
19622#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos)
19623#define COMP_SR_C1IF COMP_SR_C1IF_Msk
19624#define COMP_SR_C2IF_Pos (17U)
19625#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos)
19626#define COMP_SR_C2IF COMP_SR_C2IF_Msk
19627/******************* Bit definition for COMP_ICFR register ********************/
19628#define COMP_ICFR_C1IF_Pos (16U)
19629#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos)
19630#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
19631#define COMP_ICFR_C2IF_Pos (17U)
19632#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos)
19633#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
19634/******************* Bit definition for COMP_OR register ********************/
19635#define COMP_OR_AFOPA6_Pos (0U)
19636#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos)
19637#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
19638#define COMP_OR_AFOPA8_Pos (1U)
19639#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos)
19640#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
19641#define COMP_OR_AFOPB12_Pos (2U)
19642#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos)
19643#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
19644#define COMP_OR_AFOPE6_Pos (3U)
19645#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos)
19646#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
19647#define COMP_OR_AFOPE15_Pos (4U)
19648#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos)
19649#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
19650#define COMP_OR_AFOPG2_Pos (5U)
19651#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos)
19652#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
19653#define COMP_OR_AFOPG3_Pos (6U)
19654#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos)
19655#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
19656#define COMP_OR_AFOPG4_Pos (7U)
19657#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos)
19658#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
19659#define COMP_OR_AFOPI1_Pos (8U)
19660#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos)
19661#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
19662#define COMP_OR_AFOPI4_Pos (9U)
19663#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos)
19664#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
19665#define COMP_OR_AFOPK2_Pos (10U)
19666#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos)
19667#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
19668
19670#define COMP_CFGRx_EN_Pos (0U)
19671#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos)
19672#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk
19673#define COMP_CFGRx_BRGEN_Pos (1U)
19674#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos)
19675#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk
19676#define COMP_CFGRx_SCALEN_Pos (2U)
19677#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos)
19678#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk
19679#define COMP_CFGRx_POLARITY_Pos (3U)
19680#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos)
19681#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk
19682#define COMP_CFGRx_WINMODE_Pos (4U)
19683#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos)
19684#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk
19685#define COMP_CFGRx_ITEN_Pos (6U)
19686#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos)
19687#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk
19688#define COMP_CFGRx_HYST_Pos (8U)
19689#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos)
19690#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk
19691#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos)
19692#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos)
19693#define COMP_CFGRx_PWRMODE_Pos (12U)
19694#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos)
19695#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk
19696#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos)
19697#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos)
19698#define COMP_CFGRx_INMSEL_Pos (16U)
19699#define COMP_CFGRx_INMSEL_Msk (0xFUL << COMP_CFGRx_INMSEL_Pos)
19700#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk
19701#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos)
19702#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos)
19703#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos)
19704#define COMP_CFGRx_INMSEL_3 (0x8UL << COMP_CFGRx_INMSEL_Pos)
19705#define COMP_CFGRx_INPSEL_Pos (20U)
19706#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos)
19707#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk
19708#define COMP_CFGRx_INP2SEL_Pos (22U)
19709#define COMP_CFGRx_INP2SEL_Msk (0x1UL << COMP_CFGRx_INP2SEL_Pos)
19710#define COMP_CFGRx_INP2SEL COMP_CFGRx_INP2SEL_Msk
19711#define COMP_CFGRx_BLANKING_Pos (24U)
19712#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos)
19713#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk
19714#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos)
19715#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos)
19716#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos)
19717#define COMP_CFGRx_LOCK_Pos (31U)
19718#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos)
19719#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk
19722/******************************************************************************/
19723/* */
19724/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
19725/* */
19726/******************************************************************************/
19727/****************** Bit definition for USART_CR1 register *******************/
19728#define USART_CR1_UE_Pos (0U)
19729#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
19730#define USART_CR1_UE USART_CR1_UE_Msk
19731#define USART_CR1_UESM_Pos (1U)
19732#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
19733#define USART_CR1_UESM USART_CR1_UESM_Msk
19734#define USART_CR1_RE_Pos (2U)
19735#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
19736#define USART_CR1_RE USART_CR1_RE_Msk
19737#define USART_CR1_TE_Pos (3U)
19738#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
19739#define USART_CR1_TE USART_CR1_TE_Msk
19740#define USART_CR1_IDLEIE_Pos (4U)
19741#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
19742#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
19743#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
19744#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
19745#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk
19746#define USART_CR1_TCIE_Pos (6U)
19747#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
19748#define USART_CR1_TCIE USART_CR1_TCIE_Msk
19749#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
19750#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
19751#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk
19752#define USART_CR1_PEIE_Pos (8U)
19753#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
19754#define USART_CR1_PEIE USART_CR1_PEIE_Msk
19755#define USART_CR1_PS_Pos (9U)
19756#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
19757#define USART_CR1_PS USART_CR1_PS_Msk
19758#define USART_CR1_PCE_Pos (10U)
19759#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
19760#define USART_CR1_PCE USART_CR1_PCE_Msk
19761#define USART_CR1_WAKE_Pos (11U)
19762#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
19763#define USART_CR1_WAKE USART_CR1_WAKE_Msk
19764#define USART_CR1_M_Pos (12U)
19765#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
19766#define USART_CR1_M USART_CR1_M_Msk
19767#define USART_CR1_M0_Pos (12U)
19768#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
19769#define USART_CR1_M0 USART_CR1_M0_Msk
19770#define USART_CR1_MME_Pos (13U)
19771#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
19772#define USART_CR1_MME USART_CR1_MME_Msk
19773#define USART_CR1_CMIE_Pos (14U)
19774#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
19775#define USART_CR1_CMIE USART_CR1_CMIE_Msk
19776#define USART_CR1_OVER8_Pos (15U)
19777#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
19778#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
19779#define USART_CR1_DEDT_Pos (16U)
19780#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
19781#define USART_CR1_DEDT USART_CR1_DEDT_Msk
19782#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
19783#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
19784#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
19785#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
19786#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
19787#define USART_CR1_DEAT_Pos (21U)
19788#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
19789#define USART_CR1_DEAT USART_CR1_DEAT_Msk
19790#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
19791#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
19792#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
19793#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
19794#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
19795#define USART_CR1_RTOIE_Pos (26U)
19796#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
19797#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
19798#define USART_CR1_EOBIE_Pos (27U)
19799#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
19800#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
19801#define USART_CR1_M1_Pos (28U)
19802#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
19803#define USART_CR1_M1 USART_CR1_M1_Msk
19804#define USART_CR1_FIFOEN_Pos (29U)
19805#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
19806#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
19807#define USART_CR1_TXFEIE_Pos (30U)
19808#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
19809#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
19810#define USART_CR1_RXFFIE_Pos (31U)
19811#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
19812#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
19814/* Legacy define */
19815#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
19816#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
19817
19818/****************** Bit definition for USART_CR2 register *******************/
19819#define USART_CR2_SLVEN_Pos (0U)
19820#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
19821#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
19822#define USART_CR2_DIS_NSS_Pos (3U)
19823#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
19824#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
19825#define USART_CR2_ADDM7_Pos (4U)
19826#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
19827#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
19828#define USART_CR2_LBDL_Pos (5U)
19829#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
19830#define USART_CR2_LBDL USART_CR2_LBDL_Msk
19831#define USART_CR2_LBDIE_Pos (6U)
19832#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
19833#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
19834#define USART_CR2_LBCL_Pos (8U)
19835#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
19836#define USART_CR2_LBCL USART_CR2_LBCL_Msk
19837#define USART_CR2_CPHA_Pos (9U)
19838#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
19839#define USART_CR2_CPHA USART_CR2_CPHA_Msk
19840#define USART_CR2_CPOL_Pos (10U)
19841#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
19842#define USART_CR2_CPOL USART_CR2_CPOL_Msk
19843#define USART_CR2_CLKEN_Pos (11U)
19844#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
19845#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
19846#define USART_CR2_STOP_Pos (12U)
19847#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
19848#define USART_CR2_STOP USART_CR2_STOP_Msk
19849#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
19850#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
19851#define USART_CR2_LINEN_Pos (14U)
19852#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
19853#define USART_CR2_LINEN USART_CR2_LINEN_Msk
19854#define USART_CR2_SWAP_Pos (15U)
19855#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
19856#define USART_CR2_SWAP USART_CR2_SWAP_Msk
19857#define USART_CR2_RXINV_Pos (16U)
19858#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
19859#define USART_CR2_RXINV USART_CR2_RXINV_Msk
19860#define USART_CR2_TXINV_Pos (17U)
19861#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
19862#define USART_CR2_TXINV USART_CR2_TXINV_Msk
19863#define USART_CR2_DATAINV_Pos (18U)
19864#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
19865#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
19866#define USART_CR2_MSBFIRST_Pos (19U)
19867#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
19868#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
19869#define USART_CR2_ABREN_Pos (20U)
19870#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
19871#define USART_CR2_ABREN USART_CR2_ABREN_Msk
19872#define USART_CR2_ABRMODE_Pos (21U)
19873#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
19874#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
19875#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
19876#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
19877#define USART_CR2_RTOEN_Pos (23U)
19878#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
19879#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
19880#define USART_CR2_ADD_Pos (24U)
19881#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
19882#define USART_CR2_ADD USART_CR2_ADD_Msk
19884/****************** Bit definition for USART_CR3 register *******************/
19885#define USART_CR3_EIE_Pos (0U)
19886#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
19887#define USART_CR3_EIE USART_CR3_EIE_Msk
19888#define USART_CR3_IREN_Pos (1U)
19889#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
19890#define USART_CR3_IREN USART_CR3_IREN_Msk
19891#define USART_CR3_IRLP_Pos (2U)
19892#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
19893#define USART_CR3_IRLP USART_CR3_IRLP_Msk
19894#define USART_CR3_HDSEL_Pos (3U)
19895#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
19896#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
19897#define USART_CR3_NACK_Pos (4U)
19898#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
19899#define USART_CR3_NACK USART_CR3_NACK_Msk
19900#define USART_CR3_SCEN_Pos (5U)
19901#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
19902#define USART_CR3_SCEN USART_CR3_SCEN_Msk
19903#define USART_CR3_DMAR_Pos (6U)
19904#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
19905#define USART_CR3_DMAR USART_CR3_DMAR_Msk
19906#define USART_CR3_DMAT_Pos (7U)
19907#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
19908#define USART_CR3_DMAT USART_CR3_DMAT_Msk
19909#define USART_CR3_RTSE_Pos (8U)
19910#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
19911#define USART_CR3_RTSE USART_CR3_RTSE_Msk
19912#define USART_CR3_CTSE_Pos (9U)
19913#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
19914#define USART_CR3_CTSE USART_CR3_CTSE_Msk
19915#define USART_CR3_CTSIE_Pos (10U)
19916#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
19917#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
19918#define USART_CR3_ONEBIT_Pos (11U)
19919#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
19920#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
19921#define USART_CR3_OVRDIS_Pos (12U)
19922#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
19923#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
19924#define USART_CR3_DDRE_Pos (13U)
19925#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
19926#define USART_CR3_DDRE USART_CR3_DDRE_Msk
19927#define USART_CR3_DEM_Pos (14U)
19928#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
19929#define USART_CR3_DEM USART_CR3_DEM_Msk
19930#define USART_CR3_DEP_Pos (15U)
19931#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
19932#define USART_CR3_DEP USART_CR3_DEP_Msk
19933#define USART_CR3_SCARCNT_Pos (17U)
19934#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
19935#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
19936#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
19937#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
19938#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
19939#define USART_CR3_WUS_Pos (20U)
19940#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
19941#define USART_CR3_WUS USART_CR3_WUS_Msk
19942#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
19943#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
19944#define USART_CR3_WUFIE_Pos (22U)
19945#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
19946#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
19947#define USART_CR3_TXFTIE_Pos (23U)
19948#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
19949#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
19950#define USART_CR3_TCBGTIE_Pos (24U)
19951#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
19952#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
19953#define USART_CR3_RXFTCFG_Pos (25U)
19954#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
19955#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
19956#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
19957#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
19958#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
19959#define USART_CR3_RXFTIE_Pos (28U)
19960#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
19961#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
19962#define USART_CR3_TXFTCFG_Pos (29U)
19963#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
19964#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
19965#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
19966#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
19967#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
19969/****************** Bit definition for USART_BRR register *******************/
19970#define USART_BRR_DIV_FRACTION_Pos (0U)
19971#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
19972#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
19973#define USART_BRR_DIV_MANTISSA_Pos (4U)
19974#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
19975#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
19977/****************** Bit definition for USART_GTPR register ******************/
19978#define USART_GTPR_PSC_Pos (0U)
19979#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
19980#define USART_GTPR_PSC USART_GTPR_PSC_Msk
19981#define USART_GTPR_GT_Pos (8U)
19982#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
19983#define USART_GTPR_GT USART_GTPR_GT_Msk
19985/******************* Bit definition for USART_RTOR register *****************/
19986#define USART_RTOR_RTO_Pos (0U)
19987#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
19988#define USART_RTOR_RTO USART_RTOR_RTO_Msk
19989#define USART_RTOR_BLEN_Pos (24U)
19990#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
19991#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
19993/******************* Bit definition for USART_RQR register ******************/
19994#define USART_RQR_ABRRQ_Pos (0U)
19995#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
19996#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
19997#define USART_RQR_SBKRQ_Pos (1U)
19998#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
19999#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
20000#define USART_RQR_MMRQ_Pos (2U)
20001#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
20002#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
20003#define USART_RQR_RXFRQ_Pos (3U)
20004#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
20005#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
20006#define USART_RQR_TXFRQ_Pos (4U)
20007#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
20008#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
20010/******************* Bit definition for USART_ISR register ******************/
20011#define USART_ISR_PE_Pos (0U)
20012#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
20013#define USART_ISR_PE USART_ISR_PE_Msk
20014#define USART_ISR_FE_Pos (1U)
20015#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
20016#define USART_ISR_FE USART_ISR_FE_Msk
20017#define USART_ISR_NE_Pos (2U)
20018#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
20019#define USART_ISR_NE USART_ISR_NE_Msk
20020#define USART_ISR_ORE_Pos (3U)
20021#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
20022#define USART_ISR_ORE USART_ISR_ORE_Msk
20023#define USART_ISR_IDLE_Pos (4U)
20024#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
20025#define USART_ISR_IDLE USART_ISR_IDLE_Msk
20026#define USART_ISR_RXNE_RXFNE_Pos (5U)
20027#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
20028#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk
20029#define USART_ISR_TC_Pos (6U)
20030#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
20031#define USART_ISR_TC USART_ISR_TC_Msk
20032#define USART_ISR_TXE_TXFNF_Pos (7U)
20033#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)
20034#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk
20035#define USART_ISR_LBDF_Pos (8U)
20036#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
20037#define USART_ISR_LBDF USART_ISR_LBDF_Msk
20038#define USART_ISR_CTSIF_Pos (9U)
20039#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
20040#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
20041#define USART_ISR_CTS_Pos (10U)
20042#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
20043#define USART_ISR_CTS USART_ISR_CTS_Msk
20044#define USART_ISR_RTOF_Pos (11U)
20045#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
20046#define USART_ISR_RTOF USART_ISR_RTOF_Msk
20047#define USART_ISR_EOBF_Pos (12U)
20048#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
20049#define USART_ISR_EOBF USART_ISR_EOBF_Msk
20050#define USART_ISR_UDR_Pos (13U)
20051#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
20052#define USART_ISR_UDR USART_ISR_UDR_Msk
20053#define USART_ISR_ABRE_Pos (14U)
20054#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
20055#define USART_ISR_ABRE USART_ISR_ABRE_Msk
20056#define USART_ISR_ABRF_Pos (15U)
20057#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
20058#define USART_ISR_ABRF USART_ISR_ABRF_Msk
20059#define USART_ISR_BUSY_Pos (16U)
20060#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
20061#define USART_ISR_BUSY USART_ISR_BUSY_Msk
20062#define USART_ISR_CMF_Pos (17U)
20063#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
20064#define USART_ISR_CMF USART_ISR_CMF_Msk
20065#define USART_ISR_SBKF_Pos (18U)
20066#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
20067#define USART_ISR_SBKF USART_ISR_SBKF_Msk
20068#define USART_ISR_RWU_Pos (19U)
20069#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
20070#define USART_ISR_RWU USART_ISR_RWU_Msk
20071#define USART_ISR_WUF_Pos (20U)
20072#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
20073#define USART_ISR_WUF USART_ISR_WUF_Msk
20074#define USART_ISR_TEACK_Pos (21U)
20075#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
20076#define USART_ISR_TEACK USART_ISR_TEACK_Msk
20077#define USART_ISR_REACK_Pos (22U)
20078#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
20079#define USART_ISR_REACK USART_ISR_REACK_Msk
20080#define USART_ISR_TXFE_Pos (23U)
20081#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
20082#define USART_ISR_TXFE USART_ISR_TXFE_Msk
20083#define USART_ISR_RXFF_Pos (24U)
20084#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
20085#define USART_ISR_RXFF USART_ISR_RXFF_Msk
20086#define USART_ISR_TCBGT_Pos (25U)
20087#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
20088#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
20089#define USART_ISR_RXFT_Pos (26U)
20090#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
20091#define USART_ISR_RXFT USART_ISR_RXFT_Msk
20092#define USART_ISR_TXFT_Pos (27U)
20093#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
20094#define USART_ISR_TXFT USART_ISR_TXFT_Msk
20096/******************* Bit definition for USART_ICR register ******************/
20097#define USART_ICR_PECF_Pos (0U)
20098#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
20099#define USART_ICR_PECF USART_ICR_PECF_Msk
20100#define USART_ICR_FECF_Pos (1U)
20101#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
20102#define USART_ICR_FECF USART_ICR_FECF_Msk
20103#define USART_ICR_NECF_Pos (2U)
20104#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
20105#define USART_ICR_NECF USART_ICR_NECF_Msk
20106#define USART_ICR_ORECF_Pos (3U)
20107#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
20108#define USART_ICR_ORECF USART_ICR_ORECF_Msk
20109#define USART_ICR_IDLECF_Pos (4U)
20110#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
20111#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
20112#define USART_ICR_TXFECF_Pos (5U)
20113#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
20114#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
20115#define USART_ICR_TCCF_Pos (6U)
20116#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
20117#define USART_ICR_TCCF USART_ICR_TCCF_Msk
20118#define USART_ICR_TCBGTCF_Pos (7U)
20119#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
20120#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
20121#define USART_ICR_LBDCF_Pos (8U)
20122#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
20123#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
20124#define USART_ICR_CTSCF_Pos (9U)
20125#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
20126#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
20127#define USART_ICR_RTOCF_Pos (11U)
20128#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
20129#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
20130#define USART_ICR_EOBCF_Pos (12U)
20131#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
20132#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
20133#define USART_ICR_UDRCF_Pos (13U)
20134#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
20135#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
20136#define USART_ICR_CMCF_Pos (17U)
20137#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
20138#define USART_ICR_CMCF USART_ICR_CMCF_Msk
20139#define USART_ICR_WUCF_Pos (20U)
20140#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
20141#define USART_ICR_WUCF USART_ICR_WUCF_Msk
20143/******************* Bit definition for USART_RDR register ******************/
20144#define USART_RDR_RDR_Pos (0U)
20145#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
20146#define USART_RDR_RDR USART_RDR_RDR_Msk
20148/******************* Bit definition for USART_TDR register ******************/
20149#define USART_TDR_TDR_Pos (0U)
20150#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
20151#define USART_TDR_TDR USART_TDR_TDR_Msk
20153/******************* Bit definition for USART_PRESC register ******************/
20154#define USART_PRESC_PRESCALER_Pos (0U)
20155#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
20156#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
20157#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
20158#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
20159#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
20160#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
20162/******************************************************************************/
20163/* */
20164/* Single Wire Protocol Master Interface (SWPMI) */
20165/* */
20166/******************************************************************************/
20167
20168/******************* Bit definition for SWPMI_CR register ********************/
20169#define SWPMI_CR_RXDMA_Pos (0U)
20170#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
20171#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
20172#define SWPMI_CR_TXDMA_Pos (1U)
20173#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
20174#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
20175#define SWPMI_CR_RXMODE_Pos (2U)
20176#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
20177#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
20178#define SWPMI_CR_TXMODE_Pos (3U)
20179#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
20180#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
20181#define SWPMI_CR_LPBK_Pos (4U)
20182#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
20183#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
20184#define SWPMI_CR_SWPACT_Pos (5U)
20185#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
20186#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
20187#define SWPMI_CR_DEACT_Pos (10U)
20188#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
20189#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
20190#define SWPMI_CR_SWPEN_Pos (11U)
20191#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos)
20192#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk
20194/******************* Bit definition for SWPMI_BRR register ********************/
20195#define SWPMI_BRR_BR_Pos (0U)
20196#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos)
20197#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
20199/******************* Bit definition for SWPMI_ISR register ********************/
20200#define SWPMI_ISR_RXBFF_Pos (0U)
20201#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
20202#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
20203#define SWPMI_ISR_TXBEF_Pos (1U)
20204#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
20205#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
20206#define SWPMI_ISR_RXBERF_Pos (2U)
20207#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
20208#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
20209#define SWPMI_ISR_RXOVRF_Pos (3U)
20210#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
20211#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
20212#define SWPMI_ISR_TXUNRF_Pos (4U)
20213#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
20214#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
20215#define SWPMI_ISR_RXNE_Pos (5U)
20216#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
20217#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
20218#define SWPMI_ISR_TXE_Pos (6U)
20219#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
20220#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
20221#define SWPMI_ISR_TCF_Pos (7U)
20222#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
20223#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
20224#define SWPMI_ISR_SRF_Pos (8U)
20225#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
20226#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
20227#define SWPMI_ISR_SUSP_Pos (9U)
20228#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
20229#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
20230#define SWPMI_ISR_DEACTF_Pos (10U)
20231#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
20232#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
20233#define SWPMI_ISR_RDYF_Pos (11U)
20234#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos)
20235#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk
20237/******************* Bit definition for SWPMI_ICR register ********************/
20238#define SWPMI_ICR_CRXBFF_Pos (0U)
20239#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
20240#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
20241#define SWPMI_ICR_CTXBEF_Pos (1U)
20242#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
20243#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
20244#define SWPMI_ICR_CRXBERF_Pos (2U)
20245#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
20246#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
20247#define SWPMI_ICR_CRXOVRF_Pos (3U)
20248#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
20249#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
20250#define SWPMI_ICR_CTXUNRF_Pos (4U)
20251#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
20252#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
20253#define SWPMI_ICR_CTCF_Pos (7U)
20254#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
20255#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
20256#define SWPMI_ICR_CSRF_Pos (8U)
20257#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
20258#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
20259#define SWPMI_ICR_CRDYF_Pos (11U)
20260#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos)
20261#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk
20263/******************* Bit definition for SWPMI_IER register ********************/
20264#define SWPMI_IER_RXBFIE_Pos (0U)
20265#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
20266#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
20267#define SWPMI_IER_TXBEIE_Pos (1U)
20268#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
20269#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
20270#define SWPMI_IER_RXBERIE_Pos (2U)
20271#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
20272#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
20273#define SWPMI_IER_RXOVRIE_Pos (3U)
20274#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
20275#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
20276#define SWPMI_IER_TXUNRIE_Pos (4U)
20277#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
20278#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
20279#define SWPMI_IER_RIE_Pos (5U)
20280#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
20281#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
20282#define SWPMI_IER_TIE_Pos (6U)
20283#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
20284#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
20285#define SWPMI_IER_TCIE_Pos (7U)
20286#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
20287#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
20288#define SWPMI_IER_SRIE_Pos (8U)
20289#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
20290#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
20291#define SWPMI_IER_RDYIE_Pos (11U)
20292#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos)
20293#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk
20295/******************* Bit definition for SWPMI_RFL register ********************/
20296#define SWPMI_RFL_RFL_Pos (0U)
20297#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
20298#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
20299#define SWPMI_RFL_RFL_0_1 (0x00000003U)
20301/******************* Bit definition for SWPMI_TDR register ********************/
20302#define SWPMI_TDR_TD_Pos (0U)
20303#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
20304#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
20306/******************* Bit definition for SWPMI_RDR register ********************/
20307#define SWPMI_RDR_RD_Pos (0U)
20308#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
20309#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
20312/******************* Bit definition for SWPMI_OR register ********************/
20313#define SWPMI_OR_TBYP_Pos (0U)
20314#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
20315#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
20316#define SWPMI_OR_CLASS_Pos (1U)
20317#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
20318#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
20320/******************************************************************************/
20321/* */
20322/* Window WATCHDOG */
20323/* */
20324/******************************************************************************/
20325/******************* Bit definition for WWDG_CR register ********************/
20326#define WWDG_CR_T_Pos (0U)
20327#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
20328#define WWDG_CR_T WWDG_CR_T_Msk
20329#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
20330#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
20331#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
20332#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
20333#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
20334#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
20335#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
20337#define WWDG_CR_WDGA_Pos (7U)
20338#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
20339#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
20341/******************* Bit definition for WWDG_CFR register *******************/
20342#define WWDG_CFR_W_Pos (0U)
20343#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
20344#define WWDG_CFR_W WWDG_CFR_W_Msk
20345#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
20346#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
20347#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
20348#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
20349#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
20350#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
20351#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
20353#define WWDG_CFR_EWI_Pos (9U)
20354#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
20355#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
20357#define WWDG_CFR_WDGTB_Pos (11U)
20358#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
20359#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
20360#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
20361#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
20362#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
20364/******************* Bit definition for WWDG_SR register ********************/
20365#define WWDG_SR_EWIF_Pos (0U)
20366#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
20367#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
20370/******************************************************************************/
20371/* */
20372/* DBG */
20373/* */
20374/******************************************************************************/
20375/********************************* DEVICE ID ********************************/
20376#define STM32H7_DEV_ID 0x480UL
20377
20378/******************** Bit definition for DBGMCU_IDCODE register *************/
20379#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
20380#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
20381#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
20382#define DBGMCU_IDCODE_REV_ID_Pos (16U)
20383#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
20384#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
20385
20386/******************** Bit definition for DBGMCU_CR register *****************/
20387#define DBGMCU_CR_DBG_SLEEPCD_Pos (0U)
20388#define DBGMCU_CR_DBG_SLEEPCD_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos)
20389#define DBGMCU_CR_DBG_SLEEPCD DBGMCU_CR_DBG_SLEEPCD_Msk
20390#define DBGMCU_CR_DBG_STOPCD_Pos (1U)
20391#define DBGMCU_CR_DBG_STOPCD_Msk (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)
20392#define DBGMCU_CR_DBG_STOPCD DBGMCU_CR_DBG_STOPCD_Msk
20393#define DBGMCU_CR_DBG_STANDBYCD_Pos (2U)
20394#define DBGMCU_CR_DBG_STANDBYCD_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos)
20395#define DBGMCU_CR_DBG_STANDBYCD DBGMCU_CR_DBG_STANDBYCD_Msk
20396
20397/* Legacy defines */
20398#define DBGMCU_CR_DBG_SLEEPD1_Pos DBGMCU_CR_DBG_SLEEPCD_Pos
20399#define DBGMCU_CR_DBG_SLEEPD1_Msk DBGMCU_CR_DBG_SLEEPCD_Msk
20400#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPCD
20401#define DBGMCU_CR_DBG_STOPD1_Pos DBGMCU_CR_DBG_STOPCD_Pos
20402#define DBGMCU_CR_DBG_STOPD1_Msk DBGMCU_CR_DBG_STOPCD_Msk
20403#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPCD
20404#define DBGMCU_CR_DBG_STANDBYD1_Pos DBGMCU_CR_DBG_STANDBYCD_Pos
20405#define DBGMCU_CR_DBG_STANDBYD1_Msk DBGMCU_CR_DBG_STANDBYCD_Msk
20406#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYCD
20407#define DBGMCU_CR_DBG_STOPSRD_Pos (7U)
20408#define DBGMCU_CR_DBG_STOPSRD_Msk (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)
20409#define DBGMCU_CR_DBG_STOPSRD DBGMCU_CR_DBG_STOPSRD_Msk
20410#define DBGMCU_CR_DBG_STANDBYSRD_Pos (8U)
20411#define DBGMCU_CR_DBG_STANDBYSRD_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos)
20412#define DBGMCU_CR_DBG_STANDBYSRD DBGMCU_CR_DBG_STANDBYSRD_Msk
20413
20414/* Legacy defines */
20415#define DBGMCU_CR_DBG_STOPD3_Pos DBGMCU_CR_DBG_STOPSRD_Pos
20416#define DBGMCU_CR_DBG_STOPD3_Msk DBGMCU_CR_DBG_STOPSRD_Msk
20417#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPSRD
20418#define DBGMCU_CR_DBG_STANDBYD3_Pos DBGMCU_CR_DBG_STANDBYSRD_Pos
20419#define DBGMCU_CR_DBG_STANDBYD3_Msk DBGMCU_CR_DBG_STANDBYSRD_Msk
20420#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYSRD
20421
20422#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
20423#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
20424#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
20425#define DBGMCU_CR_DBG_CKCDEN_Pos (21U)
20426#define DBGMCU_CR_DBG_CKCDEN_Msk (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)
20427#define DBGMCU_CR_DBG_CKCDEN DBGMCU_CR_DBG_CKCDEN_Msk
20428#define DBGMCU_CR_DBG_CKSRDEN_Pos (22U)
20429#define DBGMCU_CR_DBG_CKSRDEN_Msk (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)
20430#define DBGMCU_CR_DBG_CKSRDEN DBGMCU_CR_DBG_CKSRDEN_Msk
20431
20432/* Legacy defines */
20433#define DBGMCU_CR_DBG_CKD1EN_Pos DBGMCU_CR_DBG_CKCDEN_Pos
20434#define DBGMCU_CR_DBG_CKD1EN_Msk DBGMCU_CR_DBG_CKCDEN_Msk
20435#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKCDEN
20436#define DBGMCU_CR_DBG_CKD3EN_Pos DBGMCU_CR_DBG_CKSRDEN_Pos
20437#define DBGMCU_CR_DBG_CKD3EN_Msk DBGMCU_CR_DBG_CKSRDEN_Msk
20438#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKSRDEN
20439
20440#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
20441#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
20442#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
20443
20444/******************** Bit definition for APB3FZ1 register ************/
20445#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
20446#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
20447#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
20448/******************** Bit definition for APB1LFZ1 register ************/
20449#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
20450#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
20451#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
20452#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
20453#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
20454#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
20455#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
20456#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
20457#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
20458#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
20459#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
20460#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
20461#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
20462#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
20463#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
20464#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
20465#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
20466#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
20467#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
20468#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
20469#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
20470#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
20471#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
20472#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
20473#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
20474#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
20475#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
20476#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
20477#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
20478#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
20479#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
20480#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
20481#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
20482#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
20483#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
20484#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
20485#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
20486#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
20487#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
20488
20489/******************** Bit definition for APB2FZ1 register ************/
20490#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
20491#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
20492#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
20493#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
20494#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
20495#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
20496#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
20497#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
20498#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
20499#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
20500#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
20501#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
20502#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
20503#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
20504#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
20505/******************** Bit definition for APB4FZ1 register ************/
20506#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
20507#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
20508#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
20509#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
20510#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
20511#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
20512#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
20513#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
20514#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
20515#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
20516#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
20517#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
20518#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
20519#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
20520#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
20521/******************************************************************************/
20522/* */
20523/* RAM ECC monitoring */
20524/* */
20525/******************************************************************************/
20526/****************** Bit definition for RAMECC_IER register ******************/
20527#define RAMECC_IER_GECCDEBWIE_Pos (3U)
20528#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
20529#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk
20530#define RAMECC_IER_GECCDEIE_Pos (2U)
20531#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos)
20532#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk
20533#define RAMECC_IER_GECCSEIE_Pos (1U)
20534#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos)
20535#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk
20536#define RAMECC_IER_GIE_Pos (0U)
20537#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos)
20538#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk
20540/******************* Bit definition for RAMECC_CR register ******************/
20541#define RAMECC_CR_ECCELEN_Pos (5U)
20542#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos)
20543#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk
20544#define RAMECC_CR_ECCDEBWIE_Pos (4U)
20545#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
20546#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk
20547#define RAMECC_CR_ECCDEIE_Pos (3U)
20548#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos)
20549#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk
20550#define RAMECC_CR_ECCSEIE_Pos (2U)
20551#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos)
20552#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk
20554/******************* Bit definition for RAMECC_SR register ******************/
20555#define RAMECC_SR_DEBWDF_Pos (2U)
20556#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos)
20557#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk
20558#define RAMECC_SR_DEDF_Pos (1U)
20559#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos)
20560#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk
20561#define RAMECC_SR_SEDCF_Pos (0U)
20562#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos)
20563#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk
20565/****************** Bit definition for RAMECC_FAR register ******************/
20566#define RAMECC_FAR_FADD_Pos (0U)
20567#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
20568#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk
20570/****************** Bit definition for RAMECC_FDRL register *****************/
20571#define RAMECC_FAR_FDATAL_Pos (0U)
20572#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)
20573#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk
20575/****************** Bit definition for RAMECC_FDRH register *****************/
20576#define RAMECC_FAR_FDATAH_Pos (0U)
20577#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)
20578#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
20579
20580/***************** Bit definition for RAMECC_FECR register ******************/
20581#define RAMECC_FECR_FEC_Pos (0U)
20582#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
20583#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk
20585/******************************************************************************/
20586/* */
20587/* MDIOS */
20588/* */
20589/******************************************************************************/
20590/******************** Bit definition for MDIOS_CR register *******************/
20591#define MDIOS_CR_EN_Pos (0U)
20592#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
20593#define MDIOS_CR_EN MDIOS_CR_EN_Msk
20594#define MDIOS_CR_WRIE_Pos (1U)
20595#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
20596#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
20597#define MDIOS_CR_RDIE_Pos (2U)
20598#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
20599#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
20600#define MDIOS_CR_EIE_Pos (3U)
20601#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
20602#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
20603#define MDIOS_CR_DPC_Pos (7U)
20604#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
20605#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
20606#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
20607#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
20608#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
20609#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
20610#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
20611#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
20612#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
20613#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
20615/******************** Bit definition for MDIOS_SR register *******************/
20616#define MDIOS_SR_PERF_Pos (0U)
20617#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
20618#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
20619#define MDIOS_SR_SERF_Pos (1U)
20620#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
20621#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
20622#define MDIOS_SR_TERF_Pos (2U)
20623#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
20624#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
20626/******************** Bit definition for MDIOS_CLRFR register *******************/
20627#define MDIOS_SR_CPERF_Pos (0U)
20628#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos)
20629#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk
20630#define MDIOS_SR_CSERF_Pos (1U)
20631#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos)
20632#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk
20633#define MDIOS_SR_CTERF_Pos (2U)
20634#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos)
20635#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk
20637/******************************************************************************/
20638/* */
20639/* USB_OTG */
20640/* */
20641/******************************************************************************/
20642/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
20643#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
20644#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
20645#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
20646#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
20647#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
20648#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
20649#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
20650#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
20651#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
20652#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
20653#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
20654#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
20655#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
20656#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
20657#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
20658#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
20659#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
20660#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
20661#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
20662#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
20663#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
20664#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
20665#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
20666#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
20667#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
20668#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
20669#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
20670#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
20671#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
20672#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
20673#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
20674#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
20675#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
20676#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
20677#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
20678#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
20679#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
20680#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
20681#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
20682#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
20683#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
20684#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
20685#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
20686#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
20687#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
20688#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
20689#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
20690#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
20691#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
20692#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
20693#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
20694#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
20695#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
20696#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
20698/******************** Bit definition forUSB_OTG_HCFG register ********************/
20699
20700#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
20701#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
20702#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
20703#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
20704#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
20705#define USB_OTG_HCFG_FSLSS_Pos (2U)
20706#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
20707#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
20709/******************** Bit definition forUSB_OTG_DCFG register ********************/
20710
20711#define USB_OTG_DCFG_DSPD_Pos (0U)
20712#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
20713#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
20714#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
20715#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
20716#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
20717#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
20718#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
20720#define USB_OTG_DCFG_DAD_Pos (4U)
20721#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
20722#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
20723#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
20724#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
20725#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
20726#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
20727#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
20728#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
20729#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
20731#define USB_OTG_DCFG_PFIVL_Pos (11U)
20732#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
20733#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
20734#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
20735#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
20737#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
20738#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
20739#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
20740#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
20741#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
20743/******************** Bit definition forUSB_OTG_PCGCR register ********************/
20744#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
20745#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
20746#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
20747#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
20748#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
20749#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
20750#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
20751#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
20752#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
20754/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
20755#define USB_OTG_GOTGINT_SEDET_Pos (2U)
20756#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
20757#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
20758#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
20759#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
20760#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
20761#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
20762#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
20763#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
20764#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
20765#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
20766#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
20767#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
20768#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
20769#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
20770#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
20771#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
20772#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
20774/******************** Bit definition forUSB_OTG_DCTL register ********************/
20775#define USB_OTG_DCTL_RWUSIG_Pos (0U)
20776#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
20777#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
20778#define USB_OTG_DCTL_SDIS_Pos (1U)
20779#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
20780#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
20781#define USB_OTG_DCTL_GINSTS_Pos (2U)
20782#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
20783#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
20784#define USB_OTG_DCTL_GONSTS_Pos (3U)
20785#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
20786#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
20788#define USB_OTG_DCTL_TCTL_Pos (4U)
20789#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
20790#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
20791#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
20792#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
20793#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
20794#define USB_OTG_DCTL_SGINAK_Pos (7U)
20795#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
20796#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
20797#define USB_OTG_DCTL_CGINAK_Pos (8U)
20798#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
20799#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
20800#define USB_OTG_DCTL_SGONAK_Pos (9U)
20801#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
20802#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
20803#define USB_OTG_DCTL_CGONAK_Pos (10U)
20804#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
20805#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
20806#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
20807#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
20808#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
20810/******************** Bit definition forUSB_OTG_HFIR register ********************/
20811#define USB_OTG_HFIR_FRIVL_Pos (0U)
20812#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
20813#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
20815/******************** Bit definition forUSB_OTG_HFNUM register ********************/
20816#define USB_OTG_HFNUM_FRNUM_Pos (0U)
20817#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
20818#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
20819#define USB_OTG_HFNUM_FTREM_Pos (16U)
20820#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
20821#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
20823/******************** Bit definition forUSB_OTG_DSTS register ********************/
20824#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
20825#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
20826#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
20828#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
20829#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
20830#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
20831#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
20832#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
20833#define USB_OTG_DSTS_EERR_Pos (3U)
20834#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
20835#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
20836#define USB_OTG_DSTS_FNSOF_Pos (8U)
20837#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
20838#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
20840/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
20841#define USB_OTG_GAHBCFG_GINT_Pos (0U)
20842#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
20843#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
20845#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
20846#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
20847#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
20848#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
20849#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
20850#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
20851#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
20852#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
20853#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
20854#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
20855#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
20856#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
20857#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
20858#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
20859#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
20860#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
20861#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
20863/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
20864
20865#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
20866#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
20867#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
20868#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
20869#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
20870#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
20871#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
20872#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
20873#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
20874#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
20875#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
20876#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
20877#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
20878#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
20879#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
20881#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
20882#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
20883#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
20884#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
20885#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
20886#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
20887#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
20888#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
20889#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
20890#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
20891#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
20892#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
20893#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
20894#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
20895#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
20896#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
20897#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
20898#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
20899#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
20900#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
20901#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
20902#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
20903#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
20904#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
20905#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
20906#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
20907#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
20908#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
20909#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
20910#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
20911#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
20912#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
20913#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
20914#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
20915#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
20916#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
20917#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
20918#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
20919#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
20920#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
20921#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
20922#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
20923#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
20924#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
20925#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
20926#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
20928/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
20929#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
20930#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
20931#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
20932#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
20933#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
20934#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
20935#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
20936#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
20937#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
20938#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
20939#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
20940#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
20941#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
20942#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
20943#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
20945#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
20946#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
20947#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
20948#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
20949#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
20950#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
20951#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
20952#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
20953#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
20954#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
20955#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
20956#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
20957#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
20958#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
20960/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
20961#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
20962#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
20963#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
20964#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
20965#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
20966#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
20967#define USB_OTG_DIEPMSK_TOM_Pos (3U)
20968#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
20969#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
20970#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
20971#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
20972#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
20973#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
20974#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
20975#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
20976#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
20977#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
20978#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
20979#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
20980#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
20981#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
20982#define USB_OTG_DIEPMSK_BIM_Pos (9U)
20983#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
20984#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
20986/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
20987#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
20988#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
20989#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
20991#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
20992#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
20993#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
20994#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
20995#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
20996#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
20997#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
20998#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
20999#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
21000#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
21001#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
21003#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
21004#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21005#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
21006#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21007#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21008#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21009#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21010#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21011#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21012#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21013#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
21015/******************** Bit definition forUSB_OTG_HAINT register ********************/
21016#define USB_OTG_HAINT_HAINT_Pos (0U)
21017#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
21018#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
21020/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
21021#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
21022#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
21023#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
21024#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
21025#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
21026#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
21027#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
21028#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
21029#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
21030#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
21031#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
21032#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
21033#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
21034#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
21035#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
21036#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
21037#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
21038#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
21039#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
21040#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
21041#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
21042#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
21043#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
21044#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
21045#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
21046#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
21047#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
21048#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
21049#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
21050#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
21051#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
21052#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
21053#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
21054#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
21055#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
21056#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
21058/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
21059#define USB_OTG_GINTSTS_CMOD_Pos (0U)
21060#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
21061#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
21062#define USB_OTG_GINTSTS_MMIS_Pos (1U)
21063#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
21064#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
21065#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
21066#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
21067#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
21068#define USB_OTG_GINTSTS_SOF_Pos (3U)
21069#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
21070#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
21071#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
21072#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
21073#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
21074#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
21075#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
21076#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
21077#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
21078#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
21079#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
21080#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
21081#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
21082#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
21083#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
21084#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
21085#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
21086#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
21087#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
21088#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
21089#define USB_OTG_GINTSTS_USBRST_Pos (12U)
21090#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
21091#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
21092#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
21093#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
21094#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
21095#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
21096#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
21097#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
21098#define USB_OTG_GINTSTS_EOPF_Pos (15U)
21099#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
21100#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
21101#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
21102#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
21103#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
21104#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
21105#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
21106#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
21107#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
21108#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
21109#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
21110#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
21111#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
21112#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
21113#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
21114#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
21115#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
21116#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
21117#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
21118#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
21119#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
21120#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
21121#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
21122#define USB_OTG_GINTSTS_HCINT_Pos (25U)
21123#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
21124#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
21125#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
21126#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
21127#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
21128#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
21129#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
21130#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
21131#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
21132#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
21133#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
21134#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
21135#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
21136#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
21137#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
21138#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
21139#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
21140#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
21141#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
21142#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
21144/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
21145#define USB_OTG_GINTMSK_MMISM_Pos (1U)
21146#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
21147#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
21148#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
21149#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
21150#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
21151#define USB_OTG_GINTMSK_SOFM_Pos (3U)
21152#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
21153#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
21154#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
21155#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
21156#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
21157#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
21158#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
21159#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
21160#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
21161#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
21162#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
21163#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
21164#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
21165#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
21166#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
21167#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
21168#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
21169#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
21170#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
21171#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
21172#define USB_OTG_GINTMSK_USBRST_Pos (12U)
21173#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
21174#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
21175#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
21176#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
21177#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
21178#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
21179#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
21180#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
21181#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
21182#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
21183#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
21184#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
21185#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
21186#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
21187#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
21188#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
21189#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
21190#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
21191#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
21192#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
21193#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
21194#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
21195#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
21196#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
21197#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
21198#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
21199#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
21200#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
21201#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
21202#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
21203#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
21204#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
21205#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
21206#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
21207#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
21208#define USB_OTG_GINTMSK_HCIM_Pos (25U)
21209#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
21210#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
21211#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
21212#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
21213#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
21214#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
21215#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
21216#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
21217#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
21218#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
21219#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
21220#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
21221#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
21222#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
21223#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
21224#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
21225#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
21226#define USB_OTG_GINTMSK_WUIM_Pos (31U)
21227#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
21228#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
21230/******************** Bit definition forUSB_OTG_DAINT register ********************/
21231#define USB_OTG_DAINT_IEPINT_Pos (0U)
21232#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
21233#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
21234#define USB_OTG_DAINT_OEPINT_Pos (16U)
21235#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
21236#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
21238/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
21239#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
21240#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
21241#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
21243/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
21244#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
21245#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
21246#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
21247#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
21248#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
21249#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
21250#define USB_OTG_GRXSTSP_DPID_Pos (15U)
21251#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
21252#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
21253#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
21254#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
21255#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
21257/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
21258#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
21259#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
21260#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
21261#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
21262#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
21263#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
21265/******************** Bit definition for OTG register ********************/
21266
21267#define USB_OTG_CHNUM_Pos (0U)
21268#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
21269#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
21270#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
21271#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
21272#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
21273#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
21274#define USB_OTG_BCNT_Pos (4U)
21275#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
21276#define USB_OTG_BCNT USB_OTG_BCNT_Msk
21278#define USB_OTG_DPID_Pos (15U)
21279#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
21280#define USB_OTG_DPID USB_OTG_DPID_Msk
21281#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
21282#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
21284#define USB_OTG_PKTSTS_Pos (17U)
21285#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
21286#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
21287#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
21288#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
21289#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
21290#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
21292#define USB_OTG_EPNUM_Pos (0U)
21293#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
21294#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
21295#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
21296#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
21297#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
21298#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
21300#define USB_OTG_FRMNUM_Pos (21U)
21301#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
21302#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
21303#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
21304#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
21305#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
21306#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
21308/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
21309#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
21310#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
21311#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
21313/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
21314#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
21315#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
21316#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
21318/******************** Bit definition for OTG register ********************/
21319#define USB_OTG_NPTXFSA_Pos (0U)
21320#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
21321#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
21322#define USB_OTG_NPTXFD_Pos (16U)
21323#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
21324#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
21325#define USB_OTG_TX0FSA_Pos (0U)
21326#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
21327#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
21328#define USB_OTG_TX0FD_Pos (16U)
21329#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
21330#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
21332/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
21333#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
21334#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
21335#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
21337/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
21338#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
21339#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
21340#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
21342#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
21343#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21344#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
21345#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21346#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21347#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21348#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21349#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21350#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21351#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21352#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
21354#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
21355#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21356#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
21357#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21358#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21359#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21360#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21361#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21362#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21363#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
21365/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
21366#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
21367#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
21368#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
21369#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
21370#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
21371#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
21373#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
21374#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21375#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
21376#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21377#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21378#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21379#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21380#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21381#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21382#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21383#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21384#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
21385#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
21386#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
21387#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
21389#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
21390#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21391#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
21392#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21393#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21394#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21395#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21396#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21397#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21398#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21399#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21400#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
21401#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
21402#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
21403#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
21405/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
21406#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
21407#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
21408#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
21410/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
21411#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
21412#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
21413#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
21414#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
21415#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
21416#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
21418/******************** Bit definition forUSB_OTG_GCCFG register ********************/
21419#define USB_OTG_GCCFG_DCDET_Pos (0U)
21420#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
21421#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
21422#define USB_OTG_GCCFG_PDET_Pos (1U)
21423#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
21424#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
21425#define USB_OTG_GCCFG_SDET_Pos (2U)
21426#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
21427#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
21428#define USB_OTG_GCCFG_PS2DET_Pos (3U)
21429#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
21430#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
21431#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
21432#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
21433#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
21434#define USB_OTG_GCCFG_BCDEN_Pos (17U)
21435#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
21436#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
21437#define USB_OTG_GCCFG_DCDEN_Pos (18U)
21438#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
21439#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
21440#define USB_OTG_GCCFG_PDEN_Pos (19U)
21441#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
21442#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
21443#define USB_OTG_GCCFG_SDEN_Pos (20U)
21444#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
21445#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
21446#define USB_OTG_GCCFG_VBDEN_Pos (21U)
21447#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
21448#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
21450/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
21451#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
21452#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
21453#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk
21454#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
21455#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
21456#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk
21458/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
21459#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
21460#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
21461#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
21462#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
21463#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
21464#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
21466/******************** Bit definition forUSB_OTG_CID register ********************/
21467#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
21468#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
21469#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
21471/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
21472#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
21473#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
21474#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
21475#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
21476#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
21477#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
21478#define USB_OTG_GLPMCFG_BESL_Pos (2U)
21479#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
21480#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
21481#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
21482#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
21483#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
21484#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
21485#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
21486#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
21487#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
21488#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
21489#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
21490#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
21491#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
21492#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
21493#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
21494#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
21495#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
21496#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
21497#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
21498#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
21499#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
21500#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
21501#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
21502#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
21503#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
21504#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
21505#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
21506#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
21507#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
21508#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
21509#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
21510#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
21511#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
21512#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
21513#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
21514#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
21515#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
21516#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
21518/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
21519#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
21520#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
21521#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
21522#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
21523#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
21524#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
21525#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
21526#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
21527#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
21528#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
21529#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
21530#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
21531#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
21532#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
21533#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
21534#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
21535#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
21536#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
21537#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
21538#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
21539#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
21540#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
21541#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
21542#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
21543#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
21544#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
21545#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
21547/******************** Bit definition forUSB_OTG_HPRT register ********************/
21548#define USB_OTG_HPRT_PCSTS_Pos (0U)
21549#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
21550#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
21551#define USB_OTG_HPRT_PCDET_Pos (1U)
21552#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
21553#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
21554#define USB_OTG_HPRT_PENA_Pos (2U)
21555#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
21556#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
21557#define USB_OTG_HPRT_PENCHNG_Pos (3U)
21558#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
21559#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
21560#define USB_OTG_HPRT_POCA_Pos (4U)
21561#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
21562#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
21563#define USB_OTG_HPRT_POCCHNG_Pos (5U)
21564#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
21565#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
21566#define USB_OTG_HPRT_PRES_Pos (6U)
21567#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
21568#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
21569#define USB_OTG_HPRT_PSUSP_Pos (7U)
21570#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
21571#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
21572#define USB_OTG_HPRT_PRST_Pos (8U)
21573#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
21574#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
21576#define USB_OTG_HPRT_PLSTS_Pos (10U)
21577#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
21578#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
21579#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
21580#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
21581#define USB_OTG_HPRT_PPWR_Pos (12U)
21582#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
21583#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
21585#define USB_OTG_HPRT_PTCTL_Pos (13U)
21586#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
21587#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
21588#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
21589#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
21590#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
21591#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
21593#define USB_OTG_HPRT_PSPD_Pos (17U)
21594#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
21595#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
21596#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
21597#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
21599/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
21600#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
21601#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
21602#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
21603#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
21604#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
21605#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
21606#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
21607#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
21608#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
21609#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
21610#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
21611#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
21612#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
21613#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
21614#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
21615#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
21616#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
21617#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
21618#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
21619#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
21620#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
21621#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
21622#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
21623#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
21624#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
21625#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
21626#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
21627#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
21628#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
21629#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
21630#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
21631#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
21632#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
21634/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
21635#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
21636#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
21637#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
21638#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
21639#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
21640#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
21642/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
21643#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
21644#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
21645#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
21646#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
21647#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
21648#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
21649#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
21650#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
21651#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
21652#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
21653#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
21654#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
21656#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
21657#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
21658#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
21659#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
21660#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
21661#define USB_OTG_DIEPCTL_STALL_Pos (21U)
21662#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
21663#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
21665#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
21666#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
21667#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
21668#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
21669#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
21670#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
21671#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
21672#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
21673#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
21674#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
21675#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
21676#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
21677#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
21678#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
21679#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
21680#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
21681#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
21682#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
21683#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
21684#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
21685#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
21686#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
21687#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
21688#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
21689#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
21691/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
21692#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
21693#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
21694#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
21696#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
21697#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
21698#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
21699#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
21700#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
21701#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
21702#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
21703#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
21704#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
21705#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
21706#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
21707#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
21708#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
21710#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
21711#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
21712#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
21713#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
21714#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
21716#define USB_OTG_HCCHAR_MC_Pos (20U)
21717#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
21718#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
21719#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
21720#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
21722#define USB_OTG_HCCHAR_DAD_Pos (22U)
21723#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
21724#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
21725#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
21726#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
21727#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
21728#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
21729#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
21730#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
21731#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
21732#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
21733#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
21734#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
21735#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
21736#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
21737#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
21738#define USB_OTG_HCCHAR_CHENA_Pos (31U)
21739#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
21740#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
21742/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
21743
21744#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
21745#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
21746#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
21747#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21748#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21749#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21750#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21751#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21752#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21753#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
21755#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
21756#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
21757#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
21758#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21759#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21760#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21761#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21762#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21763#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21764#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
21766#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
21767#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
21768#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
21769#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
21770#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
21771#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
21772#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
21773#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
21774#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
21775#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
21776#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
21778/******************** Bit definition forUSB_OTG_HCINT register ********************/
21779#define USB_OTG_HCINT_XFRC_Pos (0U)
21780#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
21781#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
21782#define USB_OTG_HCINT_CHH_Pos (1U)
21783#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
21784#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
21785#define USB_OTG_HCINT_AHBERR_Pos (2U)
21786#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
21787#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
21788#define USB_OTG_HCINT_STALL_Pos (3U)
21789#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
21790#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
21791#define USB_OTG_HCINT_NAK_Pos (4U)
21792#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
21793#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
21794#define USB_OTG_HCINT_ACK_Pos (5U)
21795#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
21796#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
21797#define USB_OTG_HCINT_NYET_Pos (6U)
21798#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
21799#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
21800#define USB_OTG_HCINT_TXERR_Pos (7U)
21801#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
21802#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
21803#define USB_OTG_HCINT_BBERR_Pos (8U)
21804#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
21805#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
21806#define USB_OTG_HCINT_FRMOR_Pos (9U)
21807#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
21808#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
21809#define USB_OTG_HCINT_DTERR_Pos (10U)
21810#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
21811#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
21813/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
21814#define USB_OTG_DIEPINT_XFRC_Pos (0U)
21815#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
21816#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
21817#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
21818#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
21819#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
21820#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
21821#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
21822#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
21823#define USB_OTG_DIEPINT_TOC_Pos (3U)
21824#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
21825#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
21826#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
21827#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
21828#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
21829#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
21830#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
21831#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
21832#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
21833#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
21834#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
21835#define USB_OTG_DIEPINT_TXFE_Pos (7U)
21836#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
21837#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
21838#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
21839#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
21840#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
21841#define USB_OTG_DIEPINT_BNA_Pos (9U)
21842#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
21843#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
21844#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
21845#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
21846#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
21847#define USB_OTG_DIEPINT_BERR_Pos (12U)
21848#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
21849#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
21850#define USB_OTG_DIEPINT_NAK_Pos (13U)
21851#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
21852#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
21854/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
21855#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
21856#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
21857#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
21858#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
21859#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
21860#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
21861#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
21862#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
21863#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
21864#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
21865#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
21866#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
21867#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
21868#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
21869#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
21870#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
21871#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
21872#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
21873#define USB_OTG_HCINTMSK_NYET_Pos (6U)
21874#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
21875#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
21876#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
21877#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
21878#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
21879#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
21880#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
21881#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
21882#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
21883#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
21884#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
21885#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
21886#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
21887#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
21889/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
21890
21891#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
21892#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
21893#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
21894#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
21895#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
21896#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
21897#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
21898#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
21899#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
21900/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
21901#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
21902#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
21903#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
21904#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
21905#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
21906#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
21907#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
21908#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
21909#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
21910#define USB_OTG_HCTSIZ_DPID_Pos (29U)
21911#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
21912#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
21913#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
21914#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
21916/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
21917#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
21918#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
21919#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
21921/******************** Bit definition forUSB_OTG_HCDMA register ********************/
21922#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
21923#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
21924#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
21926/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
21927#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
21928#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
21929#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
21931/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
21932#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
21933#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
21934#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
21935#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
21936#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
21937#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
21939/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
21940
21941#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
21942#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
21943#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
21944#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
21945#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
21946#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
21947#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
21948#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
21949#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
21950#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
21951#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
21952#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
21953#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
21954#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
21955#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
21956#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
21957#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
21958#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
21959#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
21960#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
21961#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
21962#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
21963#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
21964#define USB_OTG_DOEPCTL_STALL_Pos (21U)
21965#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
21966#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
21967#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
21968#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
21969#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
21970#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
21971#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
21972#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
21973#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
21974#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
21975#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
21976#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
21977#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
21978#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
21980/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
21981#define USB_OTG_DOEPINT_XFRC_Pos (0U)
21982#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
21983#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
21984#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
21985#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
21986#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
21987#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
21988#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
21989#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
21990#define USB_OTG_DOEPINT_STUP_Pos (3U)
21991#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
21992#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
21993#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
21994#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
21995#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
21996#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
21997#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
21998#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
21999#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
22000#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
22001#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
22002#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
22003#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
22004#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
22005#define USB_OTG_DOEPINT_BNA_Pos (9U)
22006#define USB_OTG_DOEPINT_BNA_Msk (0x1UL << USB_OTG_DOEPINT_BNA_Pos)
22007#define USB_OTG_DOEPINT_BNA USB_OTG_DOEPINT_BNA_Msk
22008#define USB_OTG_DOEPINT_BERR_Pos (12U)
22009#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
22010#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk
22011#define USB_OTG_DOEPINT_NAK_Pos (13U)
22012#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
22013#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
22014#define USB_OTG_DOEPINT_NYET_Pos (14U)
22015#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
22016#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
22017#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
22018#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
22019#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
22021/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
22022
22023#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
22024#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
22025#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
22026#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
22027#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
22028#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
22030#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
22031#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
22032#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
22033#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
22034#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
22036/******************** Bit definition for PCGCCTL register ********************/
22037#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
22038#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
22039#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
22040#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
22041#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
22042#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
22043#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
22044#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
22045#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
22059/******************************* ADC Instances ********************************/
22060#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
22061 ((INSTANCE) == ADC2))
22062
22063#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
22064
22065#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
22066
22067/******************************** COMP Instances ******************************/
22068#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
22069 ((INSTANCE) == COMP2))
22070
22071#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
22072/******************** COMP Instances with window mode capability **************/
22073#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
22074
22075/******************************** DTS Instances ******************************/
22076#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)
22077
22078/******************************* CRC Instances ********************************/
22079#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
22080
22081/******************************* DAC Instances ********************************/
22082#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \
22083 ((INSTANCE) == DAC2))
22084/******************************* DCMI Instances *******************************/
22085#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
22086
22087/******************************* DELAYBLOCK Instances *******************************/
22088#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
22089 ((INSTANCE) == DLYB_SDMMC2) || \
22090 ((INSTANCE) == DLYB_OCTOSPI1) || \
22091 ((INSTANCE) == DLYB_OCTOSPI2) )
22092/****************************** DFSDM Instances *******************************/
22093#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
22094 ((INSTANCE) == DFSDM1_Filter1) || \
22095 ((INSTANCE) == DFSDM1_Filter2) || \
22096 ((INSTANCE) == DFSDM1_Filter3) || \
22097 ((INSTANCE) == DFSDM1_Filter4) || \
22098 ((INSTANCE) == DFSDM1_Filter5) || \
22099 ((INSTANCE) == DFSDM1_Filter6) || \
22100 ((INSTANCE) == DFSDM1_Filter7) || \
22101 ((INSTANCE) == DFSDM2_Filter0))
22102#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
22103 ((INSTANCE) == DFSDM1_Channel1) || \
22104 ((INSTANCE) == DFSDM1_Channel2) || \
22105 ((INSTANCE) == DFSDM1_Channel3) || \
22106 ((INSTANCE) == DFSDM1_Channel4) || \
22107 ((INSTANCE) == DFSDM1_Channel5) || \
22108 ((INSTANCE) == DFSDM1_Channel6) || \
22109 ((INSTANCE) == DFSDM1_Channel7) || \
22110 ((INSTANCE) == DFSDM2_Channel0) || \
22111 ((INSTANCE) == DFSDM2_Channel1))
22112/****************************** RAMECC Instances ******************************/
22113#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1) || \
22114 ((INSTANCE) == RAMECC_Monitor2) || \
22115 ((INSTANCE) == RAMECC_Monitor3))
22116
22117/******************************** DMA Instances *******************************/
22118#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22119 ((INSTANCE) == DMA1_Stream1) || \
22120 ((INSTANCE) == DMA1_Stream2) || \
22121 ((INSTANCE) == DMA1_Stream3) || \
22122 ((INSTANCE) == DMA1_Stream4) || \
22123 ((INSTANCE) == DMA1_Stream5) || \
22124 ((INSTANCE) == DMA1_Stream6) || \
22125 ((INSTANCE) == DMA1_Stream7) || \
22126 ((INSTANCE) == DMA2_Stream0) || \
22127 ((INSTANCE) == DMA2_Stream1) || \
22128 ((INSTANCE) == DMA2_Stream2) || \
22129 ((INSTANCE) == DMA2_Stream3) || \
22130 ((INSTANCE) == DMA2_Stream4) || \
22131 ((INSTANCE) == DMA2_Stream5) || \
22132 ((INSTANCE) == DMA2_Stream6) || \
22133 ((INSTANCE) == DMA2_Stream7) || \
22134 ((INSTANCE) == BDMA1_Channel0) || \
22135 ((INSTANCE) == BDMA1_Channel1) || \
22136 ((INSTANCE) == BDMA1_Channel2) || \
22137 ((INSTANCE) == BDMA1_Channel3) || \
22138 ((INSTANCE) == BDMA1_Channel4) || \
22139 ((INSTANCE) == BDMA1_Channel5) || \
22140 ((INSTANCE) == BDMA1_Channel6) || \
22141 ((INSTANCE) == BDMA1_Channel7) || \
22142 ((INSTANCE) == BDMA2_Channel0) || \
22143 ((INSTANCE) == BDMA2_Channel1) || \
22144 ((INSTANCE) == BDMA2_Channel2) || \
22145 ((INSTANCE) == BDMA2_Channel3) || \
22146 ((INSTANCE) == BDMA2_Channel4) || \
22147 ((INSTANCE) == BDMA2_Channel5) || \
22148 ((INSTANCE) == BDMA2_Channel6) || \
22149 ((INSTANCE) == BDMA2_Channel7))
22150
22151/****************************** BDMA CHANNEL Instances ***************************/
22152#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \
22153 ((INSTANCE) == BDMA1_Channel1) || \
22154 ((INSTANCE) == BDMA1_Channel2) || \
22155 ((INSTANCE) == BDMA1_Channel3) || \
22156 ((INSTANCE) == BDMA1_Channel4) || \
22157 ((INSTANCE) == BDMA1_Channel5) || \
22158 ((INSTANCE) == BDMA1_Channel6) || \
22159 ((INSTANCE) == BDMA1_Channel7) || \
22160 ((INSTANCE) == BDMA2_Channel0) || \
22161 ((INSTANCE) == BDMA2_Channel1) || \
22162 ((INSTANCE) == BDMA2_Channel2) || \
22163 ((INSTANCE) == BDMA2_Channel3) || \
22164 ((INSTANCE) == BDMA2_Channel4) || \
22165 ((INSTANCE) == BDMA2_Channel5) || \
22166 ((INSTANCE) == BDMA2_Channel6) || \
22167 ((INSTANCE) == BDMA2_Channel7))
22168
22169/****************************** DMA DMAMUX ALL Instances ***************************/
22170#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22171 ((INSTANCE) == DMA1_Stream1) || \
22172 ((INSTANCE) == DMA1_Stream2) || \
22173 ((INSTANCE) == DMA1_Stream3) || \
22174 ((INSTANCE) == DMA1_Stream4) || \
22175 ((INSTANCE) == DMA1_Stream5) || \
22176 ((INSTANCE) == DMA1_Stream6) || \
22177 ((INSTANCE) == DMA1_Stream7) || \
22178 ((INSTANCE) == DMA2_Stream0) || \
22179 ((INSTANCE) == DMA2_Stream1) || \
22180 ((INSTANCE) == DMA2_Stream2) || \
22181 ((INSTANCE) == DMA2_Stream3) || \
22182 ((INSTANCE) == DMA2_Stream4) || \
22183 ((INSTANCE) == DMA2_Stream5) || \
22184 ((INSTANCE) == DMA2_Stream6) || \
22185 ((INSTANCE) == DMA2_Stream7) || \
22186 ((INSTANCE) == BDMA2_Channel0) || \
22187 ((INSTANCE) == BDMA2_Channel1) || \
22188 ((INSTANCE) == BDMA2_Channel2) || \
22189 ((INSTANCE) == BDMA2_Channel3) || \
22190 ((INSTANCE) == BDMA2_Channel4) || \
22191 ((INSTANCE) == BDMA2_Channel5) || \
22192 ((INSTANCE) == BDMA2_Channel6) || \
22193 ((INSTANCE) == BDMA2_Channel7))
22194
22195/****************************** BDMA DMAMUX Instances ***************************/
22196#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA2_Channel0) || \
22197 ((INSTANCE) == BDMA2_Channel1) || \
22198 ((INSTANCE) == BDMA2_Channel2) || \
22199 ((INSTANCE) == BDMA2_Channel3) || \
22200 ((INSTANCE) == BDMA2_Channel4) || \
22201 ((INSTANCE) == BDMA2_Channel5) || \
22202 ((INSTANCE) == BDMA2_Channel6) || \
22203 ((INSTANCE) == BDMA2_Channel7))
22204
22205/****************************** DMA STREAM Instances ***************************/
22206#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22207 ((INSTANCE) == DMA1_Stream1) || \
22208 ((INSTANCE) == DMA1_Stream2) || \
22209 ((INSTANCE) == DMA1_Stream3) || \
22210 ((INSTANCE) == DMA1_Stream4) || \
22211 ((INSTANCE) == DMA1_Stream5) || \
22212 ((INSTANCE) == DMA1_Stream6) || \
22213 ((INSTANCE) == DMA1_Stream7) || \
22214 ((INSTANCE) == DMA2_Stream0) || \
22215 ((INSTANCE) == DMA2_Stream1) || \
22216 ((INSTANCE) == DMA2_Stream2) || \
22217 ((INSTANCE) == DMA2_Stream3) || \
22218 ((INSTANCE) == DMA2_Stream4) || \
22219 ((INSTANCE) == DMA2_Stream5) || \
22220 ((INSTANCE) == DMA2_Stream6) || \
22221 ((INSTANCE) == DMA2_Stream7))
22222
22223/****************************** DMA DMAMUX Instances ***************************/
22224#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22225 ((INSTANCE) == DMA1_Stream1) || \
22226 ((INSTANCE) == DMA1_Stream2) || \
22227 ((INSTANCE) == DMA1_Stream3) || \
22228 ((INSTANCE) == DMA1_Stream4) || \
22229 ((INSTANCE) == DMA1_Stream5) || \
22230 ((INSTANCE) == DMA1_Stream6) || \
22231 ((INSTANCE) == DMA1_Stream7) || \
22232 ((INSTANCE) == DMA2_Stream0) || \
22233 ((INSTANCE) == DMA2_Stream1) || \
22234 ((INSTANCE) == DMA2_Stream2) || \
22235 ((INSTANCE) == DMA2_Stream3) || \
22236 ((INSTANCE) == DMA2_Stream4) || \
22237 ((INSTANCE) == DMA2_Stream5) || \
22238 ((INSTANCE) == DMA2_Stream6) || \
22239 ((INSTANCE) == DMA2_Stream7))
22240
22241/******************************** DMA Request Generator Instances **************/
22242#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
22243 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
22244 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
22245 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
22246 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
22247 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
22248 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
22249 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
22250 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
22251 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
22252 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
22253 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
22254 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
22255 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
22256 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
22257 ((INSTANCE) == DMAMUX2_RequestGenerator7))
22258
22259/******************************* DMA2D Instances *******************************/
22260#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
22261
22262/******************************* OTFDEC Instances ******************************/
22263#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \
22264 ((__INSTANCE__) == OTFDEC2))
22265
22266/****************************** PSSI Instance *********************************/
22267#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)
22268
22269/******************************** MDMA Request Generator Instances **************/
22270#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
22271 ((INSTANCE) == MDMA_Channel1) || \
22272 ((INSTANCE) == MDMA_Channel2) || \
22273 ((INSTANCE) == MDMA_Channel3) || \
22274 ((INSTANCE) == MDMA_Channel4) || \
22275 ((INSTANCE) == MDMA_Channel5) || \
22276 ((INSTANCE) == MDMA_Channel6) || \
22277 ((INSTANCE) == MDMA_Channel7) || \
22278 ((INSTANCE) == MDMA_Channel8) || \
22279 ((INSTANCE) == MDMA_Channel9) || \
22280 ((INSTANCE) == MDMA_Channel10) || \
22281 ((INSTANCE) == MDMA_Channel11) || \
22282 ((INSTANCE) == MDMA_Channel12) || \
22283 ((INSTANCE) == MDMA_Channel13) || \
22284 ((INSTANCE) == MDMA_Channel14) || \
22285 ((INSTANCE) == MDMA_Channel15))
22286
22287
22288/******************************* FDCAN Instances ******************************/
22289#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
22290 ((__INSTANCE__) == FDCAN2))
22291
22292#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
22293
22294/******************************* GFXMMU Instances *******************************/
22295#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)
22296
22297/******************************* GPIO Instances *******************************/
22298#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
22299 ((INSTANCE) == GPIOB) || \
22300 ((INSTANCE) == GPIOC) || \
22301 ((INSTANCE) == GPIOD) || \
22302 ((INSTANCE) == GPIOE) || \
22303 ((INSTANCE) == GPIOF) || \
22304 ((INSTANCE) == GPIOG) || \
22305 ((INSTANCE) == GPIOH) || \
22306 ((INSTANCE) == GPIOI) || \
22307 ((INSTANCE) == GPIOJ) || \
22308 ((INSTANCE) == GPIOK))
22309
22310/******************************* GPIO AF Instances ****************************/
22311#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
22312
22313/**************************** GPIO Lock Instances *****************************/
22314/* On H7, all GPIO Bank support the Lock mechanism */
22315#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
22316
22317/******************************** HSEM Instances *******************************/
22318#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
22319#define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */
22320#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
22321#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
22322
22323#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
22324#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */
22325
22326#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
22327#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
22328
22329#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
22330#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
22331
22332/******************************** I2C Instances *******************************/
22333#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
22334 ((INSTANCE) == I2C2) || \
22335 ((INSTANCE) == I2C3) || \
22336 ((INSTANCE) == I2C4))
22337
22338/****************************** SMBUS Instances *******************************/
22339#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
22340 ((INSTANCE) == I2C2) || \
22341 ((INSTANCE) == I2C3) || \
22342 ((INSTANCE) == I2C4))
22343
22344/************** I2C Instances : wakeup capability from stop modes *************/
22345#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
22346
22347/******************************** I2S Instances *******************************/
22348#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22349 ((INSTANCE) == SPI2) || \
22350 ((INSTANCE) == SPI3) || \
22351 ((INSTANCE) == SPI6))
22352
22353/****************************** LTDC Instances ********************************/
22354#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
22355
22356/******************************* RNG Instances ********************************/
22357#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
22358
22359/****************************** RTC Instances *********************************/
22360#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
22361
22362/****************************** SDMMC Instances *********************************/
22363#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
22364 ((_INSTANCE_) == SDMMC2))
22365
22366/******************************** SPI Instances *******************************/
22367#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22368 ((INSTANCE) == SPI2) || \
22369 ((INSTANCE) == SPI3) || \
22370 ((INSTANCE) == SPI4) || \
22371 ((INSTANCE) == SPI5) || \
22372 ((INSTANCE) == SPI6))
22373
22374#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22375 ((INSTANCE) == SPI2) || \
22376 ((INSTANCE) == SPI3))
22377
22378/******************************** SWPMI Instances *****************************/
22379#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
22380
22381/****************** LPTIM Instances : All supported instances *****************/
22382#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
22383 ((INSTANCE) == LPTIM2) || \
22384 ((INSTANCE) == LPTIM3))
22385
22386/****************** LPTIM Instances : supporting encoder interface **************/
22387#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
22388 ((INSTANCE) == LPTIM2))
22389
22390/****************** TIM Instances : All supported instances *******************/
22391#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22392 ((INSTANCE) == TIM2) || \
22393 ((INSTANCE) == TIM3) || \
22394 ((INSTANCE) == TIM4) || \
22395 ((INSTANCE) == TIM5) || \
22396 ((INSTANCE) == TIM6) || \
22397 ((INSTANCE) == TIM7) || \
22398 ((INSTANCE) == TIM8) || \
22399 ((INSTANCE) == TIM12) || \
22400 ((INSTANCE) == TIM13) || \
22401 ((INSTANCE) == TIM14) || \
22402 ((INSTANCE) == TIM15) || \
22403 ((INSTANCE) == TIM16) || \
22404 ((INSTANCE) == TIM17))
22405
22406/************* TIM Instances : at least 1 capture/compare channel *************/
22407#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22408 ((INSTANCE) == TIM2) || \
22409 ((INSTANCE) == TIM3) || \
22410 ((INSTANCE) == TIM4) || \
22411 ((INSTANCE) == TIM5) || \
22412 ((INSTANCE) == TIM8) || \
22413 ((INSTANCE) == TIM12) || \
22414 ((INSTANCE) == TIM13) || \
22415 ((INSTANCE) == TIM14) || \
22416 ((INSTANCE) == TIM15) || \
22417 ((INSTANCE) == TIM16) || \
22418 ((INSTANCE) == TIM17))
22419
22420/************ TIM Instances : at least 2 capture/compare channels *************/
22421#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22422 ((INSTANCE) == TIM2) || \
22423 ((INSTANCE) == TIM3) || \
22424 ((INSTANCE) == TIM4) || \
22425 ((INSTANCE) == TIM5) || \
22426 ((INSTANCE) == TIM8) || \
22427 ((INSTANCE) == TIM12) || \
22428 ((INSTANCE) == TIM15))
22429
22430/************ TIM Instances : at least 3 capture/compare channels *************/
22431#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22432 ((INSTANCE) == TIM2) || \
22433 ((INSTANCE) == TIM3) || \
22434 ((INSTANCE) == TIM4) || \
22435 ((INSTANCE) == TIM5) || \
22436 ((INSTANCE) == TIM8))
22437
22438/************ TIM Instances : at least 4 capture/compare channels *************/
22439#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22440 ((INSTANCE) == TIM2) || \
22441 ((INSTANCE) == TIM3) || \
22442 ((INSTANCE) == TIM4) || \
22443 ((INSTANCE) == TIM5) || \
22444 ((INSTANCE) == TIM8))
22445
22446/************ TIM Instances : at least 5 capture/compare channels *************/
22447#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22448 ((INSTANCE) == TIM8))
22449/************ TIM Instances : at least 6 capture/compare channels *************/
22450#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22451 ((INSTANCE) == TIM8))
22452
22453/******************** TIM Instances : Advanced-control timers *****************/
22454#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22455 ((__INSTANCE__) == TIM8))
22456
22457/******************** TIM Instances : Advanced-control timers *****************/
22458
22459/******************* TIM Instances : Timer input XOR function *****************/
22460#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22461 ((INSTANCE) == TIM2) || \
22462 ((INSTANCE) == TIM3) || \
22463 ((INSTANCE) == TIM4) || \
22464 ((INSTANCE) == TIM5) || \
22465 ((INSTANCE) == TIM8) || \
22466 ((INSTANCE) == TIM15))
22467
22468/****************** TIM Instances : DMA requests generation (UDE) *************/
22469#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22470 ((INSTANCE) == TIM2) || \
22471 ((INSTANCE) == TIM3) || \
22472 ((INSTANCE) == TIM4) || \
22473 ((INSTANCE) == TIM5) || \
22474 ((INSTANCE) == TIM6) || \
22475 ((INSTANCE) == TIM7) || \
22476 ((INSTANCE) == TIM8) || \
22477 ((INSTANCE) == TIM15) || \
22478 ((INSTANCE) == TIM16) || \
22479 ((INSTANCE) == TIM17))
22480
22481/************ TIM Instances : DMA requests generation (CCxDE) *****************/
22482#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22483 ((INSTANCE) == TIM2) || \
22484 ((INSTANCE) == TIM3) || \
22485 ((INSTANCE) == TIM4) || \
22486 ((INSTANCE) == TIM5) || \
22487 ((INSTANCE) == TIM8) || \
22488 ((INSTANCE) == TIM15) || \
22489 ((INSTANCE) == TIM16) || \
22490 ((INSTANCE) == TIM17))
22491
22492/************ TIM Instances : DMA requests generation (COMDE) *****************/
22493#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22494 ((INSTANCE) == TIM2) || \
22495 ((INSTANCE) == TIM3) || \
22496 ((INSTANCE) == TIM4) || \
22497 ((INSTANCE) == TIM5) || \
22498 ((INSTANCE) == TIM8) || \
22499 ((INSTANCE) == TIM15))
22500
22501/******************** TIM Instances : DMA burst feature ***********************/
22502#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22503 ((INSTANCE) == TIM2) || \
22504 ((INSTANCE) == TIM3) || \
22505 ((INSTANCE) == TIM4) || \
22506 ((INSTANCE) == TIM5) || \
22507 ((INSTANCE) == TIM8))
22508
22509/*************** TIM Instances : external trigger reamp input available *******/
22510#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22511 ((INSTANCE) == TIM2) || \
22512 ((INSTANCE) == TIM3) || \
22513 ((INSTANCE) == TIM4) || \
22514 ((INSTANCE) == TIM5) || \
22515 ((INSTANCE) == TIM8))
22516
22517/****************** TIM Instances : remapping capability **********************/
22518#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22519 ((INSTANCE) == TIM2) || \
22520 ((INSTANCE) == TIM3) || \
22521 ((INSTANCE) == TIM5) || \
22522 ((INSTANCE) == TIM8) || \
22523 ((INSTANCE) == TIM16) || \
22524 ((INSTANCE) == TIM17))
22525
22526/*************** TIM Instances : external trigger reamp input available *******/
22527#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22528 ((INSTANCE) == TIM2) || \
22529 ((INSTANCE) == TIM3) || \
22530 ((INSTANCE) == TIM5) || \
22531 ((INSTANCE) == TIM8))
22532
22533/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
22534#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22535 ((INSTANCE) == TIM2) || \
22536 ((INSTANCE) == TIM3) || \
22537 ((INSTANCE) == TIM4) || \
22538 ((INSTANCE) == TIM5) || \
22539 ((INSTANCE) == TIM6) || \
22540 ((INSTANCE) == TIM7) || \
22541 ((INSTANCE) == TIM8) || \
22542 ((INSTANCE) == TIM12) || \
22543 ((INSTANCE) == TIM15))
22544
22545/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
22546#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22547 ((INSTANCE) == TIM2) || \
22548 ((INSTANCE) == TIM3) || \
22549 ((INSTANCE) == TIM4) || \
22550 ((INSTANCE) == TIM5) || \
22551 ((INSTANCE) == TIM8) || \
22552 ((INSTANCE) == TIM12) || \
22553 ((INSTANCE) == TIM15))
22554
22555/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
22556#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22557 ((INSTANCE) == TIM8))
22558
22559/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
22560#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22561 ((INSTANCE) == TIM2) || \
22562 ((INSTANCE) == TIM3) || \
22563 ((INSTANCE) == TIM4) || \
22564 ((INSTANCE) == TIM5) || \
22565 ((INSTANCE) == TIM8) || \
22566 ((INSTANCE) == TIM15) || \
22567 ((INSTANCE) == TIM16) || \
22568 ((INSTANCE) == TIM17))
22569
22570/****************** TIM Instances : supporting commutation event *************/
22571#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22572 ((INSTANCE) == TIM8) || \
22573 ((INSTANCE) == TIM15) || \
22574 ((INSTANCE) == TIM16) || \
22575 ((INSTANCE) == TIM17))
22576
22577/****************** TIM Instances : supporting encoder interface **************/
22578#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22579 ((__INSTANCE__) == TIM2) || \
22580 ((__INSTANCE__) == TIM3) || \
22581 ((__INSTANCE__) == TIM4) || \
22582 ((__INSTANCE__) == TIM5) || \
22583 ((__INSTANCE__) == TIM8))
22584
22585/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
22586#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22587 ((INSTANCE) == TIM8))
22588/******************* TIM Instances : output(s) available **********************/
22589#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
22590 ((((INSTANCE) == TIM1) && \
22591 (((CHANNEL) == TIM_CHANNEL_1) || \
22592 ((CHANNEL) == TIM_CHANNEL_2) || \
22593 ((CHANNEL) == TIM_CHANNEL_3) || \
22594 ((CHANNEL) == TIM_CHANNEL_4) || \
22595 ((CHANNEL) == TIM_CHANNEL_5) || \
22596 ((CHANNEL) == TIM_CHANNEL_6))) \
22597 || \
22598 (((INSTANCE) == TIM2) && \
22599 (((CHANNEL) == TIM_CHANNEL_1) || \
22600 ((CHANNEL) == TIM_CHANNEL_2) || \
22601 ((CHANNEL) == TIM_CHANNEL_3) || \
22602 ((CHANNEL) == TIM_CHANNEL_4))) \
22603 || \
22604 (((INSTANCE) == TIM3) && \
22605 (((CHANNEL) == TIM_CHANNEL_1)|| \
22606 ((CHANNEL) == TIM_CHANNEL_2) || \
22607 ((CHANNEL) == TIM_CHANNEL_3) || \
22608 ((CHANNEL) == TIM_CHANNEL_4))) \
22609 || \
22610 (((INSTANCE) == TIM4) && \
22611 (((CHANNEL) == TIM_CHANNEL_1) || \
22612 ((CHANNEL) == TIM_CHANNEL_2) || \
22613 ((CHANNEL) == TIM_CHANNEL_3) || \
22614 ((CHANNEL) == TIM_CHANNEL_4))) \
22615 || \
22616 (((INSTANCE) == TIM5) && \
22617 (((CHANNEL) == TIM_CHANNEL_1) || \
22618 ((CHANNEL) == TIM_CHANNEL_2) || \
22619 ((CHANNEL) == TIM_CHANNEL_3) || \
22620 ((CHANNEL) == TIM_CHANNEL_4))) \
22621 || \
22622 (((INSTANCE) == TIM8) && \
22623 (((CHANNEL) == TIM_CHANNEL_1) || \
22624 ((CHANNEL) == TIM_CHANNEL_2) || \
22625 ((CHANNEL) == TIM_CHANNEL_3) || \
22626 ((CHANNEL) == TIM_CHANNEL_4) || \
22627 ((CHANNEL) == TIM_CHANNEL_5) || \
22628 ((CHANNEL) == TIM_CHANNEL_6))) \
22629 || \
22630 (((INSTANCE) == TIM12) && \
22631 (((CHANNEL) == TIM_CHANNEL_1) || \
22632 ((CHANNEL) == TIM_CHANNEL_2))) \
22633 || \
22634 (((INSTANCE) == TIM13) && \
22635 (((CHANNEL) == TIM_CHANNEL_1))) \
22636 || \
22637 (((INSTANCE) == TIM14) && \
22638 (((CHANNEL) == TIM_CHANNEL_1))) \
22639 || \
22640 (((INSTANCE) == TIM15) && \
22641 (((CHANNEL) == TIM_CHANNEL_1) || \
22642 ((CHANNEL) == TIM_CHANNEL_2))) \
22643 || \
22644 (((INSTANCE) == TIM16) && \
22645 (((CHANNEL) == TIM_CHANNEL_1))) \
22646 || \
22647 (((INSTANCE) == TIM17) && \
22648 (((CHANNEL) == TIM_CHANNEL_1))))
22649
22650/****************** TIM Instances : supporting the break function *************/
22651#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
22652 (((INSTANCE) == TIM1) || \
22653 ((INSTANCE) == TIM8) || \
22654 ((INSTANCE) == TIM15) || \
22655 ((INSTANCE) == TIM16) || \
22656 ((INSTANCE) == TIM17))
22657
22658/************** TIM Instances : supporting Break source selection *************/
22659#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22660 ((INSTANCE) == TIM8))
22661
22662/****************** TIM Instances : supporting complementary output(s) ********/
22663#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
22664 ((((INSTANCE) == TIM1) && \
22665 (((CHANNEL) == TIM_CHANNEL_1) || \
22666 ((CHANNEL) == TIM_CHANNEL_2) || \
22667 ((CHANNEL) == TIM_CHANNEL_3))) \
22668 || \
22669 (((INSTANCE) == TIM8) && \
22670 (((CHANNEL) == TIM_CHANNEL_1) || \
22671 ((CHANNEL) == TIM_CHANNEL_2) || \
22672 ((CHANNEL) == TIM_CHANNEL_3))) \
22673 || \
22674 (((INSTANCE) == TIM15) && \
22675 ((CHANNEL) == TIM_CHANNEL_1)) \
22676 || \
22677 (((INSTANCE) == TIM16) && \
22678 ((CHANNEL) == TIM_CHANNEL_1)) \
22679 || \
22680 (((INSTANCE) == TIM17) && \
22681 ((CHANNEL) == TIM_CHANNEL_1)))
22682
22683/****************** TIM Instances : supporting counting mode selection ********/
22684#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
22685 (((INSTANCE) == TIM1) || \
22686 ((INSTANCE) == TIM2) || \
22687 ((INSTANCE) == TIM3) || \
22688 ((INSTANCE) == TIM4) || \
22689 ((INSTANCE) == TIM5) || \
22690 ((INSTANCE) == TIM8))
22691
22692/****************** TIM Instances : supporting repetition counter *************/
22693#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
22694 (((INSTANCE) == TIM1) || \
22695 ((INSTANCE) == TIM8) || \
22696 ((INSTANCE) == TIM15) || \
22697 ((INSTANCE) == TIM16) || \
22698 ((INSTANCE) == TIM17))
22699
22700/****************** TIM Instances : supporting synchronization ****************/
22701#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
22702 (((__INSTANCE__) == TIM1) || \
22703 ((__INSTANCE__) == TIM2) || \
22704 ((__INSTANCE__) == TIM3) || \
22705 ((__INSTANCE__) == TIM4) || \
22706 ((__INSTANCE__) == TIM5) || \
22707 ((__INSTANCE__) == TIM6) || \
22708 ((__INSTANCE__) == TIM8) || \
22709 ((__INSTANCE__) == TIM12) || \
22710 ((__INSTANCE__) == TIM15))
22711
22712/****************** TIM Instances : supporting clock division *****************/
22713#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
22714 (((INSTANCE) == TIM1) || \
22715 ((INSTANCE) == TIM2) || \
22716 ((INSTANCE) == TIM3) || \
22717 ((INSTANCE) == TIM4) || \
22718 ((INSTANCE) == TIM5) || \
22719 ((INSTANCE) == TIM8) || \
22720 ((INSTANCE) == TIM15) || \
22721 ((INSTANCE) == TIM16) || \
22722 ((INSTANCE) == TIM17))
22723
22724/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
22725#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
22726 (((INSTANCE) == TIM1) || \
22727 ((INSTANCE) == TIM2) || \
22728 ((INSTANCE) == TIM3) || \
22729 ((INSTANCE) == TIM4) || \
22730 ((INSTANCE) == TIM5) || \
22731 ((INSTANCE) == TIM8))
22732
22733/****************** TIM Instances : supporting external clock mode 2 **********/
22734#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
22735 (((INSTANCE) == TIM1) || \
22736 ((INSTANCE) == TIM2) || \
22737 ((INSTANCE) == TIM3) || \
22738 ((INSTANCE) == TIM4) || \
22739 ((INSTANCE) == TIM5) || \
22740 ((INSTANCE) == TIM8))
22741
22742/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
22743#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
22744 (((INSTANCE) == TIM1) || \
22745 ((INSTANCE) == TIM2) || \
22746 ((INSTANCE) == TIM3) || \
22747 ((INSTANCE) == TIM4) || \
22748 ((INSTANCE) == TIM5) || \
22749 ((INSTANCE) == TIM8) || \
22750 ((INSTANCE) == TIM12) || \
22751 ((INSTANCE) == TIM15))
22752
22753/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
22754#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
22755 (((INSTANCE) == TIM1) || \
22756 ((INSTANCE) == TIM2) || \
22757 ((INSTANCE) == TIM3) || \
22758 ((INSTANCE) == TIM4) || \
22759 ((INSTANCE) == TIM5) || \
22760 ((INSTANCE) == TIM8) || \
22761 ((INSTANCE) == TIM12) || \
22762 ((INSTANCE) == TIM15))
22763
22764/****************** TIM Instances : supporting OCxREF clear *******************/
22765#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
22766 (((INSTANCE) == TIM1) || \
22767 ((INSTANCE) == TIM2) || \
22768 ((INSTANCE) == TIM3))
22769
22770/****************** TIM Instances : TIM_32B_COUNTER ***************************/
22771#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
22772 (((INSTANCE) == TIM2) || \
22773 ((INSTANCE) == TIM5))
22774
22775/****************** TIM Instances : TIM_BKIN2 ***************************/
22776#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
22777 (((INSTANCE) == TIM1) || \
22778 ((INSTANCE) == TIM8))
22779
22780/****************** TIM Instances : supporting Hall sensor interface **********/
22781#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22782 ((__INSTANCE__) == TIM2) || \
22783 ((__INSTANCE__) == TIM3) || \
22784 ((__INSTANCE__) == TIM4) || \
22785 ((__INSTANCE__) == TIM5) || \
22786 ((__INSTANCE__) == TIM15) || \
22787 ((__INSTANCE__) == TIM8))
22788
22789/******************** USART Instances : Synchronous mode **********************/
22790#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22791 ((INSTANCE) == USART2) || \
22792 ((INSTANCE) == USART3) || \
22793 ((INSTANCE) == USART6) || \
22794 ((INSTANCE) == USART10))
22795
22796/******************** USART Instances : SPI slave mode ************************/
22797#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22798 ((INSTANCE) == USART2) || \
22799 ((INSTANCE) == USART3) || \
22800 ((INSTANCE) == USART6) || \
22801 ((INSTANCE) == USART10))
22802
22803/******************** UART Instances : Asynchronous mode **********************/
22804#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22805 ((INSTANCE) == USART2) || \
22806 ((INSTANCE) == USART3) || \
22807 ((INSTANCE) == UART4) || \
22808 ((INSTANCE) == UART5) || \
22809 ((INSTANCE) == USART6) || \
22810 ((INSTANCE) == UART7) || \
22811 ((INSTANCE) == UART8) || \
22812 ((INSTANCE) == UART9) || \
22813 ((INSTANCE) == USART10))
22814
22815/******************** UART Instances : FIFO mode.******************************/
22816#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22817 ((INSTANCE) == USART2) || \
22818 ((INSTANCE) == USART3) || \
22819 ((INSTANCE) == UART4) || \
22820 ((INSTANCE) == UART5) || \
22821 ((INSTANCE) == USART6) || \
22822 ((INSTANCE) == UART7) || \
22823 ((INSTANCE) == UART8) || \
22824 ((INSTANCE) == UART9) || \
22825 ((INSTANCE) == USART10)|| \
22826 ((INSTANCE) == LPUART1))
22827
22828/****************** UART Instances : Auto Baud Rate detection *****************/
22829#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22830 ((INSTANCE) == USART2) || \
22831 ((INSTANCE) == USART3) || \
22832 ((INSTANCE) == UART4) || \
22833 ((INSTANCE) == UART5) || \
22834 ((INSTANCE) == USART6) || \
22835 ((INSTANCE) == UART7) || \
22836 ((INSTANCE) == UART8) || \
22837 ((INSTANCE) == UART9) || \
22838 ((INSTANCE) == USART10))
22839
22840/*********************** UART Instances : Driver Enable ***********************/
22841#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22842 ((INSTANCE) == USART2) || \
22843 ((INSTANCE) == USART3) || \
22844 ((INSTANCE) == UART4) || \
22845 ((INSTANCE) == UART5) || \
22846 ((INSTANCE) == USART6) || \
22847 ((INSTANCE) == UART7) || \
22848 ((INSTANCE) == UART8) || \
22849 ((INSTANCE) == UART9) || \
22850 ((INSTANCE) == USART10)|| \
22851 ((INSTANCE) == LPUART1))
22852
22853/********************* UART Instances : Half-Duplex mode **********************/
22854#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22855 ((INSTANCE) == USART2) || \
22856 ((INSTANCE) == USART3) || \
22857 ((INSTANCE) == UART4) || \
22858 ((INSTANCE) == UART5) || \
22859 ((INSTANCE) == USART6) || \
22860 ((INSTANCE) == UART7) || \
22861 ((INSTANCE) == UART8) || \
22862 ((INSTANCE) == UART9) || \
22863 ((INSTANCE) == USART10)|| \
22864 ((INSTANCE) == LPUART1))
22865
22866/******************* UART Instances : Hardware Flow control *******************/
22867#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22868 ((INSTANCE) == USART2) || \
22869 ((INSTANCE) == USART3) || \
22870 ((INSTANCE) == UART4) || \
22871 ((INSTANCE) == UART5) || \
22872 ((INSTANCE) == USART6) || \
22873 ((INSTANCE) == UART7) || \
22874 ((INSTANCE) == UART8) || \
22875 ((INSTANCE) == UART9) || \
22876 ((INSTANCE) == USART10)|| \
22877 ((INSTANCE) == LPUART1))
22878
22879/************************* UART Instances : LIN mode **************************/
22880#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22881 ((INSTANCE) == USART2) || \
22882 ((INSTANCE) == USART3) || \
22883 ((INSTANCE) == UART4) || \
22884 ((INSTANCE) == UART5) || \
22885 ((INSTANCE) == USART6) || \
22886 ((INSTANCE) == UART7) || \
22887 ((INSTANCE) == UART8) || \
22888 ((INSTANCE) == UART9) || \
22889 ((INSTANCE) == USART10))
22890
22891/****************** UART Instances : Wake-up from Stop mode *******************/
22892#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22893 ((INSTANCE) == USART2) || \
22894 ((INSTANCE) == USART3) || \
22895 ((INSTANCE) == UART4) || \
22896 ((INSTANCE) == UART5) || \
22897 ((INSTANCE) == USART6) || \
22898 ((INSTANCE) == UART7) || \
22899 ((INSTANCE) == UART8) || \
22900 ((INSTANCE) == UART9) || \
22901 ((INSTANCE) == USART10)|| \
22902 ((INSTANCE) == LPUART1))
22903
22904/************************* UART Instances : IRDA mode *************************/
22905#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22906 ((INSTANCE) == USART2) || \
22907 ((INSTANCE) == USART3) || \
22908 ((INSTANCE) == UART4) || \
22909 ((INSTANCE) == UART5) || \
22910 ((INSTANCE) == USART6) || \
22911 ((INSTANCE) == UART7) || \
22912 ((INSTANCE) == UART8) || \
22913 ((INSTANCE) == UART9) || \
22914 ((INSTANCE) == USART10))
22915
22916/********************* USART Instances : Smard card mode **********************/
22917#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22918 ((INSTANCE) == USART2) || \
22919 ((INSTANCE) == USART3) || \
22920 ((INSTANCE) == USART6) ||\
22921 ((INSTANCE) == USART10))
22922
22923/****************************** LPUART Instance *******************************/
22924#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
22925
22926/****************************** IWDG Instances ********************************/
22927#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
22928/****************************** USB Instances ********************************/
22929#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
22930
22931/****************************** WWDG Instances ********************************/
22932#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
22933/****************************** MDIOS Instances ********************************/
22934#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
22935
22936/****************************** CEC Instances *********************************/
22937#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
22938
22939/****************************** SAI Instances ********************************/
22940#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
22941 ((INSTANCE) == SAI1_Block_B) || \
22942 ((INSTANCE) == SAI2_Block_A) || \
22943 ((INSTANCE) == SAI2_Block_B))
22944
22945/****************************** SPDIFRX Instances ********************************/
22946#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
22947
22948/****************************** OPAMP Instances *******************************/
22949#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
22950 ((INSTANCE) == OPAMP2))
22951
22952#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
22953
22954/*********************** USB OTG PCD Instances ********************************/
22955#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
22956
22957/*********************** USB OTG HCD Instances ********************************/
22958#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
22959
22960/******************************************************************************/
22961/* For a painless codes migration between the STM32H7xx device product */
22962/* lines, or with STM32F7xx devices the aliases defined below are put */
22963/* in place to overcome the differences in the interrupt handlers and IRQn */
22964/* definitions. No need to update developed interrupt code when moving */
22965/* across product lines within the same STM32H7 Family */
22966/******************************************************************************/
22967
22968/* Aliases for __IRQn */
22969#define RNG_IRQn HASH_RNG_IRQn
22970#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
22971#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
22972#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
22973#define PVD_IRQn PVD_AVD_IRQn
22974
22975/* Aliases for BDMA __IRQn */
22976#define BDMA_Channel0_IRQn BDMA2_Channel0_IRQn
22977#define BDMA_Channel1_IRQn BDMA2_Channel1_IRQn
22978#define BDMA_Channel2_IRQn BDMA2_Channel2_IRQn
22979#define BDMA_Channel3_IRQn BDMA2_Channel3_IRQn
22980#define BDMA_Channel4_IRQn BDMA2_Channel4_IRQn
22981#define BDMA_Channel5_IRQn BDMA2_Channel5_IRQn
22982#define BDMA_Channel6_IRQn BDMA2_Channel6_IRQn
22983#define BDMA_Channel7_IRQn BDMA2_Channel7_IRQn
22984
22985/* Aliases for PWR __IRQn */
22986#define PVD_AVD_IRQn PVD_PVM_IRQn
22987
22988/* Aliases for DCMI/PSSI __IRQn */
22989#define DCMI_IRQn DCMI_PSSI_IRQn
22990
22991/* Aliases for __IRQHandler */
22992#define RNG_IRQHandler HASH_RNG_IRQHandler
22993#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
22994#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
22995#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
22996#define PVD_IRQHandler PVD_AVD_IRQHandler
22997
22998
22999/* Aliases for BDMA __IRQHandler */
23000#define BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler
23001#define BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler
23002#define BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler
23003#define BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler
23004#define BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler
23005#define BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler
23006#define BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler
23007#define BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler
23008
23009/* Aliases for PWR __IRQHandler */
23010#define PVD_AVD_IRQHandler PVD_PVM_IRQHandler
23011
23012/* Aliases for DCMI/PSSI __IRQHandler */
23013#define DCMI_IRQHandler DCMI_PSSI_IRQHandler
23014
23015/* Alias for BDMA defines */
23016#define BDMA_BASE BDMA2_BASE
23017#define BDMA_Channel0_BASE BDMA2_Channel0_BASE
23018#define BDMA_Channel1_BASE BDMA2_Channel1_BASE
23019#define BDMA_Channel2_BASE BDMA2_Channel2_BASE
23020#define BDMA_Channel3_BASE BDMA2_Channel3_BASE
23021#define BDMA_Channel4_BASE BDMA2_Channel4_BASE
23022#define BDMA_Channel5_BASE BDMA2_Channel5_BASE
23023#define BDMA_Channel6_BASE BDMA2_Channel6_BASE
23024#define BDMA_Channel7_BASE BDMA2_Channel7_BASE
23025
23026#define BDMA BDMA2
23027#define BDMA_Channel0 BDMA2_Channel0
23028#define BDMA_Channel1 BDMA2_Channel1
23029#define BDMA_Channel2 BDMA2_Channel2
23030#define BDMA_Channel3 BDMA2_Channel3
23031#define BDMA_Channel4 BDMA2_Channel4
23032#define BDMA_Channel5 BDMA2_Channel5
23033#define BDMA_Channel6 BDMA2_Channel6
23034#define BDMA_Channel7 BDMA2_Channel7
23035
23036/* Alias for PWR defines */
23037#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD
23038#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD
23039#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD
23040
23041#define PWR_D3CR_VOS PWR_SRDCR_VOS
23042
23043#define PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0
23044#define PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1
23045#define PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY
23046
23059#ifdef __cplusplus
23060}
23061#endif /* __cplusplus */
23062
23063#endif /* STM32H7B3xxQ_H */
23064
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h7b3xxq.h:49
CRS_IRQn
@ CRS_IRQn
Definition: stm32h7b3xxq.h:189
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32h7b3xxq.h:58
DFSDM2_IRQn
@ DFSDM2_IRQn
Definition: stm32h7b3xxq.h:103
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32h7b3xxq.h:69
MDIOS_IRQn
@ MDIOS_IRQn
Definition: stm32h7b3xxq.h:167
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32h7b3xxq.h:74
BDMA2_Channel0_IRQn
@ BDMA2_Channel0_IRQn
Definition: stm32h7b3xxq.h:174
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32h7b3xxq.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32h7b3xxq.h:156
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32h7b3xxq.h:134
BDMA2_Channel3_IRQn
@ BDMA2_Channel3_IRQn
Definition: stm32h7b3xxq.h:177
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32h7b3xxq.h:117
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32h7b3xxq.h:128
LPTIM3_IRQn
@ LPTIM3_IRQn
Definition: stm32h7b3xxq.h:184
TIM15_IRQn
@ TIM15_IRQn
Definition: stm32h7b3xxq.h:163
DTS_IRQn
@ DTS_IRQn
Definition: stm32h7b3xxq.h:191
UART7_IRQn
@ UART7_IRQn
Definition: stm32h7b3xxq.h:141
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32h7b3xxq.h:93
UART9_IRQn
@ UART9_IRQn
Definition: stm32h7b3xxq.h:185
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32h7b3xxq.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32h7b3xxq.h:53
TIM17_IRQn
@ TIM17_IRQn
Definition: stm32h7b3xxq.h:165
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32h7b3xxq.h:146
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32h7b3xxq.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32h7b3xxq.h:89
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition: stm32h7b3xxq.h:148
DCMI_PSSI_IRQn
@ DCMI_PSSI_IRQn
Definition: stm32h7b3xxq.h:137
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32h7b3xxq.h:129
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32h7b3xxq.h:104
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32h7b3xxq.h:80
USART2_IRQn
@ USART2_IRQn
Definition: stm32h7b3xxq.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32h7b3xxq.h:120
BDMA2_Channel7_IRQn
@ BDMA2_Channel7_IRQn
Definition: stm32h7b3xxq.h:181
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32h7b3xxq.h:56
ADC_IRQn
@ ADC_IRQn
Definition: stm32h7b3xxq.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32h7b3xxq.h:112
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32h7b3xxq.h:97
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32h7b3xxq.h:85
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32h7b3xxq.h:116
UART8_IRQn
@ UART8_IRQn
Definition: stm32h7b3xxq.h:142
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32h7b3xxq.h:81
RCC_IRQn
@ RCC_IRQn
Definition: stm32h7b3xxq.h:66
BDMA1_IRQn
@ BDMA1_IRQn
Definition: stm32h7b3xxq.h:197
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32h7b3xxq.h:183
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32h7b3xxq.h:115
DFSDM1_FLT5_IRQn
@ DFSDM1_FLT5_IRQn
Definition: stm32h7b3xxq.h:124
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32h7b3xxq.h:133
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32h7b3xxq.h:95
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32h7b3xxq.h:158
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32h7b3xxq.h:107
JPEG_IRQn
@ JPEG_IRQn
Definition: stm32h7b3xxq.h:168
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32h7b3xxq.h:55
DMAMUX2_OVR_IRQn
@ DMAMUX2_OVR_IRQn
Definition: stm32h7b3xxq.h:173
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32h7b3xxq.h:155
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32h7b3xxq.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32h7b3xxq.h:132
CRYP_IRQn
@ CRYP_IRQn
Definition: stm32h7b3xxq.h:138
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32h7b3xxq.h:161
BDMA2_Channel1_IRQn
@ BDMA2_Channel1_IRQn
Definition: stm32h7b3xxq.h:175
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32h7b3xxq.h:86
BDMA2_Channel5_IRQn
@ BDMA2_Channel5_IRQn
Definition: stm32h7b3xxq.h:179
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32h7b3xxq.h:131
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32h7b3xxq.h:54
HASH_RNG_IRQn
@ HASH_RNG_IRQn
Definition: stm32h7b3xxq.h:139
DMAMUX1_OVR_IRQn
@ DMAMUX1_OVR_IRQn
Definition: stm32h7b3xxq.h:157
CEC_IRQn
@ CEC_IRQn
Definition: stm32h7b3xxq.h:153
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32h7b3xxq.h:144
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32h7b3xxq.h:57
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32h7b3xxq.h:65
BDMA2_Channel2_IRQn
@ BDMA2_Channel2_IRQn
Definition: stm32h7b3xxq.h:176
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32h7b3xxq.h:162
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32h7b3xxq.h:127
GFXMMU_IRQn
@ GFXMMU_IRQn
Definition: stm32h7b3xxq.h:196
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32h7b3xxq.h:61
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32h7b3xxq.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32h7b3xxq.h:90
OTFDEC2_IRQn
@ OTFDEC2_IRQn
Definition: stm32h7b3xxq.h:195
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32h7b3xxq.h:118
DFSDM1_FLT4_IRQn
@ DFSDM1_FLT4_IRQn
Definition: stm32h7b3xxq.h:123
OCTOSPI1_IRQn
@ OCTOSPI1_IRQn
Definition: stm32h7b3xxq.h:151
BDMA2_Channel4_IRQn
@ BDMA2_Channel4_IRQn
Definition: stm32h7b3xxq.h:178
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32h7b3xxq.h:135
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32h7b3xxq.h:110
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32h7b3xxq.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32h7b3xxq.h:101
DFSDM1_FLT6_IRQn
@ DFSDM1_FLT6_IRQn
Definition: stm32h7b3xxq.h:125
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32h7b3xxq.h:143
OCTOSPI2_IRQn
@ OCTOSPI2_IRQn
Definition: stm32h7b3xxq.h:193
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32h7b3xxq.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32h7b3xxq.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32h7b3xxq.h:152
SPI6_IRQn
@ SPI6_IRQn
Definition: stm32h7b3xxq.h:145
FPU_IRQn
@ FPU_IRQn
Definition: stm32h7b3xxq.h:140
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32h7b3xxq.h:105
USART6_IRQn
@ USART6_IRQn
Definition: stm32h7b3xxq.h:130
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32h7b3xxq.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32h7b3xxq.h:136
OTFDEC1_IRQn
@ OTFDEC1_IRQn
Definition: stm32h7b3xxq.h:194
DAC2_IRQn
@ DAC2_IRQn
Definition: stm32h7b3xxq.h:172
HSEM1_IRQn
@ HSEM1_IRQn
Definition: stm32h7b3xxq.h:171
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32h7b3xxq.h:160
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32h7b3xxq.h:52
FMC_IRQn
@ FMC_IRQn
Definition: stm32h7b3xxq.h:109
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32h7b3xxq.h:67
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32h7b3xxq.h:71
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32h7b3xxq.h:150
BDMA2_Channel6_IRQn
@ BDMA2_Channel6_IRQn
Definition: stm32h7b3xxq.h:180
USART10_IRQn
@ USART10_IRQn
Definition: stm32h7b3xxq.h:186
FDCAN_CAL_IRQn
@ FDCAN_CAL_IRQn
Definition: stm32h7b3xxq.h:122
RTC_TAMP_STAMP_CSS_LSE_IRQn
@ RTC_TAMP_STAMP_CSS_LSE_IRQn
Definition: stm32h7b3xxq.h:63
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32h7b3xxq.h:119
DFSDM1_FLT7_IRQn
@ DFSDM1_FLT7_IRQn
Definition: stm32h7b3xxq.h:126
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32h7b3xxq.h:87
UART5_IRQn
@ UART5_IRQn
Definition: stm32h7b3xxq.h:114
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32h7b3xxq.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32h7b3xxq.h:149
WWDG_RST_IRQn
@ WWDG_RST_IRQn
Definition: stm32h7b3xxq.h:188
WAKEUP_PIN_IRQn
@ WAKEUP_PIN_IRQn
Definition: stm32h7b3xxq.h:192
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32h7b3xxq.h:154
ECC_IRQn
@ ECC_IRQn
Definition: stm32h7b3xxq.h:190
MDIOS_WKUP_IRQn
@ MDIOS_WKUP_IRQn
Definition: stm32h7b3xxq.h:166
USART1_IRQn
@ USART1_IRQn
Definition: stm32h7b3xxq.h:98
COMP_IRQn
@ COMP_IRQn
Definition: stm32h7b3xxq.h:182
MDMA_IRQn
@ MDMA_IRQn
Definition: stm32h7b3xxq.h:169
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32h7b3xxq.h:70
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32h7b3xxq.h:51
UART4_IRQn
@ UART4_IRQn
Definition: stm32h7b3xxq.h:113
PVD_PVM_IRQn
@ PVD_PVM_IRQn
Definition: stm32h7b3xxq.h:62
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32h7b3xxq.h:106
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32h7b3xxq.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32h7b3xxq.h:121
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32h7b3xxq.h:111
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32h7b3xxq.h:108
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32h7b3xxq.h:76
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32h7b3xxq.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32h7b3xxq.h:88
LTDC_IRQn
@ LTDC_IRQn
Definition: stm32h7b3xxq.h:147
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32h7b3xxq.h:82
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32h7b3xxq.h:187
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32h7b3xxq.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32h7b3xxq.h:170
USART3_IRQn
@ USART3_IRQn
Definition: stm32h7b3xxq.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32h7b3xxq.h:102
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32h7b3xxq.h:159
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32h7b3xxq.h:83
TIM16_IRQn
@ TIM16_IRQn
Definition: stm32h7b3xxq.h:164
SCR
#define SCR
Scratch register.
Definition: uart.h:94
FCR
#define FCR
FIFO Control Register (write)
Definition: uart.h:89
DR
#define DR
Bits definition of the Line Status Register (LSR)
Definition: uart.h:123
IER
#define IER
Interrupt Enable Register.
Definition: uart.h:85
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
AFR
#define AFR
Alternate Function register.
Definition: uart.h:99
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32h723xx.h:418
COMPOPT_TypeDef
Comparator.
Definition: stm32h723xx.h:1576
COMP_Common_TypeDef
Definition: stm32h723xx.h:1588
COMP_TypeDef
Definition: stm32h723xx.h:1583
CRC_TypeDef
CRC calculation unit.
Definition: stm32h723xx.h:442
CRS_TypeDef
Clock Recovery System.
Definition: stm32h723xx.h:456
CRYP_TypeDef
Crypto Processor.
Definition: stm32h730xx.h:1670
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DBGMCU_TypeDef
Debug MCU.
Definition: stm32h723xx.h:531
DCMI_TypeDef
DCMI.
Definition: stm32h723xx.h:561
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32h723xx.h:518
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32h723xx.h:496
DLYB_TypeDef
Delay Block DLYB.
Definition: stm32h723xx.h:1443
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32h723xx.h:686
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition: stm32h723xx.h:645
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32h723xx.h:601
DMA_TypeDef
Definition: stm32h723xx.h:611
DTS_TypeDef
DTS.
Definition: stm32h723xx.h:1504
EXTI_Core_TypeDef
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
Definition: stm32h723xx.h:936
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32h723xx.h:891
FDCAN_ClockCalibrationUnit_TypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:403
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:315
FLASH_TypeDef
FLASH Registers.
Definition: stm32h723xx.h:956
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32h723xx.h:1015
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32h723xx.h:1006
FMC_Bank2_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32h723xx.h:1024
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32h723xx.h:1038
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5 and 6.
Definition: stm32h723xx.h:1053
GFXMMU_TypeDef
GFXMMU registers.
Definition: stm32h7a3xx.h:874
GPIO_TypeDef
General Purpose I/O.
Definition: stm32h723xx.h:1066
GPV_TypeDef
Global Programmer View.
Definition: stm32h723xx.h:1966
HASH_DIGEST_TypeDef
HASH_DIGEST.
Definition: stm32h730xx.h:1730
HASH_TypeDef
HASH.
Definition: stm32h730xx.h:1714
HSEM_Common_TypeDef
Definition: stm32h723xx.h:1467
HSEM_TypeDef
HW Semaphore HSEM.
Definition: stm32h723xx.h:1453
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32h723xx.h:1152
JPEG_TypeDef
JPEG Codec.
Definition: stm32h743xx.h:1126
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32h723xx.h:1559
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32h723xx.h:1191
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32h723xx.h:1166
MDIOS_TypeDef
MDIOS.
Definition: stm32h723xx.h:1681
MDMA_Channel_TypeDef
Definition: stm32h723xx.h:664
MDMA_TypeDef
MDMA Controller.
Definition: stm32h723xx.h:659
OCTOSPIM_TypeDef
OCTO Serial Peripheral Interface IO Manager.
Definition: stm32h723xx.h:1952
OCTOSPI_TypeDef
OCTO Serial Peripheral Interface.
Definition: stm32h723xx.h:1887
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32h723xx.h:1083
OTFDEC_Region_TypeDef
OTFD register.
Definition: stm32h730xx.h:2037
OTFDEC_TypeDef
Definition: stm32h730xx.h:2050
PSSI_TypeDef
PSSI.
Definition: stm32h723xx.h:580
PWR_TypeDef
Power Control.
Definition: stm32h723xx.h:1214
RAMECC_MonitorTypeDef
RAM_ECC_Specific_Registers.
Definition: stm32h723xx.h:1644
RAMECC_TypeDef
Definition: stm32h723xx.h:1654
RCC_TypeDef
Reset and Clock Control.
Definition: stm32h723xx.h:1233
RNG_TypeDef
RNG.
Definition: stm32h723xx.h:1668
RTC_TypeDef
Real-Time Clock.
Definition: stm32h723xx.h:1307
SAI_Block_TypeDef
Definition: stm32h723xx.h:1375
SAI_TypeDef
Serial Audio Interface.
Definition: stm32h723xx.h:1367
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32h723xx.h:1408
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32h723xx.h:1391
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
SYSCFG_TypeDef
System configuration controller.
Definition: stm32h723xx.h:1094
TAMP_TypeDef
Tamper and backup registers.
Definition: stm32h7a3xx.h:1184
TIM_TypeDef
TIM.
Definition: stm32h723xx.h:1525
TTCAN_TypeDef
TTFD Controller Area Network.
Definition: stm32h723xx.h:376
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32h723xx.h:1596
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32h723xx.h:1796
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32h723xx.h:1761
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32h723xx.h:1869
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32h723xx.h:1855
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32h723xx.h:1824
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32h723xx.h:1840
VREFBUF_TypeDef
VREFBUF.
Definition: stm32h723xx.h:304
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32h723xx.h:1633
_pr
Definition: hexdump.h:39
system_stm32h7xx.h
CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
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