RTEMS 6.1-rc1
stm32h745xg.h
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1
33#ifndef STM32H745xG_H
34#define STM32H745xG_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
48typedef enum
49{
50/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
51 NonMaskableInt_IRQn = -14,
52 HardFault_IRQn = -13,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_AVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 FDCAN1_IT0_IRQn = 19,
81 FDCAN2_IT0_IRQn = 20,
82 FDCAN1_IT1_IRQn = 21,
83 FDCAN2_IT1_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_IRQn = 24,
86 TIM1_UP_IRQn = 25,
87 TIM1_TRG_COM_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 TIM8_BRK_TIM12_IRQn = 43,
104 TIM8_UP_TIM13_IRQn = 44,
105 TIM8_TRG_COM_TIM14_IRQn = 45,
106 TIM8_CC_IRQn = 46,
107 DMA1_Stream7_IRQn = 47,
108 FMC_IRQn = 48,
109 SDMMC1_IRQn = 49,
110 TIM5_IRQn = 50,
111 SPI3_IRQn = 51,
112 UART4_IRQn = 52,
113 UART5_IRQn = 53,
114 TIM6_DAC_IRQn = 54,
115 TIM7_IRQn = 55,
116 DMA2_Stream0_IRQn = 56,
117 DMA2_Stream1_IRQn = 57,
118 DMA2_Stream2_IRQn = 58,
119 DMA2_Stream3_IRQn = 59,
120 DMA2_Stream4_IRQn = 60,
121 ETH_IRQn = 61,
122 ETH_WKUP_IRQn = 62,
123 FDCAN_CAL_IRQn = 63,
124 CM7_SEV_IRQn = 64,
125 CM4_SEV_IRQn = 65,
126 DMA2_Stream5_IRQn = 68,
127 DMA2_Stream6_IRQn = 69,
128 DMA2_Stream7_IRQn = 70,
129 USART6_IRQn = 71,
130 I2C3_EV_IRQn = 72,
131 I2C3_ER_IRQn = 73,
132 OTG_HS_EP1_OUT_IRQn = 74,
133 OTG_HS_EP1_IN_IRQn = 75,
134 OTG_HS_WKUP_IRQn = 76,
135 OTG_HS_IRQn = 77,
136 DCMI_IRQn = 78,
137 RNG_IRQn = 80,
138 FPU_IRQn = 81,
139 UART7_IRQn = 82,
140 UART8_IRQn = 83,
141 SPI4_IRQn = 84,
142 SPI5_IRQn = 85,
143 SPI6_IRQn = 86,
144 SAI1_IRQn = 87,
145 LTDC_IRQn = 88,
146 LTDC_ER_IRQn = 89,
147 DMA2D_IRQn = 90,
148 SAI2_IRQn = 91,
149 QUADSPI_IRQn = 92,
150 LPTIM1_IRQn = 93,
151 CEC_IRQn = 94,
152 I2C4_EV_IRQn = 95,
153 I2C4_ER_IRQn = 96,
154 SPDIF_RX_IRQn = 97,
155 OTG_FS_EP1_OUT_IRQn = 98,
156 OTG_FS_EP1_IN_IRQn = 99,
157 OTG_FS_WKUP_IRQn = 100,
158 OTG_FS_IRQn = 101,
159 DMAMUX1_OVR_IRQn = 102,
160 HRTIM1_Master_IRQn = 103,
161 HRTIM1_TIMA_IRQn = 104,
162 HRTIM1_TIMB_IRQn = 105,
163 HRTIM1_TIMC_IRQn = 106,
164 HRTIM1_TIMD_IRQn = 107,
165 HRTIM1_TIME_IRQn = 108,
166 HRTIM1_FLT_IRQn = 109,
167 DFSDM1_FLT0_IRQn = 110,
168 DFSDM1_FLT1_IRQn = 111,
169 DFSDM1_FLT2_IRQn = 112,
170 DFSDM1_FLT3_IRQn = 113,
171 SAI3_IRQn = 114,
172 SWPMI1_IRQn = 115,
173 TIM15_IRQn = 116,
174 TIM16_IRQn = 117,
175 TIM17_IRQn = 118,
176 MDIOS_WKUP_IRQn = 119,
177 MDIOS_IRQn = 120,
178 JPEG_IRQn = 121,
179 MDMA_IRQn = 122,
180 SDMMC2_IRQn = 124,
181 HSEM1_IRQn = 125,
182 HSEM2_IRQn = 126,
183 ADC3_IRQn = 127,
184 DMAMUX2_OVR_IRQn = 128,
185 BDMA_Channel0_IRQn = 129,
186 BDMA_Channel1_IRQn = 130,
187 BDMA_Channel2_IRQn = 131,
188 BDMA_Channel3_IRQn = 132,
189 BDMA_Channel4_IRQn = 133,
190 BDMA_Channel5_IRQn = 134,
191 BDMA_Channel6_IRQn = 135,
192 BDMA_Channel7_IRQn = 136,
193 COMP_IRQn = 137 ,
194 LPTIM2_IRQn = 138,
195 LPTIM3_IRQn = 139,
196 LPTIM4_IRQn = 140,
197 LPTIM5_IRQn = 141,
198 LPUART1_IRQn = 142,
199 WWDG_RST_IRQn = 143,
200 CRS_IRQn = 144,
201 ECC_IRQn = 145,
202 SAI4_IRQn = 146,
203 HOLD_CORE_IRQn = 148,
204 WAKEUP_PIN_IRQn = 149,
205} IRQn_Type;
206
214#define DUAL_CORE
216#define SMPS
223#ifdef CORE_CM4
224#define __CM4_REV 0x0001U
225#define __MPU_PRESENT 1U
226#define __NVIC_PRIO_BITS 4U
227#define __Vendor_SysTickConfig 0U
228#define __FPU_PRESENT 1U
230#include "core_cm4.h"
231#else /* CORE_CM7 */
232#ifdef CORE_CM7
233#define __CM7_REV 0x0100U
234#define __MPU_PRESENT 1U
235#define __NVIC_PRIO_BITS 4U
236#define __Vendor_SysTickConfig 0U
237#define __FPU_PRESENT 1U
238#define __ICACHE_PRESENT 1U
239#define __DCACHE_PRESENT 1U
240#include "core_cm7.h"
241#else /* UNKNOWN_CORE */
242#error Please #define CORE_CM4 or CORE_CM7
243#endif /* CORE_CM7 */
244#endif /* CORE_CM4 */
245
254#include "system_stm32h7xx.h"
255#include <stdint.h>
256
265typedef struct
266{
267 __IO uint32_t ISR;
268 __IO uint32_t IER;
269 __IO uint32_t CR;
270 __IO uint32_t CFGR;
271 __IO uint32_t CFGR2;
272 __IO uint32_t SMPR1;
273 __IO uint32_t SMPR2;
274 __IO uint32_t PCSEL;
275 __IO uint32_t LTR1;
276 __IO uint32_t HTR1;
277 uint32_t RESERVED1;
278 uint32_t RESERVED2;
279 __IO uint32_t SQR1;
280 __IO uint32_t SQR2;
281 __IO uint32_t SQR3;
282 __IO uint32_t SQR4;
283 __IO uint32_t DR;
284 uint32_t RESERVED3;
285 uint32_t RESERVED4;
286 __IO uint32_t JSQR;
287 uint32_t RESERVED5[4];
288 __IO uint32_t OFR1;
289 __IO uint32_t OFR2;
290 __IO uint32_t OFR3;
291 __IO uint32_t OFR4;
292 uint32_t RESERVED6[4];
293 __IO uint32_t JDR1;
294 __IO uint32_t JDR2;
295 __IO uint32_t JDR3;
296 __IO uint32_t JDR4;
297 uint32_t RESERVED7[4];
298 __IO uint32_t AWD2CR;
299 __IO uint32_t AWD3CR;
300 uint32_t RESERVED8;
301 uint32_t RESERVED9;
302 __IO uint32_t LTR2;
303 __IO uint32_t HTR2;
304 __IO uint32_t LTR3;
305 __IO uint32_t HTR3;
306 __IO uint32_t DIFSEL;
307 __IO uint32_t CALFACT;
308 __IO uint32_t CALFACT2;
309} ADC_TypeDef;
310
311
312typedef struct
313{
314__IO uint32_t CSR;
315uint32_t RESERVED;
316__IO uint32_t CCR;
317__IO uint32_t CDR;
318__IO uint32_t CDR2;
320} ADC_Common_TypeDef;
321
326typedef struct
327{
328 __IO uint32_t CTR;
329}ART_TypeDef;
330
335typedef struct
336{
337 __IO uint32_t CSR;
338 __IO uint32_t CCR;
339} VREFBUF_TypeDef;
340
341
346typedef struct
347{
348 __IO uint32_t CREL;
349 __IO uint32_t ENDN;
350 __IO uint32_t RESERVED1;
351 __IO uint32_t DBTP;
352 __IO uint32_t TEST;
353 __IO uint32_t RWD;
354 __IO uint32_t CCCR;
355 __IO uint32_t NBTP;
356 __IO uint32_t TSCC;
357 __IO uint32_t TSCV;
358 __IO uint32_t TOCC;
359 __IO uint32_t TOCV;
360 __IO uint32_t RESERVED2[4];
361 __IO uint32_t ECR;
362 __IO uint32_t PSR;
363 __IO uint32_t TDCR;
364 __IO uint32_t RESERVED3;
365 __IO uint32_t IR;
366 __IO uint32_t IE;
367 __IO uint32_t ILS;
368 __IO uint32_t ILE;
369 __IO uint32_t RESERVED4[8];
370 __IO uint32_t GFC;
371 __IO uint32_t SIDFC;
372 __IO uint32_t XIDFC;
373 __IO uint32_t RESERVED5;
374 __IO uint32_t XIDAM;
375 __IO uint32_t HPMS;
376 __IO uint32_t NDAT1;
377 __IO uint32_t NDAT2;
378 __IO uint32_t RXF0C;
379 __IO uint32_t RXF0S;
380 __IO uint32_t RXF0A;
381 __IO uint32_t RXBC;
382 __IO uint32_t RXF1C;
383 __IO uint32_t RXF1S;
384 __IO uint32_t RXF1A;
385 __IO uint32_t RXESC;
386 __IO uint32_t TXBC;
387 __IO uint32_t TXFQS;
388 __IO uint32_t TXESC;
389 __IO uint32_t TXBRP;
390 __IO uint32_t TXBAR;
391 __IO uint32_t TXBCR;
392 __IO uint32_t TXBTO;
393 __IO uint32_t TXBCF;
394 __IO uint32_t TXBTIE;
395 __IO uint32_t TXBCIE;
396 __IO uint32_t RESERVED6[2];
397 __IO uint32_t TXEFC;
398 __IO uint32_t TXEFS;
399 __IO uint32_t TXEFA;
400 __IO uint32_t RESERVED7;
401} FDCAN_GlobalTypeDef;
402
407typedef struct
408{
409 __IO uint32_t TTTMC;
410 __IO uint32_t TTRMC;
411 __IO uint32_t TTOCF;
412 __IO uint32_t TTMLM;
413 __IO uint32_t TURCF;
414 __IO uint32_t TTOCN;
415 __IO uint32_t TTGTP;
416 __IO uint32_t TTTMK;
417 __IO uint32_t TTIR;
418 __IO uint32_t TTIE;
419 __IO uint32_t TTILS;
420 __IO uint32_t TTOST;
421 __IO uint32_t TURNA;
422 __IO uint32_t TTLGT;
423 __IO uint32_t TTCTC;
424 __IO uint32_t TTCPT;
425 __IO uint32_t TTCSM;
426 __IO uint32_t RESERVED1[111];
427 __IO uint32_t TTTS;
428} TTCAN_TypeDef;
429
434typedef struct
435{
436 __IO uint32_t CREL;
437 __IO uint32_t CCFG;
438 __IO uint32_t CSTAT;
439 __IO uint32_t CWD;
440 __IO uint32_t IR;
441 __IO uint32_t IE;
442} FDCAN_ClockCalibrationUnit_TypeDef;
443
444
449typedef struct
450{
451 __IO uint32_t CR;
452 __IO uint32_t CFGR;
453 __IO uint32_t TXDR;
454 __IO uint32_t RXDR;
455 __IO uint32_t ISR;
456 __IO uint32_t IER;
457}CEC_TypeDef;
458
463typedef struct
464{
465 __IO uint32_t DR;
466 __IO uint32_t IDR;
467 __IO uint32_t CR;
468 uint32_t RESERVED2;
469 __IO uint32_t INIT;
470 __IO uint32_t POL;
471} CRC_TypeDef;
472
473
477typedef struct
478{
479__IO uint32_t CR;
480__IO uint32_t CFGR;
481__IO uint32_t ISR;
482__IO uint32_t ICR;
483} CRS_TypeDef;
484
485
490typedef struct
491{
492 __IO uint32_t CR;
493 __IO uint32_t SWTRIGR;
494 __IO uint32_t DHR12R1;
495 __IO uint32_t DHR12L1;
496 __IO uint32_t DHR8R1;
497 __IO uint32_t DHR12R2;
498 __IO uint32_t DHR12L2;
499 __IO uint32_t DHR8R2;
500 __IO uint32_t DHR12RD;
501 __IO uint32_t DHR12LD;
502 __IO uint32_t DHR8RD;
503 __IO uint32_t DOR1;
504 __IO uint32_t DOR2;
505 __IO uint32_t SR;
506 __IO uint32_t CCR;
507 __IO uint32_t MCR;
508 __IO uint32_t SHSR1;
509 __IO uint32_t SHSR2;
510 __IO uint32_t SHHR;
511 __IO uint32_t SHRR;
512} DAC_TypeDef;
513
517typedef struct
518{
519 __IO uint32_t FLTCR1;
520 __IO uint32_t FLTCR2;
521 __IO uint32_t FLTISR;
522 __IO uint32_t FLTICR;
523 __IO uint32_t FLTJCHGR;
524 __IO uint32_t FLTFCR;
525 __IO uint32_t FLTJDATAR;
526 __IO uint32_t FLTRDATAR;
527 __IO uint32_t FLTAWHTR;
528 __IO uint32_t FLTAWLTR;
529 __IO uint32_t FLTAWSR;
530 __IO uint32_t FLTAWCFR;
531 __IO uint32_t FLTEXMAX;
532 __IO uint32_t FLTEXMIN;
533 __IO uint32_t FLTCNVTIMR;
534} DFSDM_Filter_TypeDef;
535
539typedef struct
540{
541 __IO uint32_t CHCFGR1;
542 __IO uint32_t CHCFGR2;
543 __IO uint32_t CHAWSCDR;
545 __IO uint32_t CHWDATAR;
546 __IO uint32_t CHDATINR;
547} DFSDM_Channel_TypeDef;
548
552typedef struct
553{
554 __IO uint32_t IDCODE;
555 __IO uint32_t CR;
556 __IO uint32_t RESERVED4[11];
557 __IO uint32_t APB3FZ1;
558 __IO uint32_t APB3FZ2;
559 __IO uint32_t APB1LFZ1;
560 __IO uint32_t APB1LFZ2;
561 __IO uint32_t APB1HFZ1;
562 __IO uint32_t APB1HFZ2;
563 __IO uint32_t APB2FZ1;
564 __IO uint32_t APB2FZ2;
565 __IO uint32_t APB4FZ1;
566 __IO uint32_t APB4FZ2;
568}DBGMCU_TypeDef;
573typedef struct
574{
575 __IO uint32_t CR;
576 __IO uint32_t SR;
577 __IO uint32_t RISR;
578 __IO uint32_t IER;
579 __IO uint32_t MISR;
580 __IO uint32_t ICR;
581 __IO uint32_t ESCR;
582 __IO uint32_t ESUR;
583 __IO uint32_t CWSTRTR;
584 __IO uint32_t CWSIZER;
585 __IO uint32_t DR;
586} DCMI_TypeDef;
587
592typedef struct
593{
594 __IO uint32_t CR;
595 __IO uint32_t NDTR;
596 __IO uint32_t PAR;
597 __IO uint32_t M0AR;
598 __IO uint32_t M1AR;
599 __IO uint32_t FCR;
600} DMA_Stream_TypeDef;
601
602typedef struct
603{
604 __IO uint32_t LISR;
605 __IO uint32_t HISR;
606 __IO uint32_t LIFCR;
607 __IO uint32_t HIFCR;
608} DMA_TypeDef;
609
610typedef struct
611{
612 __IO uint32_t CCR;
613 __IO uint32_t CNDTR;
614 __IO uint32_t CPAR;
615 __IO uint32_t CM0AR;
616 __IO uint32_t CM1AR;
617} BDMA_Channel_TypeDef;
618
619typedef struct
620{
621 __IO uint32_t ISR;
622 __IO uint32_t IFCR;
623} BDMA_TypeDef;
624
625typedef struct
626{
627 __IO uint32_t CCR;
628}DMAMUX_Channel_TypeDef;
629
630typedef struct
631{
632 __IO uint32_t CSR;
633 __IO uint32_t CFR;
634}DMAMUX_ChannelStatus_TypeDef;
635
636typedef struct
637{
638 __IO uint32_t RGCR;
639}DMAMUX_RequestGen_TypeDef;
640
641typedef struct
642{
643 __IO uint32_t RGSR;
644 __IO uint32_t RGCFR;
645}DMAMUX_RequestGenStatus_TypeDef;
646
650typedef struct
651{
652 __IO uint32_t GISR0;
653}MDMA_TypeDef;
654
655typedef struct
656{
657 __IO uint32_t CISR;
658 __IO uint32_t CIFCR;
659 __IO uint32_t CESR;
660 __IO uint32_t CCR;
661 __IO uint32_t CTCR;
662 __IO uint32_t CBNDTR;
663 __IO uint32_t CSAR;
664 __IO uint32_t CDAR;
665 __IO uint32_t CBRUR;
666 __IO uint32_t CLAR;
667 __IO uint32_t CTBR;
668 uint32_t RESERVED0;
669 __IO uint32_t CMAR;
670 __IO uint32_t CMDR;
671}MDMA_Channel_TypeDef;
672
677typedef struct
678{
679 __IO uint32_t CR;
680 __IO uint32_t ISR;
681 __IO uint32_t IFCR;
682 __IO uint32_t FGMAR;
683 __IO uint32_t FGOR;
684 __IO uint32_t BGMAR;
685 __IO uint32_t BGOR;
686 __IO uint32_t FGPFCCR;
687 __IO uint32_t FGCOLR;
688 __IO uint32_t BGPFCCR;
689 __IO uint32_t BGCOLR;
690 __IO uint32_t FGCMAR;
691 __IO uint32_t BGCMAR;
692 __IO uint32_t OPFCCR;
693 __IO uint32_t OCOLR;
694 __IO uint32_t OMAR;
695 __IO uint32_t OOR;
696 __IO uint32_t NLR;
697 __IO uint32_t LWR;
698 __IO uint32_t AMTCR;
699 uint32_t RESERVED[236];
700 __IO uint32_t FGCLUT[256];
701 __IO uint32_t BGCLUT[256];
702} DMA2D_TypeDef;
703
704
708typedef struct
709{
710 __IO uint32_t MACCR;
711 __IO uint32_t MACECR;
712 __IO uint32_t MACPFR;
713 __IO uint32_t MACWTR;
714 __IO uint32_t MACHT0R;
715 __IO uint32_t MACHT1R;
716 uint32_t RESERVED1[14];
717 __IO uint32_t MACVTR;
718 uint32_t RESERVED2;
719 __IO uint32_t MACVHTR;
720 uint32_t RESERVED3;
721 __IO uint32_t MACVIR;
722 __IO uint32_t MACIVIR;
723 uint32_t RESERVED4[2];
724 __IO uint32_t MACTFCR;
725 uint32_t RESERVED5[7];
726 __IO uint32_t MACRFCR;
727 uint32_t RESERVED6[7];
728 __IO uint32_t MACISR;
729 __IO uint32_t MACIER;
730 __IO uint32_t MACRXTXSR;
731 uint32_t RESERVED7;
732 __IO uint32_t MACPCSR;
733 __IO uint32_t MACRWKPFR;
734 uint32_t RESERVED8[2];
735 __IO uint32_t MACLCSR;
736 __IO uint32_t MACLTCR;
737 __IO uint32_t MACLETR;
738 __IO uint32_t MAC1USTCR;
739 uint32_t RESERVED9[12];
740 __IO uint32_t MACVR;
741 __IO uint32_t MACDR;
742 uint32_t RESERVED10;
743 __IO uint32_t MACHWF0R;
744 __IO uint32_t MACHWF1R;
745 __IO uint32_t MACHWF2R;
746 uint32_t RESERVED11[54];
747 __IO uint32_t MACMDIOAR;
748 __IO uint32_t MACMDIODR;
749 uint32_t RESERVED12[2];
750 __IO uint32_t MACARPAR;
751 uint32_t RESERVED13[59];
752 __IO uint32_t MACA0HR;
753 __IO uint32_t MACA0LR;
754 __IO uint32_t MACA1HR;
755 __IO uint32_t MACA1LR;
756 __IO uint32_t MACA2HR;
757 __IO uint32_t MACA2LR;
758 __IO uint32_t MACA3HR;
759 __IO uint32_t MACA3LR;
760 uint32_t RESERVED14[248];
761 __IO uint32_t MMCCR;
762 __IO uint32_t MMCRIR;
763 __IO uint32_t MMCTIR;
764 __IO uint32_t MMCRIMR;
765 __IO uint32_t MMCTIMR;
766 uint32_t RESERVED15[14];
767 __IO uint32_t MMCTSCGPR;
768 __IO uint32_t MMCTMCGPR;
769 uint32_t RESERVED16[5];
770 __IO uint32_t MMCTPCGR;
771 uint32_t RESERVED17[10];
772 __IO uint32_t MMCRCRCEPR;
773 __IO uint32_t MMCRAEPR;
774 uint32_t RESERVED18[10];
775 __IO uint32_t MMCRUPGR;
776 uint32_t RESERVED19[9];
777 __IO uint32_t MMCTLPIMSTR;
778 __IO uint32_t MMCTLPITCR;
779 __IO uint32_t MMCRLPIMSTR;
780 __IO uint32_t MMCRLPITCR;
781 uint32_t RESERVED20[65];
782 __IO uint32_t MACL3L4C0R;
783 __IO uint32_t MACL4A0R;
784 uint32_t RESERVED21[2];
785 __IO uint32_t MACL3A0R0R;
786 __IO uint32_t MACL3A1R0R;
787 __IO uint32_t MACL3A2R0R;
788 __IO uint32_t MACL3A3R0R;
789 uint32_t RESERVED22[4];
790 __IO uint32_t MACL3L4C1R;
791 __IO uint32_t MACL4A1R;
792 uint32_t RESERVED23[2];
793 __IO uint32_t MACL3A0R1R;
794 __IO uint32_t MACL3A1R1R;
795 __IO uint32_t MACL3A2R1R;
796 __IO uint32_t MACL3A3R1R;
797 uint32_t RESERVED24[108];
798 __IO uint32_t MACTSCR;
799 __IO uint32_t MACSSIR;
800 __IO uint32_t MACSTSR;
801 __IO uint32_t MACSTNR;
802 __IO uint32_t MACSTSUR;
803 __IO uint32_t MACSTNUR;
804 __IO uint32_t MACTSAR;
805 uint32_t RESERVED25;
806 __IO uint32_t MACTSSR;
807 uint32_t RESERVED26[3];
808 __IO uint32_t MACTTSSNR;
809 __IO uint32_t MACTTSSSR;
810 uint32_t RESERVED27[2];
811 __IO uint32_t MACACR;
812 uint32_t RESERVED28;
813 __IO uint32_t MACATSNR;
814 __IO uint32_t MACATSSR;
815 __IO uint32_t MACTSIACR;
816 __IO uint32_t MACTSEACR;
817 __IO uint32_t MACTSICNR;
818 __IO uint32_t MACTSECNR;
819 uint32_t RESERVED29[4];
820 __IO uint32_t MACPPSCR;
821 uint32_t RESERVED30[3];
822 __IO uint32_t MACPPSTTSR;
823 __IO uint32_t MACPPSTTNR;
824 __IO uint32_t MACPPSIR;
825 __IO uint32_t MACPPSWR;
826 uint32_t RESERVED31[12];
827 __IO uint32_t MACPOCR;
828 __IO uint32_t MACSPI0R;
829 __IO uint32_t MACSPI1R;
830 __IO uint32_t MACSPI2R;
831 __IO uint32_t MACLMIR;
832 uint32_t RESERVED32[11];
833 __IO uint32_t MTLOMR;
834 uint32_t RESERVED33[7];
835 __IO uint32_t MTLISR;
836 uint32_t RESERVED34[55];
837 __IO uint32_t MTLTQOMR;
838 __IO uint32_t MTLTQUR;
839 __IO uint32_t MTLTQDR;
840 uint32_t RESERVED35[8];
841 __IO uint32_t MTLQICSR;
842 __IO uint32_t MTLRQOMR;
843 __IO uint32_t MTLRQMPOCR;
844 __IO uint32_t MTLRQDR;
845 uint32_t RESERVED36[177];
846 __IO uint32_t DMAMR;
847 __IO uint32_t DMASBMR;
848 __IO uint32_t DMAISR;
849 __IO uint32_t DMADSR;
850 uint32_t RESERVED37[60];
851 __IO uint32_t DMACCR;
852 __IO uint32_t DMACTCR;
853 __IO uint32_t DMACRCR;
854 uint32_t RESERVED38[2];
855 __IO uint32_t DMACTDLAR;
856 uint32_t RESERVED39;
857 __IO uint32_t DMACRDLAR;
858 __IO uint32_t DMACTDTPR;
859 uint32_t RESERVED40;
860 __IO uint32_t DMACRDTPR;
861 __IO uint32_t DMACTDRLR;
862 __IO uint32_t DMACRDRLR;
863 __IO uint32_t DMACIER;
864 __IO uint32_t DMACRIWTR;
865__IO uint32_t DMACSFCSR;
866 uint32_t RESERVED41;
867 __IO uint32_t DMACCATDR;
868 uint32_t RESERVED42;
869 __IO uint32_t DMACCARDR;
870 uint32_t RESERVED43;
871 __IO uint32_t DMACCATBR;
872 uint32_t RESERVED44;
873 __IO uint32_t DMACCARBR;
874 __IO uint32_t DMACSR;
875uint32_t RESERVED45[2];
876__IO uint32_t DMACMFCR;
877}ETH_TypeDef;
882typedef struct
883{
884__IO uint32_t RTSR1;
885__IO uint32_t FTSR1;
886__IO uint32_t SWIER1;
887__IO uint32_t D3PMR1;
888__IO uint32_t D3PCR1L;
889__IO uint32_t D3PCR1H;
890uint32_t RESERVED1[2];
891__IO uint32_t RTSR2;
892__IO uint32_t FTSR2;
893__IO uint32_t SWIER2;
894__IO uint32_t D3PMR2;
895__IO uint32_t D3PCR2L;
896__IO uint32_t D3PCR2H;
897uint32_t RESERVED2[2];
898__IO uint32_t RTSR3;
899__IO uint32_t FTSR3;
900__IO uint32_t SWIER3;
901__IO uint32_t D3PMR3;
902__IO uint32_t D3PCR3L;
903__IO uint32_t D3PCR3H;
904uint32_t RESERVED3[10];
905__IO uint32_t IMR1;
906__IO uint32_t EMR1;
907__IO uint32_t PR1;
908uint32_t RESERVED4;
909__IO uint32_t IMR2;
910__IO uint32_t EMR2;
911__IO uint32_t PR2;
912uint32_t RESERVED5;
913__IO uint32_t IMR3;
914__IO uint32_t EMR3;
915__IO uint32_t PR3;
916uint32_t RESERVED6[5];
917__IO uint32_t C2IMR1;
918__IO uint32_t C2EMR1;
919__IO uint32_t C2PR1;
920uint32_t RESERVED7;
921__IO uint32_t C2IMR2;
922__IO uint32_t C2EMR2;
923__IO uint32_t C2PR2;
924uint32_t RESERVED8;
925__IO uint32_t C2IMR3;
926__IO uint32_t C2EMR3;
927__IO uint32_t C2PR3;
929}EXTI_TypeDef;
930
940typedef struct
941{
942__IO uint32_t IMR1;
943__IO uint32_t EMR1;
944__IO uint32_t PR1;
945uint32_t RESERVED1;
946__IO uint32_t IMR2;
947__IO uint32_t EMR2;
948__IO uint32_t PR2;
949uint32_t RESERVED2;
950__IO uint32_t IMR3;
951__IO uint32_t EMR3;
952__IO uint32_t PR3;
953}EXTI_Core_TypeDef;
954
955
960typedef struct
961{
962 __IO uint32_t ACR;
963 __IO uint32_t KEYR1;
964 __IO uint32_t OPTKEYR;
965 __IO uint32_t CR1;
966 __IO uint32_t SR1;
967 __IO uint32_t CCR1;
968 __IO uint32_t OPTCR;
969 __IO uint32_t OPTSR_CUR;
970 __IO uint32_t OPTSR_PRG;
971 __IO uint32_t OPTCCR;
972 __IO uint32_t PRAR_CUR1;
973 __IO uint32_t PRAR_PRG1;
974 __IO uint32_t SCAR_CUR1;
975 __IO uint32_t SCAR_PRG1;
976 __IO uint32_t WPSN_CUR1;
977 __IO uint32_t WPSN_PRG1;
978 __IO uint32_t BOOT7_CUR;
979 __IO uint32_t BOOT7_PRG;
980 __IO uint32_t BOOT4_CUR;
981 __IO uint32_t BOOT4_PRG;
982 __IO uint32_t CRCCR1;
983 __IO uint32_t CRCSADD1;
984 __IO uint32_t CRCEADD1;
985 __IO uint32_t CRCDATA;
986 __IO uint32_t ECC_FA1;
987 uint32_t RESERVED1[40];
988 __IO uint32_t KEYR2;
989 uint32_t RESERVED2;
990 __IO uint32_t CR2;
991 __IO uint32_t SR2;
992 __IO uint32_t CCR2;
993 uint32_t RESERVED3[4];
994 __IO uint32_t PRAR_CUR2;
995 __IO uint32_t PRAR_PRG2;
996 __IO uint32_t SCAR_CUR2;
997 __IO uint32_t SCAR_PRG2;
998 __IO uint32_t WPSN_CUR2;
999 __IO uint32_t WPSN_PRG2;
1000 uint32_t RESERVED4[4];
1001 __IO uint32_t CRCCR2;
1002 __IO uint32_t CRCSADD2;
1003 __IO uint32_t CRCEADD2;
1004 __IO uint32_t CRCDATA2;
1005 __IO uint32_t ECC_FA2;
1006} FLASH_TypeDef;
1007
1012typedef struct
1013{
1014 __IO uint32_t BTCR[8];
1015} FMC_Bank1_TypeDef;
1016
1021typedef struct
1022{
1023 __IO uint32_t BWTR[7];
1024} FMC_Bank1E_TypeDef;
1025
1030typedef struct
1031{
1032 __IO uint32_t PCR2;
1033 __IO uint32_t SR2;
1034 __IO uint32_t PMEM2;
1035 __IO uint32_t PATT2;
1036 uint32_t RESERVED0;
1037 __IO uint32_t ECCR2;
1038} FMC_Bank2_TypeDef;
1039
1044typedef struct
1045{
1046 __IO uint32_t PCR;
1047 __IO uint32_t SR;
1048 __IO uint32_t PMEM;
1049 __IO uint32_t PATT;
1050 uint32_t RESERVED;
1051 __IO uint32_t ECCR;
1052} FMC_Bank3_TypeDef;
1053
1059typedef struct
1060{
1061 __IO uint32_t SDCR[2];
1062 __IO uint32_t SDTR[2];
1063 __IO uint32_t SDCMR;
1064 __IO uint32_t SDRTR;
1065 __IO uint32_t SDSR;
1066} FMC_Bank5_6_TypeDef;
1067
1072typedef struct
1073{
1074 __IO uint32_t MODER;
1075 __IO uint32_t OTYPER;
1076 __IO uint32_t OSPEEDR;
1077 __IO uint32_t PUPDR;
1078 __IO uint32_t IDR;
1079 __IO uint32_t ODR;
1080 __IO uint32_t BSRR;
1081 __IO uint32_t LCKR;
1082 __IO uint32_t AFR[2];
1083} GPIO_TypeDef;
1084
1089typedef struct
1090{
1091 __IO uint32_t CSR;
1092 __IO uint32_t OTR;
1093 __IO uint32_t HSOTR;
1094} OPAMP_TypeDef;
1095
1100typedef struct
1101{
1102 uint32_t RESERVED1;
1103 __IO uint32_t PMCR;
1104 __IO uint32_t EXTICR[4];
1105 __IO uint32_t CFGR;
1106 uint32_t RESERVED2;
1107 __IO uint32_t CCCSR;
1108 __IO uint32_t CCVR;
1109 __IO uint32_t CCCR;
1110 __IO uint32_t PWRCR;
1111 uint32_t RESERVED3[61];
1112 __IO uint32_t PKGR;
1113 uint32_t RESERVED4[118];
1114 __IO uint32_t UR0;
1115 __IO uint32_t UR1;
1116 __IO uint32_t UR2;
1117 __IO uint32_t UR3;
1118 __IO uint32_t UR4;
1119 __IO uint32_t UR5;
1120 __IO uint32_t UR6;
1121 __IO uint32_t UR7;
1122 __IO uint32_t UR8;
1123 __IO uint32_t UR9;
1124 __IO uint32_t UR10;
1125 __IO uint32_t UR11;
1126 __IO uint32_t UR12;
1127 __IO uint32_t UR13;
1128 __IO uint32_t UR14;
1129 __IO uint32_t UR15;
1130 __IO uint32_t UR16;
1131 __IO uint32_t UR17;
1133} SYSCFG_TypeDef;
1134
1139typedef struct
1140{
1141 __IO uint32_t CR1;
1142 __IO uint32_t CR2;
1143 __IO uint32_t OAR1;
1144 __IO uint32_t OAR2;
1145 __IO uint32_t TIMINGR;
1146 __IO uint32_t TIMEOUTR;
1147 __IO uint32_t ISR;
1148 __IO uint32_t ICR;
1149 __IO uint32_t PECR;
1150 __IO uint32_t RXDR;
1151 __IO uint32_t TXDR;
1152} I2C_TypeDef;
1153
1158typedef struct
1159{
1160 __IO uint32_t KR;
1161 __IO uint32_t PR;
1162 __IO uint32_t RLR;
1163 __IO uint32_t SR;
1164 __IO uint32_t WINR;
1165} IWDG_TypeDef;
1166
1167
1171typedef struct
1172{
1173 __IO uint32_t CONFR0;
1174 __IO uint32_t CONFR1;
1175 __IO uint32_t CONFR2;
1176 __IO uint32_t CONFR3;
1177 __IO uint32_t CONFR4;
1178 __IO uint32_t CONFR5;
1179 __IO uint32_t CONFR6;
1180 __IO uint32_t CONFR7;
1181 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1182 __IO uint32_t CR;
1183 __IO uint32_t SR;
1184 __IO uint32_t CFR;
1185 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1186 __IO uint32_t DIR;
1187 __IO uint32_t DOR;
1188 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1189 __IO uint32_t QMEM0[16];
1190 __IO uint32_t QMEM1[16];
1191 __IO uint32_t QMEM2[16];
1192 __IO uint32_t QMEM3[16];
1193 __IO uint32_t HUFFMIN[16];
1194 __IO uint32_t HUFFBASE[32];
1195 __IO uint32_t HUFFSYMB[84];
1196 __IO uint32_t DHTMEM[103];
1197 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1198 __IO uint32_t HUFFENC_AC0[88];
1199 __IO uint32_t HUFFENC_AC1[88];
1200 __IO uint32_t HUFFENC_DC0[8];
1201 __IO uint32_t HUFFENC_DC1[8];
1203} JPEG_TypeDef;
1204
1209typedef struct
1210{
1211 uint32_t RESERVED0[2];
1212 __IO uint32_t SSCR;
1213 __IO uint32_t BPCR;
1214 __IO uint32_t AWCR;
1215 __IO uint32_t TWCR;
1216 __IO uint32_t GCR;
1217 uint32_t RESERVED1[2];
1218 __IO uint32_t SRCR;
1219 uint32_t RESERVED2[1];
1220 __IO uint32_t BCCR;
1221 uint32_t RESERVED3[1];
1222 __IO uint32_t IER;
1223 __IO uint32_t ISR;
1224 __IO uint32_t ICR;
1225 __IO uint32_t LIPCR;
1226 __IO uint32_t CPSR;
1227 __IO uint32_t CDSR;
1228} LTDC_TypeDef;
1229
1234typedef struct
1235{
1236 __IO uint32_t CR;
1237 __IO uint32_t WHPCR;
1238 __IO uint32_t WVPCR;
1239 __IO uint32_t CKCR;
1240 __IO uint32_t PFCR;
1241 __IO uint32_t CACR;
1242 __IO uint32_t DCCR;
1243 __IO uint32_t BFCR;
1244 uint32_t RESERVED0[2];
1245 __IO uint32_t CFBAR;
1246 __IO uint32_t CFBLR;
1247 __IO uint32_t CFBLNR;
1248 uint32_t RESERVED1[3];
1249 __IO uint32_t CLUTWR;
1251} LTDC_Layer_TypeDef;
1252
1257typedef struct
1258{
1259 __IO uint32_t CR1;
1260 __IO uint32_t CSR1;
1261 __IO uint32_t CR2;
1262 __IO uint32_t CR3;
1263 __IO uint32_t CPUCR;
1264 __IO uint32_t CPU2CR;
1265 __IO uint32_t D3CR;
1266 uint32_t RESERVED1;
1267 __IO uint32_t WKUPCR;
1268 __IO uint32_t WKUPFR;
1269 __IO uint32_t WKUPEPR;
1270} PWR_TypeDef;
1271
1276typedef struct
1277{
1278 __IO uint32_t CR;
1279 __IO uint32_t HSICFGR;
1280 __IO uint32_t CRRCR;
1281 __IO uint32_t CSICFGR;
1282 __IO uint32_t CFGR;
1283 uint32_t RESERVED1;
1284 __IO uint32_t D1CFGR;
1285 __IO uint32_t D2CFGR;
1286 __IO uint32_t D3CFGR;
1287 uint32_t RESERVED2;
1288 __IO uint32_t PLLCKSELR;
1289 __IO uint32_t PLLCFGR;
1290 __IO uint32_t PLL1DIVR;
1291 __IO uint32_t PLL1FRACR;
1292 __IO uint32_t PLL2DIVR;
1293 __IO uint32_t PLL2FRACR;
1294 __IO uint32_t PLL3DIVR;
1295 __IO uint32_t PLL3FRACR;
1296 uint32_t RESERVED3;
1297 __IO uint32_t D1CCIPR;
1298 __IO uint32_t D2CCIP1R;
1299 __IO uint32_t D2CCIP2R;
1300 __IO uint32_t D3CCIPR;
1301 uint32_t RESERVED4;
1302 __IO uint32_t CIER;
1303 __IO uint32_t CIFR;
1304 __IO uint32_t CICR;
1305 uint32_t RESERVED5;
1306 __IO uint32_t BDCR;
1307 __IO uint32_t CSR;
1308 uint32_t RESERVED6;
1309 __IO uint32_t AHB3RSTR;
1310 __IO uint32_t AHB1RSTR;
1311 __IO uint32_t AHB2RSTR;
1312 __IO uint32_t AHB4RSTR;
1313 __IO uint32_t APB3RSTR;
1314 __IO uint32_t APB1LRSTR;
1315 __IO uint32_t APB1HRSTR;
1316 __IO uint32_t APB2RSTR;
1317 __IO uint32_t APB4RSTR;
1318 __IO uint32_t GCR;
1319 uint32_t RESERVED8;
1320 __IO uint32_t D3AMR;
1321 uint32_t RESERVED11[9];
1322 __IO uint32_t RSR;
1323 __IO uint32_t AHB3ENR;
1324 __IO uint32_t AHB1ENR;
1325 __IO uint32_t AHB2ENR;
1326 __IO uint32_t AHB4ENR;
1327 __IO uint32_t APB3ENR;
1328 __IO uint32_t APB1LENR;
1329 __IO uint32_t APB1HENR;
1330 __IO uint32_t APB2ENR;
1331 __IO uint32_t APB4ENR;
1332 uint32_t RESERVED12;
1333 __IO uint32_t AHB3LPENR;
1334 __IO uint32_t AHB1LPENR;
1335 __IO uint32_t AHB2LPENR;
1336 __IO uint32_t AHB4LPENR;
1337 __IO uint32_t APB3LPENR;
1338 __IO uint32_t APB1LLPENR;
1339 __IO uint32_t APB1HLPENR;
1340 __IO uint32_t APB2LPENR;
1341 __IO uint32_t APB4LPENR;
1342 uint32_t RESERVED13[4];
1344} RCC_TypeDef;
1345
1346typedef struct
1347{
1348 __IO uint32_t RSR;
1349 __IO uint32_t AHB3ENR;
1350 __IO uint32_t AHB1ENR;
1351 __IO uint32_t AHB2ENR;
1352 __IO uint32_t AHB4ENR;
1353 __IO uint32_t APB3ENR;
1354 __IO uint32_t APB1LENR;
1355 __IO uint32_t APB1HENR;
1356 __IO uint32_t APB2ENR;
1357 __IO uint32_t APB4ENR;
1358 uint32_t RESERVED9;
1359 __IO uint32_t AHB3LPENR;
1360 __IO uint32_t AHB1LPENR;
1361 __IO uint32_t AHB2LPENR;
1362 __IO uint32_t AHB4LPENR;
1363 __IO uint32_t APB3LPENR;
1364 __IO uint32_t APB1LLPENR;
1365 __IO uint32_t APB1HLPENR;
1366 __IO uint32_t APB2LPENR;
1367 __IO uint32_t APB4LPENR;
1368 uint32_t RESERVED10[4];
1370} RCC_Core_TypeDef;
1371
1375typedef struct
1376{
1377 __IO uint32_t TR;
1378 __IO uint32_t DR;
1379 __IO uint32_t CR;
1380 __IO uint32_t ISR;
1381 __IO uint32_t PRER;
1382 __IO uint32_t WUTR;
1383 uint32_t RESERVED;
1384 __IO uint32_t ALRMAR;
1385 __IO uint32_t ALRMBR;
1386 __IO uint32_t WPR;
1387 __IO uint32_t SSR;
1388 __IO uint32_t SHIFTR;
1389 __IO uint32_t TSTR;
1390 __IO uint32_t TSDR;
1391 __IO uint32_t TSSSR;
1392 __IO uint32_t CALR;
1393 __IO uint32_t TAMPCR;
1394 __IO uint32_t ALRMASSR;
1395 __IO uint32_t ALRMBSSR;
1396 __IO uint32_t OR;
1397 __IO uint32_t BKP0R;
1398 __IO uint32_t BKP1R;
1399 __IO uint32_t BKP2R;
1400 __IO uint32_t BKP3R;
1401 __IO uint32_t BKP4R;
1402 __IO uint32_t BKP5R;
1403 __IO uint32_t BKP6R;
1404 __IO uint32_t BKP7R;
1405 __IO uint32_t BKP8R;
1406 __IO uint32_t BKP9R;
1407 __IO uint32_t BKP10R;
1408 __IO uint32_t BKP11R;
1409 __IO uint32_t BKP12R;
1410 __IO uint32_t BKP13R;
1411 __IO uint32_t BKP14R;
1412 __IO uint32_t BKP15R;
1413 __IO uint32_t BKP16R;
1414 __IO uint32_t BKP17R;
1415 __IO uint32_t BKP18R;
1416 __IO uint32_t BKP19R;
1417 __IO uint32_t BKP20R;
1418 __IO uint32_t BKP21R;
1419 __IO uint32_t BKP22R;
1420 __IO uint32_t BKP23R;
1421 __IO uint32_t BKP24R;
1422 __IO uint32_t BKP25R;
1423 __IO uint32_t BKP26R;
1424 __IO uint32_t BKP27R;
1425 __IO uint32_t BKP28R;
1426 __IO uint32_t BKP29R;
1427 __IO uint32_t BKP30R;
1428 __IO uint32_t BKP31R;
1429} RTC_TypeDef;
1430
1435typedef struct
1436{
1437 __IO uint32_t GCR;
1438 uint32_t RESERVED0[16];
1439 __IO uint32_t PDMCR;
1440 __IO uint32_t PDMDLY;
1441} SAI_TypeDef;
1442
1443typedef struct
1444{
1445 __IO uint32_t CR1;
1446 __IO uint32_t CR2;
1447 __IO uint32_t FRCR;
1448 __IO uint32_t SLOTR;
1449 __IO uint32_t IMR;
1450 __IO uint32_t SR;
1451 __IO uint32_t CLRFR;
1452 __IO uint32_t DR;
1453} SAI_Block_TypeDef;
1454
1459typedef struct
1460{
1461 __IO uint32_t CR;
1462 __IO uint32_t IMR;
1463 __IO uint32_t SR;
1464 __IO uint32_t IFCR;
1465 __IO uint32_t DR;
1466 __IO uint32_t CSR;
1467 __IO uint32_t DIR;
1468 uint32_t RESERVED2;
1469} SPDIFRX_TypeDef;
1470
1471
1476typedef struct
1477{
1478 __IO uint32_t POWER;
1479 __IO uint32_t CLKCR;
1480 __IO uint32_t ARG;
1481 __IO uint32_t CMD;
1482 __I uint32_t RESPCMD;
1483 __I uint32_t RESP1;
1484 __I uint32_t RESP2;
1485 __I uint32_t RESP3;
1486 __I uint32_t RESP4;
1487 __IO uint32_t DTIMER;
1488 __IO uint32_t DLEN;
1489 __IO uint32_t DCTRL;
1490 __I uint32_t DCOUNT;
1491 __I uint32_t STA;
1492 __IO uint32_t ICR;
1493 __IO uint32_t MASK;
1494 __IO uint32_t ACKTIME;
1495 uint32_t RESERVED0[3];
1496 __IO uint32_t IDMACTRL;
1497 __IO uint32_t IDMABSIZE;
1498 __IO uint32_t IDMABASE0;
1499 __IO uint32_t IDMABASE1;
1500 uint32_t RESERVED1[8];
1501 __IO uint32_t FIFO;
1502 uint32_t RESERVED2[222];
1503 __IO uint32_t IPVR;
1504} SDMMC_TypeDef;
1505
1506
1511typedef struct
1512{
1513 __IO uint32_t CR;
1514 __IO uint32_t CFGR;
1515} DLYB_TypeDef;
1516
1521typedef struct
1522{
1523 __IO uint32_t R[32];
1524 __IO uint32_t RLR[32];
1525 __IO uint32_t C1IER;
1526 __IO uint32_t C1ICR;
1527 __IO uint32_t C1ISR;
1528 __IO uint32_t C1MISR;
1529 __IO uint32_t C2IER;
1530 __IO uint32_t C2ICR;
1531 __IO uint32_t C2ISR;
1532 __IO uint32_t C2MISR;
1533 uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1534 __IO uint32_t CR;
1535 __IO uint32_t KEYR;
1537} HSEM_TypeDef;
1538
1539typedef struct
1540{
1541 __IO uint32_t IER;
1542 __IO uint32_t ICR;
1543 __IO uint32_t ISR;
1544 __IO uint32_t MISR;
1545} HSEM_Common_TypeDef;
1546
1551typedef struct
1552{
1553 __IO uint32_t CR1;
1554 __IO uint32_t CR2;
1555 __IO uint32_t CFG1;
1556 __IO uint32_t CFG2;
1557 __IO uint32_t IER;
1558 __IO uint32_t SR;
1559 __IO uint32_t IFCR;
1560 uint32_t RESERVED0;
1561 __IO uint32_t TXDR;
1562 uint32_t RESERVED1[3];
1563 __IO uint32_t RXDR;
1564 uint32_t RESERVED2[3];
1565 __IO uint32_t CRCPOLY;
1566 __IO uint32_t TXCRC;
1567 __IO uint32_t RXCRC;
1568 __IO uint32_t UDRDR;
1569 __IO uint32_t I2SCFGR;
1571} SPI_TypeDef;
1576typedef struct
1577{
1578 __IO uint32_t CR;
1579 __IO uint32_t DCR;
1580 __IO uint32_t SR;
1581 __IO uint32_t FCR;
1582 __IO uint32_t DLR;
1583 __IO uint32_t CCR;
1584 __IO uint32_t AR;
1585 __IO uint32_t ABR;
1586 __IO uint32_t DR;
1587 __IO uint32_t PSMKR;
1588 __IO uint32_t PSMAR;
1589 __IO uint32_t PIR;
1590 __IO uint32_t LPTR;
1591} QUADSPI_TypeDef;
1592
1597typedef struct
1598{
1599 __IO uint32_t CR1;
1600 __IO uint32_t CR2;
1601 __IO uint32_t SMCR;
1602 __IO uint32_t DIER;
1603 __IO uint32_t SR;
1604 __IO uint32_t EGR;
1605 __IO uint32_t CCMR1;
1606 __IO uint32_t CCMR2;
1607 __IO uint32_t CCER;
1608 __IO uint32_t CNT;
1609 __IO uint32_t PSC;
1610 __IO uint32_t ARR;
1611 __IO uint32_t RCR;
1612 __IO uint32_t CCR1;
1613 __IO uint32_t CCR2;
1614 __IO uint32_t CCR3;
1615 __IO uint32_t CCR4;
1616 __IO uint32_t BDTR;
1617 __IO uint32_t DCR;
1618 __IO uint32_t DMAR;
1619 uint32_t RESERVED1;
1620 __IO uint32_t CCMR3;
1621 __IO uint32_t CCR5;
1622 __IO uint32_t CCR6;
1623 __IO uint32_t AF1;
1624 __IO uint32_t AF2;
1625 __IO uint32_t TISEL;
1626} TIM_TypeDef;
1627
1631typedef struct
1632{
1633 __IO uint32_t ISR;
1634 __IO uint32_t ICR;
1635 __IO uint32_t IER;
1636 __IO uint32_t CFGR;
1637 __IO uint32_t CR;
1638 __IO uint32_t CMP;
1639 __IO uint32_t ARR;
1640 __IO uint32_t CNT;
1641 uint32_t RESERVED1;
1642 __IO uint32_t CFGR2;
1643} LPTIM_TypeDef;
1644
1648typedef struct
1649{
1650 __IO uint32_t SR;
1651 __IO uint32_t ICFR;
1652 __IO uint32_t OR;
1653} COMPOPT_TypeDef;
1654
1655typedef struct
1656{
1657 __IO uint32_t CFGR;
1658} COMP_TypeDef;
1659
1660typedef struct
1661{
1662 __IO uint32_t CFGR;
1663} COMP_Common_TypeDef;
1668typedef struct
1669{
1670 __IO uint32_t CR1;
1671 __IO uint32_t CR2;
1672 __IO uint32_t CR3;
1673 __IO uint32_t BRR;
1674 __IO uint32_t GTPR;
1675 __IO uint32_t RTOR;
1676 __IO uint32_t RQR;
1677 __IO uint32_t ISR;
1678 __IO uint32_t ICR;
1679 __IO uint32_t RDR;
1680 __IO uint32_t TDR;
1681 __IO uint32_t PRESC;
1682} USART_TypeDef;
1683
1687typedef struct
1688{
1689 __IO uint32_t CR;
1690 __IO uint32_t BRR;
1691 uint32_t RESERVED1;
1692 __IO uint32_t ISR;
1693 __IO uint32_t ICR;
1694 __IO uint32_t IER;
1695 __IO uint32_t RFL;
1696 __IO uint32_t TDR;
1697 __IO uint32_t RDR;
1698 __IO uint32_t OR;
1699} SWPMI_TypeDef;
1700
1705typedef struct
1706{
1707 __IO uint32_t CR;
1708 __IO uint32_t CFR;
1709 __IO uint32_t SR;
1710} WWDG_TypeDef;
1711
1712
1716typedef struct
1717{
1718 __IO uint32_t CR;
1719 __IO uint32_t SR;
1720 __IO uint32_t FAR;
1721 __IO uint32_t FDRL;
1722 __IO uint32_t FDRH;
1723 __IO uint32_t FECR;
1724} RAMECC_MonitorTypeDef;
1725
1726typedef struct
1727{
1728 __IO uint32_t IER;
1729} RAMECC_TypeDef;
1739/* HRTIM master registers definition */
1740typedef struct
1741{
1742 __IO uint32_t MCR;
1743 __IO uint32_t MISR;
1744 __IO uint32_t MICR;
1745 __IO uint32_t MDIER;
1746 __IO uint32_t MCNTR;
1747 __IO uint32_t MPER;
1748 __IO uint32_t MREP;
1749 __IO uint32_t MCMP1R;
1750 uint32_t RESERVED0;
1751 __IO uint32_t MCMP2R;
1752 __IO uint32_t MCMP3R;
1753 __IO uint32_t MCMP4R;
1754 uint32_t RESERVED1[20];
1755}HRTIM_Master_TypeDef;
1756
1757/* HRTIM Timer A to E registers definition */
1758typedef struct
1759{
1760 __IO uint32_t TIMxCR;
1761 __IO uint32_t TIMxISR;
1762 __IO uint32_t TIMxICR;
1763 __IO uint32_t TIMxDIER;
1764 __IO uint32_t CNTxR;
1765 __IO uint32_t PERxR;
1766 __IO uint32_t REPxR;
1767 __IO uint32_t CMP1xR;
1768 __IO uint32_t CMP1CxR;
1769 __IO uint32_t CMP2xR;
1770 __IO uint32_t CMP3xR;
1771 __IO uint32_t CMP4xR;
1772 __IO uint32_t CPT1xR;
1773 __IO uint32_t CPT2xR;
1774 __IO uint32_t DTxR;
1775 __IO uint32_t SETx1R;
1776 __IO uint32_t RSTx1R;
1777 __IO uint32_t SETx2R;
1778 __IO uint32_t RSTx2R;
1779 __IO uint32_t EEFxR1;
1780 __IO uint32_t EEFxR2;
1781 __IO uint32_t RSTxR;
1782 __IO uint32_t CHPxR;
1783 __IO uint32_t CPT1xCR;
1784 __IO uint32_t CPT2xCR;
1785 __IO uint32_t OUTxR;
1786 __IO uint32_t FLTxR;
1787 uint32_t RESERVED0[5];
1788}HRTIM_Timerx_TypeDef;
1789
1790/* HRTIM common register definition */
1791typedef struct
1792{
1793 __IO uint32_t CR1;
1794 __IO uint32_t CR2;
1795 __IO uint32_t ISR;
1796 __IO uint32_t ICR;
1797 __IO uint32_t IER;
1798 __IO uint32_t OENR;
1799 __IO uint32_t ODISR;
1800 __IO uint32_t ODSR;
1801 __IO uint32_t BMCR;
1802 __IO uint32_t BMTRGR;
1803 __IO uint32_t BMCMPR;
1804 __IO uint32_t BMPER;
1805 __IO uint32_t EECR1;
1806 __IO uint32_t EECR2;
1807 __IO uint32_t EECR3;
1808 __IO uint32_t ADC1R;
1809 __IO uint32_t ADC2R;
1810 __IO uint32_t ADC3R;
1811 __IO uint32_t ADC4R;
1812 __IO uint32_t RESERVED0;
1813 __IO uint32_t FLTINR1;
1814 __IO uint32_t FLTINR2;
1815 __IO uint32_t BDMUPR;
1816 __IO uint32_t BDTAUPR;
1817 __IO uint32_t BDTBUPR;
1818 __IO uint32_t BDTCUPR;
1819 __IO uint32_t BDTDUPR;
1820 __IO uint32_t BDTEUPR;
1821 __IO uint32_t BDMADR;
1822}HRTIM_Common_TypeDef;
1823
1824/* HRTIM register definition */
1825typedef struct {
1826 HRTIM_Master_TypeDef sMasterRegs;
1827 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1828 uint32_t RESERVED0[32];
1829 HRTIM_Common_TypeDef sCommonRegs;
1830}HRTIM_TypeDef;
1835typedef struct
1836{
1837 __IO uint32_t CR;
1838 __IO uint32_t SR;
1839 __IO uint32_t DR;
1840} RNG_TypeDef;
1841
1846typedef struct
1847{
1848 __IO uint32_t CR;
1849 __IO uint32_t WRFR;
1850 __IO uint32_t CWRFR;
1851 __IO uint32_t RDFR;
1852 __IO uint32_t CRDFR;
1853 __IO uint32_t SR;
1854 __IO uint32_t CLRFR;
1855 uint32_t RESERVED[57];
1856 __IO uint32_t DINR0;
1857 __IO uint32_t DINR1;
1858 __IO uint32_t DINR2;
1859 __IO uint32_t DINR3;
1860 __IO uint32_t DINR4;
1861 __IO uint32_t DINR5;
1862 __IO uint32_t DINR6;
1863 __IO uint32_t DINR7;
1864 __IO uint32_t DINR8;
1865 __IO uint32_t DINR9;
1866 __IO uint32_t DINR10;
1867 __IO uint32_t DINR11;
1868 __IO uint32_t DINR12;
1869 __IO uint32_t DINR13;
1870 __IO uint32_t DINR14;
1871 __IO uint32_t DINR15;
1872 __IO uint32_t DINR16;
1873 __IO uint32_t DINR17;
1874 __IO uint32_t DINR18;
1875 __IO uint32_t DINR19;
1876 __IO uint32_t DINR20;
1877 __IO uint32_t DINR21;
1878 __IO uint32_t DINR22;
1879 __IO uint32_t DINR23;
1880 __IO uint32_t DINR24;
1881 __IO uint32_t DINR25;
1882 __IO uint32_t DINR26;
1883 __IO uint32_t DINR27;
1884 __IO uint32_t DINR28;
1885 __IO uint32_t DINR29;
1886 __IO uint32_t DINR30;
1887 __IO uint32_t DINR31;
1888 __IO uint32_t DOUTR0;
1889 __IO uint32_t DOUTR1;
1890 __IO uint32_t DOUTR2;
1891 __IO uint32_t DOUTR3;
1892 __IO uint32_t DOUTR4;
1893 __IO uint32_t DOUTR5;
1894 __IO uint32_t DOUTR6;
1895 __IO uint32_t DOUTR7;
1896 __IO uint32_t DOUTR8;
1897 __IO uint32_t DOUTR9;
1898 __IO uint32_t DOUTR10;
1899 __IO uint32_t DOUTR11;
1900 __IO uint32_t DOUTR12;
1901 __IO uint32_t DOUTR13;
1902 __IO uint32_t DOUTR14;
1903 __IO uint32_t DOUTR15;
1904 __IO uint32_t DOUTR16;
1905 __IO uint32_t DOUTR17;
1906 __IO uint32_t DOUTR18;
1907 __IO uint32_t DOUTR19;
1908 __IO uint32_t DOUTR20;
1909 __IO uint32_t DOUTR21;
1910 __IO uint32_t DOUTR22;
1911 __IO uint32_t DOUTR23;
1912 __IO uint32_t DOUTR24;
1913 __IO uint32_t DOUTR25;
1914 __IO uint32_t DOUTR26;
1915 __IO uint32_t DOUTR27;
1916 __IO uint32_t DOUTR28;
1917 __IO uint32_t DOUTR29;
1918 __IO uint32_t DOUTR30;
1919 __IO uint32_t DOUTR31;
1920} MDIOS_TypeDef;
1921
1922
1926typedef struct
1927{
1928 __IO uint32_t GOTGCTL;
1929 __IO uint32_t GOTGINT;
1930 __IO uint32_t GAHBCFG;
1931 __IO uint32_t GUSBCFG;
1932 __IO uint32_t GRSTCTL;
1933 __IO uint32_t GINTSTS;
1934 __IO uint32_t GINTMSK;
1935 __IO uint32_t GRXSTSR;
1936 __IO uint32_t GRXSTSP;
1937 __IO uint32_t GRXFSIZ;
1938 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1939 __IO uint32_t HNPTXSTS;
1940 uint32_t Reserved30[2];
1941 __IO uint32_t GCCFG;
1942 __IO uint32_t CID;
1943 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1944 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1945 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1946 __IO uint32_t GHWCFG3;
1947 uint32_t Reserved6;
1948 __IO uint32_t GLPMCFG;
1949 __IO uint32_t GPWRDN;
1950 __IO uint32_t GDFIFOCFG;
1951 __IO uint32_t GADPCTL;
1952 uint32_t Reserved43[39];
1953 __IO uint32_t HPTXFSIZ;
1954 __IO uint32_t DIEPTXF[0x0F];
1955} USB_OTG_GlobalTypeDef;
1956
1957
1961typedef struct
1962{
1963 __IO uint32_t DCFG;
1964 __IO uint32_t DCTL;
1965 __IO uint32_t DSTS;
1966 uint32_t Reserved0C;
1967 __IO uint32_t DIEPMSK;
1968 __IO uint32_t DOEPMSK;
1969 __IO uint32_t DAINT;
1970 __IO uint32_t DAINTMSK;
1971 uint32_t Reserved20;
1972 uint32_t Reserved9;
1973 __IO uint32_t DVBUSDIS;
1974 __IO uint32_t DVBUSPULSE;
1975 __IO uint32_t DTHRCTL;
1976 __IO uint32_t DIEPEMPMSK;
1977 __IO uint32_t DEACHINT;
1978 __IO uint32_t DEACHMSK;
1979 uint32_t Reserved40;
1980 __IO uint32_t DINEP1MSK;
1981 uint32_t Reserved44[15];
1982 __IO uint32_t DOUTEP1MSK;
1983} USB_OTG_DeviceTypeDef;
1984
1985
1989typedef struct
1990{
1991 __IO uint32_t DIEPCTL;
1992 uint32_t Reserved04;
1993 __IO uint32_t DIEPINT;
1994 uint32_t Reserved0C;
1995 __IO uint32_t DIEPTSIZ;
1996 __IO uint32_t DIEPDMA;
1997 __IO uint32_t DTXFSTS;
1998 uint32_t Reserved18;
1999} USB_OTG_INEndpointTypeDef;
2000
2001
2005typedef struct
2006{
2007 __IO uint32_t DOEPCTL;
2008 uint32_t Reserved04;
2009 __IO uint32_t DOEPINT;
2010 uint32_t Reserved0C;
2011 __IO uint32_t DOEPTSIZ;
2012 __IO uint32_t DOEPDMA;
2013 uint32_t Reserved18[2];
2014} USB_OTG_OUTEndpointTypeDef;
2015
2016
2020typedef struct
2021{
2022 __IO uint32_t HCFG;
2023 __IO uint32_t HFIR;
2024 __IO uint32_t HFNUM;
2025 uint32_t Reserved40C;
2026 __IO uint32_t HPTXSTS;
2027 __IO uint32_t HAINT;
2028 __IO uint32_t HAINTMSK;
2029} USB_OTG_HostTypeDef;
2030
2034typedef struct
2035{
2036 __IO uint32_t HCCHAR;
2037 __IO uint32_t HCSPLT;
2038 __IO uint32_t HCINT;
2039 __IO uint32_t HCINTMSK;
2040 __IO uint32_t HCTSIZ;
2041 __IO uint32_t HCDMA;
2042 uint32_t Reserved[2];
2043} USB_OTG_HostChannelTypeDef;
2053typedef struct
2054{
2055 uint32_t RESERVED0[2036];
2056 __IO uint32_t AXI_PERIPH_ID_4;
2057 uint32_t AXI_PERIPH_ID_5;
2058 uint32_t AXI_PERIPH_ID_6;
2059 uint32_t AXI_PERIPH_ID_7;
2060 __IO uint32_t AXI_PERIPH_ID_0;
2061 __IO uint32_t AXI_PERIPH_ID_1;
2062 __IO uint32_t AXI_PERIPH_ID_2;
2063 __IO uint32_t AXI_PERIPH_ID_3;
2064 __IO uint32_t AXI_COMP_ID_0;
2065 __IO uint32_t AXI_COMP_ID_1;
2066 __IO uint32_t AXI_COMP_ID_2;
2067 __IO uint32_t AXI_COMP_ID_3;
2068 uint32_t RESERVED1[2];
2069 __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;
2070 uint32_t RESERVED2[6];
2071 __IO uint32_t AXI_TARG1_FN_MOD2;
2072 uint32_t RESERVED3;
2073 __IO uint32_t AXI_TARG1_FN_MOD_LB;
2074 uint32_t RESERVED4[54];
2075 __IO uint32_t AXI_TARG1_FN_MOD;
2076 uint32_t RESERVED5[959];
2077 __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;
2078 uint32_t RESERVED6[6];
2079 __IO uint32_t AXI_TARG2_FN_MOD2;
2080 uint32_t RESERVED7;
2081 __IO uint32_t AXI_TARG2_FN_MOD_LB;
2082 uint32_t RESERVED8[54];
2083 __IO uint32_t AXI_TARG2_FN_MOD;
2084 uint32_t RESERVED9[959];
2085 __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;
2086 uint32_t RESERVED10[1023];
2087 __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;
2088 uint32_t RESERVED11[1023];
2089 __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;
2090 uint32_t RESERVED12[1023];
2091 __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;
2092 uint32_t RESERVED13[1023];
2093 __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;
2094 uint32_t RESERVED14[6];
2095 __IO uint32_t AXI_TARG7_FN_MOD2;
2096 uint32_t RESERVED15;
2097 __IO uint32_t AXI_TARG7_FN_MOD_LB;
2098 uint32_t RESERVED16[54];
2099 __IO uint32_t AXI_TARG7_FN_MOD;
2100 uint32_t RESERVED17[59334];
2101 __IO uint32_t AXI_INI1_FN_MOD2;
2102 __IO uint32_t AXI_INI1_FN_MOD_AHB;
2103 uint32_t RESERVED18[53];
2104 __IO uint32_t AXI_INI1_READ_QOS;
2105 __IO uint32_t AXI_INI1_WRITE_QOS;
2106 __IO uint32_t AXI_INI1_FN_MOD;
2107 uint32_t RESERVED19[1021];
2108 __IO uint32_t AXI_INI2_READ_QOS;
2109 __IO uint32_t AXI_INI2_WRITE_QOS;
2110 __IO uint32_t AXI_INI2_FN_MOD;
2111 uint32_t RESERVED20[966];
2112 __IO uint32_t AXI_INI3_FN_MOD2;
2113 __IO uint32_t AXI_INI3_FN_MOD_AHB;
2114 uint32_t RESERVED21[53];
2115 __IO uint32_t AXI_INI3_READ_QOS;
2116 __IO uint32_t AXI_INI3_WRITE_QOS;
2117 __IO uint32_t AXI_INI3_FN_MOD;
2118 uint32_t RESERVED22[1021];
2119 __IO uint32_t AXI_INI4_READ_QOS;
2120 __IO uint32_t AXI_INI4_WRITE_QOS;
2121 __IO uint32_t AXI_INI4_FN_MOD;
2122 uint32_t RESERVED23[1021];
2123 __IO uint32_t AXI_INI5_READ_QOS;
2124 __IO uint32_t AXI_INI5_WRITE_QOS;
2125 __IO uint32_t AXI_INI5_FN_MOD;
2126 uint32_t RESERVED24[1021];
2127 __IO uint32_t AXI_INI6_READ_QOS;
2128 __IO uint32_t AXI_INI6_WRITE_QOS;
2129 __IO uint32_t AXI_INI6_FN_MOD;
2130 uint32_t RESERVED25[1021];
2131 __IO uint32_t AXI_INI7_READ_QOS;
2132 __IO uint32_t AXI_INI7_WRITE_QOS;
2133 __IO uint32_t AXI_INI7_FN_MOD;
2135} GPV_TypeDef;
2136
2140#define D1_ITCMRAM_BASE (0x00000000UL)
2141#define D1_ITCMICP_BASE (0x00100000UL)
2142#define D1_DTCMRAM_BASE (0x20000000UL)
2143#define D1_AXIFLASH_BASE (0x08000000UL)
2144#define D1_AXIICP_BASE (0x1FF00000UL)
2145#define D1_AXISRAM_BASE (0x24000000UL)
2147#define D2_AXISRAM_BASE (0x10000000UL)
2148#define D2_AHBSRAM_BASE (0x30000000UL)
2150#define D3_BKPSRAM_BASE (0x38800000UL)
2151#define D3_SRAM_BASE (0x38000000UL)
2153#define PERIPH_BASE (0x40000000UL)
2154#define QSPI_BASE (0x90000000UL)
2156#define FLASH_BANK1_BASE (0x08000000UL)
2157#define FLASH_BANK2_BASE (0x08100000UL)
2158#define FLASH_END (0x081FFFFFUL)
2160/* Legacy define */
2161#define FLASH_BASE FLASH_BANK1_BASE
2162
2164#define UID_BASE (0x1FF1E800UL)
2165#define FLASHSIZE_BASE (0x1FF1E880UL)
2169#define D2_APB1PERIPH_BASE PERIPH_BASE
2170#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2171#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2172#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2173
2174#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2175#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2176
2177#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2178#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2179
2181#define APB1PERIPH_BASE PERIPH_BASE
2182#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2183#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2184#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2185
2186
2189#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2190#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2191#define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2192#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2193#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2194#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2195#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2196#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2197#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2198#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2199
2202#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2203#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2204#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2205#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2206#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2207#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2208#define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
2209#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2210#define ETH_MAC_BASE (ETH_BASE)
2211
2213#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2214#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2215#define USB_OTG_GLOBAL_BASE (0x000UL)
2216#define USB_OTG_DEVICE_BASE (0x800UL)
2217#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2218#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2219#define USB_OTG_EP_REG_SIZE (0x20UL)
2220#define USB_OTG_HOST_BASE (0x400UL)
2221#define USB_OTG_HOST_PORT_BASE (0x440UL)
2222#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2223#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2224#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2225#define USB_OTG_FIFO_BASE (0x1000UL)
2226#define USB_OTG_FIFO_SIZE (0x1000UL)
2227
2230#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2231#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2232#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2233#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2234#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2235
2237#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2238#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2239#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2240#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2241#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2242#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2243#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2244#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2245#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2246#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2247#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2248#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2249#define RCC_C1_BASE (RCC_BASE + 0x130UL)
2250#define RCC_C2_BASE (RCC_BASE + 0x190UL)
2251#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2252#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2253#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2254#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2255#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2256#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2257#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2258#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2259
2261#define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2262#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2263#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2264#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2265
2267#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2268#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2269#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2270#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2271#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2272#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2273#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2274#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2275#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2276#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2277
2278#define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)
2279
2280#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2281#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2282#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2283#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2284#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2285#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2286#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2287#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2288#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2289#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2290#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2291#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2292#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2293#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2294#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2295#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2296#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2297#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2298#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2299#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2300#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2301#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2302#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2303#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2304
2307#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2308#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2309#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2310#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2311#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2312#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2313#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2314#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2315#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2316#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2317#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2318#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2319#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2320#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2321#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2322#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2323#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2324#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2325#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2326#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2327#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2328#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2329#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2330#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2331#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2332#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2333#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2334#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2335#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2336#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2337#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2338#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2339#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2340#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2341#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2342#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2343#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2344#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2345#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2346
2347
2349#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2350#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2351#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2352#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2353#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2354#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2355#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2356#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2357#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2358#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2359#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2360#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2361#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2362#define COMP2_BASE (COMP12_BASE + 0x10UL)
2363#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2364#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2365#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2366
2367#define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)
2368
2369#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2370#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2371#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2372
2373
2374
2375
2376#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2377#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2378#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2379#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2380#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2381#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2382#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2383#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2384
2385#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2386#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2387#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2388#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2389#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2390#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2391#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2392#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2393
2394#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2395#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2396#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2397#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2398#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2399#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2400#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2401#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2402
2403#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2404#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2405
2406#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2407#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2408#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2409#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2410#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2411#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2412#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2413#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2414
2415#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2416#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2417#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2418#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2419#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2420#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2421#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2422#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2423
2424#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2425#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2426#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2427#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2428#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2429#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2430#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2431#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2432#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2433#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2434#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2435#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2436#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2437#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2438#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2439#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2440
2441#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2442#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2443#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2444#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2445#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2446#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2447#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2448#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2449
2450#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2451#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2452
2454#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2455#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2456#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2457#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2458#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2459
2460/* Debug MCU registers base address */
2461#define DBGMCU_BASE (0x5C001000UL)
2462
2463#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2464#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2465#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2466#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2467#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2468#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2469#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2470#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2471#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2472#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2473#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2474#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2475#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2476#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2477#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2478#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2479
2480#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2481#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2482#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2483#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2484#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2485
2486#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2487#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2488#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2489#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2490#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2491
2492#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2493#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2494
2495
2496
2497#define GPV_BASE (PERIPH_BASE + 0x11000000UL)
2506#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2507#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2508#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2509#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2510#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2511#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2512#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2513#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2514#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2515#define RTC ((RTC_TypeDef *) RTC_BASE)
2516#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2517
2518#define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)
2519#define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
2520
2521#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2522#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2523#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2524#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2525#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2526#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2527#define USART2 ((USART_TypeDef *) USART2_BASE)
2528#define USART3 ((USART_TypeDef *) USART3_BASE)
2529#define USART6 ((USART_TypeDef *) USART6_BASE)
2530#define UART7 ((USART_TypeDef *) UART7_BASE)
2531#define UART8 ((USART_TypeDef *) UART8_BASE)
2532#define CRS ((CRS_TypeDef *) CRS_BASE)
2533#define UART4 ((USART_TypeDef *) UART4_BASE)
2534#define UART5 ((USART_TypeDef *) UART5_BASE)
2535#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2536#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2537#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2538#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2539#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2540#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2541#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2542#define CEC ((CEC_TypeDef *) CEC_BASE)
2543#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2544#define PWR ((PWR_TypeDef *) PWR_BASE)
2545#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2546#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2547#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2548#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2549#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2550#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2551#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2552
2553#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2554#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2555#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2556#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2557#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2558#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2559#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2560#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2561
2562
2563#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2564#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2565#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2566#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2567#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2568#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2569#define USART1 ((USART_TypeDef *) USART1_BASE)
2570#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2571#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2572#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2573#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2574#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2575#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2576#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2577#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2578#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2579#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2580#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2581#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2582#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2583#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2584#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2585#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2586#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2587#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2588#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2589#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2590#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2591#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2592#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2593
2594#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2595#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2596#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2597#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2598#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2599#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2600#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2601#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2602#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2603#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2604#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2605#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2606#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2607#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2608#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2609#define RCC ((RCC_TypeDef *) RCC_BASE)
2610#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
2611#define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
2612
2613#define ART ((ART_TypeDef *) ART_BASE)
2614#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2615#define CRC ((CRC_TypeDef *) CRC_BASE)
2616
2617#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2618#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2619#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2620#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2621#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2622#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2623#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2624#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2625#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2626#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2627#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2628
2629#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2630#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2631#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2632#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2633#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2634
2635#define RNG ((RNG_TypeDef *) RNG_BASE)
2636#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2637#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2638
2639#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2640#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2641#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2642#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2643#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2644#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2645#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2646#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2647#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2648
2649#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2650#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2651#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2652#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2653#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2654#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2655
2656#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2657#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2658#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2659#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2660#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2661#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2662
2663#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2664#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2665#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2666
2667#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2668#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2669#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2670#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2671#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2672#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2673#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2674#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2675#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2676
2677
2678#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2679#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2680#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2681#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2682#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2683#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2684#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2685#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2686
2687#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2688#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2689
2690#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2691#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2692#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2693#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2694#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2695#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2696#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2697#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2698#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2699
2700#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2701#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2702#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2703#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2704#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2705#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2706#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2707#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2708#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2709
2710
2711#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2712#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2713#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2714#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2715#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2716#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2717#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2718#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2719#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2720#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2721#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2722#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2723#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2724#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2725#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2726#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2727#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2728
2729#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2730#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2731#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2732#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2733#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2734#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2735#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2736#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2737
2738#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2739#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2740
2741
2742#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2743#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2744#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2745#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2746#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2747
2748
2749#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2750#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2751#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2752#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2753
2754#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2755
2756#define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2757#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2758#if defined(CORE_CM4)
2759#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
2760#else /* CORE_CM7 */
2761#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2762#endif /* CORE_CM4 */
2763
2764#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2765#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2766#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2767
2768#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2769
2770#define ETH ((ETH_TypeDef *)ETH_BASE)
2771#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2772#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2773#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2774#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2775#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2776#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2777#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2778#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2779#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2780#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2781#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2782#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2783#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2784#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2785#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2786#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2787#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2788
2789
2790#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2791#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2792
2793/* Legacy defines */
2794#define USB_OTG_HS USB1_OTG_HS
2795#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2796#define USB_OTG_FS USB2_OTG_FS
2797#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2798
2799#define GPV ((GPV_TypeDef *) GPV_BASE)
2800
2812#define LSI_STARTUP_TIME 130U
2822/******************************************************************************/
2823/* Peripheral Registers_Bits_Definition */
2824/******************************************************************************/
2825
2826/******************************************************************************/
2827/* */
2828/* Analog to Digital Converter */
2829/* */
2830/******************************************************************************/
2831/******************************* ADC VERSION ********************************/
2832#define ADC_VER_V5_X
2833/******************** Bit definition for ADC_ISR register ********************/
2834#define ADC_ISR_ADRDY_Pos (0U)
2835#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
2836#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
2837#define ADC_ISR_EOSMP_Pos (1U)
2838#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
2839#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
2840#define ADC_ISR_EOC_Pos (2U)
2841#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
2842#define ADC_ISR_EOC ADC_ISR_EOC_Msk
2843#define ADC_ISR_EOS_Pos (3U)
2844#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
2845#define ADC_ISR_EOS ADC_ISR_EOS_Msk
2846#define ADC_ISR_OVR_Pos (4U)
2847#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
2848#define ADC_ISR_OVR ADC_ISR_OVR_Msk
2849#define ADC_ISR_JEOC_Pos (5U)
2850#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
2851#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
2852#define ADC_ISR_JEOS_Pos (6U)
2853#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
2854#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
2855#define ADC_ISR_AWD1_Pos (7U)
2856#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
2857#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
2858#define ADC_ISR_AWD2_Pos (8U)
2859#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
2860#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
2861#define ADC_ISR_AWD3_Pos (9U)
2862#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
2863#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
2864#define ADC_ISR_JQOVF_Pos (10U)
2865#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
2866#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
2867#define ADC_ISR_LDORDY_Pos (12U)
2868#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
2869#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
2871/******************** Bit definition for ADC_IER register ********************/
2872#define ADC_IER_ADRDYIE_Pos (0U)
2873#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
2874#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
2875#define ADC_IER_EOSMPIE_Pos (1U)
2876#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
2877#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
2878#define ADC_IER_EOCIE_Pos (2U)
2879#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
2880#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
2881#define ADC_IER_EOSIE_Pos (3U)
2882#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
2883#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
2884#define ADC_IER_OVRIE_Pos (4U)
2885#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
2886#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
2887#define ADC_IER_JEOCIE_Pos (5U)
2888#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
2889#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
2890#define ADC_IER_JEOSIE_Pos (6U)
2891#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
2892#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
2893#define ADC_IER_AWD1IE_Pos (7U)
2894#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
2895#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
2896#define ADC_IER_AWD2IE_Pos (8U)
2897#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
2898#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
2899#define ADC_IER_AWD3IE_Pos (9U)
2900#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
2901#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
2902#define ADC_IER_JQOVFIE_Pos (10U)
2903#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
2904#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
2906/******************** Bit definition for ADC_CR register ********************/
2907#define ADC_CR_ADEN_Pos (0U)
2908#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
2909#define ADC_CR_ADEN ADC_CR_ADEN_Msk
2910#define ADC_CR_ADDIS_Pos (1U)
2911#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
2912#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
2913#define ADC_CR_ADSTART_Pos (2U)
2914#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
2915#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
2916#define ADC_CR_JADSTART_Pos (3U)
2917#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
2918#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
2919#define ADC_CR_ADSTP_Pos (4U)
2920#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
2921#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
2922#define ADC_CR_JADSTP_Pos (5U)
2923#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
2924#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
2925#define ADC_CR_BOOST_Pos (8U)
2926#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos)
2927#define ADC_CR_BOOST ADC_CR_BOOST_Msk
2928#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos)
2929#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos)
2930#define ADC_CR_ADCALLIN_Pos (16U)
2931#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos)
2932#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk
2933#define ADC_CR_LINCALRDYW1_Pos (22U)
2934#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos)
2935#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk
2936#define ADC_CR_LINCALRDYW2_Pos (23U)
2937#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos)
2938#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk
2939#define ADC_CR_LINCALRDYW3_Pos (24U)
2940#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos)
2941#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk
2942#define ADC_CR_LINCALRDYW4_Pos (25U)
2943#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos)
2944#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk
2945#define ADC_CR_LINCALRDYW5_Pos (26U)
2946#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos)
2947#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk
2948#define ADC_CR_LINCALRDYW6_Pos (27U)
2949#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos)
2950#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk
2951#define ADC_CR_ADVREGEN_Pos (28U)
2952#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
2953#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
2954#define ADC_CR_DEEPPWD_Pos (29U)
2955#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
2956#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
2957#define ADC_CR_ADCALDIF_Pos (30U)
2958#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
2959#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
2960#define ADC_CR_ADCAL_Pos (31U)
2961#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
2962#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
2964/******************** Bit definition for ADC_CFGR register ********************/
2965#define ADC_CFGR_DMNGT_Pos (0U)
2966#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos)
2967#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk
2968#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos)
2969#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos)
2971#define ADC_CFGR_RES_Pos (2U)
2972#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos)
2973#define ADC_CFGR_RES ADC_CFGR_RES_Msk
2974#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
2975#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
2976#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos)
2978#define ADC_CFGR_EXTSEL_Pos (5U)
2979#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
2980#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
2981#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos)
2982#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos)
2983#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos)
2984#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos)
2985#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
2987#define ADC_CFGR_EXTEN_Pos (10U)
2988#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
2989#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
2990#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
2991#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
2993#define ADC_CFGR_OVRMOD_Pos (12U)
2994#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
2995#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
2996#define ADC_CFGR_CONT_Pos (13U)
2997#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
2998#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
2999#define ADC_CFGR_AUTDLY_Pos (14U)
3000#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
3001#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
3003#define ADC_CFGR_DISCEN_Pos (16U)
3004#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
3005#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
3007#define ADC_CFGR_DISCNUM_Pos (17U)
3008#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
3009#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
3010#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
3011#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
3012#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
3014#define ADC_CFGR_JDISCEN_Pos (20U)
3015#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
3016#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
3017#define ADC_CFGR_JQM_Pos (21U)
3018#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
3019#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
3020#define ADC_CFGR_AWD1SGL_Pos (22U)
3021#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
3022#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
3023#define ADC_CFGR_AWD1EN_Pos (23U)
3024#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
3025#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
3026#define ADC_CFGR_JAWD1EN_Pos (24U)
3027#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
3028#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
3029#define ADC_CFGR_JAUTO_Pos (25U)
3030#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
3031#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
3033#define ADC_CFGR_AWD1CH_Pos (26U)
3034#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
3035#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
3036#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
3037#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
3038#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
3039#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
3040#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
3042#define ADC_CFGR_JQDIS_Pos (31U)
3043#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
3044#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
3046/******************** Bit definition for ADC_CFGR2 register ********************/
3047#define ADC_CFGR2_ROVSE_Pos (0U)
3048#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
3049#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
3050#define ADC_CFGR2_JOVSE_Pos (1U)
3051#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
3052#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
3054#define ADC_CFGR2_OVSS_Pos (5U)
3055#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
3056#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
3057#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
3058#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
3059#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
3060#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
3062#define ADC_CFGR2_TROVS_Pos (9U)
3063#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
3064#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
3065#define ADC_CFGR2_ROVSM_Pos (10U)
3066#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
3067#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
3069#define ADC_CFGR2_RSHIFT1_Pos (11U)
3070#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
3071#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk
3072#define ADC_CFGR2_RSHIFT2_Pos (12U)
3073#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
3074#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk
3075#define ADC_CFGR2_RSHIFT3_Pos (13U)
3076#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
3077#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk
3078#define ADC_CFGR2_RSHIFT4_Pos (14U)
3079#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
3080#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk
3082#define ADC_CFGR2_OVSR_Pos (16U)
3083#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos)
3084#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
3085#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos)
3086#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos)
3087#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos)
3088#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos)
3089#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos)
3090#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos)
3091#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos)
3092#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos)
3093#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos)
3094#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos)
3096#define ADC_CFGR2_LSHIFT_Pos (28U)
3097#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos)
3098#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk
3099#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos)
3100#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos)
3101#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos)
3102#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos)
3104/******************** Bit definition for ADC_SMPR1 register ********************/
3105#define ADC_SMPR1_SMP0_Pos (0U)
3106#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
3107#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
3108#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
3109#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
3110#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
3112#define ADC_SMPR1_SMP1_Pos (3U)
3113#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
3114#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
3115#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
3116#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
3117#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
3119#define ADC_SMPR1_SMP2_Pos (6U)
3120#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
3121#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
3122#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
3123#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
3124#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
3126#define ADC_SMPR1_SMP3_Pos (9U)
3127#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
3128#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
3129#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
3130#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
3131#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
3133#define ADC_SMPR1_SMP4_Pos (12U)
3134#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
3135#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
3136#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
3137#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
3138#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
3140#define ADC_SMPR1_SMP5_Pos (15U)
3141#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
3142#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
3143#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
3144#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
3145#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
3147#define ADC_SMPR1_SMP6_Pos (18U)
3148#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
3149#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
3150#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
3151#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
3152#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
3154#define ADC_SMPR1_SMP7_Pos (21U)
3155#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
3156#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
3157#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
3158#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
3159#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
3161#define ADC_SMPR1_SMP8_Pos (24U)
3162#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
3163#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
3164#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
3165#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
3166#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
3168#define ADC_SMPR1_SMP9_Pos (27U)
3169#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
3170#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
3171#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
3172#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
3173#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
3175/******************** Bit definition for ADC_SMPR2 register ********************/
3176#define ADC_SMPR2_SMP10_Pos (0U)
3177#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
3178#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
3179#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
3180#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
3181#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
3183#define ADC_SMPR2_SMP11_Pos (3U)
3184#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
3185#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
3186#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
3187#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
3188#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
3190#define ADC_SMPR2_SMP12_Pos (6U)
3191#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
3192#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
3193#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
3194#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
3195#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
3197#define ADC_SMPR2_SMP13_Pos (9U)
3198#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
3199#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
3200#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
3201#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
3202#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
3204#define ADC_SMPR2_SMP14_Pos (12U)
3205#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
3206#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
3207#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
3208#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
3209#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
3211#define ADC_SMPR2_SMP15_Pos (15U)
3212#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
3213#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
3214#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
3215#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
3216#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
3218#define ADC_SMPR2_SMP16_Pos (18U)
3219#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
3220#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
3221#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
3222#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
3223#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
3225#define ADC_SMPR2_SMP17_Pos (21U)
3226#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
3227#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
3228#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
3229#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
3230#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
3232#define ADC_SMPR2_SMP18_Pos (24U)
3233#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
3234#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
3235#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
3236#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
3237#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
3239#define ADC_SMPR2_SMP19_Pos (27U)
3240#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos)
3241#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk
3242#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos)
3243#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos)
3244#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
3246/******************** Bit definition for ADC_PCSEL register ********************/
3247#define ADC_PCSEL_PCSEL_Pos (0U)
3248#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
3249#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk
3250#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos)
3251#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos)
3252#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos)
3253#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos)
3254#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos)
3255#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos)
3256#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos)
3257#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos)
3258#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos)
3259#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos)
3260#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos)
3261#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos)
3262#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos)
3263#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos)
3264#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos)
3265#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos)
3266#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos)
3267#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos)
3268#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos)
3269#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos)
3271/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3272#define ADC_LTR_LT_Pos (0U)
3273#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos)
3274#define ADC_LTR_LT ADC_LTR_LT_Msk
3276/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3277#define ADC_HTR_HT_Pos (0U)
3278#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos)
3279#define ADC_HTR_HT ADC_HTR_HT_Msk
3282/******************** Bit definition for ADC_SQR1 register ********************/
3283#define ADC_SQR1_L_Pos (0U)
3284#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3285#define ADC_SQR1_L ADC_SQR1_L_Msk
3286#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3287#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3288#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3289#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3291#define ADC_SQR1_SQ1_Pos (6U)
3292#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
3293#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
3294#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
3295#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
3296#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
3297#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
3298#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
3300#define ADC_SQR1_SQ2_Pos (12U)
3301#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
3302#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
3303#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
3304#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
3305#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
3306#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
3307#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
3309#define ADC_SQR1_SQ3_Pos (18U)
3310#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
3311#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
3312#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
3313#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
3314#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
3315#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
3316#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
3318#define ADC_SQR1_SQ4_Pos (24U)
3319#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
3320#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
3321#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
3322#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
3323#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
3324#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
3325#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
3327/******************** Bit definition for ADC_SQR2 register ********************/
3328#define ADC_SQR2_SQ5_Pos (0U)
3329#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
3330#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
3331#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
3332#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
3333#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
3334#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
3335#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
3337#define ADC_SQR2_SQ6_Pos (6U)
3338#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
3339#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
3340#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
3341#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
3342#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
3343#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
3344#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
3346#define ADC_SQR2_SQ7_Pos (12U)
3347#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3348#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3349#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3350#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3351#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3352#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3353#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3355#define ADC_SQR2_SQ8_Pos (18U)
3356#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3357#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3358#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3359#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3360#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3361#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3362#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3364#define ADC_SQR2_SQ9_Pos (24U)
3365#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3366#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3367#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3368#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3369#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3370#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3371#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3373/******************** Bit definition for ADC_SQR3 register ********************/
3374#define ADC_SQR3_SQ10_Pos (0U)
3375#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
3376#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
3377#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
3378#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
3379#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
3380#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
3381#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
3383#define ADC_SQR3_SQ11_Pos (6U)
3384#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
3385#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
3386#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
3387#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
3388#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
3389#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
3390#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
3392#define ADC_SQR3_SQ12_Pos (12U)
3393#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
3394#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
3395#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
3396#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
3397#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
3398#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
3399#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
3401#define ADC_SQR3_SQ13_Pos (18U)
3402#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
3403#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
3404#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
3405#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
3406#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
3407#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
3408#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
3410#define ADC_SQR3_SQ14_Pos (24U)
3411#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
3412#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
3413#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
3414#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
3415#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
3416#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
3417#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
3419/******************** Bit definition for ADC_SQR4 register ********************/
3420#define ADC_SQR4_SQ15_Pos (0U)
3421#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
3422#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
3423#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
3424#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
3425#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
3426#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
3427#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
3429#define ADC_SQR4_SQ16_Pos (6U)
3430#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
3431#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
3432#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
3433#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
3434#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
3435#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
3436#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
3437/******************** Bit definition for ADC_DR register ********************/
3438#define ADC_DR_RDATA_Pos (0U)
3439#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
3440#define ADC_DR_RDATA ADC_DR_RDATA_Msk
3442/******************** Bit definition for ADC_JSQR register ********************/
3443#define ADC_JSQR_JL_Pos (0U)
3444#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3445#define ADC_JSQR_JL ADC_JSQR_JL_Msk
3446#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3447#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3449#define ADC_JSQR_JEXTSEL_Pos (2U)
3450#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
3451#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
3452#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos)
3453#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos)
3454#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos)
3455#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos)
3456#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
3458#define ADC_JSQR_JEXTEN_Pos (7U)
3459#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
3460#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
3461#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
3462#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
3464#define ADC_JSQR_JSQ1_Pos (9U)
3465#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3466#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3467#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3468#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3469#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3470#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3471#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3473#define ADC_JSQR_JSQ2_Pos (15U)
3474#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3475#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3476#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3477#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3478#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3479#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3480#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3482#define ADC_JSQR_JSQ3_Pos (21U)
3483#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3484#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3485#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3486#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3487#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3488#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3489#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3491#define ADC_JSQR_JSQ4_Pos (27U)
3492#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3493#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3494#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3495#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3496#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3497#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3498#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3500/******************** Bit definition for ADC_OFR1 register ********************/
3501#define ADC_OFR1_OFFSET1_Pos (0U)
3502#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
3503#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
3504#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
3505#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
3506#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
3507#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
3508#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
3509#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
3510#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
3511#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
3512#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
3513#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
3514#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
3515#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
3516#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
3517#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
3518#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
3519#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
3520#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
3521#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
3522#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
3523#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
3524#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
3525#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
3526#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
3527#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
3528#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
3529#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
3531#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3532#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
3533#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
3534#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
3535#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
3536#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
3537#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
3538#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
3540#define ADC_OFR1_SSATE_Pos (31U)
3541#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos)
3542#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk
3545/******************** Bit definition for ADC_OFR2 register ********************/
3546#define ADC_OFR2_OFFSET2_Pos (0U)
3547#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
3548#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
3549#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
3550#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
3551#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
3552#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
3553#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
3554#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
3555#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
3556#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
3557#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
3558#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
3559#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
3560#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
3561#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
3562#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
3563#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
3564#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
3565#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
3566#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
3567#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
3568#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
3569#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
3570#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
3571#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
3572#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
3573#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
3574#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
3576#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3577#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
3578#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
3579#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
3580#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
3581#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
3582#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
3583#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
3585#define ADC_OFR2_SSATE_Pos (31U)
3586#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos)
3587#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk
3590/******************** Bit definition for ADC_OFR3 register ********************/
3591#define ADC_OFR3_OFFSET3_Pos (0U)
3592#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
3593#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
3594#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
3595#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
3596#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
3597#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
3598#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
3599#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
3600#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
3601#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
3602#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
3603#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
3604#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
3605#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
3606#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
3607#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
3608#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
3609#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
3610#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
3611#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
3612#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
3613#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
3614#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
3615#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
3616#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
3617#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
3618#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
3619#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
3621#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3622#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
3623#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
3624#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
3625#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
3626#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
3627#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
3628#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
3630#define ADC_OFR3_SSATE_Pos (31U)
3631#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos)
3632#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk
3635/******************** Bit definition for ADC_OFR4 register ********************/
3636#define ADC_OFR4_OFFSET4_Pos (0U)
3637#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
3638#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
3639#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
3640#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
3641#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
3642#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
3643#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
3644#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
3645#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
3646#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
3647#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
3648#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
3649#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
3650#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
3651#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
3652#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
3653#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
3654#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
3655#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
3656#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
3657#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
3658#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
3659#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
3660#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
3661#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
3662#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
3663#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
3664#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
3666#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3667#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
3668#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
3669#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
3670#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
3671#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
3672#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
3673#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
3675#define ADC_OFR4_SSATE_Pos (31U)
3676#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos)
3677#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk
3680/******************** Bit definition for ADC_JDR1 register ********************/
3681#define ADC_JDR1_JDATA_Pos (0U)
3682#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
3683#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3684#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos)
3685#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos)
3686#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos)
3687#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos)
3688#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos)
3689#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos)
3690#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos)
3691#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos)
3692#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos)
3693#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos)
3694#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos)
3695#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos)
3696#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos)
3697#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos)
3698#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos)
3699#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos)
3700#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos)
3701#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos)
3702#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos)
3703#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos)
3704#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos)
3705#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos)
3706#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos)
3707#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos)
3708#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos)
3709#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos)
3710#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos)
3711#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos)
3712#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos)
3713#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos)
3714#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos)
3715#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos)
3717/******************** Bit definition for ADC_JDR2 register ********************/
3718#define ADC_JDR2_JDATA_Pos (0U)
3719#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
3720#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3721#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos)
3722#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos)
3723#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos)
3724#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos)
3725#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos)
3726#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos)
3727#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos)
3728#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos)
3729#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos)
3730#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos)
3731#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos)
3732#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos)
3733#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos)
3734#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos)
3735#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos)
3736#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos)
3737#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos)
3738#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos)
3739#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos)
3740#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos)
3741#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos)
3742#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos)
3743#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos)
3744#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos)
3745#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos)
3746#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos)
3747#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos)
3748#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos)
3749#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos)
3750#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos)
3751#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos)
3752#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos)
3754/******************** Bit definition for ADC_JDR3 register ********************/
3755#define ADC_JDR3_JDATA_Pos (0U)
3756#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
3757#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3758#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos)
3759#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos)
3760#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos)
3761#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos)
3762#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos)
3763#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos)
3764#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos)
3765#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos)
3766#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos)
3767#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos)
3768#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos)
3769#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos)
3770#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos)
3771#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos)
3772#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos)
3773#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos)
3774#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos)
3775#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos)
3776#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos)
3777#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos)
3778#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos)
3779#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos)
3780#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos)
3781#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos)
3782#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos)
3783#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos)
3784#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos)
3785#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos)
3786#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos)
3787#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos)
3788#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos)
3789#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos)
3791/******************** Bit definition for ADC_JDR4 register ********************/
3792#define ADC_JDR4_JDATA_Pos (0U)
3793#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
3794#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3795#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos)
3796#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos)
3797#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos)
3798#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos)
3799#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos)
3800#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos)
3801#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos)
3802#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos)
3803#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos)
3804#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos)
3805#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos)
3806#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos)
3807#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos)
3808#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos)
3809#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos)
3810#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos)
3811#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
3812#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos)
3813#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos)
3814#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos)
3815#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos)
3816#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos)
3817#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos)
3818#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos)
3819#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos)
3820#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos)
3821#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos)
3822#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos)
3823#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos)
3824#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos)
3825#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos)
3826#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos)
3828/******************** Bit definition for ADC_AWD2CR register ********************/
3829#define ADC_AWD2CR_AWD2CH_Pos (0U)
3830#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
3831#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
3832#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
3833#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
3834#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
3835#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
3836#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
3837#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
3838#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
3839#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
3840#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
3841#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
3842#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
3843#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
3844#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
3845#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
3846#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
3847#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
3848#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
3849#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
3850#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
3851#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
3853/******************** Bit definition for ADC_AWD3CR register ********************/
3854#define ADC_AWD3CR_AWD3CH_Pos (0U)
3855#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
3856#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
3857#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
3858#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
3859#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
3860#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
3861#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
3862#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
3863#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
3864#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
3865#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
3866#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
3867#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
3868#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
3869#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
3870#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
3871#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
3872#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
3873#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
3874#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
3875#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
3876#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
3878/******************** Bit definition for ADC_DIFSEL register ********************/
3879#define ADC_DIFSEL_DIFSEL_Pos (0U)
3880#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
3881#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
3882#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
3883#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
3884#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
3885#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
3886#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
3887#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
3888#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
3889#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
3890#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
3891#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
3892#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
3893#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
3894#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
3895#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
3896#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
3897#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
3898#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
3899#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
3900#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
3901#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
3903/******************** Bit definition for ADC_CALFACT register ********************/
3904#define ADC_CALFACT_CALFACT_S_Pos (0U)
3905#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
3906#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
3907#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
3908#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
3909#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
3910#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
3911#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
3912#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
3913#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
3914#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
3915#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
3916#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
3917#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
3918#define ADC_CALFACT_CALFACT_D_Pos (16U)
3919#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
3920#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
3921#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
3922#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
3923#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
3924#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
3925#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
3926#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
3927#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
3928#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
3929#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
3930#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
3931#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
3933/******************** Bit definition for ADC_CALFACT2 register ********************/
3934#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3935#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
3936#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk
3937#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
3938#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
3939#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
3940#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
3941#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
3942#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
3943#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
3944#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
3945#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
3946#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
3947#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
3948#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
3949#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
3950#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
3951#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
3952#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
3953#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
3954#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
3955#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
3956#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
3957#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
3958#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
3959#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
3960#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
3961#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3962#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3963#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3964#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3965#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3966#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3968/************************* ADC Common registers *****************************/
3969/******************** Bit definition for ADC_CSR register ********************/
3970#define ADC_CSR_ADRDY_MST_Pos (0U)
3971#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
3972#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
3973#define ADC_CSR_EOSMP_MST_Pos (1U)
3974#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
3975#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
3976#define ADC_CSR_EOC_MST_Pos (2U)
3977#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
3978#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
3979#define ADC_CSR_EOS_MST_Pos (3U)
3980#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
3981#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
3982#define ADC_CSR_OVR_MST_Pos (4U)
3983#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
3984#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
3985#define ADC_CSR_JEOC_MST_Pos (5U)
3986#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
3987#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
3988#define ADC_CSR_JEOS_MST_Pos (6U)
3989#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
3990#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
3991#define ADC_CSR_AWD1_MST_Pos (7U)
3992#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
3993#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
3994#define ADC_CSR_AWD2_MST_Pos (8U)
3995#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
3996#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
3997#define ADC_CSR_AWD3_MST_Pos (9U)
3998#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
3999#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
4000#define ADC_CSR_JQOVF_MST_Pos (10U)
4001#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
4002#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
4003#define ADC_CSR_ADRDY_SLV_Pos (16U)
4004#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
4005#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
4006#define ADC_CSR_EOSMP_SLV_Pos (17U)
4007#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
4008#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
4009#define ADC_CSR_EOC_SLV_Pos (18U)
4010#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
4011#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
4012#define ADC_CSR_EOS_SLV_Pos (19U)
4013#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
4014#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
4015#define ADC_CSR_OVR_SLV_Pos (20U)
4016#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
4017#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
4018#define ADC_CSR_JEOC_SLV_Pos (21U)
4019#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
4020#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
4021#define ADC_CSR_JEOS_SLV_Pos (22U)
4022#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
4023#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
4024#define ADC_CSR_AWD1_SLV_Pos (23U)
4025#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
4026#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
4027#define ADC_CSR_AWD2_SLV_Pos (24U)
4028#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
4029#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
4030#define ADC_CSR_AWD3_SLV_Pos (25U)
4031#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
4032#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
4033#define ADC_CSR_JQOVF_SLV_Pos (26U)
4034#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
4035#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
4037/******************** Bit definition for ADC_CCR register ********************/
4038#define ADC_CCR_DUAL_Pos (0U)
4039#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
4040#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
4041#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
4042#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
4043#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
4044#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
4045#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
4047#define ADC_CCR_DELAY_Pos (8U)
4048#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
4049#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
4050#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
4051#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
4052#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
4053#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
4056#define ADC_CCR_DAMDF_Pos (14U)
4057#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos)
4058#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk
4059#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos)
4060#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos)
4062#define ADC_CCR_CKMODE_Pos (16U)
4063#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
4064#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
4065#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
4066#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
4068#define ADC_CCR_PRESC_Pos (18U)
4069#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
4070#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
4071#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
4072#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
4073#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
4074#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
4076#define ADC_CCR_VREFEN_Pos (22U)
4077#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
4078#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
4079#define ADC_CCR_TSEN_Pos (23U)
4080#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
4081#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
4082#define ADC_CCR_VBATEN_Pos (24U)
4083#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
4084#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
4086/******************** Bit definition for ADC_CDR register *******************/
4087#define ADC_CDR_RDATA_MST_Pos (0U)
4088#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
4089#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
4091#define ADC_CDR_RDATA_SLV_Pos (16U)
4092#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
4093#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
4095/******************** Bit definition for ADC_CDR2 register ******************/
4096#define ADC_CDR2_RDATA_ALT_Pos (0U)
4097#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
4098#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk
4100/******************************************************************************/
4101/* */
4102/* ART accelerator */
4103/* */
4104/******************************************************************************/
4105/******************* Bit definition for ART_CTR register ********************/
4106#define ART_CTR_EN_Pos (0U)
4107#define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos)
4108#define ART_CTR_EN ART_CTR_EN_Msk
4110#define ART_CTR_PCACHEADDR_Pos (8U)
4111#define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos)
4112#define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk
4114/******************************************************************************/
4115/* */
4116/* VREFBUF */
4117/* */
4118/******************************************************************************/
4119/******************* Bit definition for VREFBUF_CSR register ****************/
4120#define VREFBUF_CSR_ENVR_Pos (0U)
4121#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
4122#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
4123#define VREFBUF_CSR_HIZ_Pos (1U)
4124#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
4125#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
4126#define VREFBUF_CSR_VRR_Pos (3U)
4127#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
4128#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
4129#define VREFBUF_CSR_VRS_Pos (4U)
4130#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos)
4131#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
4133#define VREFBUF_CSR_VRS_OUT1 (0U)
4134#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4135#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
4136#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk
4137#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4138#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
4139#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk
4140#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4141#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
4142#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk
4144/******************* Bit definition for VREFBUF_CCR register ****************/
4145#define VREFBUF_CCR_TRIM_Pos (0U)
4146#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
4147#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
4149/******************************************************************************/
4150/* */
4151/* Flexible Datarate Controller Area Network */
4152/* */
4153/******************************************************************************/
4155/***************** Bit definition for FDCAN_CREL register *******************/
4156#define FDCAN_CREL_DAY_Pos (0U)
4157#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
4158#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
4159#define FDCAN_CREL_MON_Pos (8U)
4160#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
4161#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
4162#define FDCAN_CREL_YEAR_Pos (16U)
4163#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
4164#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
4165#define FDCAN_CREL_SUBSTEP_Pos (20U)
4166#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
4167#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
4168#define FDCAN_CREL_STEP_Pos (24U)
4169#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
4170#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
4171#define FDCAN_CREL_REL_Pos (28U)
4172#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
4173#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
4175/***************** Bit definition for FDCAN_ENDN register *******************/
4176#define FDCAN_ENDN_ETV_Pos (0U)
4177#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
4178#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
4180/***************** Bit definition for FDCAN_DBTP register *******************/
4181#define FDCAN_DBTP_DSJW_Pos (0U)
4182#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
4183#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
4184#define FDCAN_DBTP_DTSEG2_Pos (4U)
4185#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
4186#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
4187#define FDCAN_DBTP_DTSEG1_Pos (8U)
4188#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
4189#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
4190#define FDCAN_DBTP_DBRP_Pos (16U)
4191#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
4192#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
4193#define FDCAN_DBTP_TDC_Pos (23U)
4194#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
4195#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
4197/***************** Bit definition for FDCAN_TEST register *******************/
4198#define FDCAN_TEST_LBCK_Pos (4U)
4199#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
4200#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
4201#define FDCAN_TEST_TX_Pos (5U)
4202#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4203#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4204#define FDCAN_TEST_RX_Pos (7U)
4205#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4206#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4208/***************** Bit definition for FDCAN_RWD register ********************/
4209#define FDCAN_RWD_WDC_Pos (0U)
4210#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4211#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4212#define FDCAN_RWD_WDV_Pos (8U)
4213#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4214#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4216/***************** Bit definition for FDCAN_CCCR register ********************/
4217#define FDCAN_CCCR_INIT_Pos (0U)
4218#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4219#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4220#define FDCAN_CCCR_CCE_Pos (1U)
4221#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4222#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4223#define FDCAN_CCCR_ASM_Pos (2U)
4224#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4225#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4226#define FDCAN_CCCR_CSA_Pos (3U)
4227#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4228#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4229#define FDCAN_CCCR_CSR_Pos (4U)
4230#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4231#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4232#define FDCAN_CCCR_MON_Pos (5U)
4233#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4234#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4235#define FDCAN_CCCR_DAR_Pos (6U)
4236#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4237#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4238#define FDCAN_CCCR_TEST_Pos (7U)
4239#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4240#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4241#define FDCAN_CCCR_FDOE_Pos (8U)
4242#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4243#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4244#define FDCAN_CCCR_BRSE_Pos (9U)
4245#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4246#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4247#define FDCAN_CCCR_PXHD_Pos (12U)
4248#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4249#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4250#define FDCAN_CCCR_EFBI_Pos (13U)
4251#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4252#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4253#define FDCAN_CCCR_TXP_Pos (14U)
4254#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4255#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4256#define FDCAN_CCCR_NISO_Pos (15U)
4257#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4258#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4260/***************** Bit definition for FDCAN_NBTP register ********************/
4261#define FDCAN_NBTP_NTSEG2_Pos (0U)
4262#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4263#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4264#define FDCAN_NBTP_NTSEG1_Pos (8U)
4265#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4266#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4267#define FDCAN_NBTP_NBRP_Pos (16U)
4268#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4269#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4270#define FDCAN_NBTP_NSJW_Pos (25U)
4271#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4272#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4274/***************** Bit definition for FDCAN_TSCC register ********************/
4275#define FDCAN_TSCC_TSS_Pos (0U)
4276#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4277#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4278#define FDCAN_TSCC_TCP_Pos (16U)
4279#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4280#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4282/***************** Bit definition for FDCAN_TSCV register ********************/
4283#define FDCAN_TSCV_TSC_Pos (0U)
4284#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4285#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4287/***************** Bit definition for FDCAN_TOCC register ********************/
4288#define FDCAN_TOCC_ETOC_Pos (0U)
4289#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4290#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4291#define FDCAN_TOCC_TOS_Pos (1U)
4292#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4293#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4294#define FDCAN_TOCC_TOP_Pos (16U)
4295#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4296#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4298/***************** Bit definition for FDCAN_TOCV register ********************/
4299#define FDCAN_TOCV_TOC_Pos (0U)
4300#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4301#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4303/***************** Bit definition for FDCAN_ECR register *********************/
4304#define FDCAN_ECR_TEC_Pos (0U)
4305#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4306#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4307#define FDCAN_ECR_REC_Pos (8U)
4308#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4309#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4310#define FDCAN_ECR_RP_Pos (15U)
4311#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4312#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4313#define FDCAN_ECR_CEL_Pos (16U)
4314#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4315#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4317/***************** Bit definition for FDCAN_PSR register *********************/
4318#define FDCAN_PSR_LEC_Pos (0U)
4319#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4320#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4321#define FDCAN_PSR_ACT_Pos (3U)
4322#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4323#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4324#define FDCAN_PSR_EP_Pos (5U)
4325#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4326#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4327#define FDCAN_PSR_EW_Pos (6U)
4328#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4329#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4330#define FDCAN_PSR_BO_Pos (7U)
4331#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4332#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4333#define FDCAN_PSR_DLEC_Pos (8U)
4334#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4335#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4336#define FDCAN_PSR_RESI_Pos (11U)
4337#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4338#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4339#define FDCAN_PSR_RBRS_Pos (12U)
4340#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4341#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4342#define FDCAN_PSR_REDL_Pos (13U)
4343#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4344#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4345#define FDCAN_PSR_PXE_Pos (14U)
4346#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4347#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4348#define FDCAN_PSR_TDCV_Pos (16U)
4349#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4350#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4352/***************** Bit definition for FDCAN_TDCR register ********************/
4353#define FDCAN_TDCR_TDCF_Pos (0U)
4354#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4355#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4356#define FDCAN_TDCR_TDCO_Pos (8U)
4357#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4358#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4360/***************** Bit definition for FDCAN_IR register **********************/
4361#define FDCAN_IR_RF0N_Pos (0U)
4362#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4363#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4364#define FDCAN_IR_RF0W_Pos (1U)
4365#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos)
4366#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk
4367#define FDCAN_IR_RF0F_Pos (2U)
4368#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4369#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4370#define FDCAN_IR_RF0L_Pos (3U)
4371#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4372#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4373#define FDCAN_IR_RF1N_Pos (4U)
4374#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4375#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4376#define FDCAN_IR_RF1W_Pos (5U)
4377#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos)
4378#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk
4379#define FDCAN_IR_RF1F_Pos (6U)
4380#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4381#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4382#define FDCAN_IR_RF1L_Pos (7U)
4383#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4384#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4385#define FDCAN_IR_HPM_Pos (8U)
4386#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4387#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4388#define FDCAN_IR_TC_Pos (9U)
4389#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4390#define FDCAN_IR_TC FDCAN_IR_TC_Msk
4391#define FDCAN_IR_TCF_Pos (10U)
4392#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4393#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4394#define FDCAN_IR_TFE_Pos (11U)
4395#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4396#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4397#define FDCAN_IR_TEFN_Pos (12U)
4398#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4399#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4400#define FDCAN_IR_TEFW_Pos (13U)
4401#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos)
4402#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk
4403#define FDCAN_IR_TEFF_Pos (14U)
4404#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4405#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4406#define FDCAN_IR_TEFL_Pos (15U)
4407#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4408#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4409#define FDCAN_IR_TSW_Pos (16U)
4410#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4411#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4412#define FDCAN_IR_MRAF_Pos (17U)
4413#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4414#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4415#define FDCAN_IR_TOO_Pos (18U)
4416#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4417#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4418#define FDCAN_IR_DRX_Pos (19U)
4419#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos)
4420#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk
4421#define FDCAN_IR_ELO_Pos (22U)
4422#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4423#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4424#define FDCAN_IR_EP_Pos (23U)
4425#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4426#define FDCAN_IR_EP FDCAN_IR_EP_Msk
4427#define FDCAN_IR_EW_Pos (24U)
4428#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4429#define FDCAN_IR_EW FDCAN_IR_EW_Msk
4430#define FDCAN_IR_BO_Pos (25U)
4431#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4432#define FDCAN_IR_BO FDCAN_IR_BO_Msk
4433#define FDCAN_IR_WDI_Pos (26U)
4434#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4435#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4436#define FDCAN_IR_PEA_Pos (27U)
4437#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4438#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4439#define FDCAN_IR_PED_Pos (28U)
4440#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4441#define FDCAN_IR_PED FDCAN_IR_PED_Msk
4442#define FDCAN_IR_ARA_Pos (29U)
4443#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4444#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4446/***************** Bit definition for FDCAN_IE register **********************/
4447#define FDCAN_IE_RF0NE_Pos (0U)
4448#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4449#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4450#define FDCAN_IE_RF0WE_Pos (1U)
4451#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos)
4452#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk
4453#define FDCAN_IE_RF0FE_Pos (2U)
4454#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4455#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4456#define FDCAN_IE_RF0LE_Pos (3U)
4457#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4458#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4459#define FDCAN_IE_RF1NE_Pos (4U)
4460#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4461#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4462#define FDCAN_IE_RF1WE_Pos (5U)
4463#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos)
4464#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
4465#define FDCAN_IE_RF1FE_Pos (6U)
4466#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4467#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4468#define FDCAN_IE_RF1LE_Pos (7U)
4469#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4470#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4471#define FDCAN_IE_HPME_Pos (8U)
4472#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4473#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4474#define FDCAN_IE_TCE_Pos (9U)
4475#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4476#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4477#define FDCAN_IE_TCFE_Pos (10U)
4478#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4479#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4480#define FDCAN_IE_TFEE_Pos (11U)
4481#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4482#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4483#define FDCAN_IE_TEFNE_Pos (12U)
4484#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4485#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4486#define FDCAN_IE_TEFWE_Pos (13U)
4487#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos)
4488#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk
4489#define FDCAN_IE_TEFFE_Pos (14U)
4490#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4491#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4492#define FDCAN_IE_TEFLE_Pos (15U)
4493#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4494#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4495#define FDCAN_IE_TSWE_Pos (16U)
4496#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4497#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4498#define FDCAN_IE_MRAFE_Pos (17U)
4499#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4500#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4501#define FDCAN_IE_TOOE_Pos (18U)
4502#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4503#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4504#define FDCAN_IE_DRXE_Pos (19U)
4505#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos)
4506#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk
4507#define FDCAN_IE_BECE_Pos (20U)
4508#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos)
4509#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk
4510#define FDCAN_IE_BEUE_Pos (21U)
4511#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos)
4512#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk
4513#define FDCAN_IE_ELOE_Pos (22U)
4514#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4515#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4516#define FDCAN_IE_EPE_Pos (23U)
4517#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4518#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4519#define FDCAN_IE_EWE_Pos (24U)
4520#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4521#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4522#define FDCAN_IE_BOE_Pos (25U)
4523#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4524#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4525#define FDCAN_IE_WDIE_Pos (26U)
4526#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4527#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4528#define FDCAN_IE_PEAE_Pos (27U)
4529#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4530#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4531#define FDCAN_IE_PEDE_Pos (28U)
4532#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4533#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4534#define FDCAN_IE_ARAE_Pos (29U)
4535#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4536#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4538/***************** Bit definition for FDCAN_ILS register **********************/
4539#define FDCAN_ILS_RF0NL_Pos (0U)
4540#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos)
4541#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk
4542#define FDCAN_ILS_RF0WL_Pos (1U)
4543#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos)
4544#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk
4545#define FDCAN_ILS_RF0FL_Pos (2U)
4546#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos)
4547#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk
4548#define FDCAN_ILS_RF0LL_Pos (3U)
4549#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos)
4550#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk
4551#define FDCAN_ILS_RF1NL_Pos (4U)
4552#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos)
4553#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk
4554#define FDCAN_ILS_RF1WL_Pos (5U)
4555#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos)
4556#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk
4557#define FDCAN_ILS_RF1FL_Pos (6U)
4558#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos)
4559#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk
4560#define FDCAN_ILS_RF1LL_Pos (7U)
4561#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos)
4562#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk
4563#define FDCAN_ILS_HPML_Pos (8U)
4564#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos)
4565#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk
4566#define FDCAN_ILS_TCL_Pos (9U)
4567#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos)
4568#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk
4569#define FDCAN_ILS_TCFL_Pos (10U)
4570#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos)
4571#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk
4572#define FDCAN_ILS_TFEL_Pos (11U)
4573#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos)
4574#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk
4575#define FDCAN_ILS_TEFNL_Pos (12U)
4576#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos)
4577#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk
4578#define FDCAN_ILS_TEFWL_Pos (13U)
4579#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos)
4580#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk
4581#define FDCAN_ILS_TEFFL_Pos (14U)
4582#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos)
4583#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk
4584#define FDCAN_ILS_TEFLL_Pos (15U)
4585#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos)
4586#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk
4587#define FDCAN_ILS_TSWL_Pos (16U)
4588#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos)
4589#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk
4590#define FDCAN_ILS_MRAFE_Pos (17U)
4591#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos)
4592#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
4593#define FDCAN_ILS_TOOE_Pos (18U)
4594#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos)
4595#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk
4596#define FDCAN_ILS_DRXE_Pos (19U)
4597#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos)
4598#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk
4599#define FDCAN_ILS_BECE_Pos (20U)
4600#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos)
4601#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk
4602#define FDCAN_ILS_BEUE_Pos (21U)
4603#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos)
4604#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk
4605#define FDCAN_ILS_ELOE_Pos (22U)
4606#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos)
4607#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk
4608#define FDCAN_ILS_EPE_Pos (23U)
4609#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos)
4610#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk
4611#define FDCAN_ILS_EWE_Pos (24U)
4612#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos)
4613#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk
4614#define FDCAN_ILS_BOE_Pos (25U)
4615#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos)
4616#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk
4617#define FDCAN_ILS_WDIE_Pos (26U)
4618#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos)
4619#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk
4620#define FDCAN_ILS_PEAE_Pos (27U)
4621#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos)
4622#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk
4623#define FDCAN_ILS_PEDE_Pos (28U)
4624#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos)
4625#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk
4626#define FDCAN_ILS_ARAE_Pos (29U)
4627#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos)
4628#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk
4630/***************** Bit definition for FDCAN_ILE register **********************/
4631#define FDCAN_ILE_EINT0_Pos (0U)
4632#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4633#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4634#define FDCAN_ILE_EINT1_Pos (1U)
4635#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4636#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4638/***************** Bit definition for FDCAN_GFC register **********************/
4639#define FDCAN_GFC_RRFE_Pos (0U)
4640#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos)
4641#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk
4642#define FDCAN_GFC_RRFS_Pos (1U)
4643#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos)
4644#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk
4645#define FDCAN_GFC_ANFE_Pos (2U)
4646#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos)
4647#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk
4648#define FDCAN_GFC_ANFS_Pos (4U)
4649#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos)
4650#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk
4652/***************** Bit definition for FDCAN_SIDFC register ********************/
4653#define FDCAN_SIDFC_FLSSA_Pos (2U)
4654#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
4655#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk
4656#define FDCAN_SIDFC_LSS_Pos (16U)
4657#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos)
4658#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk
4660/***************** Bit definition for FDCAN_XIDFC register ********************/
4661#define FDCAN_XIDFC_FLESA_Pos (2U)
4662#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
4663#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk
4664#define FDCAN_XIDFC_LSE_Pos (16U)
4665#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos)
4666#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk
4668/***************** Bit definition for FDCAN_XIDAM register ********************/
4669#define FDCAN_XIDAM_EIDM_Pos (0U)
4670#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4671#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4673/***************** Bit definition for FDCAN_HPMS register *********************/
4674#define FDCAN_HPMS_BIDX_Pos (0U)
4675#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos)
4676#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4677#define FDCAN_HPMS_MSI_Pos (6U)
4678#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4679#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4680#define FDCAN_HPMS_FIDX_Pos (8U)
4681#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos)
4682#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4683#define FDCAN_HPMS_FLST_Pos (15U)
4684#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4685#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4687/***************** Bit definition for FDCAN_NDAT1 register ********************/
4688#define FDCAN_NDAT1_ND0_Pos (0U)
4689#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos)
4690#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk
4691#define FDCAN_NDAT1_ND1_Pos (1U)
4692#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos)
4693#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk
4694#define FDCAN_NDAT1_ND2_Pos (2U)
4695#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos)
4696#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk
4697#define FDCAN_NDAT1_ND3_Pos (3U)
4698#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos)
4699#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk
4700#define FDCAN_NDAT1_ND4_Pos (4U)
4701#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos)
4702#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk
4703#define FDCAN_NDAT1_ND5_Pos (5U)
4704#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos)
4705#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk
4706#define FDCAN_NDAT1_ND6_Pos (6U)
4707#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos)
4708#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk
4709#define FDCAN_NDAT1_ND7_Pos (7U)
4710#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos)
4711#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk
4712#define FDCAN_NDAT1_ND8_Pos (8U)
4713#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos)
4714#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk
4715#define FDCAN_NDAT1_ND9_Pos (9U)
4716#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos)
4717#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk
4718#define FDCAN_NDAT1_ND10_Pos (10U)
4719#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos)
4720#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
4721#define FDCAN_NDAT1_ND11_Pos (11U)
4722#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos)
4723#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk
4724#define FDCAN_NDAT1_ND12_Pos (12U)
4725#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos)
4726#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk
4727#define FDCAN_NDAT1_ND13_Pos (13U)
4728#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos)
4729#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk
4730#define FDCAN_NDAT1_ND14_Pos (14U)
4731#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos)
4732#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk
4733#define FDCAN_NDAT1_ND15_Pos (15U)
4734#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos)
4735#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk
4736#define FDCAN_NDAT1_ND16_Pos (16U)
4737#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos)
4738#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk
4739#define FDCAN_NDAT1_ND17_Pos (17U)
4740#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos)
4741#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk
4742#define FDCAN_NDAT1_ND18_Pos (18U)
4743#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos)
4744#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk
4745#define FDCAN_NDAT1_ND19_Pos (19U)
4746#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos)
4747#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk
4748#define FDCAN_NDAT1_ND20_Pos (20U)
4749#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos)
4750#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk
4751#define FDCAN_NDAT1_ND21_Pos (21U)
4752#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos)
4753#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk
4754#define FDCAN_NDAT1_ND22_Pos (22U)
4755#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos)
4756#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk
4757#define FDCAN_NDAT1_ND23_Pos (23U)
4758#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos)
4759#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk
4760#define FDCAN_NDAT1_ND24_Pos (24U)
4761#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos)
4762#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk
4763#define FDCAN_NDAT1_ND25_Pos (25U)
4764#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos)
4765#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk
4766#define FDCAN_NDAT1_ND26_Pos (26U)
4767#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos)
4768#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk
4769#define FDCAN_NDAT1_ND27_Pos (27U)
4770#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos)
4771#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk
4772#define FDCAN_NDAT1_ND28_Pos (28U)
4773#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos)
4774#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk
4775#define FDCAN_NDAT1_ND29_Pos (29U)
4776#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos)
4777#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk
4778#define FDCAN_NDAT1_ND30_Pos (30U)
4779#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos)
4780#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk
4781#define FDCAN_NDAT1_ND31_Pos (31U)
4782#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos)
4783#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk
4785/***************** Bit definition for FDCAN_NDAT2 register ********************/
4786#define FDCAN_NDAT2_ND32_Pos (0U)
4787#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos)
4788#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk
4789#define FDCAN_NDAT2_ND33_Pos (1U)
4790#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos)
4791#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk
4792#define FDCAN_NDAT2_ND34_Pos (2U)
4793#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos)
4794#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk
4795#define FDCAN_NDAT2_ND35_Pos (3U)
4796#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos)
4797#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk
4798#define FDCAN_NDAT2_ND36_Pos (4U)
4799#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos)
4800#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk
4801#define FDCAN_NDAT2_ND37_Pos (5U)
4802#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos)
4803#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk
4804#define FDCAN_NDAT2_ND38_Pos (6U)
4805#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos)
4806#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk
4807#define FDCAN_NDAT2_ND39_Pos (7U)
4808#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos)
4809#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk
4810#define FDCAN_NDAT2_ND40_Pos (8U)
4811#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos)
4812#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk
4813#define FDCAN_NDAT2_ND41_Pos (9U)
4814#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos)
4815#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk
4816#define FDCAN_NDAT2_ND42_Pos (10U)
4817#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos)
4818#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk
4819#define FDCAN_NDAT2_ND43_Pos (11U)
4820#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos)
4821#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk
4822#define FDCAN_NDAT2_ND44_Pos (12U)
4823#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos)
4824#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk
4825#define FDCAN_NDAT2_ND45_Pos (13U)
4826#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos)
4827#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk
4828#define FDCAN_NDAT2_ND46_Pos (14U)
4829#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos)
4830#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk
4831#define FDCAN_NDAT2_ND47_Pos (15U)
4832#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos)
4833#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk
4834#define FDCAN_NDAT2_ND48_Pos (16U)
4835#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos)
4836#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk
4837#define FDCAN_NDAT2_ND49_Pos (17U)
4838#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos)
4839#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk
4840#define FDCAN_NDAT2_ND50_Pos (18U)
4841#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos)
4842#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk
4843#define FDCAN_NDAT2_ND51_Pos (19U)
4844#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos)
4845#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk
4846#define FDCAN_NDAT2_ND52_Pos (20U)
4847#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos)
4848#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
4849#define FDCAN_NDAT2_ND53_Pos (21U)
4850#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos)
4851#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk
4852#define FDCAN_NDAT2_ND54_Pos (22U)
4853#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos)
4854#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk
4855#define FDCAN_NDAT2_ND55_Pos (23U)
4856#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos)
4857#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk
4858#define FDCAN_NDAT2_ND56_Pos (24U)
4859#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos)
4860#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk
4861#define FDCAN_NDAT2_ND57_Pos (25U)
4862#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos)
4863#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk
4864#define FDCAN_NDAT2_ND58_Pos (26U)
4865#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos)
4866#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk
4867#define FDCAN_NDAT2_ND59_Pos (27U)
4868#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos)
4869#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk
4870#define FDCAN_NDAT2_ND60_Pos (28U)
4871#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos)
4872#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk
4873#define FDCAN_NDAT2_ND61_Pos (29U)
4874#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos)
4875#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk
4876#define FDCAN_NDAT2_ND62_Pos (30U)
4877#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos)
4878#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk
4879#define FDCAN_NDAT2_ND63_Pos (31U)
4880#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos)
4881#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk
4883/***************** Bit definition for FDCAN_RXF0C register ********************/
4884#define FDCAN_RXF0C_F0SA_Pos (2U)
4885#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
4886#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk
4887#define FDCAN_RXF0C_F0S_Pos (16U)
4888#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos)
4889#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk
4890#define FDCAN_RXF0C_F0WM_Pos (24U)
4891#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
4892#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk
4893#define FDCAN_RXF0C_F0OM_Pos (31U)
4894#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos)
4895#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk
4897/***************** Bit definition for FDCAN_RXF0S register ********************/
4898#define FDCAN_RXF0S_F0FL_Pos (0U)
4899#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
4900#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
4901#define FDCAN_RXF0S_F0GI_Pos (8U)
4902#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
4903#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
4904#define FDCAN_RXF0S_F0PI_Pos (16U)
4905#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
4906#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
4907#define FDCAN_RXF0S_F0F_Pos (24U)
4908#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
4909#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
4910#define FDCAN_RXF0S_RF0L_Pos (25U)
4911#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
4912#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
4914/***************** Bit definition for FDCAN_RXF0A register ********************/
4915#define FDCAN_RXF0A_F0AI_Pos (0U)
4916#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
4917#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
4919/***************** Bit definition for FDCAN_RXBC register ********************/
4920#define FDCAN_RXBC_RBSA_Pos (2U)
4921#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
4922#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk
4924/***************** Bit definition for FDCAN_RXF1C register ********************/
4925#define FDCAN_RXF1C_F1SA_Pos (2U)
4926#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
4927#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk
4928#define FDCAN_RXF1C_F1S_Pos (16U)
4929#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos)
4930#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk
4931#define FDCAN_RXF1C_F1WM_Pos (24U)
4932#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
4933#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk
4934#define FDCAN_RXF1C_F1OM_Pos (31U)
4935#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos)
4936#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk
4938/***************** Bit definition for FDCAN_RXF1S register ********************/
4939#define FDCAN_RXF1S_F1FL_Pos (0U)
4940#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
4941#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
4942#define FDCAN_RXF1S_F1GI_Pos (8U)
4943#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
4944#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
4945#define FDCAN_RXF1S_F1PI_Pos (16U)
4946#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
4947#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
4948#define FDCAN_RXF1S_F1F_Pos (24U)
4949#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
4950#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
4951#define FDCAN_RXF1S_RF1L_Pos (25U)
4952#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
4953#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
4955/***************** Bit definition for FDCAN_RXF1A register ********************/
4956#define FDCAN_RXF1A_F1AI_Pos (0U)
4957#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
4958#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
4960/***************** Bit definition for FDCAN_RXESC register ********************/
4961#define FDCAN_RXESC_F0DS_Pos (0U)
4962#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos)
4963#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk
4964#define FDCAN_RXESC_F1DS_Pos (4U)
4965#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos)
4966#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk
4967#define FDCAN_RXESC_RBDS_Pos (8U)
4968#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos)
4969#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk
4971/***************** Bit definition for FDCAN_TXBC register *********************/
4972#define FDCAN_TXBC_TBSA_Pos (2U)
4973#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
4974#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk
4975#define FDCAN_TXBC_NDTB_Pos (16U)
4976#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
4977#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk
4978#define FDCAN_TXBC_TFQS_Pos (24U)
4979#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos)
4980#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk
4981#define FDCAN_TXBC_TFQM_Pos (30U)
4982#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
4983#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
4985/***************** Bit definition for FDCAN_TXFQS register *********************/
4986#define FDCAN_TXFQS_TFFL_Pos (0U)
4987#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
4988#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
4989#define FDCAN_TXFQS_TFGI_Pos (8U)
4990#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
4991#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
4992#define FDCAN_TXFQS_TFQPI_Pos (16U)
4993#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
4994#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
4995#define FDCAN_TXFQS_TFQF_Pos (21U)
4996#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
4997#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
4999/***************** Bit definition for FDCAN_TXESC register *********************/
5000#define FDCAN_TXESC_TBDS_Pos (0U)
5001#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos)
5002#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk
5004/***************** Bit definition for FDCAN_TXBRP register *********************/
5005#define FDCAN_TXBRP_TRP_Pos (0U)
5006#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
5007#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
5009/***************** Bit definition for FDCAN_TXBAR register *********************/
5010#define FDCAN_TXBAR_AR_Pos (0U)
5011#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
5012#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
5014/***************** Bit definition for FDCAN_TXBCR register *********************/
5015#define FDCAN_TXBCR_CR_Pos (0U)
5016#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
5017#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
5019/***************** Bit definition for FDCAN_TXBTO register *********************/
5020#define FDCAN_TXBTO_TO_Pos (0U)
5021#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
5022#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
5024/***************** Bit definition for FDCAN_TXBCF register *********************/
5025#define FDCAN_TXBCF_CF_Pos (0U)
5026#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
5027#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
5029/***************** Bit definition for FDCAN_TXBTIE register ********************/
5030#define FDCAN_TXBTIE_TIE_Pos (0U)
5031#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
5032#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
5034/***************** Bit definition for FDCAN_ TXBCIE register *******************/
5035#define FDCAN_TXBCIE_CFIE_Pos (0U)
5036#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
5037#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
5039/***************** Bit definition for FDCAN_TXEFC register *********************/
5040#define FDCAN_TXEFC_EFSA_Pos (2U)
5041#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
5042#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk
5043#define FDCAN_TXEFC_EFS_Pos (16U)
5044#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos)
5045#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk
5046#define FDCAN_TXEFC_EFWM_Pos (24U)
5047#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
5048#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk
5050/***************** Bit definition for FDCAN_TXEFS register *********************/
5051#define FDCAN_TXEFS_EFFL_Pos (0U)
5052#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
5053#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
5054#define FDCAN_TXEFS_EFGI_Pos (8U)
5055#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
5056#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
5057#define FDCAN_TXEFS_EFPI_Pos (16U)
5058#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
5059#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
5060#define FDCAN_TXEFS_EFF_Pos (24U)
5061#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
5062#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
5063#define FDCAN_TXEFS_TEFL_Pos (25U)
5064#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
5065#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
5067/***************** Bit definition for FDCAN_TXEFA register *********************/
5068#define FDCAN_TXEFA_EFAI_Pos (0U)
5069#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
5070#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
5072/***************** Bit definition for FDCAN_TTTMC register *********************/
5073#define FDCAN_TTTMC_TMSA_Pos (2U)
5074#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
5075#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk
5076#define FDCAN_TTTMC_TME_Pos (16U)
5077#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos)
5078#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk
5080/***************** Bit definition for FDCAN_TTRMC register *********************/
5081#define FDCAN_TTRMC_RID_Pos (0U)
5082#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
5083#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk
5084#define FDCAN_TTRMC_XTD_Pos (30U)
5085#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos)
5086#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk
5087#define FDCAN_TTRMC_RMPS_Pos (31U)
5088#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos)
5089#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk
5091/***************** Bit definition for FDCAN_TTOCF register *********************/
5092#define FDCAN_TTOCF_OM_Pos (0U)
5093#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos)
5094#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk
5095#define FDCAN_TTOCF_GEN_Pos (3U)
5096#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos)
5097#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk
5098#define FDCAN_TTOCF_TM_Pos (4U)
5099#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos)
5100#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk
5101#define FDCAN_TTOCF_LDSDL_Pos (5U)
5102#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
5103#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk
5104#define FDCAN_TTOCF_IRTO_Pos (8U)
5105#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
5106#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk
5107#define FDCAN_TTOCF_EECS_Pos (15U)
5108#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos)
5109#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk
5110#define FDCAN_TTOCF_AWL_Pos (16U)
5111#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos)
5112#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk
5113#define FDCAN_TTOCF_EGTF_Pos (24U)
5114#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos)
5115#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk
5116#define FDCAN_TTOCF_ECC_Pos (25U)
5117#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos)
5118#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk
5119#define FDCAN_TTOCF_EVTP_Pos (26U)
5120#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos)
5121#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk
5123/***************** Bit definition for FDCAN_TTMLM register *********************/
5124#define FDCAN_TTMLM_CCM_Pos (0U)
5125#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos)
5126#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk
5127#define FDCAN_TTMLM_CSS_Pos (6U)
5128#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos)
5129#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk
5130#define FDCAN_TTMLM_TXEW_Pos (8U)
5131#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos)
5132#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk
5133#define FDCAN_TTMLM_ENTT_Pos (16U)
5134#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
5135#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk
5137/***************** Bit definition for FDCAN_TURCF register *********************/
5138#define FDCAN_TURCF_NCL_Pos (0U)
5139#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
5140#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk
5141#define FDCAN_TURCF_DC_Pos (16U)
5142#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos)
5143#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk
5144#define FDCAN_TURCF_ELT_Pos (31U)
5145#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos)
5146#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk
5148/***************** Bit definition for FDCAN_TTOCN register ********************/
5149#define FDCAN_TTOCN_SGT_Pos (0U)
5150#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos)
5151#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk
5152#define FDCAN_TTOCN_ECS_Pos (1U)
5153#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos)
5154#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk
5155#define FDCAN_TTOCN_SWP_Pos (2U)
5156#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos)
5157#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk
5158#define FDCAN_TTOCN_SWS_Pos (3U)
5159#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos)
5160#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk
5161#define FDCAN_TTOCN_RTIE_Pos (5U)
5162#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos)
5163#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk
5164#define FDCAN_TTOCN_TMC_Pos (6U)
5165#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos)
5166#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk
5167#define FDCAN_TTOCN_TTIE_Pos (8U)
5168#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos)
5169#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk
5170#define FDCAN_TTOCN_GCS_Pos (9U)
5171#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos)
5172#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk
5173#define FDCAN_TTOCN_FGP_Pos (10U)
5174#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos)
5175#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk
5176#define FDCAN_TTOCN_TMG_Pos (11U)
5177#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos)
5178#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk
5179#define FDCAN_TTOCN_NIG_Pos (12U)
5180#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos)
5181#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk
5182#define FDCAN_TTOCN_ESCN_Pos (13U)
5183#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos)
5184#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk
5185#define FDCAN_TTOCN_LCKC_Pos (15U)
5186#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos)
5187#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk
5189/***************** Bit definition for FDCAN_TTGTP register ********************/
5190#define FDCAN_TTGTP_TP_Pos (0U)
5191#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
5192#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk
5193#define FDCAN_TTGTP_CTP_Pos (16U)
5194#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
5195#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk
5197/***************** Bit definition for FDCAN_TTTMK register ********************/
5198#define FDCAN_TTTMK_TM_Pos (0U)
5199#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
5200#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk
5201#define FDCAN_TTTMK_TICC_Pos (16U)
5202#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos)
5203#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk
5204#define FDCAN_TTTMK_LCKM_Pos (31U)
5205#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos)
5206#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk
5208/***************** Bit definition for FDCAN_TTIR register ********************/
5209#define FDCAN_TTIR_SBC_Pos (0U)
5210#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos)
5211#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk
5212#define FDCAN_TTIR_SMC_Pos (1U)
5213#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos)
5214#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk
5215#define FDCAN_TTIR_CSM_Pos (2U)
5216#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos)
5217#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk
5218#define FDCAN_TTIR_SOG_Pos (3U)
5219#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos)
5220#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk
5221#define FDCAN_TTIR_RTMI_Pos (4U)
5222#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos)
5223#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk
5224#define FDCAN_TTIR_TTMI_Pos (5U)
5225#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos)
5226#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk
5227#define FDCAN_TTIR_SWE_Pos (6U)
5228#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos)
5229#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk
5230#define FDCAN_TTIR_GTW_Pos (7U)
5231#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos)
5232#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
5233#define FDCAN_TTIR_GTD_Pos (8U)
5234#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos)
5235#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk
5236#define FDCAN_TTIR_GTE_Pos (9U)
5237#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos)
5238#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk
5239#define FDCAN_TTIR_TXU_Pos (10U)
5240#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos)
5241#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk
5242#define FDCAN_TTIR_TXO_Pos (11U)
5243#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos)
5244#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk
5245#define FDCAN_TTIR_SE1_Pos (12U)
5246#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos)
5247#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk
5248#define FDCAN_TTIR_SE2_Pos (13U)
5249#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos)
5250#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk
5251#define FDCAN_TTIR_ELC_Pos (14U)
5252#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos)
5253#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk
5254#define FDCAN_TTIR_IWT_Pos (15U)
5255#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos)
5256#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk
5257#define FDCAN_TTIR_WT_Pos (16U)
5258#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos)
5259#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk
5260#define FDCAN_TTIR_AW_Pos (17U)
5261#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos)
5262#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk
5263#define FDCAN_TTIR_CER_Pos (18U)
5264#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos)
5265#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk
5267/***************** Bit definition for FDCAN_TTIE register ********************/
5268#define FDCAN_TTIE_SBCE_Pos (0U)
5269#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos)
5270#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk
5271#define FDCAN_TTIE_SMCE_Pos (1U)
5272#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos)
5273#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk
5274#define FDCAN_TTIE_CSME_Pos (2U)
5275#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos)
5276#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk
5277#define FDCAN_TTIE_SOGE_Pos (3U)
5278#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos)
5279#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk
5280#define FDCAN_TTIE_RTMIE_Pos (4U)
5281#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos)
5282#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk
5283#define FDCAN_TTIE_TTMIE_Pos (5U)
5284#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos)
5285#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk
5286#define FDCAN_TTIE_SWEE_Pos (6U)
5287#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos)
5288#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk
5289#define FDCAN_TTIE_GTWE_Pos (7U)
5290#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos)
5291#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk
5292#define FDCAN_TTIE_GTDE_Pos (8U)
5293#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos)
5294#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk
5295#define FDCAN_TTIE_GTEE_Pos (9U)
5296#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos)
5297#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk
5298#define FDCAN_TTIE_TXUE_Pos (10U)
5299#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos)
5300#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk
5301#define FDCAN_TTIE_TXOE_Pos (11U)
5302#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos)
5303#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk
5304#define FDCAN_TTIE_SE1E_Pos (12U)
5305#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos)
5306#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk
5307#define FDCAN_TTIE_SE2E_Pos (13U)
5308#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos)
5309#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk
5310#define FDCAN_TTIE_ELCE_Pos (14U)
5311#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos)
5312#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk
5313#define FDCAN_TTIE_IWTE_Pos (15U)
5314#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos)
5315#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk
5316#define FDCAN_TTIE_WTE_Pos (16U)
5317#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos)
5318#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk
5319#define FDCAN_TTIE_AWE_Pos (17U)
5320#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos)
5321#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk
5322#define FDCAN_TTIE_CERE_Pos (18U)
5323#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos)
5324#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk
5326/***************** Bit definition for FDCAN_TTILS register ********************/
5327#define FDCAN_TTILS_SBCS_Pos (0U)
5328#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos)
5329#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk
5330#define FDCAN_TTILS_SMCS_Pos (1U)
5331#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos)
5332#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk
5333#define FDCAN_TTILS_CSMS_Pos (2U)
5334#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos)
5335#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk
5336#define FDCAN_TTILS_SOGS_Pos (3U)
5337#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos)
5338#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk
5339#define FDCAN_TTILS_RTMIS_Pos (4U)
5340#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos)
5341#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk
5342#define FDCAN_TTILS_TTMIS_Pos (5U)
5343#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos)
5344#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk
5345#define FDCAN_TTILS_SWES_Pos (6U)
5346#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos)
5347#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk
5348#define FDCAN_TTILS_GTWS_Pos (7U)
5349#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos)
5350#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk
5351#define FDCAN_TTILS_GTDS_Pos (8U)
5352#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos)
5353#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk
5354#define FDCAN_TTILS_GTES_Pos (9U)
5355#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos)
5356#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk
5357#define FDCAN_TTILS_TXUS_Pos (10U)
5358#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos)
5359#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk
5360#define FDCAN_TTILS_TXOS_Pos (11U)
5361#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos)
5362#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk
5363#define FDCAN_TTILS_SE1S_Pos (12U)
5364#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos)
5365#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk
5366#define FDCAN_TTILS_SE2S_Pos (13U)
5367#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos)
5368#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk
5369#define FDCAN_TTILS_ELCS_Pos (14U)
5370#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos)
5371#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk
5372#define FDCAN_TTILS_IWTS_Pos (15U)
5373#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos)
5374#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk
5375#define FDCAN_TTILS_WTS_Pos (16U)
5376#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos)
5377#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk
5378#define FDCAN_TTILS_AWS_Pos (17U)
5379#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos)
5380#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk
5381#define FDCAN_TTILS_CERS_Pos (18U)
5382#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos)
5383#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk
5385/***************** Bit definition for FDCAN_TTOST register ********************/
5386#define FDCAN_TTOST_EL_Pos (0U)
5387#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos)
5388#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk
5389#define FDCAN_TTOST_MS_Pos (2U)
5390#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos)
5391#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk
5392#define FDCAN_TTOST_SYS_Pos (4U)
5393#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos)
5394#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk
5395#define FDCAN_TTOST_QGTP_Pos (6U)
5396#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos)
5397#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk
5398#define FDCAN_TTOST_QCS_Pos (7U)
5399#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos)
5400#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk
5401#define FDCAN_TTOST_RTO_Pos (8U)
5402#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos)
5403#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk
5404#define FDCAN_TTOST_WGTD_Pos (22U)
5405#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos)
5406#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk
5407#define FDCAN_TTOST_GFI_Pos (23U)
5408#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos)
5409#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk
5410#define FDCAN_TTOST_TMP_Pos (24U)
5411#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos)
5412#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk
5413#define FDCAN_TTOST_GSI_Pos (27U)
5414#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos)
5415#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk
5416#define FDCAN_TTOST_WFE_Pos (28U)
5417#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos)
5418#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk
5419#define FDCAN_TTOST_AWE_Pos (29U)
5420#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos)
5421#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk
5422#define FDCAN_TTOST_WECS_Pos (30U)
5423#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos)
5424#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk
5425#define FDCAN_TTOST_SPL_Pos (31U)
5426#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos)
5427#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk
5429/***************** Bit definition for FDCAN_TURNA register ********************/
5430#define FDCAN_TURNA_NAV_Pos (0U)
5431#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
5432#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk
5434/***************** Bit definition for FDCAN_TTLGT register ********************/
5435#define FDCAN_TTLGT_LT_Pos (0U)
5436#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
5437#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk
5438#define FDCAN_TTLGT_GT_Pos (16U)
5439#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
5440#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk
5442/***************** Bit definition for FDCAN_TTCTC register ********************/
5443#define FDCAN_TTCTC_CT_Pos (0U)
5444#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
5445#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk
5446#define FDCAN_TTCTC_CC_Pos (16U)
5447#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos)
5448#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk
5450/***************** Bit definition for FDCAN_TTCPT register ********************/
5451#define FDCAN_TTCPT_CCV_Pos (0U)
5452#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos)
5453#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk
5454#define FDCAN_TTCPT_SWV_Pos (16U)
5455#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
5456#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk
5458/***************** Bit definition for FDCAN_TTCSM register ********************/
5459#define FDCAN_TTCSM_CSM_Pos (0U)
5460#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
5461#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk
5463/***************** Bit definition for FDCAN_TTTS register *********************/
5464#define FDCAN_TTTS_SWTSEL_Pos (0U)
5465#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
5466#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk
5467#define FDCAN_TTTS_EVTSEL_Pos (4U)
5468#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
5469#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk
5471/********************************************************************************/
5472/* */
5473/* FDCANCCU (Clock Calibration unit) */
5474/* */
5475/********************************************************************************/
5476
5477/***************** Bit definition for FDCANCCU_CREL register ******************/
5478#define FDCANCCU_CREL_DAY_Pos (0U)
5479#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos)
5480#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk
5481#define FDCANCCU_CREL_MON_Pos (8U)
5482#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos)
5483#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk
5484#define FDCANCCU_CREL_YEAR_Pos (16U)
5485#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos)
5486#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk
5487#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5488#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
5489#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk
5490#define FDCANCCU_CREL_STEP_Pos (24U)
5491#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos)
5492#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk
5493#define FDCANCCU_CREL_REL_Pos (28U)
5494#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos)
5495#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk
5497/***************** Bit definition for FDCANCCU_CCFG register ******************/
5498#define FDCANCCU_CCFG_TQBT_Pos (0U)
5499#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
5500#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk
5501#define FDCANCCU_CCFG_BCC_Pos (6U)
5502#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos)
5503#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk
5504#define FDCANCCU_CCFG_CFL_Pos (7U)
5505#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos)
5506#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk
5507#define FDCANCCU_CCFG_OCPM_Pos (8U)
5508#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
5509#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk
5510#define FDCANCCU_CCFG_CDIV_Pos (16U)
5511#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
5512#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk
5513#define FDCANCCU_CCFG_SWR_Pos (31U)
5514#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos)
5515#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk
5517/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5518#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5519#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
5520#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk
5521#define FDCANCCU_CSTAT_TQC_Pos (18U)
5522#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
5523#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk
5524#define FDCANCCU_CSTAT_CALS_Pos (30U)
5525#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
5526#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk
5528/****************** Bit definition for FDCANCCU_CWD register ******************/
5529#define FDCANCCU_CWD_WDC_Pos (0U)
5530#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
5531#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk
5532#define FDCANCCU_CWD_WDV_Pos (16U)
5533#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
5534#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk
5536/****************** Bit definition for FDCANCCU_IR register *******************/
5537#define FDCANCCU_IR_CWE_Pos (0U)
5538#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos)
5539#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk
5540#define FDCANCCU_IR_CSC_Pos (1U)
5541#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos)
5542#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk
5544/****************** Bit definition for FDCANCCU_IE register *******************/
5545#define FDCANCCU_IE_CWEE_Pos (0U)
5546#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos)
5547#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk
5548#define FDCANCCU_IE_CSCE_Pos (1U)
5549#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos)
5550#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk
5552/******************************************************************************/
5553/* */
5554/* HDMI-CEC (CEC) */
5555/* */
5556/******************************************************************************/
5557
5558/******************* Bit definition for CEC_CR register *********************/
5559#define CEC_CR_CECEN_Pos (0U)
5560#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5561#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5562#define CEC_CR_TXSOM_Pos (1U)
5563#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5564#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5565#define CEC_CR_TXEOM_Pos (2U)
5566#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5567#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5569/******************* Bit definition for CEC_CFGR register *******************/
5570#define CEC_CFGR_SFT_Pos (0U)
5571#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5572#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5573#define CEC_CFGR_RXTOL_Pos (3U)
5574#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5575#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5576#define CEC_CFGR_BRESTP_Pos (4U)
5577#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5578#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5579#define CEC_CFGR_BREGEN_Pos (5U)
5580#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5581#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5582#define CEC_CFGR_LBPEGEN_Pos (6U)
5583#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5584#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5585#define CEC_CFGR_SFTOPT_Pos (8U)
5586#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5587#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5588#define CEC_CFGR_BRDNOGEN_Pos (7U)
5589#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5590#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5591#define CEC_CFGR_OAR_Pos (16U)
5592#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5593#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5594#define CEC_CFGR_LSTN_Pos (31U)
5595#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5596#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5598/******************* Bit definition for CEC_TXDR register *******************/
5599#define CEC_TXDR_TXD_Pos (0U)
5600#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5601#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5603/******************* Bit definition for CEC_RXDR register *******************/
5604#define CEC_RXDR_RXD_Pos (0U)
5605#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5606#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5608/******************* Bit definition for CEC_ISR register ********************/
5609#define CEC_ISR_RXBR_Pos (0U)
5610#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5611#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5612#define CEC_ISR_RXEND_Pos (1U)
5613#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5614#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5615#define CEC_ISR_RXOVR_Pos (2U)
5616#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5617#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5618#define CEC_ISR_BRE_Pos (3U)
5619#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5620#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5621#define CEC_ISR_SBPE_Pos (4U)
5622#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5623#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5624#define CEC_ISR_LBPE_Pos (5U)
5625#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5626#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5627#define CEC_ISR_RXACKE_Pos (6U)
5628#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5629#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5630#define CEC_ISR_ARBLST_Pos (7U)
5631#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5632#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5633#define CEC_ISR_TXBR_Pos (8U)
5634#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5635#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5636#define CEC_ISR_TXEND_Pos (9U)
5637#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5638#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5639#define CEC_ISR_TXUDR_Pos (10U)
5640#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5641#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5642#define CEC_ISR_TXERR_Pos (11U)
5643#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5644#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5645#define CEC_ISR_TXACKE_Pos (12U)
5646#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5647#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5649/******************* Bit definition for CEC_IER register ********************/
5650#define CEC_IER_RXBRIE_Pos (0U)
5651#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5652#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5653#define CEC_IER_RXENDIE_Pos (1U)
5654#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5655#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5656#define CEC_IER_RXOVRIE_Pos (2U)
5657#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5658#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5659#define CEC_IER_BREIE_Pos (3U)
5660#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5661#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5662#define CEC_IER_SBPEIE_Pos (4U)
5663#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5664#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5665#define CEC_IER_LBPEIE_Pos (5U)
5666#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5667#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5668#define CEC_IER_RXACKEIE_Pos (6U)
5669#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5670#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5671#define CEC_IER_ARBLSTIE_Pos (7U)
5672#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5673#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5674#define CEC_IER_TXBRIE_Pos (8U)
5675#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5676#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5677#define CEC_IER_TXENDIE_Pos (9U)
5678#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5679#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5680#define CEC_IER_TXUDRIE_Pos (10U)
5681#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5682#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5683#define CEC_IER_TXERRIE_Pos (11U)
5684#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5685#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5686#define CEC_IER_TXACKEIE_Pos (12U)
5687#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5688#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5690/******************************************************************************/
5691/* */
5692/* CRC calculation unit */
5693/* */
5694/******************************************************************************/
5695/******************* Bit definition for CRC_DR register *********************/
5696#define CRC_DR_DR_Pos (0U)
5697#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5698#define CRC_DR_DR CRC_DR_DR_Msk
5700/******************* Bit definition for CRC_IDR register ********************/
5701#define CRC_IDR_IDR_Pos (0U)
5702#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
5703#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5705/******************** Bit definition for CRC_CR register ********************/
5706#define CRC_CR_RESET_Pos (0U)
5707#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5708#define CRC_CR_RESET CRC_CR_RESET_Msk
5709#define CRC_CR_POLYSIZE_Pos (3U)
5710#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5711#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5712#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5713#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5714#define CRC_CR_REV_IN_Pos (5U)
5715#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5716#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5717#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5718#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5719#define CRC_CR_REV_OUT_Pos (7U)
5720#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5721#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5723/******************* Bit definition for CRC_INIT register *******************/
5724#define CRC_INIT_INIT_Pos (0U)
5725#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5726#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5728/******************* Bit definition for CRC_POL register ********************/
5729#define CRC_POL_POL_Pos (0U)
5730#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5731#define CRC_POL_POL CRC_POL_POL_Msk
5733/******************************************************************************/
5734/* */
5735/* CRS Clock Recovery System */
5736/******************************************************************************/
5737
5738/******************* Bit definition for CRS_CR register *********************/
5739#define CRS_CR_SYNCOKIE_Pos (0U)
5740#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5741#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5742#define CRS_CR_SYNCWARNIE_Pos (1U)
5743#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5744#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5745#define CRS_CR_ERRIE_Pos (2U)
5746#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5747#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5748#define CRS_CR_ESYNCIE_Pos (3U)
5749#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5750#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5751#define CRS_CR_CEN_Pos (5U)
5752#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5753#define CRS_CR_CEN CRS_CR_CEN_Msk
5754#define CRS_CR_AUTOTRIMEN_Pos (6U)
5755#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5756#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5757#define CRS_CR_SWSYNC_Pos (7U)
5758#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5759#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5760#define CRS_CR_TRIM_Pos (8U)
5761#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5762#define CRS_CR_TRIM CRS_CR_TRIM_Msk
5764/******************* Bit definition for CRS_CFGR register *********************/
5765#define CRS_CFGR_RELOAD_Pos (0U)
5766#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5767#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5768#define CRS_CFGR_FELIM_Pos (16U)
5769#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5770#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5772#define CRS_CFGR_SYNCDIV_Pos (24U)
5773#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5774#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5775#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5776#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5777#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5779#define CRS_CFGR_SYNCSRC_Pos (28U)
5780#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5781#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5782#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5783#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5785#define CRS_CFGR_SYNCPOL_Pos (31U)
5786#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5787#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5789/******************* Bit definition for CRS_ISR register *********************/
5790#define CRS_ISR_SYNCOKF_Pos (0U)
5791#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5792#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5793#define CRS_ISR_SYNCWARNF_Pos (1U)
5794#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5795#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5796#define CRS_ISR_ERRF_Pos (2U)
5797#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5798#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5799#define CRS_ISR_ESYNCF_Pos (3U)
5800#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5801#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5802#define CRS_ISR_SYNCERR_Pos (8U)
5803#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
5804#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
5805#define CRS_ISR_SYNCMISS_Pos (9U)
5806#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
5807#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
5808#define CRS_ISR_TRIMOVF_Pos (10U)
5809#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
5810#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
5811#define CRS_ISR_FEDIR_Pos (15U)
5812#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
5813#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
5814#define CRS_ISR_FECAP_Pos (16U)
5815#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
5816#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
5818/******************* Bit definition for CRS_ICR register *********************/
5819#define CRS_ICR_SYNCOKC_Pos (0U)
5820#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
5821#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
5822#define CRS_ICR_SYNCWARNC_Pos (1U)
5823#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
5824#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
5825#define CRS_ICR_ERRC_Pos (2U)
5826#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
5827#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
5828#define CRS_ICR_ESYNCC_Pos (3U)
5829#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
5830#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
5832/******************************************************************************/
5833/* */
5834/* Digital to Analog Converter */
5835/* */
5836/******************************************************************************/
5837/******************** Bit definition for DAC_CR register ********************/
5838#define DAC_CR_EN1_Pos (0U)
5839#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5840#define DAC_CR_EN1 DAC_CR_EN1_Msk
5841#define DAC_CR_TEN1_Pos (1U)
5842#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5843#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5845#define DAC_CR_TSEL1_Pos (2U)
5846#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
5847#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5848#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5849#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5850#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5851#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
5854#define DAC_CR_WAVE1_Pos (6U)
5855#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5856#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5857#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5858#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5860#define DAC_CR_MAMP1_Pos (8U)
5861#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5862#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5863#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5864#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5865#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5866#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5868#define DAC_CR_DMAEN1_Pos (12U)
5869#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5870#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5871#define DAC_CR_DMAUDRIE1_Pos (13U)
5872#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5873#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5874#define DAC_CR_CEN1_Pos (14U)
5875#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
5876#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
5878#define DAC_CR_EN2_Pos (16U)
5879#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5880#define DAC_CR_EN2 DAC_CR_EN2_Msk
5881#define DAC_CR_TEN2_Pos (17U)
5882#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5883#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5885#define DAC_CR_TSEL2_Pos (18U)
5886#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
5887#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5888#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5889#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5890#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5891#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
5894#define DAC_CR_WAVE2_Pos (22U)
5895#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5896#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5897#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5898#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5900#define DAC_CR_MAMP2_Pos (24U)
5901#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5902#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5903#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5904#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5905#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5906#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5908#define DAC_CR_DMAEN2_Pos (28U)
5909#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5910#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5911#define DAC_CR_DMAUDRIE2_Pos (29U)
5912#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5913#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5914#define DAC_CR_CEN2_Pos (30U)
5915#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
5916#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
5918/***************** Bit definition for DAC_SWTRIGR register ******************/
5919#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5920#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5921#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5922#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5923#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5924#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5926/***************** Bit definition for DAC_DHR12R1 register ******************/
5927#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5928#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5929#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5931/***************** Bit definition for DAC_DHR12L1 register ******************/
5932#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5933#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5934#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5936/****************** Bit definition for DAC_DHR8R1 register ******************/
5937#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5938#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5939#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5941/***************** Bit definition for DAC_DHR12R2 register ******************/
5942#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5943#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5944#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5946/***************** Bit definition for DAC_DHR12L2 register ******************/
5947#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5948#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5949#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5951/****************** Bit definition for DAC_DHR8R2 register ******************/
5952#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5953#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5954#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5956/***************** Bit definition for DAC_DHR12RD register ******************/
5957#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5958#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5959#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5960#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5961#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5962#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5964/***************** Bit definition for DAC_DHR12LD register ******************/
5965#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5966#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5967#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5968#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5969#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5970#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5972/****************** Bit definition for DAC_DHR8RD register ******************/
5973#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5974#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5975#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5976#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5977#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5978#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5980/******************* Bit definition for DAC_DOR1 register *******************/
5981#define DAC_DOR1_DACC1DOR_Pos (0U)
5982#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5983#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5985/******************* Bit definition for DAC_DOR2 register *******************/
5986#define DAC_DOR2_DACC2DOR_Pos (0U)
5987#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5988#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5990/******************** Bit definition for DAC_SR register ********************/
5991#define DAC_SR_DMAUDR1_Pos (13U)
5992#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5993#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5994#define DAC_SR_CAL_FLAG1_Pos (14U)
5995#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
5996#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
5997#define DAC_SR_BWST1_Pos (15U)
5998#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos)
5999#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
6001#define DAC_SR_DMAUDR2_Pos (29U)
6002#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
6003#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
6004#define DAC_SR_CAL_FLAG2_Pos (30U)
6005#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
6006#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
6007#define DAC_SR_BWST2_Pos (31U)
6008#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
6009#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
6011/******************* Bit definition for DAC_CCR register ********************/
6012#define DAC_CCR_OTRIM1_Pos (0U)
6013#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
6014#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
6015#define DAC_CCR_OTRIM2_Pos (16U)
6016#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
6017#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
6019/******************* Bit definition for DAC_MCR register *******************/
6020#define DAC_MCR_MODE1_Pos (0U)
6021#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
6022#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
6023#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
6024#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
6025#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
6027#define DAC_MCR_MODE2_Pos (16U)
6028#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
6029#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
6030#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
6031#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
6032#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
6034/****************** Bit definition for DAC_SHSR1 register ******************/
6035#define DAC_SHSR1_TSAMPLE1_Pos (0U)
6036#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
6037#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
6039/****************** Bit definition for DAC_SHSR2 register ******************/
6040#define DAC_SHSR2_TSAMPLE2_Pos (0U)
6041#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
6042#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
6044/****************** Bit definition for DAC_SHHR register ******************/
6045#define DAC_SHHR_THOLD1_Pos (0U)
6046#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
6047#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
6048#define DAC_SHHR_THOLD2_Pos (16U)
6049#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
6050#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
6052/****************** Bit definition for DAC_SHRR register ******************/
6053#define DAC_SHRR_TREFRESH1_Pos (0U)
6054#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
6055#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
6056#define DAC_SHRR_TREFRESH2_Pos (16U)
6057#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
6058#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
6060/******************************************************************************/
6061/* */
6062/* DCMI */
6063/* */
6064/******************************************************************************/
6065/******************** Bits definition for DCMI_CR register ******************/
6066#define DCMI_CR_CAPTURE_Pos (0U)
6067#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
6068#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6069#define DCMI_CR_CM_Pos (1U)
6070#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
6071#define DCMI_CR_CM DCMI_CR_CM_Msk
6072#define DCMI_CR_CROP_Pos (2U)
6073#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
6074#define DCMI_CR_CROP DCMI_CR_CROP_Msk
6075#define DCMI_CR_JPEG_Pos (3U)
6076#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
6077#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6078#define DCMI_CR_ESS_Pos (4U)
6079#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
6080#define DCMI_CR_ESS DCMI_CR_ESS_Msk
6081#define DCMI_CR_PCKPOL_Pos (5U)
6082#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
6083#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6084#define DCMI_CR_HSPOL_Pos (6U)
6085#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
6086#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6087#define DCMI_CR_VSPOL_Pos (7U)
6088#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
6089#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6090#define DCMI_CR_FCRC_0 (0x00000100U)
6091#define DCMI_CR_FCRC_1 (0x00000200U)
6092#define DCMI_CR_EDM_0 (0x00000400U)
6093#define DCMI_CR_EDM_1 (0x00000800U)
6094#define DCMI_CR_CRE_Pos (12U)
6095#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
6096#define DCMI_CR_CRE DCMI_CR_CRE_Msk
6097#define DCMI_CR_ENABLE_Pos (14U)
6098#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
6099#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6100#define DCMI_CR_BSM_Pos (16U)
6101#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
6102#define DCMI_CR_BSM DCMI_CR_BSM_Msk
6103#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
6104#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
6105#define DCMI_CR_OEBS_Pos (18U)
6106#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
6107#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6108#define DCMI_CR_LSM_Pos (19U)
6109#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
6110#define DCMI_CR_LSM DCMI_CR_LSM_Msk
6111#define DCMI_CR_OELS_Pos (20U)
6112#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
6113#define DCMI_CR_OELS DCMI_CR_OELS_Msk
6114
6115/******************** Bits definition for DCMI_SR register ******************/
6116#define DCMI_SR_HSYNC_Pos (0U)
6117#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
6118#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6119#define DCMI_SR_VSYNC_Pos (1U)
6120#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
6121#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6122#define DCMI_SR_FNE_Pos (2U)
6123#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
6124#define DCMI_SR_FNE DCMI_SR_FNE_Msk
6125
6126/******************** Bits definition for DCMI_RIS register ****************/
6127#define DCMI_RIS_FRAME_RIS_Pos (0U)
6128#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
6129#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6130#define DCMI_RIS_OVR_RIS_Pos (1U)
6131#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
6132#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6133#define DCMI_RIS_ERR_RIS_Pos (2U)
6134#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
6135#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6136#define DCMI_RIS_VSYNC_RIS_Pos (3U)
6137#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
6138#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6139#define DCMI_RIS_LINE_RIS_Pos (4U)
6140#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
6141#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6142
6143/******************** Bits definition for DCMI_IER register *****************/
6144#define DCMI_IER_FRAME_IE_Pos (0U)
6145#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
6146#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6147#define DCMI_IER_OVR_IE_Pos (1U)
6148#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
6149#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6150#define DCMI_IER_ERR_IE_Pos (2U)
6151#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
6152#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6153#define DCMI_IER_VSYNC_IE_Pos (3U)
6154#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
6155#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6156#define DCMI_IER_LINE_IE_Pos (4U)
6157#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
6158#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6159
6160
6161/******************** Bits definition for DCMI_MIS register *****************/
6162#define DCMI_MIS_FRAME_MIS_Pos (0U)
6163#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
6164#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6165#define DCMI_MIS_OVR_MIS_Pos (1U)
6166#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
6167#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6168#define DCMI_MIS_ERR_MIS_Pos (2U)
6169#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
6170#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6171#define DCMI_MIS_VSYNC_MIS_Pos (3U)
6172#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
6173#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6174#define DCMI_MIS_LINE_MIS_Pos (4U)
6175#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
6176#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6177
6178
6179/******************** Bits definition for DCMI_ICR register *****************/
6180#define DCMI_ICR_FRAME_ISC_Pos (0U)
6181#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
6182#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6183#define DCMI_ICR_OVR_ISC_Pos (1U)
6184#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
6185#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6186#define DCMI_ICR_ERR_ISC_Pos (2U)
6187#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
6188#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6189#define DCMI_ICR_VSYNC_ISC_Pos (3U)
6190#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
6191#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6192#define DCMI_ICR_LINE_ISC_Pos (4U)
6193#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
6194#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6195
6196
6197/******************** Bits definition for DCMI_ESCR register ******************/
6198#define DCMI_ESCR_FSC_Pos (0U)
6199#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6200#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6201#define DCMI_ESCR_LSC_Pos (8U)
6202#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6203#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6204#define DCMI_ESCR_LEC_Pos (16U)
6205#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6206#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6207#define DCMI_ESCR_FEC_Pos (24U)
6208#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6209#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6210
6211/******************** Bits definition for DCMI_ESUR register ******************/
6212#define DCMI_ESUR_FSU_Pos (0U)
6213#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6214#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6215#define DCMI_ESUR_LSU_Pos (8U)
6216#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6217#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6218#define DCMI_ESUR_LEU_Pos (16U)
6219#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6220#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6221#define DCMI_ESUR_FEU_Pos (24U)
6222#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6223#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6224
6225/******************** Bits definition for DCMI_CWSTRT register ******************/
6226#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6227#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6228#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6229#define DCMI_CWSTRT_VST_Pos (16U)
6230#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6231#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6232
6233/******************** Bits definition for DCMI_CWSIZE register ******************/
6234#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6235#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6236#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6237#define DCMI_CWSIZE_VLINE_Pos (16U)
6238#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6239#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6240
6241/******************** Bits definition for DCMI_DR register ******************/
6242#define DCMI_DR_BYTE0_Pos (0U)
6243#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6244#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6245#define DCMI_DR_BYTE1_Pos (8U)
6246#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6247#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6248#define DCMI_DR_BYTE2_Pos (16U)
6249#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6250#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6251#define DCMI_DR_BYTE3_Pos (24U)
6252#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6253#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6254
6255/******************************************************************************/
6256/* */
6257/* Digital Filter for Sigma Delta Modulators */
6258/* */
6259/******************************************************************************/
6260
6261/**************** DFSDM channel configuration registers ********************/
6262
6263/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6264#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6265#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6266#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6267#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6268#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6269#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6270#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6271#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6272#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6273#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6274#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6275#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6276#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6277#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6278#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6279#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6280#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6281#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6282#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6283#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6284#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6285#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6286#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6287#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6288#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6289#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6290#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6291#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6292#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6293#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6294#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6295#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6296#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6297#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6298#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6299#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6300#define DFSDM_CHCFGR1_SITP_Pos (0U)
6301#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6302#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6303#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6304#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6306/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6307#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6308#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6309#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6310#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6311#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6312#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6314/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6315#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6316#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6317#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6318#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6319#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6320#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6321#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6322#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6323#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6324#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6325#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6326#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6327#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6328#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6330/**************** Bit definition for DFSDM_CHWDATR register *******************/
6331#define DFSDM_CHWDATR_WDATA_Pos (0U)
6332#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6333#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6335/**************** Bit definition for DFSDM_CHDATINR register *****************/
6336#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6337#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6338#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6339#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6340#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6341#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6343/************************ DFSDM module registers ****************************/
6344
6345/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6346#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6347#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6348#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6349#define DFSDM_FLTCR1_FAST_Pos (29U)
6350#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6351#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6352#define DFSDM_FLTCR1_RCH_Pos (24U)
6353#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6354#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6355#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6356#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6357#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6358#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6359#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6360#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6361#define DFSDM_FLTCR1_RCONT_Pos (18U)
6362#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6363#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6364#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6365#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6366#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6367#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6368#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6369#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6370#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6371#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6372#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6373#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6374#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6375#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6376#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6377#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6378#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6379#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6381#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6382#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6383#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6384#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6385#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6386#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6387#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6388#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6389#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6390#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6391#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6392#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6393#define DFSDM_FLTCR1_DFEN_Pos (0U)
6394#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6395#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6397/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6398#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6399#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6400#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6401#define DFSDM_FLTCR2_EXCH_Pos (8U)
6402#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6403#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6404#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6405#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6406#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6407#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6408#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6409#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6410#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6411#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6412#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6413#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6414#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6415#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6416#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6417#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6418#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6419#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6420#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6421#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6422#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6423#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6424#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6426/******************** Bit definition for DFSDM_FLTISR register *******************/
6427#define DFSDM_FLTISR_SCDF_Pos (24U)
6428#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6429#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6430#define DFSDM_FLTISR_CKABF_Pos (16U)
6431#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6432#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6433#define DFSDM_FLTISR_RCIP_Pos (14U)
6434#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6435#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6436#define DFSDM_FLTISR_JCIP_Pos (13U)
6437#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6438#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6439#define DFSDM_FLTISR_AWDF_Pos (4U)
6440#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6441#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6442#define DFSDM_FLTISR_ROVRF_Pos (3U)
6443#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6444#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6445#define DFSDM_FLTISR_JOVRF_Pos (2U)
6446#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6447#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6448#define DFSDM_FLTISR_REOCF_Pos (1U)
6449#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6450#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6451#define DFSDM_FLTISR_JEOCF_Pos (0U)
6452#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6453#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6455/******************** Bit definition for DFSDM_FLTICR register *******************/
6456#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6457#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6458#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6459#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6460#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6461#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6462#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6463#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6464#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6465#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6466#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6467#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6469/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6470#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6471#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6472#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6474/******************** Bit definition for DFSDM_FLTFCR register *******************/
6475#define DFSDM_FLTFCR_FORD_Pos (29U)
6476#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6477#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6478#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6479#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6480#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6481#define DFSDM_FLTFCR_FOSR_Pos (16U)
6482#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6483#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6484#define DFSDM_FLTFCR_IOSR_Pos (0U)
6485#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6486#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6488/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6489#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6490#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6491#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6492#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6493#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6494#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6496/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6497#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6498#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6499#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6500#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6501#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6502#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6503#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6504#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6505#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6507/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6508#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6509#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6510#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6511#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6512#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6513#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6515/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6516#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6517#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6518#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6519#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6520#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6521#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6523/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6524#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6525#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6526#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6527#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6528#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6529#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6531/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6532#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6533#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6534#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6535#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6536#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6537#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6539/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6540#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6541#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6542#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6543#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6544#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6545#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6547/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6548#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6549#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6550#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6551#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6552#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6553#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6555/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6556#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6557#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6558#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6560/******************************************************************************/
6561/* */
6562/* BDMA Controller */
6563/* */
6564/******************************************************************************/
6565
6566/******************* Bit definition for BDMA_ISR register ********************/
6567#define BDMA_ISR_GIF0_Pos (0U)
6568#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos)
6569#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk
6570#define BDMA_ISR_TCIF0_Pos (1U)
6571#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos)
6572#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk
6573#define BDMA_ISR_HTIF0_Pos (2U)
6574#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos)
6575#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk
6576#define BDMA_ISR_TEIF0_Pos (3U)
6577#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos)
6578#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk
6579#define BDMA_ISR_GIF1_Pos (4U)
6580#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos)
6581#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk
6582#define BDMA_ISR_TCIF1_Pos (5U)
6583#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos)
6584#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk
6585#define BDMA_ISR_HTIF1_Pos (6U)
6586#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos)
6587#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk
6588#define BDMA_ISR_TEIF1_Pos (7U)
6589#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos)
6590#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk
6591#define BDMA_ISR_GIF2_Pos (8U)
6592#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos)
6593#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk
6594#define BDMA_ISR_TCIF2_Pos (9U)
6595#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos)
6596#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk
6597#define BDMA_ISR_HTIF2_Pos (10U)
6598#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos)
6599#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk
6600#define BDMA_ISR_TEIF2_Pos (11U)
6601#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos)
6602#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk
6603#define BDMA_ISR_GIF3_Pos (12U)
6604#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos)
6605#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk
6606#define BDMA_ISR_TCIF3_Pos (13U)
6607#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos)
6608#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk
6609#define BDMA_ISR_HTIF3_Pos (14U)
6610#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos)
6611#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk
6612#define BDMA_ISR_TEIF3_Pos (15U)
6613#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos)
6614#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk
6615#define BDMA_ISR_GIF4_Pos (16U)
6616#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos)
6617#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk
6618#define BDMA_ISR_TCIF4_Pos (17U)
6619#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos)
6620#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk
6621#define BDMA_ISR_HTIF4_Pos (18U)
6622#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos)
6623#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk
6624#define BDMA_ISR_TEIF4_Pos (19U)
6625#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos)
6626#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk
6627#define BDMA_ISR_GIF5_Pos (20U)
6628#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos)
6629#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk
6630#define BDMA_ISR_TCIF5_Pos (21U)
6631#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos)
6632#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk
6633#define BDMA_ISR_HTIF5_Pos (22U)
6634#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos)
6635#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk
6636#define BDMA_ISR_TEIF5_Pos (23U)
6637#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos)
6638#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk
6639#define BDMA_ISR_GIF6_Pos (24U)
6640#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
6641#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk
6642#define BDMA_ISR_TCIF6_Pos (25U)
6643#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos)
6644#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk
6645#define BDMA_ISR_HTIF6_Pos (26U)
6646#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos)
6647#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk
6648#define BDMA_ISR_TEIF6_Pos (27U)
6649#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos)
6650#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk
6651#define BDMA_ISR_GIF7_Pos (28U)
6652#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos)
6653#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk
6654#define BDMA_ISR_TCIF7_Pos (29U)
6655#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos)
6656#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk
6657#define BDMA_ISR_HTIF7_Pos (30U)
6658#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos)
6659#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk
6660#define BDMA_ISR_TEIF7_Pos (31U)
6661#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos)
6662#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk
6664/******************* Bit definition for BDMA_IFCR register *******************/
6665#define BDMA_IFCR_CGIF0_Pos (0U)
6666#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos)
6667#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk
6668#define BDMA_IFCR_CTCIF0_Pos (1U)
6669#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos)
6670#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk
6671#define BDMA_IFCR_CHTIF0_Pos (2U)
6672#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos)
6673#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk
6674#define BDMA_IFCR_CTEIF0_Pos (3U)
6675#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos)
6676#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk
6677#define BDMA_IFCR_CGIF1_Pos (4U)
6678#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos)
6679#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk
6680#define BDMA_IFCR_CTCIF1_Pos (5U)
6681#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos)
6682#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk
6683#define BDMA_IFCR_CHTIF1_Pos (6U)
6684#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos)
6685#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk
6686#define BDMA_IFCR_CTEIF1_Pos (7U)
6687#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos)
6688#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk
6689#define BDMA_IFCR_CGIF2_Pos (8U)
6690#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos)
6691#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk
6692#define BDMA_IFCR_CTCIF2_Pos (9U)
6693#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos)
6694#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk
6695#define BDMA_IFCR_CHTIF2_Pos (10U)
6696#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos)
6697#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk
6698#define BDMA_IFCR_CTEIF2_Pos (11U)
6699#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos)
6700#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk
6701#define BDMA_IFCR_CGIF3_Pos (12U)
6702#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos)
6703#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk
6704#define BDMA_IFCR_CTCIF3_Pos (13U)
6705#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos)
6706#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk
6707#define BDMA_IFCR_CHTIF3_Pos (14U)
6708#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos)
6709#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk
6710#define BDMA_IFCR_CTEIF3_Pos (15U)
6711#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos)
6712#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk
6713#define BDMA_IFCR_CGIF4_Pos (16U)
6714#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos)
6715#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk
6716#define BDMA_IFCR_CTCIF4_Pos (17U)
6717#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos)
6718#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk
6719#define BDMA_IFCR_CHTIF4_Pos (18U)
6720#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos)
6721#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk
6722#define BDMA_IFCR_CTEIF4_Pos (19U)
6723#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos)
6724#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk
6725#define BDMA_IFCR_CGIF5_Pos (20U)
6726#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos)
6727#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk
6728#define BDMA_IFCR_CTCIF5_Pos (21U)
6729#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos)
6730#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk
6731#define BDMA_IFCR_CHTIF5_Pos (22U)
6732#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos)
6733#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk
6734#define BDMA_IFCR_CTEIF5_Pos (23U)
6735#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos)
6736#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk
6737#define BDMA_IFCR_CGIF6_Pos (24U)
6738#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos)
6739#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk
6740#define BDMA_IFCR_CTCIF6_Pos (25U)
6741#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos)
6742#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk
6743#define BDMA_IFCR_CHTIF6_Pos (26U)
6744#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos)
6745#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk
6746#define BDMA_IFCR_CTEIF6_Pos (27U)
6747#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos)
6748#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk
6749#define BDMA_IFCR_CGIF7_Pos (28U)
6750#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos)
6751#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk
6752#define BDMA_IFCR_CTCIF7_Pos (29U)
6753#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos)
6754#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk
6755#define BDMA_IFCR_CHTIF7_Pos (30U)
6756#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos)
6757#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk
6758#define BDMA_IFCR_CTEIF7_Pos (31U)
6759#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos)
6760#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk
6762/******************* Bit definition for BDMA_CCR register ********************/
6763#define BDMA_CCR_EN_Pos (0U)
6764#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos)
6765#define BDMA_CCR_EN BDMA_CCR_EN_Msk
6766#define BDMA_CCR_TCIE_Pos (1U)
6767#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos)
6768#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
6769#define BDMA_CCR_HTIE_Pos (2U)
6770#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos)
6771#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk
6772#define BDMA_CCR_TEIE_Pos (3U)
6773#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos)
6774#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk
6775#define BDMA_CCR_DIR_Pos (4U)
6776#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos)
6777#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk
6778#define BDMA_CCR_CIRC_Pos (5U)
6779#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos)
6780#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk
6781#define BDMA_CCR_PINC_Pos (6U)
6782#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos)
6783#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk
6784#define BDMA_CCR_MINC_Pos (7U)
6785#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos)
6786#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk
6788#define BDMA_CCR_PSIZE_Pos (8U)
6789#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos)
6790#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk
6791#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos)
6792#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos)
6794#define BDMA_CCR_MSIZE_Pos (10U)
6795#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos)
6796#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk
6797#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos)
6798#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos)
6800#define BDMA_CCR_PL_Pos (12U)
6801#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos)
6802#define BDMA_CCR_PL BDMA_CCR_PL_Msk
6803#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos)
6804#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos)
6806#define BDMA_CCR_MEM2MEM_Pos (14U)
6807#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos)
6808#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk
6809#define BDMA_CCR_DBM_Pos (15U)
6810#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos)
6811#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk
6812#define BDMA_CCR_CT_Pos (16U)
6813#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos)
6814#define BDMA_CCR_CT BDMA_CCR_CT_Msk
6816/****************** Bit definition for BDMA_CNDTR register *******************/
6817#define BDMA_CNDTR_NDT_Pos (0U)
6818#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
6819#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk
6821/****************** Bit definition for BDMA_CPAR register ********************/
6822#define BDMA_CPAR_PA_Pos (0U)
6823#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
6824#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk
6826/****************** Bit definition for BDMA_CM0AR register ********************/
6827#define BDMA_CM0AR_MA_Pos (0U)
6828#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
6829#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk
6831/****************** Bit definition for BDMA_CM1AR register ********************/
6832#define BDMA_CM1AR_MA_Pos (0U)
6833#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
6834#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk
6836/******************************************************************************/
6837/* */
6838/* Ethernet MAC Registers bits definitions */
6839/* */
6840/******************************************************************************/
6841/* Bit definition for Ethernet MAC Configuration Register register */
6842#define ETH_MACCR_ARP_Pos (31U)
6843#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos)
6844#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6845#define ETH_MACCR_SARC_Pos (28U)
6846#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos)
6847#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6848#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6849#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6850#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos)
6851#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6852#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6853#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos)
6854#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6855#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6856#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos)
6857#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6858#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6859#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos)
6860#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6861#define ETH_MACCR_IPC_Pos (27U)
6862#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos)
6863#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6864#define ETH_MACCR_IPG_Pos (24U)
6865#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos)
6866#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6867#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
6868#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
6869#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
6870#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
6871#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
6872#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
6873#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
6874#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
6875#define ETH_MACCR_GPSLCE_Pos (23U)
6876#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos)
6877#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6878#define ETH_MACCR_S2KP_Pos (22U)
6879#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos)
6880#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6881#define ETH_MACCR_CST_Pos (21U)
6882#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos)
6883#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6884#define ETH_MACCR_ACS_Pos (20U)
6885#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos)
6886#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6887#define ETH_MACCR_WD_Pos (19U)
6888#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
6889#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6890#define ETH_MACCR_JD_Pos (17U)
6891#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
6892#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6893#define ETH_MACCR_JE_Pos (16U)
6894#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos)
6895#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6896#define ETH_MACCR_FES_Pos (14U)
6897#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
6898#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6899#define ETH_MACCR_DM_Pos (13U)
6900#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
6901#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6902#define ETH_MACCR_LM_Pos (12U)
6903#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
6904#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6905#define ETH_MACCR_ECRSFD_Pos (11U)
6906#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos)
6907#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6908#define ETH_MACCR_DO_Pos (10U)
6909#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos)
6910#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6911#define ETH_MACCR_DCRS_Pos (9U)
6912#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos)
6913#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6914#define ETH_MACCR_DR_Pos (8U)
6915#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos)
6916#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
6917#define ETH_MACCR_BL_Pos (5U)
6918#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
6919#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
6920#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos)
6921#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos)
6922#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos)
6923#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos)
6924#define ETH_MACCR_DC_Pos (4U)
6925#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
6926#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
6927#define ETH_MACCR_PRELEN_Pos (2U)
6928#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos)
6929#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
6930#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos)
6931#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos)
6932#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos)
6933#define ETH_MACCR_TE_Pos (1U)
6934#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
6935#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
6936#define ETH_MACCR_RE_Pos (0U)
6937#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
6938#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
6939
6940/* Bit definition for Ethernet MAC Extended Configuration Register register */
6941#define ETH_MACECR_EIPG_Pos (25U)
6942#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos)
6943#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
6944#define ETH_MACECR_EIPGEN_Pos (24U)
6945#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos)
6946#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
6947#define ETH_MACECR_USP_Pos (18U)
6948#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos)
6949#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
6950#define ETH_MACECR_SPEN_Pos (17U)
6951#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos)
6952#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
6953#define ETH_MACECR_DCRCC_Pos (16U)
6954#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos)
6955#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
6956#define ETH_MACECR_GPSL_Pos (0U)
6957#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos)
6958#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
6959
6960/* Bit definition for Ethernet MAC Packet Filter Register */
6961#define ETH_MACPFR_RA_Pos (31U)
6962#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos)
6963#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
6964#define ETH_MACPFR_DNTU_Pos (21U)
6965#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos)
6966#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
6967#define ETH_MACPFR_IPFE_Pos (20U)
6968#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos)
6969#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
6970#define ETH_MACPFR_VTFE_Pos (16U)
6971#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos)
6972#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
6973#define ETH_MACPFR_HPF_Pos (10U)
6974#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos)
6975#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
6976#define ETH_MACPFR_SAF_Pos (9U)
6977#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos)
6978#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
6979#define ETH_MACPFR_SAIF_Pos (8U)
6980#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos)
6981#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
6982#define ETH_MACPFR_PCF_Pos (6U)
6983#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos)
6984#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
6985#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
6986#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
6987#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos)
6988#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6989#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
6990#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos)
6991#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6992#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
6993#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos)
6994#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6995#define ETH_MACPFR_DBF_Pos (5U)
6996#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos)
6997#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
6998#define ETH_MACPFR_PM_Pos (4U)
6999#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos)
7000#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
7001#define ETH_MACPFR_DAIF_Pos (3U)
7002#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos)
7003#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
7004#define ETH_MACPFR_HMC_Pos (2U)
7005#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos)
7006#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
7007#define ETH_MACPFR_HUC_Pos (1U)
7008#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos)
7009#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
7010#define ETH_MACPFR_PR_Pos (0U)
7011#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos)
7012#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
7013
7014/* Bit definition for Ethernet MAC Watchdog Timeout Register */
7015#define ETH_MACWTR_PWE_Pos (8U)
7016#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos)
7017#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
7018#define ETH_MACWTR_WTO_Pos (0U)
7019#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos)
7020#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
7021#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
7022#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
7023#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
7024#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
7025#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
7026#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
7027#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
7028#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
7029#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
7030#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
7031#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
7032#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
7033#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
7034#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
7035#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
7036
7037/* Bit definition for Ethernet MAC Hash Table High Register */
7038#define ETH_MACHTHR_HTH_Pos (0U)
7039#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
7040#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
7041
7042/* Bit definition for Ethernet MAC Hash Table Low Register */
7043#define ETH_MACHTLR_HTL_Pos (0U)
7044#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
7045#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
7046
7047/* Bit definition for Ethernet MAC VLAN Tag Register */
7048#define ETH_MACVTR_EIVLRXS_Pos (31U)
7049#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos)
7050#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
7051#define ETH_MACVTR_EIVLS_Pos (28U)
7052#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos)
7053#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
7054#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
7055#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
7056#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos)
7057#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7058#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
7059#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos)
7060#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7061#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
7062#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos)
7063#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
7064#define ETH_MACVTR_ERIVLT_Pos (27U)
7065#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos)
7066#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
7067#define ETH_MACVTR_EDVLP_Pos (26U)
7068#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos)
7069#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
7070#define ETH_MACVTR_VTHM_Pos (25U)
7071#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos)
7072#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
7073#define ETH_MACVTR_EVLRXS_Pos (24U)
7074#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos)
7075#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
7076#define ETH_MACVTR_EVLS_Pos (21U)
7077#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos)
7078#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
7079#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
7080#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
7081#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos)
7082#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7083#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
7084#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos)
7085#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7086#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
7087#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos)
7088#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
7089#define ETH_MACVTR_DOVLTC_Pos (20U)
7090#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos)
7091#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
7092#define ETH_MACVTR_ERSVLM_Pos (19U)
7093#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos)
7094#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
7095#define ETH_MACVTR_ESVL_Pos (18U)
7096#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos)
7097#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7098#define ETH_MACVTR_VTIM_Pos (17U)
7099#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos)
7100#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
7101#define ETH_MACVTR_ETV_Pos (16U)
7102#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos)
7103#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
7104#define ETH_MACVTR_VL_Pos (0U)
7105#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos)
7106#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
7107#define ETH_MACVTR_VL_UP_Pos (13U)
7108#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos)
7109#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
7110#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
7111#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos)
7112#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7113#define ETH_MACVTR_VL_VID_Pos (0U)
7114#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos)
7115#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
7116
7117/* Bit definition for Ethernet MAC VLAN Hash Table Register */
7118#define ETH_MACVHTR_VLHT_Pos (0U)
7119#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos)
7120#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
7121
7122/* Bit definition for Ethernet MAC VLAN Incl Register */
7123#define ETH_MACVIR_VLTI_Pos (20U)
7124#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos)
7125#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
7126#define ETH_MACVIR_CSVL_Pos (19U)
7127#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos)
7128#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7129#define ETH_MACVIR_VLP_Pos (18U)
7130#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos)
7131#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
7132#define ETH_MACVIR_VLC_Pos (16U)
7133#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos)
7134#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7135#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
7136#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
7137#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos)
7138#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7139#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
7140#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos)
7141#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7142#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
7143#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos)
7144#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7145#define ETH_MACVIR_VLT_Pos (0U)
7146#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos)
7147#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7148#define ETH_MACVIR_VLT_UP_Pos (13U)
7149#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos)
7150#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
7151#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
7152#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
7153#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7154#define ETH_MACVIR_VLT_VID_Pos (0U)
7155#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos)
7156#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7157
7158/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
7159#define ETH_MACIVIR_VLTI_Pos (20U)
7160#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos)
7161#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
7162#define ETH_MACIVIR_CSVL_Pos (19U)
7163#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos)
7164#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7165#define ETH_MACIVIR_VLP_Pos (18U)
7166#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos)
7167#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
7168#define ETH_MACIVIR_VLC_Pos (16U)
7169#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos)
7170#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7171#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
7172#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
7173#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos)
7174#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7175#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
7176#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos)
7177#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7178#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
7179#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos)
7180#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7181#define ETH_MACIVIR_VLT_Pos (0U)
7182#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos)
7183#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7184#define ETH_MACIVIR_VLT_UP_Pos (13U)
7185#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos)
7186#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
7187#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
7188#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos)
7189#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7190#define ETH_MACIVIR_VLT_VID_Pos (0U)
7191#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos)
7192#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7193
7194/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
7195#define ETH_MACTFCR_PT_Pos (16U)
7196#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos)
7197#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
7198#define ETH_MACTFCR_DZPQ_Pos (7U)
7199#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos)
7200#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
7201#define ETH_MACTFCR_PLT_Pos (4U)
7202#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos)
7203#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7204#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
7205#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7206#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos)
7207#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7208#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7209#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos)
7210#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7211#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7212#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos)
7213#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7214#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7215#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos)
7216#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7217#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7218#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos)
7219#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7220#define ETH_MACTFCR_TFE_Pos (1U)
7221#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos)
7222#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7223#define ETH_MACTFCR_FCB_Pos (0U)
7224#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos)
7225#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7226
7227/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7228#define ETH_MACRFCR_UP_Pos (1U)
7229#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos)
7230#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7231#define ETH_MACRFCR_RFE_Pos (0U)
7232#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos)
7233#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7234
7235/* Bit definition for Ethernet MAC Interrupt Status Register */
7236#define ETH_MACISR_RXSTSIS_Pos (14U)
7237#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos)
7238#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7239#define ETH_MACISR_TXSTSIS_Pos (13U)
7240#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos)
7241#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7242#define ETH_MACISR_TSIS_Pos (12U)
7243#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos)
7244#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7245#define ETH_MACISR_MMCTXIS_Pos (10U)
7246#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos)
7247#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7248#define ETH_MACISR_MMCRXIS_Pos (9U)
7249#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos)
7250#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7251#define ETH_MACISR_MMCIS_Pos (8U)
7252#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos)
7253#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7254#define ETH_MACISR_LPIIS_Pos (5U)
7255#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos)
7256#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7257#define ETH_MACISR_PMTIS_Pos (4U)
7258#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos)
7259#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7260#define ETH_MACISR_PHYIS_Pos (3U)
7261#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos)
7262#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7263
7264/* Bit definition for Ethernet MAC Interrupt Enable Register */
7265#define ETH_MACIER_RXSTSIE_Pos (14U)
7266#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos)
7267#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7268#define ETH_MACIER_TXSTSIE_Pos (13U)
7269#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos)
7270#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7271#define ETH_MACIER_TSIE_Pos (12U)
7272#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos)
7273#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7274#define ETH_MACIER_LPIIE_Pos (5U)
7275#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos)
7276#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7277#define ETH_MACIER_PMTIE_Pos (4U)
7278#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos)
7279#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7280#define ETH_MACIER_PHYIE_Pos (3U)
7281#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos)
7282#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7283
7284/* Bit definition for Ethernet MAC Rx Tx Status Register */
7285#define ETH_MACRXTXSR_RWT_Pos (8U)
7286#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos)
7287#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7288#define ETH_MACRXTXSR_EXCOL_Pos (5U)
7289#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos)
7290#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7291#define ETH_MACRXTXSR_LCOL_Pos (4U)
7292#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos)
7293#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7294#define ETH_MACRXTXSR_EXDEF_Pos (3U)
7295#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos)
7296#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7297#define ETH_MACRXTXSR_LCARR_Pos (2U)
7298#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos)
7299#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7300#define ETH_MACRXTXSR_NCARR_Pos (1U)
7301#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos)
7302#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7303#define ETH_MACRXTXSR_TJT_Pos (0U)
7304#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos)
7305#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7306
7307/* Bit definition for Ethernet MAC PMT Control Status Register */
7308#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7309#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos)
7310#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7311#define ETH_MACPCSR_RWKPTR_Pos (24U)
7312#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos)
7313#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7314#define ETH_MACPCSR_RWKPFE_Pos (10U)
7315#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos)
7316#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7317#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7318#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos)
7319#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7320#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7321#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos)
7322#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7323#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7324#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos)
7325#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7326#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7327#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos)
7328#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7329#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7330#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos)
7331#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7332#define ETH_MACPCSR_PWRDWN_Pos (0U)
7333#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos)
7334#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7335
7336/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7337#define ETH_MACRWUPFR_D_Pos (0U)
7338#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos)
7339#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7340
7341/* Bit definition for Ethernet MAC LPI Control Status Register */
7342#define ETH_MACLCSR_LPITCSE_Pos (21U)
7343#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos)
7344#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7345#define ETH_MACLCSR_LPITE_Pos (20U)
7346#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos)
7347#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7348#define ETH_MACLCSR_LPITXA_Pos (19U)
7349#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos)
7350#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7351#define ETH_MACLCSR_PLS_Pos (17U)
7352#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos)
7353#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7354#define ETH_MACLCSR_LPIEN_Pos (16U)
7355#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos)
7356#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7357#define ETH_MACLCSR_RLPIST_Pos (9U)
7358#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos)
7359#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7360#define ETH_MACLCSR_TLPIST_Pos (8U)
7361#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos)
7362#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7363#define ETH_MACLCSR_RLPIEX_Pos (3U)
7364#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos)
7365#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7366#define ETH_MACLCSR_RLPIEN_Pos (2U)
7367#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos)
7368#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7369#define ETH_MACLCSR_TLPIEX_Pos (1U)
7370#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos)
7371#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7372#define ETH_MACLCSR_TLPIEN_Pos (0U)
7373#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos)
7374#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7375
7376/* Bit definition for Ethernet MAC LPI Timers Control Register */
7377#define ETH_MACLTCR_LST_Pos (16U)
7378#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos)
7379#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7380#define ETH_MACLTCR_TWT_Pos (0U)
7381#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos)
7382#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7383
7384/* Bit definition for Ethernet MAC LPI Entry Timer Register */
7385#define ETH_MACLETR_LPIET_Pos (0U)
7386#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos)
7387#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7388
7389/* Bit definition for Ethernet MAC 1US Tic Counter Register */
7390#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7391#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos)
7392#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7393
7394/* Bit definition for Ethernet MAC Version Register */
7395#define ETH_MACVR_USERVER_Pos (8U)
7396#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos)
7397#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7398#define ETH_MACVR_SNPSVER_Pos (0U)
7399#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos)
7400#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7401
7402/* Bit definition for Ethernet MAC Debug Register */
7403#define ETH_MACDR_TFCSTS_Pos (17U)
7404#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos)
7405#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7406#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
7407#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7408#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
7409#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7410#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7411#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos)
7412#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7413#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7414#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos)
7415#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7416#define ETH_MACDR_TPESTS_Pos (16U)
7417#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos)
7418#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7419#define ETH_MACDR_RFCFCSTS_Pos (1U)
7420#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos)
7421#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7422#define ETH_MACDR_RPESTS_Pos (0U)
7423#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos)
7424#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7425
7426/* Bit definition for Ethernet MAC HW Feature0 Register */
7427#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7428#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos)
7429#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7430#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
7431#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7432#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos)
7433#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7434#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7435#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos)
7436#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7437#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7438#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos)
7439#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7440#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7441#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos)
7442#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7443#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7444#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos)
7445#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7446#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7447#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos)
7448#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7449#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7450#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos)
7451#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7452#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7453#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos)
7454#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7455#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7456#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos)
7457#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7458#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7459#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos)
7460#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7461#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7462#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos)
7463#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7464#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7465#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos)
7466#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7467#define ETH_MACHWF0R_EEESEL_Pos (13U)
7468#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos)
7469#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7470#define ETH_MACHWF0R_TSSEL_Pos (12U)
7471#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos)
7472#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7473#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7474#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos)
7475#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7476#define ETH_MACHWF0R_MMCSEL_Pos (8U)
7477#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos)
7478#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7479#define ETH_MACHWF0R_MGKSEL_Pos (7U)
7480#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos)
7481#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7482#define ETH_MACHWF0R_RWKSEL_Pos (6U)
7483#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos)
7484#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7485#define ETH_MACHWF0R_SMASEL_Pos (5U)
7486#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos)
7487#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7488#define ETH_MACHWF0R_VLHASH_Pos (4U)
7489#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos)
7490#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7491#define ETH_MACHWF0R_PCSSEL_Pos (3U)
7492#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos)
7493#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7494#define ETH_MACHWF0R_HDSEL_Pos (2U)
7495#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos)
7496#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7497#define ETH_MACHWF0R_GMIISEL_Pos (1U)
7498#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos)
7499#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7500#define ETH_MACHWF0R_MIISEL_Pos (0U)
7501#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos)
7502#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7503
7504/* Bit definition for Ethernet MAC HW Feature1 Register */
7505#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7506#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos)
7507#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7508#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7509#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos)
7510#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7511#define ETH_MACHWF1R_AVSEL_Pos (20U)
7512#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos)
7513#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7514#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7515#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos)
7516#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7517#define ETH_MACHWF1R_TSOEN_Pos (18U)
7518#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos)
7519#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7520#define ETH_MACHWF1R_SPHEN_Pos (17U)
7521#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos)
7522#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7523#define ETH_MACHWF1R_DCBEN_Pos (16U)
7524#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos)
7525#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7526#define ETH_MACHWF1R_ADDR64_Pos (14U)
7527#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos)
7528#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7529#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos)
7530#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos)
7531#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos)
7532#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7533#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos)
7534#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7535#define ETH_MACHWF1R_PTOEN_Pos (12U)
7536#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
7537#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7538#define ETH_MACHWF1R_OSTEN_Pos (11U)
7539#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos)
7540#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7541#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7542#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos)
7543#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7544#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7545#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos)
7546#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7547
7548/* Bit definition for Ethernet MAC HW Feature2 Register */
7549#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7550#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos)
7551#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7552#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7553#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos)
7554#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7555#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7556#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos)
7557#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7558#define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7559#define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos)
7560#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7561#define ETH_MACHWF2R_TXQCNT_Pos (6U)
7562#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos)
7563#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7564#define ETH_MACHWF2R_RXQCNT_Pos (0U)
7565#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos)
7566#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7567
7568/* Bit definition for Ethernet MAC MDIO Address Register */
7569#define ETH_MACMDIOAR_PSE_Pos (27U)
7570#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos)
7571#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7572#define ETH_MACMDIOAR_BTB_Pos (26U)
7573#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos)
7574#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7575#define ETH_MACMDIOAR_PA_Pos (21U)
7576#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos)
7577#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7578#define ETH_MACMDIOAR_RDA_Pos (16U)
7579#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos)
7580#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7581#define ETH_MACMDIOAR_NTC_Pos (12U)
7582#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos)
7583#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7584#define ETH_MACMDIOAR_CR_Pos (8U)
7585#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos)
7586#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7587#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
7588#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7589#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos)
7590#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7591#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7592#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos)
7593#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7594#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7595#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos)
7596#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7597#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7598#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos)
7599#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7600#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7601#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos)
7602#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7603#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7604#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos)
7605#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7606#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7607#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos)
7608#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7609#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7610#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos)
7611#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7612#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7613#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos)
7614#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7615#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7616#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos)
7617#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7618#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7619#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos)
7620#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7621#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7622#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos)
7623#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7624#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7625#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos)
7626#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7627#define ETH_MACMDIOAR_SKAP_Pos (4U)
7628#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos)
7629#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7630#define ETH_MACMDIOAR_MOC_Pos (2U)
7631#define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos)
7632#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7633#define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7634#define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos)
7635#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7636#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7637#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos)
7638#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7639#define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7640#define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos)
7641#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7642#define ETH_MACMDIOAR_C45E_Pos (1U)
7643#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos)
7644#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7645#define ETH_MACMDIOAR_MB_Pos (0U)
7646#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos)
7647#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7648
7649/* Bit definition for Ethernet MAC MDIO Data Register */
7650#define ETH_MACMDIODR_RA_Pos (16U)
7651#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos)
7652#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7653#define ETH_MACMDIODR_MD_Pos (0U)
7654#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos)
7655#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7656
7657/* Bit definition for Ethernet ARP Address Register */
7658#define ETH_MACARPAR_ARPPA_Pos (0U)
7659#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos)
7660#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7661
7662/* Bit definition for Ethernet MAC Address 0 High Register */
7663#define ETH_MACA0HR_AE_Pos (31U)
7664#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos)
7665#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7666#define ETH_MACA0HR_ADDRHI_Pos (0U)
7667#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos)
7668#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7669
7670/* Bit definition for Ethernet MAC Address 0 Low Register */
7671#define ETH_MACA0LR_ADDRLO_Pos (0U)
7672#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos)
7673#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7674
7675/* Bit definition for Ethernet MAC Address 1 High Register */
7676#define ETH_MACA1HR_AE_Pos (31U)
7677#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
7678#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7679#define ETH_MACA1HR_SA_Pos (30U)
7680#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
7681#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7682#define ETH_MACA1HR_MBC_Pos (24U)
7683#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
7684#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7685#define ETH_MACA1HR_ADDRHI_Pos (0U)
7686#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos)
7687#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7688
7689/* Bit definition for Ethernet MAC Address 1 Low Register */
7690#define ETH_MACA1LR_ADDRLO_Pos (0U)
7691#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos)
7692#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7693
7694/* Bit definition for Ethernet MAC Address 2 High Register */
7695#define ETH_MACA2HR_AE_Pos (31U)
7696#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
7697#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
7698#define ETH_MACA2HR_SA_Pos (30U)
7699#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
7700#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
7701#define ETH_MACA2HR_MBC_Pos (24U)
7702#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
7703#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
7704#define ETH_MACA2HR_ADDRHI_Pos (0U)
7705#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos)
7706#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
7707
7708/* Bit definition for Ethernet MAC Address 2 Low Register */
7709#define ETH_MACA2LR_ADDRLO_Pos (0U)
7710#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos)
7711#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
7712
7713/* Bit definition for Ethernet MAC Address 3 High Register */
7714#define ETH_MACA3HR_AE_Pos (31U)
7715#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
7716#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
7717#define ETH_MACA3HR_SA_Pos (30U)
7718#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
7719#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
7720#define ETH_MACA3HR_MBC_Pos (24U)
7721#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
7722#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
7723#define ETH_MACA3HR_ADDRHI_Pos (0U)
7724#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos)
7725#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
7726
7727/* Bit definition for Ethernet MAC Address 3 Low Register */
7728#define ETH_MACA3LR_ADDRLO_Pos (0U)
7729#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos)
7730#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
7731
7732/* Bit definition for Ethernet MAC Address High Register */
7733#define ETH_MACAHR_AE_Pos (31U)
7734#define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos)
7735#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
7736#define ETH_MACAHR_SA_Pos (30U)
7737#define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos)
7738#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
7739#define ETH_MACAHR_MBC_Pos (24U)
7740#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos)
7741#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7742#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
7743#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
7744#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
7745#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
7746#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
7747#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
7748#define ETH_MACAHR_MACAH_Pos (0U)
7749#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos)
7750#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
7751
7752/* Bit definition for Ethernet MAC Address Low Register */
7753#define ETH_MACALR_MACAL_Pos (0U)
7754#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos)
7755#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
7756
7757/* Bit definition for Ethernet MMC Control Register */
7758#define ETH_MMCCR_UCDBC_Pos (8U)
7759#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos)
7760#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
7761#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
7762#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos)
7763#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
7764#define ETH_MMCCR_CNTPRST_Pos (4U)
7765#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos)
7766#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
7767#define ETH_MMCCR_CNTFREEZ_Pos (3U)
7768#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos)
7769#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
7770#define ETH_MMCCR_RSTONRD_Pos (2U)
7771#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos)
7772#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
7773#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
7774#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos)
7775#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
7776#define ETH_MMCCR_CNTRST_Pos (0U)
7777#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos)
7778#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
7779
7780/* Bit definition for Ethernet MMC Rx Interrupt Register */
7781#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
7782#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos)
7783#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
7784#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
7785#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos)
7786#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
7787#define ETH_MMCRIR_RXUCGPIS_Pos (17U)
7788#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos)
7789#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
7790#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
7791#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos)
7792#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
7793#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
7794#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos)
7795#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
7796
7797/* Bit definition for Ethernet MMC Tx Interrupt Register */
7798#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
7799#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos)
7800#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
7801#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
7802#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos)
7803#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
7804#define ETH_MMCTIR_TXGPKTIS_Pos (21U)
7805#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos)
7806#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
7807#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
7808#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos)
7809#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
7810#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
7811#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos)
7812#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
7813
7814/* Bit definition for Ethernet MMC Rx interrupt Mask register */
7815#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
7816#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos)
7817#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
7818#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
7819#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos)
7820#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
7821#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
7822#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos)
7823#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
7824#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
7825#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos)
7826#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
7827#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
7828#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos)
7829#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
7830
7831/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
7832#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
7833#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos)
7834#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
7835#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
7836#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos)
7837#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
7838#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
7839#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos)
7840#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
7841#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
7842#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos)
7843#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
7844#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
7845#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos)
7846#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
7847
7848/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7849#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
7850#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos)
7851#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7852
7853/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7854#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
7855#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos)
7856#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7857
7858/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7859#define ETH_MMCTPCGR_TXPKTG_Pos (0U)
7860#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos)
7861#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7862
7863/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7864#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
7865#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos)
7866#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7867
7868/* Bit definition for Ethernet MMC Rx alignment error packets register */
7869#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
7870#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos)
7871#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7872
7873/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7874#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
7875#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos)
7876#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7877
7878/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7879#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
7880#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos)
7881#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7882
7883/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7884#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
7885#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos)
7886#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7887
7888/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7889#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
7890#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos)
7891#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7892
7893/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7894#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
7895#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos)
7896#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7897
7898/* Bit definition for Ethernet MAC L3 L4 Control Register */
7899#define ETH_MACL3L4CR_L4DPIM_Pos (21U)
7900#define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos)
7901#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7902#define ETH_MACL3L4CR_L4DPM_Pos (20U)
7903#define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos)
7904#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
7905#define ETH_MACL3L4CR_L4SPIM_Pos (19U)
7906#define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos)
7907#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7908#define ETH_MACL3L4CR_L4SPM_Pos (18U)
7909#define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos)
7910#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
7911#define ETH_MACL3L4CR_L4PEN_Pos (16U)
7912#define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos)
7913#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
7914#define ETH_MACL3L4CR_L3HDBM_Pos (11U)
7915#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos)
7916#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
7917#define ETH_MACL3L4CR_L3HSBM_Pos (6U)
7918#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos)
7919#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
7920#define ETH_MACL3L4CR_L3DAIM_Pos (5U)
7921#define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos)
7922#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
7923#define ETH_MACL3L4CR_L3DAM_Pos (4U)
7924#define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos)
7925#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
7926#define ETH_MACL3L4CR_L3SAIM_Pos (3U)
7927#define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos)
7928#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
7929#define ETH_MACL3L4CR_L3SAM_Pos (2U)
7930#define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos)
7931#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
7932#define ETH_MACL3L4CR_L3PEN_Pos (0U)
7933#define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos)
7934#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
7935
7936/* Bit definition for Ethernet MAC L4 Address Register */
7937#define ETH_MACL4AR_L4DP_Pos (16U)
7938#define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos)
7939#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
7940#define ETH_MACL4AR_L4SP_Pos (0U)
7941#define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos)
7942#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
7943
7944/* Bit definition for Ethernet MAC L3 Address0 Register */
7945#define ETH_MACL3A0R_L3A0_Pos (0U)
7946#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos)
7947#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
7948
7949/* Bit definition for Ethernet MAC L4 Address1 Register */
7950#define ETH_MACL3A1R_L3A1_Pos (0U)
7951#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos)
7952#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
7953
7954/* Bit definition for Ethernet MAC L4 Address2 Register */
7955#define ETH_MACL3A2R_L3A2_Pos (0U)
7956#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos)
7957#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
7958
7959/* Bit definition for Ethernet MAC L4 Address3 Register */
7960#define ETH_MACL3A3R_L3A3_Pos (0U)
7961#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos)
7962#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
7963
7964/* Bit definition for Ethernet MAC Timestamp Control Register */
7965#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
7966#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos)
7967#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
7968#define ETH_MACTSCR_CSC_Pos (19U)
7969#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos)
7970#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
7971#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
7972#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos)
7973#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
7974#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
7975#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos)
7976#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
7977#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
7978#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos)
7979#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
7980#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
7981#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos)
7982#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
7983#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
7984#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos)
7985#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7986#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
7987#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos)
7988#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7989#define ETH_MACTSCR_TSIPENA_Pos (11U)
7990#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos)
7991#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
7992#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
7993#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos)
7994#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
7995#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
7996#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos)
7997#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
7998#define ETH_MACTSCR_TSENALL_Pos (8U)
7999#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos)
8000#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
8001#define ETH_MACTSCR_TSADDREG_Pos (5U)
8002#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos)
8003#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
8004#define ETH_MACTSCR_TSUPDT_Pos (3U)
8005#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos)
8006#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
8007#define ETH_MACTSCR_TSINIT_Pos (2U)
8008#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos)
8009#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
8010#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
8011#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos)
8012#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
8013#define ETH_MACTSCR_TSENA_Pos (0U)
8014#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos)
8015#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
8016
8017/* Bit definition for Ethernet MAC Sub-second Increment Register */
8018#define ETH_MACMACSSIR_SSINC_Pos (16U)
8019#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos)
8020#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
8021#define ETH_MACMACSSIR_SNSINC_Pos (8U)
8022#define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos)
8023#define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
8024
8025/* Bit definition for Ethernet MAC System Time Seconds Register */
8026#define ETH_MACSTSR_TSS_Pos (0U)
8027#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos)
8028#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
8029
8030/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
8031#define ETH_MACSTNR_TSSS_Pos (0U)
8032#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos)
8033#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
8034
8035/* Bit definition for Ethernet MAC System Time Seconds Update Register */
8036#define ETH_MACSTSUR_TSS_Pos (0U)
8037#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos)
8038#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
8039
8040/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
8041#define ETH_MACSTNUR_ADDSUB_Pos (31U)
8042#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos)
8043#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
8044#define ETH_MACSTNUR_TSSS_Pos (0U)
8045#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos)
8046#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
8047
8048/* Bit definition for Ethernet MAC Timestamp Addend Register */
8049#define ETH_MACTSAR_TSAR_Pos (0U)
8050#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos)
8051#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
8052
8053/* Bit definition for Ethernet MAC Timestamp Status Register */
8054#define ETH_MACTSSR_ATSNS_Pos (25U)
8055#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos)
8056#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
8057#define ETH_MACTSSR_ATSSTM_Pos (24U)
8058#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos)
8059#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
8060#define ETH_MACTSSR_ATSSTN_Pos (16U)
8061#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos)
8062#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
8063#define ETH_MACTSSR_TXTSSIS_Pos (15U)
8064#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos)
8065#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
8066#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
8067#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos)
8068#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
8069#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
8070#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos)
8071#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
8072#define ETH_MACTSSR_TSTARGT0_Pos (1U)
8073#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos)
8074#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
8075#define ETH_MACTSSR_TSSOVF_Pos (0U)
8076#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos)
8077#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
8078
8079/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
8080#define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
8081#define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos)
8082#define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
8083#define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
8084#define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos)
8085#define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
8086
8087/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
8088#define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
8089#define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos)
8090#define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
8091
8092/* Bit definition for Ethernet MAC Auxiliary Control Register*/
8093#define ETH_MACACR_ATSEN3_Pos (7U)
8094#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos)
8095#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
8096#define ETH_MACACR_ATSEN2_Pos (6U)
8097#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos)
8098#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
8099#define ETH_MACACR_ATSEN1_Pos (5U)
8100#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos)
8101#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
8102#define ETH_MACACR_ATSEN0_Pos (4U)
8103#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos)
8104#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
8105#define ETH_MACACR_ATSFC_Pos (0U)
8106#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos)
8107#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
8108
8109/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
8110#define ETH_MACATSNR_AUXTSLO_Pos (0U)
8111#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos)
8112#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
8113
8114/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
8115#define ETH_MACATSSR_AUXTSHI_Pos (0U)
8116#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos)
8117#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
8118
8119/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
8120#define ETH_MACTSIACR_OSTIAC_Pos (0U)
8121#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos)
8122#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
8123
8124/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
8125#define ETH_MACTSEACR_OSTEAC_Pos (0U)
8126#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos)
8127#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
8128
8129/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
8130#define ETH_MACTSICNR_TSIC_Pos (0U)
8131#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos)
8132#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
8133
8134/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
8135#define ETH_MACTSECNR_TSEC_Pos (0U)
8136#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos)
8137#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
8138
8139/* Bit definition for Ethernet MAC PPS Control Register */
8140#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
8141#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos)
8142#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
8143#define ETH_MACPPSCR_PPSEN0_Pos (4U)
8144#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos)
8145#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
8146#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
8147#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos)
8148#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
8149
8150/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
8151#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
8152#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos)
8153#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
8154
8155/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
8156#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
8157#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos)
8158#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
8159#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
8160#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos)
8161#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
8162
8163/* Bit definition for Ethernet MAC PPS Interval Register */
8164#define ETH_MACPPSIR_PPSINT0_Pos (0U)
8165#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos)
8166#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
8167
8168/* Bit definition for Ethernet MAC PPS Width Register */
8169#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
8170#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos)
8171#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
8172
8173/* Bit definition for Ethernet MAC PTP Offload Control Register */
8174#define ETH_MACPOCR_DN_Pos (8U)
8175#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos)
8176#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
8177#define ETH_MACPOCR_DRRDIS_Pos (6U)
8178#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos)
8179#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
8180#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
8181#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos)
8182#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
8183#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
8184#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos)
8185#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
8186#define ETH_MACPOCR_APDREQEN_Pos (2U)
8187#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos)
8188#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
8189#define ETH_MACPOCR_ASYNCEN_Pos (1U)
8190#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos)
8191#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
8192#define ETH_MACPOCR_PTOEN_Pos (0U)
8193#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos)
8194#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
8195
8196/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
8197#define ETH_MACSPI0R_SPI0_Pos (0U)
8198#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos)
8199#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
8200
8201/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
8202#define ETH_MACSPI1R_SPI1_Pos (0U)
8203#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos)
8204#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
8205
8206/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
8207#define ETH_MACSPI2R_SPI2_Pos (0U)
8208#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos)
8209#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
8210
8211/* Bit definition for Ethernet MAC Log Message Interval Register */
8212#define ETH_MACLMIR_LMPDRI_Pos (24U)
8213#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos)
8214#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
8215#define ETH_MACLMIR_DRSYNCR_Pos (8U)
8216#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos)
8217#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8218#define ETH_MACLMIR_LSI_Pos (0U)
8219#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos)
8220#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8221
8222/* Bit definition for Ethernet MTL Operation Mode Register */
8223#define ETH_MTLOMR_CNTCLR_Pos (9U)
8224#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos)
8225#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8226#define ETH_MTLOMR_CNTPRST_Pos (8U)
8227#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos)
8228#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8229#define ETH_MTLOMR_DTXSTS_Pos (1U)
8230#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos)
8231#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8232
8233/* Bit definition for Ethernet MTL Interrupt Status Register */
8234#define ETH_MTLISR_MACIS_Pos (16U)
8235#define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos)
8236#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8237#define ETH_MTLISR_QIS_Pos (0U)
8238#define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos)
8239#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8240
8241/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8242#define ETH_MTLTQOMR_TTC_Pos (4U)
8243#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos)
8244#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8245#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
8246#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
8247#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
8248#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
8249#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
8250#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
8251#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
8252#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
8253#define ETH_MTLTQOMR_TSF_Pos (1U)
8254#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos)
8255#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8256#define ETH_MTLTQOMR_FTQ_Pos (0U)
8257#define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos)
8258#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8259
8260/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8261#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8262#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos)
8263#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8264#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8265#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos)
8266#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8267
8268/* Bit definition for Ethernet MTL Tx Queue Debug Register */
8269#define ETH_MTLTQDR_STXSTSF_Pos (20U)
8270#define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos)
8271#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8272#define ETH_MTLTQDR_PTXQ_Pos (16U)
8273#define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos)
8274#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8275#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8276#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos)
8277#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8278#define ETH_MTLTQDR_TXQSTS_Pos (4U)
8279#define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos)
8280#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8281#define ETH_MTLTQDR_TWCSTS_Pos (3U)
8282#define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos)
8283#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8284#define ETH_MTLTQDR_TRCSTS_Pos (1U)
8285#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos)
8286#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8287#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
8288#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
8289#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
8290#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8291#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8292#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos)
8293#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8294
8295/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8296#define ETH_MTLQICSR_RXOIE_Pos (24U)
8297#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos)
8298#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8299#define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8300#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos)
8301#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8302#define ETH_MTLQICSR_TXUIE_Pos (8U)
8303#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos)
8304#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8305#define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8306#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos)
8307#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8308
8309/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8310#define ETH_MTLRQOMR_RQS_Pos (20U)
8311#define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos)
8312#define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8313#define ETH_MTLRQOMR_RFD_Pos (14U)
8314#define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos)
8315#define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8316#define ETH_MTLRQOMR_RFA_Pos (8U)
8317#define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos)
8318#define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8319#define ETH_MTLRQOMR_EHFC_Pos (7U)
8320#define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos)
8321#define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8322#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8323#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos)
8324#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8325#define ETH_MTLRQOMR_RSF_Pos (5U)
8326#define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos)
8327#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8328#define ETH_MTLRQOMR_FEP_Pos (4U)
8329#define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos)
8330#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8331#define ETH_MTLRQOMR_FUP_Pos (3U)
8332#define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos)
8333#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8334#define ETH_MTLRQOMR_RTC_Pos (0U)
8335#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos)
8336#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8337#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
8338#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
8339#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
8340#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
8341
8342/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8343#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8344#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos)
8345#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8346#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8347#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos)
8348#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8349#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8350#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos)
8351#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8352#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8353#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos)
8354#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8355
8356/* Bit definition for Ethernet MTL Rx Queue Debug Register */
8357#define ETH_MTLRQDR_PRXQ_Pos (16U)
8358#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos)
8359#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8360#define ETH_MTLRQDR_RXQSTS_Pos (4U)
8361#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos)
8362#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8363#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
8364#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8365#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos)
8366#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8367#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8368#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos)
8369#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8370#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8371#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos)
8372#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8373#define ETH_MTLRQDR_RRCSTS_Pos (1U)
8374#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos)
8375#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8376#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
8377#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8378#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos)
8379#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8380#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8381#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos)
8382#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8383#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8384#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos)
8385#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8386#define ETH_MTLRQDR_RWCSTS_Pos (0U)
8387#define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos)
8388#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8389
8390/* Bit definition for Ethernet MTL Rx Queue Control Register */
8391#define ETH_MTLRQCR_RQPA_Pos (3U)
8392#define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos)
8393#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8394#define ETH_MTLRQCR_RQW_Pos (0U)
8395#define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos)
8396#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8397
8398/* Bit definition for Ethernet DMA Mode Register */
8399#define ETH_DMAMR_INTM_Pos (16U)
8400#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos)
8401#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8402#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos)
8403#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos)
8404#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos)
8405#define ETH_DMAMR_PR_Pos (12U)
8406#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos)
8407#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8408#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
8409#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
8410#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
8411#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
8412#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
8413#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
8414#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
8415#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
8416#define ETH_DMAMR_TXPR_Pos (11U)
8417#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos)
8418#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8419#define ETH_DMAMR_DA_Pos (1U)
8420#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos)
8421#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8422#define ETH_DMAMR_SWR_Pos (0U)
8423#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos)
8424#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8425
8426/* Bit definition for Ethernet DMA SysBus Mode Register */
8427#define ETH_DMASBMR_RB_Pos (15U)
8428#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos)
8429#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8430#define ETH_DMASBMR_MB_Pos (14U)
8431#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos)
8432#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8433#define ETH_DMASBMR_AAL_Pos (12U)
8434#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos)
8435#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8436#define ETH_DMASBMR_FB_Pos (0U)
8437#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos)
8438#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8439
8440/* Bit definition for Ethernet DMA Interrupt Status Register */
8441#define ETH_DMAISR_MACIS_Pos (17U)
8442#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos)
8443#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8444#define ETH_DMAISR_MTLIS_Pos (16U)
8445#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos)
8446#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8447#define ETH_DMAISR_DMACIS_Pos (0U)
8448#define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos)
8449#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8450
8451/* Bit definition for Ethernet DMA Debug Status Register */
8452#define ETH_DMADSR_TPS_Pos (12U)
8453#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos)
8454#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8455#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
8456#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8457#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos)
8458#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8459#define ETH_DMADSR_TPS_WAITING_Pos (13U)
8460#define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos)
8461#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8462#define ETH_DMADSR_TPS_READING_Pos (12U)
8463#define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos)
8464#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8465#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8466#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos)
8467#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8468#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8469#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos)
8470#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8471#define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8472#define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos)
8473#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8474#define ETH_DMADSR_RPS_Pos (8U)
8475#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos)
8476#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8477#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
8478#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8479#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos)
8480#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8481#define ETH_DMADSR_RPS_WAITING_Pos (12U)
8482#define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos)
8483#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8484#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8485#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos)
8486#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8487#define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8488#define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos)
8489#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8490#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8491#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos)
8492#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8493#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8494#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos)
8495#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8496
8497/* Bit definition for Ethernet DMA Channel Control Register */
8498#define ETH_DMACCR_DSL_Pos (18U)
8499#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos)
8500#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8501#define ETH_DMACCR_DSL_0BIT (0U)
8502#define ETH_DMACCR_DSL_32BIT (0x00040000U)
8503#define ETH_DMACCR_DSL_64BIT (0x00080000U)
8504#define ETH_DMACCR_DSL_128BIT (0x00100000U)
8505#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
8506#define ETH_DMACCR_MSS_Pos (0U)
8507#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos)
8508#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8509
8510/* Bit definition for Ethernet DMA Channel Tx Control Register */
8511#define ETH_DMACTCR_TPBL_Pos (16U)
8512#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos)
8513#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8514#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
8515#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
8516#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
8517#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
8518#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
8519#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
8520#define ETH_DMACTCR_TSE_Pos (12U)
8521#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos)
8522#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8523#define ETH_DMACTCR_OSP_Pos (4U)
8524#define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos)
8525#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8526#define ETH_DMACTCR_ST_Pos (0U)
8527#define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos)
8528#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8529
8530/* Bit definition for Ethernet DMA Channel Rx Control Register */
8531#define ETH_DMACRCR_RPF_Pos (31U)
8532#define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos)
8533#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8534#define ETH_DMACRCR_RPBL_Pos (16U)
8535#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos)
8536#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8537#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
8538#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
8539#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
8540#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
8541#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
8542#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
8543#define ETH_DMACRCR_RBSZ_Pos (1U)
8544#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos)
8545#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8546#define ETH_DMACRCR_SR_Pos (0U)
8547#define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos)
8548#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8549
8550/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8551#define ETH_DMACTDLAR_TDESLA_Pos (2U)
8552#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos)
8553#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8554
8555/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8556#define ETH_DMACRDLAR_RDESLA_Pos (2U)
8557#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos)
8558#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8559
8560/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8561#define ETH_DMACTDTPR_TDT_Pos (2U)
8562#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos)
8563#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8564
8565/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8566#define ETH_DMACRDTPR_RDT_Pos (2U)
8567#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos)
8568#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8569
8570/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8571#define ETH_DMACTDRLR_TDRL_Pos (0U)
8572#define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos)
8573#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8574
8575/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8576#define ETH_DMACRDRLR_RDRL_Pos (0U)
8577#define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos)
8578#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8579
8580/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8581#define ETH_DMACIER_NIE_Pos (15U)
8582#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos)
8583#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8584#define ETH_DMACIER_AIE_Pos (14U)
8585#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos)
8586#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8587#define ETH_DMACIER_CDEE_Pos (13U)
8588#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos)
8589#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8590#define ETH_DMACIER_FBEE_Pos (12U)
8591#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos)
8592#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8593#define ETH_DMACIER_ERIE_Pos (11U)
8594#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos)
8595#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8596#define ETH_DMACIER_ETIE_Pos (10U)
8597#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos)
8598#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8599#define ETH_DMACIER_RWTE_Pos (9U)
8600#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos)
8601#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8602#define ETH_DMACIER_RSE_Pos (8U)
8603#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos)
8604#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8605#define ETH_DMACIER_RBUE_Pos (7U)
8606#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos)
8607#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8608#define ETH_DMACIER_RIE_Pos (6U)
8609#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos)
8610#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8611#define ETH_DMACIER_TBUE_Pos (2U)
8612#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos)
8613#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8614#define ETH_DMACIER_TXSE_Pos (1U)
8615#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos)
8616#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8617#define ETH_DMACIER_TIE_Pos (0U)
8618#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos)
8619#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8620
8621/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8622#define ETH_DMACRIWTR_RWT_Pos (0U)
8623#define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos)
8624#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8625
8626/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8627#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8628#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos)
8629#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8630
8631/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8632#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8633#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos)
8634#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8635
8636/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8637#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8638#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos)
8639#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8640
8641/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8642#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8643#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos)
8644#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8645
8646/* Bit definition for Ethernet DMA Channel Status Register */
8647#define ETH_DMACSR_REB_Pos (19U)
8648#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos)
8649#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8650#define ETH_DMACSR_TEB_Pos (16U)
8651#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos)
8652#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8653#define ETH_DMACSR_NIS_Pos (15U)
8654#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos)
8655#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8656#define ETH_DMACSR_AIS_Pos (14U)
8657#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos)
8658#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8659#define ETH_DMACSR_CDE_Pos (13U)
8660#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos)
8661#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8662#define ETH_DMACSR_FBE_Pos (12U)
8663#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos)
8664#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8665#define ETH_DMACSR_ERI_Pos (11U)
8666#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos)
8667#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8668#define ETH_DMACSR_ETI_Pos (10U)
8669#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos)
8670#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8671#define ETH_DMACSR_RWT_Pos (9U)
8672#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos)
8673#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8674#define ETH_DMACSR_RPS_Pos (8U)
8675#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos)
8676#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8677#define ETH_DMACSR_RBU_Pos (7U)
8678#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos)
8679#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8680#define ETH_DMACSR_RI_Pos (6U)
8681#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos)
8682#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8683#define ETH_DMACSR_TBU_Pos (2U)
8684#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos)
8685#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8686#define ETH_DMACSR_TPS_Pos (1U)
8687#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos)
8688#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8689#define ETH_DMACSR_TI_Pos (0U)
8690#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos)
8691#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8692
8693/* Bit definition for Ethernet DMA Channel missed frame count register */
8694#define ETH_DMACMFCR_MFCO_Pos (15U)
8695#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos)
8696#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
8697#define ETH_DMACMFCR_MFC_Pos (0U)
8698#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos)
8699#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
8700
8701/******************************************************************************/
8702/* */
8703/* DMA Controller */
8704/* */
8705/******************************************************************************/
8706/******************** Bits definition for DMA_SxCR register *****************/
8707#define DMA_SxCR_MBURST_Pos (23U)
8708#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
8709#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
8710#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
8711#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
8712#define DMA_SxCR_PBURST_Pos (21U)
8713#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
8714#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
8715#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
8716#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
8717#define DMA_SxCR_TRBUFF_Pos (20U)
8718#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos)
8719#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk
8720#define DMA_SxCR_CT_Pos (19U)
8721#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
8722#define DMA_SxCR_CT DMA_SxCR_CT_Msk
8723#define DMA_SxCR_DBM_Pos (18U)
8724#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
8725#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
8726#define DMA_SxCR_PL_Pos (16U)
8727#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
8728#define DMA_SxCR_PL DMA_SxCR_PL_Msk
8729#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
8730#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
8731#define DMA_SxCR_PINCOS_Pos (15U)
8732#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
8733#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
8734#define DMA_SxCR_MSIZE_Pos (13U)
8735#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
8736#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
8737#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
8738#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
8739#define DMA_SxCR_PSIZE_Pos (11U)
8740#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
8741#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
8742#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
8743#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
8744#define DMA_SxCR_MINC_Pos (10U)
8745#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
8746#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
8747#define DMA_SxCR_PINC_Pos (9U)
8748#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
8749#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
8750#define DMA_SxCR_CIRC_Pos (8U)
8751#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
8752#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
8753#define DMA_SxCR_DIR_Pos (6U)
8754#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
8755#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
8756#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
8757#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
8758#define DMA_SxCR_PFCTRL_Pos (5U)
8759#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
8760#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
8761#define DMA_SxCR_TCIE_Pos (4U)
8762#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
8763#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
8764#define DMA_SxCR_HTIE_Pos (3U)
8765#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
8766#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
8767#define DMA_SxCR_TEIE_Pos (2U)
8768#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
8769#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
8770#define DMA_SxCR_DMEIE_Pos (1U)
8771#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
8772#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
8773#define DMA_SxCR_EN_Pos (0U)
8774#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
8775#define DMA_SxCR_EN DMA_SxCR_EN_Msk
8777/******************** Bits definition for DMA_SxCNDTR register **************/
8778#define DMA_SxNDT_Pos (0U)
8779#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
8780#define DMA_SxNDT DMA_SxNDT_Msk
8781#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
8782#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
8783#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
8784#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
8785#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
8786#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
8787#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
8788#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
8789#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
8790#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
8791#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
8792#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
8793#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
8794#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
8795#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
8796#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
8798/******************** Bits definition for DMA_SxFCR register ****************/
8799#define DMA_SxFCR_FEIE_Pos (7U)
8800#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
8801#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
8802#define DMA_SxFCR_FS_Pos (3U)
8803#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
8804#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
8805#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
8806#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
8807#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
8808#define DMA_SxFCR_DMDIS_Pos (2U)
8809#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
8810#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
8811#define DMA_SxFCR_FTH_Pos (0U)
8812#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
8813#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
8814#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
8815#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
8817/******************** Bits definition for DMA_LISR register *****************/
8818#define DMA_LISR_TCIF3_Pos (27U)
8819#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
8820#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
8821#define DMA_LISR_HTIF3_Pos (26U)
8822#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
8823#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
8824#define DMA_LISR_TEIF3_Pos (25U)
8825#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
8826#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
8827#define DMA_LISR_DMEIF3_Pos (24U)
8828#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
8829#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
8830#define DMA_LISR_FEIF3_Pos (22U)
8831#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
8832#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
8833#define DMA_LISR_TCIF2_Pos (21U)
8834#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
8835#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
8836#define DMA_LISR_HTIF2_Pos (20U)
8837#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
8838#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
8839#define DMA_LISR_TEIF2_Pos (19U)
8840#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
8841#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
8842#define DMA_LISR_DMEIF2_Pos (18U)
8843#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
8844#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
8845#define DMA_LISR_FEIF2_Pos (16U)
8846#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
8847#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
8848#define DMA_LISR_TCIF1_Pos (11U)
8849#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
8850#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
8851#define DMA_LISR_HTIF1_Pos (10U)
8852#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
8853#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
8854#define DMA_LISR_TEIF1_Pos (9U)
8855#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
8856#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
8857#define DMA_LISR_DMEIF1_Pos (8U)
8858#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
8859#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
8860#define DMA_LISR_FEIF1_Pos (6U)
8861#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
8862#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
8863#define DMA_LISR_TCIF0_Pos (5U)
8864#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
8865#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
8866#define DMA_LISR_HTIF0_Pos (4U)
8867#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
8868#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
8869#define DMA_LISR_TEIF0_Pos (3U)
8870#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
8871#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
8872#define DMA_LISR_DMEIF0_Pos (2U)
8873#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
8874#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
8875#define DMA_LISR_FEIF0_Pos (0U)
8876#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
8877#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
8879/******************** Bits definition for DMA_HISR register *****************/
8880#define DMA_HISR_TCIF7_Pos (27U)
8881#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
8882#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
8883#define DMA_HISR_HTIF7_Pos (26U)
8884#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
8885#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
8886#define DMA_HISR_TEIF7_Pos (25U)
8887#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
8888#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
8889#define DMA_HISR_DMEIF7_Pos (24U)
8890#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
8891#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
8892#define DMA_HISR_FEIF7_Pos (22U)
8893#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
8894#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
8895#define DMA_HISR_TCIF6_Pos (21U)
8896#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
8897#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
8898#define DMA_HISR_HTIF6_Pos (20U)
8899#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
8900#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
8901#define DMA_HISR_TEIF6_Pos (19U)
8902#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
8903#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
8904#define DMA_HISR_DMEIF6_Pos (18U)
8905#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
8906#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
8907#define DMA_HISR_FEIF6_Pos (16U)
8908#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
8909#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
8910#define DMA_HISR_TCIF5_Pos (11U)
8911#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
8912#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
8913#define DMA_HISR_HTIF5_Pos (10U)
8914#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
8915#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
8916#define DMA_HISR_TEIF5_Pos (9U)
8917#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
8918#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
8919#define DMA_HISR_DMEIF5_Pos (8U)
8920#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
8921#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
8922#define DMA_HISR_FEIF5_Pos (6U)
8923#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
8924#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
8925#define DMA_HISR_TCIF4_Pos (5U)
8926#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
8927#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
8928#define DMA_HISR_HTIF4_Pos (4U)
8929#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
8930#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
8931#define DMA_HISR_TEIF4_Pos (3U)
8932#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
8933#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
8934#define DMA_HISR_DMEIF4_Pos (2U)
8935#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
8936#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
8937#define DMA_HISR_FEIF4_Pos (0U)
8938#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
8939#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
8941/******************** Bits definition for DMA_LIFCR register ****************/
8942#define DMA_LIFCR_CTCIF3_Pos (27U)
8943#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
8944#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
8945#define DMA_LIFCR_CHTIF3_Pos (26U)
8946#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
8947#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
8948#define DMA_LIFCR_CTEIF3_Pos (25U)
8949#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
8950#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
8951#define DMA_LIFCR_CDMEIF3_Pos (24U)
8952#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
8953#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
8954#define DMA_LIFCR_CFEIF3_Pos (22U)
8955#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
8956#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
8957#define DMA_LIFCR_CTCIF2_Pos (21U)
8958#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
8959#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
8960#define DMA_LIFCR_CHTIF2_Pos (20U)
8961#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
8962#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
8963#define DMA_LIFCR_CTEIF2_Pos (19U)
8964#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
8965#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
8966#define DMA_LIFCR_CDMEIF2_Pos (18U)
8967#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
8968#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
8969#define DMA_LIFCR_CFEIF2_Pos (16U)
8970#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
8971#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
8972#define DMA_LIFCR_CTCIF1_Pos (11U)
8973#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
8974#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
8975#define DMA_LIFCR_CHTIF1_Pos (10U)
8976#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
8977#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
8978#define DMA_LIFCR_CTEIF1_Pos (9U)
8979#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
8980#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
8981#define DMA_LIFCR_CDMEIF1_Pos (8U)
8982#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
8983#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
8984#define DMA_LIFCR_CFEIF1_Pos (6U)
8985#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
8986#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
8987#define DMA_LIFCR_CTCIF0_Pos (5U)
8988#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
8989#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
8990#define DMA_LIFCR_CHTIF0_Pos (4U)
8991#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
8992#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
8993#define DMA_LIFCR_CTEIF0_Pos (3U)
8994#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
8995#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
8996#define DMA_LIFCR_CDMEIF0_Pos (2U)
8997#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
8998#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
8999#define DMA_LIFCR_CFEIF0_Pos (0U)
9000#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
9001#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
9003/******************** Bits definition for DMA_HIFCR register ****************/
9004#define DMA_HIFCR_CTCIF7_Pos (27U)
9005#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
9006#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
9007#define DMA_HIFCR_CHTIF7_Pos (26U)
9008#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
9009#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
9010#define DMA_HIFCR_CTEIF7_Pos (25U)
9011#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
9012#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
9013#define DMA_HIFCR_CDMEIF7_Pos (24U)
9014#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
9015#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
9016#define DMA_HIFCR_CFEIF7_Pos (22U)
9017#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
9018#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
9019#define DMA_HIFCR_CTCIF6_Pos (21U)
9020#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
9021#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
9022#define DMA_HIFCR_CHTIF6_Pos (20U)
9023#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
9024#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
9025#define DMA_HIFCR_CTEIF6_Pos (19U)
9026#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
9027#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
9028#define DMA_HIFCR_CDMEIF6_Pos (18U)
9029#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
9030#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
9031#define DMA_HIFCR_CFEIF6_Pos (16U)
9032#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
9033#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
9034#define DMA_HIFCR_CTCIF5_Pos (11U)
9035#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
9036#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
9037#define DMA_HIFCR_CHTIF5_Pos (10U)
9038#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
9039#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
9040#define DMA_HIFCR_CTEIF5_Pos (9U)
9041#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
9042#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
9043#define DMA_HIFCR_CDMEIF5_Pos (8U)
9044#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
9045#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
9046#define DMA_HIFCR_CFEIF5_Pos (6U)
9047#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
9048#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
9049#define DMA_HIFCR_CTCIF4_Pos (5U)
9050#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
9051#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
9052#define DMA_HIFCR_CHTIF4_Pos (4U)
9053#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
9054#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
9055#define DMA_HIFCR_CTEIF4_Pos (3U)
9056#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
9057#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
9058#define DMA_HIFCR_CDMEIF4_Pos (2U)
9059#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
9060#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
9061#define DMA_HIFCR_CFEIF4_Pos (0U)
9062#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
9063#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
9065/****************** Bit definition for DMA_SxPAR register ********************/
9066#define DMA_SxPAR_PA_Pos (0U)
9067#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
9068#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
9070/****************** Bit definition for DMA_SxM0AR register ********************/
9071#define DMA_SxM0AR_M0A_Pos (0U)
9072#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
9073#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
9075/****************** Bit definition for DMA_SxM1AR register ********************/
9076#define DMA_SxM1AR_M1A_Pos (0U)
9077#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
9078#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
9080/******************************************************************************/
9081/* */
9082/* DMAMUX Controller */
9083/* */
9084/******************************************************************************/
9085/******************** Bits definition for DMAMUX_CxCR register **************/
9086#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
9087#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9088#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
9089#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9090#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9091#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9092#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9093#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9094#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9095#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9096#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
9097#define DMAMUX_CxCR_SOIE_Pos (8U)
9098#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
9099#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
9100#define DMAMUX_CxCR_EGE_Pos (9U)
9101#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
9102#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
9103#define DMAMUX_CxCR_SE_Pos (16U)
9104#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
9105#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
9106#define DMAMUX_CxCR_SPOL_Pos (17U)
9107#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
9108#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
9109#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
9110#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
9111#define DMAMUX_CxCR_NBREQ_Pos (19U)
9112#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
9113#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
9114#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
9115#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
9116#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
9117#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
9118#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
9119#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
9120#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
9121#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
9122#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
9123#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
9124#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
9125#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
9126#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
9128/******************** Bits definition for DMAMUX_CSR register **************/
9129#define DMAMUX_CSR_SOF0_Pos (0U)
9130#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
9131#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
9132#define DMAMUX_CSR_SOF1_Pos (1U)
9133#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
9134#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
9135#define DMAMUX_CSR_SOF2_Pos (2U)
9136#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
9137#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
9138#define DMAMUX_CSR_SOF3_Pos (3U)
9139#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
9140#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
9141#define DMAMUX_CSR_SOF4_Pos (4U)
9142#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
9143#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
9144#define DMAMUX_CSR_SOF5_Pos (5U)
9145#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
9146#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
9147#define DMAMUX_CSR_SOF6_Pos (6U)
9148#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
9149#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
9150#define DMAMUX_CSR_SOF7_Pos (7U)
9151#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
9152#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
9153#define DMAMUX_CSR_SOF8_Pos (8U)
9154#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
9155#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
9156#define DMAMUX_CSR_SOF9_Pos (9U)
9157#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
9158#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
9159#define DMAMUX_CSR_SOF10_Pos (10U)
9160#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
9161#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
9162#define DMAMUX_CSR_SOF11_Pos (11U)
9163#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
9164#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
9165#define DMAMUX_CSR_SOF12_Pos (12U)
9166#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
9167#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
9168#define DMAMUX_CSR_SOF13_Pos (13U)
9169#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
9170#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
9171#define DMAMUX_CSR_SOF14_Pos (14U)
9172#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
9173#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
9174#define DMAMUX_CSR_SOF15_Pos (15U)
9175#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
9176#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
9178/******************** Bits definition for DMAMUX_CFR register **************/
9179#define DMAMUX_CFR_CSOF0_Pos (0U)
9180#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
9181#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
9182#define DMAMUX_CFR_CSOF1_Pos (1U)
9183#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
9184#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
9185#define DMAMUX_CFR_CSOF2_Pos (2U)
9186#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
9187#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
9188#define DMAMUX_CFR_CSOF3_Pos (3U)
9189#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
9190#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
9191#define DMAMUX_CFR_CSOF4_Pos (4U)
9192#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
9193#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
9194#define DMAMUX_CFR_CSOF5_Pos (5U)
9195#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
9196#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
9197#define DMAMUX_CFR_CSOF6_Pos (6U)
9198#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
9199#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
9200#define DMAMUX_CFR_CSOF7_Pos (7U)
9201#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
9202#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
9203#define DMAMUX_CFR_CSOF8_Pos (8U)
9204#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
9205#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
9206#define DMAMUX_CFR_CSOF9_Pos (9U)
9207#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
9208#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
9209#define DMAMUX_CFR_CSOF10_Pos (10U)
9210#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
9211#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
9212#define DMAMUX_CFR_CSOF11_Pos (11U)
9213#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
9214#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
9215#define DMAMUX_CFR_CSOF12_Pos (12U)
9216#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
9217#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
9218#define DMAMUX_CFR_CSOF13_Pos (13U)
9219#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
9220#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
9221#define DMAMUX_CFR_CSOF14_Pos (14U)
9222#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
9223#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
9224#define DMAMUX_CFR_CSOF15_Pos (15U)
9225#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
9226#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
9228/******************** Bits definition for DMAMUX_RGxCR register ************/
9229#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9230#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
9231#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
9232#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
9233#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
9234#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
9235#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
9236#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
9237#define DMAMUX_RGxCR_OIE_Pos (8U)
9238#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
9239#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
9240#define DMAMUX_RGxCR_GE_Pos (16U)
9241#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
9242#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
9243#define DMAMUX_RGxCR_GPOL_Pos (17U)
9244#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
9245#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
9246#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
9247#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
9248#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9249#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
9250#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
9251#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
9252#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
9253#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
9254#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
9255#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
9257/******************** Bits definition for DMAMUX_RGSR register **************/
9258#define DMAMUX_RGSR_OF0_Pos (0U)
9259#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
9260#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
9261#define DMAMUX_RGSR_OF1_Pos (1U)
9262#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
9263#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
9264#define DMAMUX_RGSR_OF2_Pos (2U)
9265#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
9266#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
9267#define DMAMUX_RGSR_OF3_Pos (3U)
9268#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
9269#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
9270#define DMAMUX_RGSR_OF4_Pos (4U)
9271#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos)
9272#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
9273#define DMAMUX_RGSR_OF5_Pos (5U)
9274#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos)
9275#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
9276#define DMAMUX_RGSR_OF6_Pos (6U)
9277#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos)
9278#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
9279#define DMAMUX_RGSR_OF7_Pos (7U)
9280#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos)
9281#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
9283/******************** Bits definition for DMAMUX_RGCFR register **************/
9284#define DMAMUX_RGCFR_COF0_Pos (0U)
9285#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
9286#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
9287#define DMAMUX_RGCFR_COF1_Pos (1U)
9288#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
9289#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
9290#define DMAMUX_RGCFR_COF2_Pos (2U)
9291#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
9292#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
9293#define DMAMUX_RGCFR_COF3_Pos (3U)
9294#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
9295#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
9296#define DMAMUX_RGCFR_COF4_Pos (4U)
9297#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos)
9298#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
9299#define DMAMUX_RGCFR_COF5_Pos (5U)
9300#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos)
9301#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
9302#define DMAMUX_RGCFR_COF6_Pos (6U)
9303#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos)
9304#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
9305#define DMAMUX_RGCFR_COF7_Pos (7U)
9306#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos)
9307#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
9309/******************************************************************************/
9310/* */
9311/* AHB Master DMA2D Controller (DMA2D) */
9312/* */
9313/******************************************************************************/
9314
9315/******************** Bit definition for DMA2D_CR register ******************/
9316
9317#define DMA2D_CR_START_Pos (0U)
9318#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
9319#define DMA2D_CR_START DMA2D_CR_START_Msk
9320#define DMA2D_CR_SUSP_Pos (1U)
9321#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
9322#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
9323#define DMA2D_CR_ABORT_Pos (2U)
9324#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
9325#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
9326#define DMA2D_CR_LOM_Pos (6U)
9327#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos)
9328#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk
9329#define DMA2D_CR_TEIE_Pos (8U)
9330#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
9331#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
9332#define DMA2D_CR_TCIE_Pos (9U)
9333#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
9334#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
9335#define DMA2D_CR_TWIE_Pos (10U)
9336#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
9337#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
9338#define DMA2D_CR_CAEIE_Pos (11U)
9339#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
9340#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
9341#define DMA2D_CR_CTCIE_Pos (12U)
9342#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
9343#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
9344#define DMA2D_CR_CEIE_Pos (13U)
9345#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
9346#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
9347#define DMA2D_CR_MODE_Pos (16U)
9348#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos)
9349#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
9350#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
9351#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
9352#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos)
9354/******************** Bit definition for DMA2D_ISR register *****************/
9355
9356#define DMA2D_ISR_TEIF_Pos (0U)
9357#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
9358#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
9359#define DMA2D_ISR_TCIF_Pos (1U)
9360#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
9361#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
9362#define DMA2D_ISR_TWIF_Pos (2U)
9363#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
9364#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
9365#define DMA2D_ISR_CAEIF_Pos (3U)
9366#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
9367#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
9368#define DMA2D_ISR_CTCIF_Pos (4U)
9369#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
9370#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
9371#define DMA2D_ISR_CEIF_Pos (5U)
9372#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
9373#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
9375/******************** Bit definition for DMA2D_IFCR register ****************/
9376
9377#define DMA2D_IFCR_CTEIF_Pos (0U)
9378#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
9379#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
9380#define DMA2D_IFCR_CTCIF_Pos (1U)
9381#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
9382#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
9383#define DMA2D_IFCR_CTWIF_Pos (2U)
9384#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
9385#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
9386#define DMA2D_IFCR_CAECIF_Pos (3U)
9387#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
9388#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
9389#define DMA2D_IFCR_CCTCIF_Pos (4U)
9390#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
9391#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
9392#define DMA2D_IFCR_CCEIF_Pos (5U)
9393#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
9394#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
9396/******************** Bit definition for DMA2D_FGMAR register ***************/
9397
9398#define DMA2D_FGMAR_MA_Pos (0U)
9399#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
9400#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
9402/******************** Bit definition for DMA2D_FGOR register ****************/
9403
9404#define DMA2D_FGOR_LO_Pos (0U)
9405#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos)
9406#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
9408/******************** Bit definition for DMA2D_BGMAR register ***************/
9409
9410#define DMA2D_BGMAR_MA_Pos (0U)
9411#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
9412#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
9414/******************** Bit definition for DMA2D_BGOR register ****************/
9415
9416#define DMA2D_BGOR_LO_Pos (0U)
9417#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos)
9418#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
9420/******************** Bit definition for DMA2D_FGPFCCR register *************/
9421
9422#define DMA2D_FGPFCCR_CM_Pos (0U)
9423#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
9424#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
9425#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
9426#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
9427#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
9428#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
9429#define DMA2D_FGPFCCR_CCM_Pos (4U)
9430#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
9431#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
9432#define DMA2D_FGPFCCR_START_Pos (5U)
9433#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
9434#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
9435#define DMA2D_FGPFCCR_CS_Pos (8U)
9436#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
9437#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
9438#define DMA2D_FGPFCCR_AM_Pos (16U)
9439#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
9440#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
9441#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
9442#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
9443#define DMA2D_FGPFCCR_CSS_Pos (18U)
9444#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
9445#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9446#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
9447#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
9448#define DMA2D_FGPFCCR_AI_Pos (20U)
9449#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
9450#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
9451#define DMA2D_FGPFCCR_RBS_Pos (21U)
9452#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
9453#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
9454#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9455#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
9456#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
9458/******************** Bit definition for DMA2D_FGCOLR register **************/
9459
9460#define DMA2D_FGCOLR_BLUE_Pos (0U)
9461#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
9462#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
9463#define DMA2D_FGCOLR_GREEN_Pos (8U)
9464#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
9465#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
9466#define DMA2D_FGCOLR_RED_Pos (16U)
9467#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
9468#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
9470/******************** Bit definition for DMA2D_BGPFCCR register *************/
9471
9472#define DMA2D_BGPFCCR_CM_Pos (0U)
9473#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
9474#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
9475#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
9476#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
9477#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
9478#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
9479#define DMA2D_BGPFCCR_CCM_Pos (4U)
9480#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
9481#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
9482#define DMA2D_BGPFCCR_START_Pos (5U)
9483#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
9484#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
9485#define DMA2D_BGPFCCR_CS_Pos (8U)
9486#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
9487#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
9488#define DMA2D_BGPFCCR_AM_Pos (16U)
9489#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
9490#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
9491#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
9492#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
9493#define DMA2D_BGPFCCR_AI_Pos (20U)
9494#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
9495#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
9496#define DMA2D_BGPFCCR_RBS_Pos (21U)
9497#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
9498#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
9499#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9500#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
9501#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
9503/******************** Bit definition for DMA2D_BGCOLR register **************/
9504
9505#define DMA2D_BGCOLR_BLUE_Pos (0U)
9506#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
9507#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
9508#define DMA2D_BGCOLR_GREEN_Pos (8U)
9509#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
9510#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
9511#define DMA2D_BGCOLR_RED_Pos (16U)
9512#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
9513#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
9515/******************** Bit definition for DMA2D_FGCMAR register **************/
9516
9517#define DMA2D_FGCMAR_MA_Pos (0U)
9518#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
9519#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
9521/******************** Bit definition for DMA2D_BGCMAR register **************/
9522
9523#define DMA2D_BGCMAR_MA_Pos (0U)
9524#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
9525#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
9527/******************** Bit definition for DMA2D_OPFCCR register **************/
9528
9529#define DMA2D_OPFCCR_CM_Pos (0U)
9530#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
9531#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
9532#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
9533#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
9534#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
9535#define DMA2D_OPFCCR_SB_Pos (8U)
9536#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos)
9537#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk
9538#define DMA2D_OPFCCR_AI_Pos (20U)
9539#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
9540#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
9541#define DMA2D_OPFCCR_RBS_Pos (21U)
9542#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
9543#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
9545/******************** Bit definition for DMA2D_OCOLR register ***************/
9546
9549#define DMA2D_OCOLR_BLUE_1_Pos (0U)
9550#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9551#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk
9552#define DMA2D_OCOLR_GREEN_1_Pos (8U)
9553#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9554#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk
9555#define DMA2D_OCOLR_RED_1_Pos (16U)
9556#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9557#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk
9558#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9559#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9560#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk
9563#define DMA2D_OCOLR_BLUE_2_Pos (0U)
9564#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9565#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk
9566#define DMA2D_OCOLR_GREEN_2_Pos (5U)
9567#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9568#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk
9569#define DMA2D_OCOLR_RED_2_Pos (11U)
9570#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9571#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk
9574#define DMA2D_OCOLR_BLUE_3_Pos (0U)
9575#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9576#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk
9577#define DMA2D_OCOLR_GREEN_3_Pos (5U)
9578#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9579#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk
9580#define DMA2D_OCOLR_RED_3_Pos (10U)
9581#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9582#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk
9583#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9584#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9585#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk
9588#define DMA2D_OCOLR_BLUE_4_Pos (0U)
9589#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9590#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk
9591#define DMA2D_OCOLR_GREEN_4_Pos (4U)
9592#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9593#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk
9594#define DMA2D_OCOLR_RED_4_Pos (8U)
9595#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9596#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk
9597#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9598#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9599#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk
9601/******************** Bit definition for DMA2D_OMAR register ****************/
9602
9603#define DMA2D_OMAR_MA_Pos (0U)
9604#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
9605#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
9607/******************** Bit definition for DMA2D_OOR register *****************/
9608
9609#define DMA2D_OOR_LO_Pos (0U)
9610#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos)
9611#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
9613/******************** Bit definition for DMA2D_NLR register *****************/
9614
9615#define DMA2D_NLR_NL_Pos (0U)
9616#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
9617#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
9618#define DMA2D_NLR_PL_Pos (16U)
9619#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
9620#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
9622/******************** Bit definition for DMA2D_LWR register *****************/
9623
9624#define DMA2D_LWR_LW_Pos (0U)
9625#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
9626#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
9628/******************** Bit definition for DMA2D_AMTCR register ***************/
9629
9630#define DMA2D_AMTCR_EN_Pos (0U)
9631#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
9632#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
9633#define DMA2D_AMTCR_DT_Pos (8U)
9634#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
9635#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
9638/******************** Bit definition for DMA2D_FGCLUT register **************/
9639
9640/******************** Bit definition for DMA2D_BGCLUT register **************/
9641
9642
9643/******************************************************************************/
9644/* */
9645/* External Interrupt/Event Controller */
9646/* */
9647/******************************************************************************/
9648/****************** Bit definition for EXTI_RTSR1 register *******************/
9649#define EXTI_RTSR1_TR_Pos (0U)
9650#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
9651#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk
9652#define EXTI_RTSR1_TR0_Pos (0U)
9653#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos)
9654#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk
9655#define EXTI_RTSR1_TR1_Pos (1U)
9656#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos)
9657#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk
9658#define EXTI_RTSR1_TR2_Pos (2U)
9659#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos)
9660#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk
9661#define EXTI_RTSR1_TR3_Pos (3U)
9662#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos)
9663#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk
9664#define EXTI_RTSR1_TR4_Pos (4U)
9665#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos)
9666#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk
9667#define EXTI_RTSR1_TR5_Pos (5U)
9668#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos)
9669#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk
9670#define EXTI_RTSR1_TR6_Pos (6U)
9671#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos)
9672#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk
9673#define EXTI_RTSR1_TR7_Pos (7U)
9674#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos)
9675#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk
9676#define EXTI_RTSR1_TR8_Pos (8U)
9677#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos)
9678#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk
9679#define EXTI_RTSR1_TR9_Pos (9U)
9680#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos)
9681#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk
9682#define EXTI_RTSR1_TR10_Pos (10U)
9683#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos)
9684#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk
9685#define EXTI_RTSR1_TR11_Pos (11U)
9686#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos)
9687#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk
9688#define EXTI_RTSR1_TR12_Pos (12U)
9689#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos)
9690#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk
9691#define EXTI_RTSR1_TR13_Pos (13U)
9692#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos)
9693#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk
9694#define EXTI_RTSR1_TR14_Pos (14U)
9695#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos)
9696#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk
9697#define EXTI_RTSR1_TR15_Pos (15U)
9698#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos)
9699#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk
9700#define EXTI_RTSR1_TR16_Pos (16U)
9701#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos)
9702#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk
9703#define EXTI_RTSR1_TR17_Pos (17U)
9704#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos)
9705#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk
9706#define EXTI_RTSR1_TR18_Pos (18U)
9707#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos)
9708#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk
9709#define EXTI_RTSR1_TR19_Pos (19U)
9710#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos)
9711#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk
9712#define EXTI_RTSR1_TR20_Pos (20U)
9713#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos)
9714#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk
9715#define EXTI_RTSR1_TR21_Pos (21U)
9716#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos)
9717#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk
9719/****************** Bit definition for EXTI_FTSR1 register *******************/
9720#define EXTI_FTSR1_TR_Pos (0U)
9721#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
9722#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk
9723#define EXTI_FTSR1_TR0_Pos (0U)
9724#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos)
9725#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk
9726#define EXTI_FTSR1_TR1_Pos (1U)
9727#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos)
9728#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk
9729#define EXTI_FTSR1_TR2_Pos (2U)
9730#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos)
9731#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk
9732#define EXTI_FTSR1_TR3_Pos (3U)
9733#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos)
9734#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk
9735#define EXTI_FTSR1_TR4_Pos (4U)
9736#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos)
9737#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk
9738#define EXTI_FTSR1_TR5_Pos (5U)
9739#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos)
9740#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk
9741#define EXTI_FTSR1_TR6_Pos (6U)
9742#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos)
9743#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk
9744#define EXTI_FTSR1_TR7_Pos (7U)
9745#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos)
9746#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk
9747#define EXTI_FTSR1_TR8_Pos (8U)
9748#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos)
9749#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk
9750#define EXTI_FTSR1_TR9_Pos (9U)
9751#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos)
9752#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk
9753#define EXTI_FTSR1_TR10_Pos (10U)
9754#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos)
9755#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk
9756#define EXTI_FTSR1_TR11_Pos (11U)
9757#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos)
9758#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk
9759#define EXTI_FTSR1_TR12_Pos (12U)
9760#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos)
9761#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk
9762#define EXTI_FTSR1_TR13_Pos (13U)
9763#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos)
9764#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk
9765#define EXTI_FTSR1_TR14_Pos (14U)
9766#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos)
9767#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk
9768#define EXTI_FTSR1_TR15_Pos (15U)
9769#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos)
9770#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk
9771#define EXTI_FTSR1_TR16_Pos (16U)
9772#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos)
9773#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk
9774#define EXTI_FTSR1_TR17_Pos (17U)
9775#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos)
9776#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk
9777#define EXTI_FTSR1_TR18_Pos (18U)
9778#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos)
9779#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk
9780#define EXTI_FTSR1_TR19_Pos (19U)
9781#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos)
9782#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk
9783#define EXTI_FTSR1_TR20_Pos (20U)
9784#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos)
9785#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk
9786#define EXTI_FTSR1_TR21_Pos (21U)
9787#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos)
9788#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk
9790/****************** Bit definition for EXTI_SWIER1 register ******************/
9791#define EXTI_SWIER1_SWIER0_Pos (0U)
9792#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos)
9793#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk
9794#define EXTI_SWIER1_SWIER1_Pos (1U)
9795#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos)
9796#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk
9797#define EXTI_SWIER1_SWIER2_Pos (2U)
9798#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos)
9799#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk
9800#define EXTI_SWIER1_SWIER3_Pos (3U)
9801#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos)
9802#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk
9803#define EXTI_SWIER1_SWIER4_Pos (4U)
9804#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos)
9805#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk
9806#define EXTI_SWIER1_SWIER5_Pos (5U)
9807#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos)
9808#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk
9809#define EXTI_SWIER1_SWIER6_Pos (6U)
9810#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos)
9811#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk
9812#define EXTI_SWIER1_SWIER7_Pos (7U)
9813#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos)
9814#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk
9815#define EXTI_SWIER1_SWIER8_Pos (8U)
9816#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos)
9817#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk
9818#define EXTI_SWIER1_SWIER9_Pos (9U)
9819#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos)
9820#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk
9821#define EXTI_SWIER1_SWIER10_Pos (10U)
9822#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos)
9823#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk
9824#define EXTI_SWIER1_SWIER11_Pos (11U)
9825#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos)
9826#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk
9827#define EXTI_SWIER1_SWIER12_Pos (12U)
9828#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos)
9829#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk
9830#define EXTI_SWIER1_SWIER13_Pos (13U)
9831#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos)
9832#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk
9833#define EXTI_SWIER1_SWIER14_Pos (14U)
9834#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos)
9835#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk
9836#define EXTI_SWIER1_SWIER15_Pos (15U)
9837#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos)
9838#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk
9839#define EXTI_SWIER1_SWIER16_Pos (16U)
9840#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
9841#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk
9842#define EXTI_SWIER1_SWIER17_Pos (17U)
9843#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos)
9844#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk
9845#define EXTI_SWIER1_SWIER18_Pos (18U)
9846#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos)
9847#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk
9848#define EXTI_SWIER1_SWIER19_Pos (19U)
9849#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos)
9850#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk
9851#define EXTI_SWIER1_SWIER20_Pos (20U)
9852#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos)
9853#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk
9854#define EXTI_SWIER1_SWIER21_Pos (21U)
9855#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos)
9856#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk
9858/****************** Bit definition for EXTI_D3PMR1 register ******************/
9859#define EXTI_D3PMR1_MR0_Pos (0U)
9860#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos)
9861#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk
9862#define EXTI_D3PMR1_MR1_Pos (1U)
9863#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos)
9864#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk
9865#define EXTI_D3PMR1_MR2_Pos (2U)
9866#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos)
9867#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk
9868#define EXTI_D3PMR1_MR3_Pos (3U)
9869#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos)
9870#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk
9871#define EXTI_D3PMR1_MR4_Pos (4U)
9872#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos)
9873#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk
9874#define EXTI_D3PMR1_MR5_Pos (5U)
9875#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos)
9876#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk
9877#define EXTI_D3PMR1_MR6_Pos (6U)
9878#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos)
9879#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk
9880#define EXTI_D3PMR1_MR7_Pos (7U)
9881#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos)
9882#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk
9883#define EXTI_D3PMR1_MR8_Pos (8U)
9884#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos)
9885#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk
9886#define EXTI_D3PMR1_MR9_Pos (9U)
9887#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos)
9888#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk
9889#define EXTI_D3PMR1_MR10_Pos (10U)
9890#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos)
9891#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk
9892#define EXTI_D3PMR1_MR11_Pos (11U)
9893#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos)
9894#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk
9895#define EXTI_D3PMR1_MR12_Pos (12U)
9896#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos)
9897#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk
9898#define EXTI_D3PMR1_MR13_Pos (13U)
9899#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos)
9900#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk
9901#define EXTI_D3PMR1_MR14_Pos (14U)
9902#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos)
9903#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk
9904#define EXTI_D3PMR1_MR15_Pos (15U)
9905#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos)
9906#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk
9907#define EXTI_D3PMR1_MR19_Pos (19U)
9908#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos)
9909#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk
9910#define EXTI_D3PMR1_MR20_Pos (20U)
9911#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos)
9912#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk
9913#define EXTI_D3PMR1_MR21_Pos (21U)
9914#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos)
9915#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk
9916#define EXTI_D3PMR1_MR25_Pos (24U)
9917#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos)
9918#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk
9920/******************* Bit definition for EXTI_D3PCR1L register ****************/
9921#define EXTI_D3PCR1L_PCS0_Pos (0U)
9922#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
9923#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk
9924#define EXTI_D3PCR1L_PCS1_Pos (2U)
9925#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
9926#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk
9927#define EXTI_D3PCR1L_PCS2_Pos (4U)
9928#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
9929#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk
9930#define EXTI_D3PCR1L_PCS3_Pos (6U)
9931#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
9932#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk
9933#define EXTI_D3PCR1L_PCS4_Pos (8U)
9934#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
9935#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk
9936#define EXTI_D3PCR1L_PCS5_Pos (10U)
9937#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
9938#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk
9939#define EXTI_D3PCR1L_PCS6_Pos (12U)
9940#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
9941#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk
9942#define EXTI_D3PCR1L_PCS7_Pos (14U)
9943#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
9944#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk
9945#define EXTI_D3PCR1L_PCS8_Pos (16U)
9946#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
9947#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk
9948#define EXTI_D3PCR1L_PCS9_Pos (18U)
9949#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
9950#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk
9951#define EXTI_D3PCR1L_PCS10_Pos (20U)
9952#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
9953#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk
9954#define EXTI_D3PCR1L_PCS11_Pos (22U)
9955#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
9956#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk
9957#define EXTI_D3PCR1L_PCS12_Pos (24U)
9958#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
9959#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk
9960#define EXTI_D3PCR1L_PCS13_Pos (26U)
9961#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
9962#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk
9963#define EXTI_D3PCR1L_PCS14_Pos (28U)
9964#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
9965#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk
9966#define EXTI_D3PCR1L_PCS15_Pos (30U)
9967#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
9968#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk
9970/******************* Bit definition for EXTI_D3PCR1H register ****************/
9971#define EXTI_D3PCR1H_PCS19_Pos (6U)
9972#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
9973#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk
9974#define EXTI_D3PCR1H_PCS20_Pos (8U)
9975#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
9976#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk
9977#define EXTI_D3PCR1H_PCS21_Pos (10U)
9978#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
9979#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk
9980#define EXTI_D3PCR1H_PCS25_Pos (18U)
9981#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
9982#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk
9984/****************** Bit definition for EXTI_RTSR2 register *******************/
9985#define EXTI_RTSR2_TR_Pos (17U)
9986#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos)
9987#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk
9988#define EXTI_RTSR2_TR49_Pos (17U)
9989#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos)
9990#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk
9991#define EXTI_RTSR2_TR51_Pos (19U)
9992#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos)
9993#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk
9995/****************** Bit definition for EXTI_FTSR2 register *******************/
9996#define EXTI_FTSR2_TR_Pos (17U)
9997#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos)
9998#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk
9999#define EXTI_FTSR2_TR49_Pos (17U)
10000#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos)
10001#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk
10002#define EXTI_FTSR2_TR51_Pos (19U)
10003#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos)
10004#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk
10006/****************** Bit definition for EXTI_SWIER2 register ******************/
10007#define EXTI_SWIER2_SWIER49_Pos (17U)
10008#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos)
10009#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk
10010#define EXTI_SWIER2_SWIER51_Pos (19U)
10011#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos)
10012#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk
10014/****************** Bit definition for EXTI_D3PMR2 register ******************/
10015#define EXTI_D3PMR2_MR34_Pos (2U)
10016#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos)
10017#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk
10018#define EXTI_D3PMR2_MR35_Pos (3U)
10019#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos)
10020#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk
10021#define EXTI_D3PMR2_MR41_Pos (9U)
10022#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos)
10023#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk
10024#define EXTI_D3PMR2_MR48_Pos (16U)
10025#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos)
10026#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk
10027#define EXTI_D3PMR2_MR49_Pos (17U)
10028#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos)
10029#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk
10030#define EXTI_D3PMR2_MR50_Pos (18U)
10031#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos)
10032#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk
10033#define EXTI_D3PMR2_MR51_Pos (19U)
10034#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos)
10035#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk
10036#define EXTI_D3PMR2_MR52_Pos (20U)
10037#define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos)
10038#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk
10039#define EXTI_D3PMR2_MR53_Pos (21U)
10040#define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos)
10041#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk
10042/******************* Bit definition for EXTI_D3PCR2L register ****************/
10043#define EXTI_D3PCR2L_PCS34_Pos (4U)
10044#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
10045#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk
10046#define EXTI_D3PCR2L_PCS35_Pos (6U)
10047#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
10048#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk
10049#define EXTI_D3PCR2L_PCS41_Pos (18U)
10050#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
10051#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk
10054/******************* Bit definition for EXTI_D3PCR2H register ****************/
10055#define EXTI_D3PCR2H_PCS48_Pos (0U)
10056#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
10057#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk
10058#define EXTI_D3PCR2H_PCS49_Pos (2U)
10059#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
10060#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk
10061#define EXTI_D3PCR2H_PCS50_Pos (4U)
10062#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
10063#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk
10064#define EXTI_D3PCR2H_PCS51_Pos (6U)
10065#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
10066#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk
10067#define EXTI_D3PCR2H_PCS52_Pos (8U)
10068#define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos)
10069#define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk
10070#define EXTI_D3PCR2H_PCS53_Pos (10U)
10071#define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos)
10072#define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk
10073/****************** Bit definition for EXTI_RTSR3 register *******************/
10074#define EXTI_RTSR3_TR_Pos (18U)
10075#define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos)
10076#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk
10077#define EXTI_RTSR3_TR82_Pos (18U)
10078#define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos)
10079#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk
10080#define EXTI_RTSR3_TR84_Pos (20U)
10081#define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos)
10082#define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk
10083#define EXTI_RTSR3_TR85_Pos (21U)
10084#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos)
10085#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk
10086#define EXTI_RTSR3_TR86_Pos (22U)
10087#define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos)
10088#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk
10090/****************** Bit definition for EXTI_FTSR3 register *******************/
10091#define EXTI_FTSR3_TR_Pos (18U)
10092#define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos)
10093#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk
10094#define EXTI_FTSR3_TR82_Pos (18U)
10095#define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos)
10096#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk
10097#define EXTI_FTSR3_TR84_Pos (20U)
10098#define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos)
10099#define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk
10100#define EXTI_FTSR3_TR85_Pos (21U)
10101#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos)
10102#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk
10103#define EXTI_FTSR3_TR86_Pos (22U)
10104#define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos)
10105#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk
10107/****************** Bit definition for EXTI_SWIER3 register ******************/
10108#define EXTI_SWIER3_SWI_Pos (18U)
10109#define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos)
10110#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk
10111#define EXTI_SWIER3_SWIER82_Pos (18U)
10112#define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos)
10113#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk
10114#define EXTI_SWIER3_SWIER84_Pos (20U)
10115#define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos)
10116#define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk
10117#define EXTI_SWIER3_SWIER85_Pos (21U)
10118#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos)
10119#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk
10120#define EXTI_SWIER3_SWIER86_Pos (22U)
10121#define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos)
10122#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk
10124/******************* Bit definition for EXTI_IMR1 register *******************/
10125#define EXTI_IMR1_IM_Pos (0U)
10126#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
10127#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
10128#define EXTI_IMR1_IM0_Pos (0U)
10129#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
10130#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
10131#define EXTI_IMR1_IM1_Pos (1U)
10132#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
10133#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
10134#define EXTI_IMR1_IM2_Pos (2U)
10135#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
10136#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
10137#define EXTI_IMR1_IM3_Pos (3U)
10138#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
10139#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
10140#define EXTI_IMR1_IM4_Pos (4U)
10141#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
10142#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
10143#define EXTI_IMR1_IM5_Pos (5U)
10144#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
10145#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
10146#define EXTI_IMR1_IM6_Pos (6U)
10147#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
10148#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
10149#define EXTI_IMR1_IM7_Pos (7U)
10150#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
10151#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
10152#define EXTI_IMR1_IM8_Pos (8U)
10153#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
10154#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
10155#define EXTI_IMR1_IM9_Pos (9U)
10156#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
10157#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
10158#define EXTI_IMR1_IM10_Pos (10U)
10159#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
10160#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
10161#define EXTI_IMR1_IM11_Pos (11U)
10162#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
10163#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
10164#define EXTI_IMR1_IM12_Pos (12U)
10165#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
10166#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
10167#define EXTI_IMR1_IM13_Pos (13U)
10168#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
10169#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
10170#define EXTI_IMR1_IM14_Pos (14U)
10171#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
10172#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
10173#define EXTI_IMR1_IM15_Pos (15U)
10174#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
10175#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
10176#define EXTI_IMR1_IM16_Pos (16U)
10177#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
10178#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
10179#define EXTI_IMR1_IM17_Pos (17U)
10180#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
10181#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
10182#define EXTI_IMR1_IM18_Pos (18U)
10183#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
10184#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
10185#define EXTI_IMR1_IM19_Pos (19U)
10186#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
10187#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
10188#define EXTI_IMR1_IM20_Pos (20U)
10189#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
10190#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
10191#define EXTI_IMR1_IM21_Pos (21U)
10192#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
10193#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
10194#define EXTI_IMR1_IM22_Pos (22U)
10195#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
10196#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
10197#define EXTI_IMR1_IM23_Pos (23U)
10198#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
10199#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
10200#define EXTI_IMR1_IM24_Pos (24U)
10201#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
10202#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
10203#define EXTI_IMR1_IM25_Pos (25U)
10204#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
10205#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
10206#define EXTI_IMR1_IM26_Pos (26U)
10207#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
10208#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
10209#define EXTI_IMR1_IM27_Pos (27U)
10210#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
10211#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
10212#define EXTI_IMR1_IM28_Pos (28U)
10213#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
10214#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
10215#define EXTI_IMR1_IM29_Pos (29U)
10216#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
10217#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
10218#define EXTI_IMR1_IM30_Pos (30U)
10219#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
10220#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
10221#define EXTI_IMR1_IM31_Pos (31U)
10222#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
10223#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
10225/******************* Bit definition for EXTI_EMR1 register *******************/
10226#define EXTI_EMR1_EM_Pos (0U)
10227#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
10228#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk
10229#define EXTI_EMR1_EM0_Pos (0U)
10230#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
10231#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
10232#define EXTI_EMR1_EM1_Pos (1U)
10233#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
10234#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
10235#define EXTI_EMR1_EM2_Pos (2U)
10236#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
10237#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
10238#define EXTI_EMR1_EM3_Pos (3U)
10239#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
10240#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
10241#define EXTI_EMR1_EM4_Pos (4U)
10242#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
10243#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
10244#define EXTI_EMR1_EM5_Pos (5U)
10245#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
10246#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
10247#define EXTI_EMR1_EM6_Pos (6U)
10248#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
10249#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
10250#define EXTI_EMR1_EM7_Pos (7U)
10251#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
10252#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
10253#define EXTI_EMR1_EM8_Pos (8U)
10254#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
10255#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
10256#define EXTI_EMR1_EM9_Pos (9U)
10257#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
10258#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
10259#define EXTI_EMR1_EM10_Pos (10U)
10260#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
10261#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
10262#define EXTI_EMR1_EM11_Pos (11U)
10263#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
10264#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
10265#define EXTI_EMR1_EM12_Pos (12U)
10266#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
10267#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
10268#define EXTI_EMR1_EM13_Pos (13U)
10269#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
10270#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
10271#define EXTI_EMR1_EM14_Pos (14U)
10272#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
10273#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
10274#define EXTI_EMR1_EM15_Pos (15U)
10275#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
10276#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
10277#define EXTI_EMR1_EM16_Pos (16U)
10278#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
10279#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
10280#define EXTI_EMR1_EM17_Pos (17U)
10281#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
10282#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
10283#define EXTI_EMR1_EM18_Pos (18U)
10284#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
10285#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
10286#define EXTI_EMR1_EM20_Pos (20U)
10287#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
10288#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
10289#define EXTI_EMR1_EM21_Pos (21U)
10290#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
10291#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
10292#define EXTI_EMR1_EM22_Pos (22U)
10293#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
10294#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
10295#define EXTI_EMR1_EM23_Pos (23U)
10296#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
10297#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
10298#define EXTI_EMR1_EM24_Pos (24U)
10299#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
10300#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
10301#define EXTI_EMR1_EM25_Pos (25U)
10302#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
10303#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
10304#define EXTI_EMR1_EM26_Pos (26U)
10305#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
10306#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
10307#define EXTI_EMR1_EM27_Pos (27U)
10308#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
10309#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
10310#define EXTI_EMR1_EM28_Pos (28U)
10311#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
10312#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
10313#define EXTI_EMR1_EM29_Pos (29U)
10314#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
10315#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
10316#define EXTI_EMR1_EM30_Pos (30U)
10317#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
10318#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
10319#define EXTI_EMR1_EM31_Pos (31U)
10320#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
10321#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
10323/******************* Bit definition for EXTI_PR1 register ********************/
10324#define EXTI_PR1_PR_Pos (0U)
10325#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos)
10326#define EXTI_PR1_PR EXTI_PR1_PR_Msk
10327#define EXTI_PR1_PR0_Pos (0U)
10328#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos)
10329#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk
10330#define EXTI_PR1_PR1_Pos (1U)
10331#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos)
10332#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk
10333#define EXTI_PR1_PR2_Pos (2U)
10334#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos)
10335#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk
10336#define EXTI_PR1_PR3_Pos (3U)
10337#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos)
10338#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk
10339#define EXTI_PR1_PR4_Pos (4U)
10340#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos)
10341#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk
10342#define EXTI_PR1_PR5_Pos (5U)
10343#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos)
10344#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk
10345#define EXTI_PR1_PR6_Pos (6U)
10346#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos)
10347#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk
10348#define EXTI_PR1_PR7_Pos (7U)
10349#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos)
10350#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk
10351#define EXTI_PR1_PR8_Pos (8U)
10352#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
10353#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk
10354#define EXTI_PR1_PR9_Pos (9U)
10355#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos)
10356#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk
10357#define EXTI_PR1_PR10_Pos (10U)
10358#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos)
10359#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk
10360#define EXTI_PR1_PR11_Pos (11U)
10361#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos)
10362#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk
10363#define EXTI_PR1_PR12_Pos (12U)
10364#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos)
10365#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk
10366#define EXTI_PR1_PR13_Pos (13U)
10367#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos)
10368#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk
10369#define EXTI_PR1_PR14_Pos (14U)
10370#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos)
10371#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk
10372#define EXTI_PR1_PR15_Pos (15U)
10373#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos)
10374#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk
10375#define EXTI_PR1_PR16_Pos (16U)
10376#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos)
10377#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk
10378#define EXTI_PR1_PR17_Pos (17U)
10379#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos)
10380#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk
10381#define EXTI_PR1_PR18_Pos (18U)
10382#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos)
10383#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk
10384#define EXTI_PR1_PR19_Pos (19U)
10385#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos)
10386#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk
10387#define EXTI_PR1_PR20_Pos (20U)
10388#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos)
10389#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk
10390#define EXTI_PR1_PR21_Pos (21U)
10391#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos)
10392#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk
10394/******************* Bit definition for EXTI_IMR2 register *******************/
10395#define EXTI_IMR2_IM_Pos (0U)
10396#define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)
10397#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
10398#define EXTI_IMR2_IM32_Pos (0U)
10399#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
10400#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
10401#define EXTI_IMR2_IM33_Pos (1U)
10402#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
10403#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
10404#define EXTI_IMR2_IM34_Pos (2U)
10405#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
10406#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
10407#define EXTI_IMR2_IM35_Pos (3U)
10408#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
10409#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
10410#define EXTI_IMR2_IM36_Pos (4U)
10411#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
10412#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
10413#define EXTI_IMR2_IM37_Pos (5U)
10414#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
10415#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
10416#define EXTI_IMR2_IM38_Pos (6U)
10417#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
10418#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
10419#define EXTI_IMR2_IM39_Pos (7U)
10420#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
10421#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
10422#define EXTI_IMR2_IM40_Pos (8U)
10423#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
10424#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
10425#define EXTI_IMR2_IM41_Pos (9U)
10426#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
10427#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
10428#define EXTI_IMR2_IM42_Pos (10U)
10429#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
10430#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
10431#define EXTI_IMR2_IM43_Pos (11U)
10432#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)
10433#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk
10434#define EXTI_IMR2_IM44_Pos (12U)
10435#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos)
10436#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk
10437#define EXTI_IMR2_IM46_Pos (14U)
10438#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos)
10439#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk
10440#define EXTI_IMR2_IM47_Pos (15U)
10441#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos)
10442#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk
10443#define EXTI_IMR2_IM48_Pos (16U)
10444#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos)
10445#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk
10446#define EXTI_IMR2_IM49_Pos (17U)
10447#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos)
10448#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk
10449#define EXTI_IMR2_IM50_Pos (18U)
10450#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos)
10451#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk
10452#define EXTI_IMR2_IM51_Pos (19U)
10453#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos)
10454#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk
10455#define EXTI_IMR2_IM52_Pos (20U)
10456#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos)
10457#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk
10458#define EXTI_IMR2_IM53_Pos (21U)
10459#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos)
10460#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk
10461#define EXTI_IMR2_IM54_Pos (22U)
10462#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos)
10463#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk
10464#define EXTI_IMR2_IM55_Pos (23U)
10465#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos)
10466#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk
10467#define EXTI_IMR2_IM56_Pos (24U)
10468#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos)
10469#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk
10470#define EXTI_IMR2_IM57_Pos (25U)
10471#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos)
10472#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk
10473#define EXTI_IMR2_IM58_Pos (26U)
10474#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos)
10475#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk
10476#define EXTI_IMR2_IM59_Pos (27U)
10477#define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos)
10478#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk
10479#define EXTI_IMR2_IM60_Pos (28U)
10480#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
10481#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk
10482#define EXTI_IMR2_IM61_Pos (29U)
10483#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos)
10484#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk
10485#define EXTI_IMR2_IM62_Pos (30U)
10486#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos)
10487#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk
10488#define EXTI_IMR2_IM63_Pos (31U)
10489#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos)
10490#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk
10492/******************* Bit definition for EXTI_EMR2 register *******************/
10493#define EXTI_EMR2_EM_Pos (0U)
10494#define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)
10495#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
10496#define EXTI_EMR2_EM32_Pos (0U)
10497#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
10498#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
10499#define EXTI_EMR2_EM33_Pos (1U)
10500#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
10501#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
10502#define EXTI_EMR2_EM34_Pos (2U)
10503#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
10504#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
10505#define EXTI_EMR2_EM35_Pos (3U)
10506#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
10507#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
10508#define EXTI_EMR2_EM36_Pos (4U)
10509#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
10510#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
10511#define EXTI_EMR2_EM37_Pos (5U)
10512#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
10513#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
10514#define EXTI_EMR2_EM38_Pos (6U)
10515#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
10516#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
10517#define EXTI_EMR2_EM39_Pos (7U)
10518#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
10519#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
10520#define EXTI_EMR2_EM40_Pos (8U)
10521#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
10522#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
10523#define EXTI_EMR2_EM41_Pos (9U)
10524#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
10525#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
10526#define EXTI_EMR2_EM42_Pos (10U)
10527#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
10528#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
10529#define EXTI_EMR2_EM43_Pos (11U)
10530#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos)
10531#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk
10532#define EXTI_EMR2_EM44_Pos (12U)
10533#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos)
10534#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk
10535#define EXTI_EMR2_EM46_Pos (14U)
10536#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos)
10537#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk
10538#define EXTI_EMR2_EM47_Pos (15U)
10539#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos)
10540#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk
10541#define EXTI_EMR2_EM48_Pos (16U)
10542#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos)
10543#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk
10544#define EXTI_EMR2_EM49_Pos (17U)
10545#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos)
10546#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk
10547#define EXTI_EMR2_EM50_Pos (18U)
10548#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos)
10549#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk
10550#define EXTI_EMR2_EM51_Pos (19U)
10551#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos)
10552#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk
10553#define EXTI_EMR2_EM52_Pos (20U)
10554#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos)
10555#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk
10556#define EXTI_EMR2_EM53_Pos (21U)
10557#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos)
10558#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk
10559#define EXTI_EMR2_EM54_Pos (22U)
10560#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos)
10561#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk
10562#define EXTI_EMR2_EM55_Pos (23U)
10563#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos)
10564#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk
10565#define EXTI_EMR2_EM56_Pos (24U)
10566#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos)
10567#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk
10568#define EXTI_EMR2_EM57_Pos (25U)
10569#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos)
10570#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk
10571#define EXTI_EMR2_EM58_Pos (26U)
10572#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos)
10573#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk
10574#define EXTI_EMR2_EM59_Pos (27U)
10575#define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos)
10576#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk
10577#define EXTI_EMR2_EM60_Pos (28U)
10578#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos)
10579#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk
10580#define EXTI_EMR2_EM61_Pos (29U)
10581#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos)
10582#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk
10583#define EXTI_EMR2_EM62_Pos (30U)
10584#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos)
10585#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk
10586#define EXTI_EMR2_EM63_Pos (31U)
10587#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos)
10588#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk
10590/******************* Bit definition for EXTI_PR2 register ********************/
10591#define EXTI_PR2_PR_Pos (17U)
10592#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos)
10593#define EXTI_PR2_PR EXTI_PR2_PR_Msk
10594#define EXTI_PR2_PR49_Pos (17U)
10595#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos)
10596#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk
10597#define EXTI_PR2_PR51_Pos (19U)
10598#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos)
10599#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk
10601/******************* Bit definition for EXTI_IMR3 register *******************/
10602#define EXTI_IMR3_IM_Pos (0U)
10603#define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)
10604#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk
10605#define EXTI_IMR3_IM64_Pos (0U)
10606#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos)
10607#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk
10608#define EXTI_IMR3_IM65_Pos (1U)
10609#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos)
10610#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk
10611#define EXTI_IMR3_IM66_Pos (2U)
10612#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos)
10613#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk
10614#define EXTI_IMR3_IM67_Pos (3U)
10615#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos)
10616#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk
10617#define EXTI_IMR3_IM68_Pos (4U)
10618#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos)
10619#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk
10620#define EXTI_IMR3_IM69_Pos (5U)
10621#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos)
10622#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk
10623#define EXTI_IMR3_IM70_Pos (6U)
10624#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos)
10625#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk
10626#define EXTI_IMR3_IM71_Pos (7U)
10627#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos)
10628#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk
10629#define EXTI_IMR3_IM72_Pos (8U)
10630#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos)
10631#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk
10632#define EXTI_IMR3_IM73_Pos (9U)
10633#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos)
10634#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk
10635#define EXTI_IMR3_IM74_Pos (10U)
10636#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos)
10637#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk
10638#define EXTI_IMR3_IM75_Pos (11U)
10639#define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos)
10640#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk
10641#define EXTI_IMR3_IM76_Pos (12U)
10642#define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos)
10643#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk
10644#define EXTI_IMR3_IM77_Pos (13U)
10645#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos)
10646#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk
10647#define EXTI_IMR3_IM78_Pos (14U)
10648#define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos)
10649#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk
10650#define EXTI_IMR3_IM79_Pos (15U)
10651#define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos)
10652#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk
10653#define EXTI_IMR3_IM80_Pos (16U)
10654#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos)
10655#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk
10656#define EXTI_IMR3_IM82_Pos (18U)
10657#define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos)
10658#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk
10659#define EXTI_IMR3_IM84_Pos (20U)
10660#define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos)
10661#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk
10662#define EXTI_IMR3_IM85_Pos (21U)
10663#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos)
10664#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk
10665#define EXTI_IMR3_IM86_Pos (22U)
10666#define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos)
10667#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk
10668#define EXTI_IMR3_IM87_Pos (23U)
10669#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos)
10670#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk
10673/******************* Bit definition for EXTI_EMR3 register *******************/
10674#define EXTI_EMR3_EM_Pos (0U)
10675#define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)
10676#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk
10677#define EXTI_EMR3_EM64_Pos (0U)
10678#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos)
10679#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk
10680#define EXTI_EMR3_EM65_Pos (1U)
10681#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos)
10682#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk
10683#define EXTI_EMR3_EM66_Pos (2U)
10684#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos)
10685#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk
10686#define EXTI_EMR3_EM67_Pos (3U)
10687#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos)
10688#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk
10689#define EXTI_EMR3_EM68_Pos (4U)
10690#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos)
10691#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk
10692#define EXTI_EMR3_EM69_Pos (5U)
10693#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos)
10694#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk
10695#define EXTI_EMR3_EM70_Pos (6U)
10696#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos)
10697#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk
10698#define EXTI_EMR3_EM71_Pos (7U)
10699#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos)
10700#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk
10701#define EXTI_EMR3_EM72_Pos (8U)
10702#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos)
10703#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk
10704#define EXTI_EMR3_EM73_Pos (9U)
10705#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos)
10706#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk
10707#define EXTI_EMR3_EM74_Pos (10U)
10708#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos)
10709#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk
10710#define EXTI_EMR3_EM75_Pos (11U)
10711#define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos)
10712#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk
10713#define EXTI_EMR3_EM76_Pos (12U)
10714#define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos)
10715#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk
10716#define EXTI_EMR3_EM77_Pos (13U)
10717#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos)
10718#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk
10719#define EXTI_EMR3_EM78_Pos (14U)
10720#define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos)
10721#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk
10722#define EXTI_EMR3_EM79_Pos (15U)
10723#define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos)
10724#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk
10725#define EXTI_EMR3_EM80_Pos (16U)
10726#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos)
10727#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk
10728#define EXTI_EMR3_EM81_Pos (17U)
10729#define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos)
10730#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk
10731#define EXTI_EMR3_EM82_Pos (18U)
10732#define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos)
10733#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk
10734#define EXTI_EMR3_EM84_Pos (20U)
10735#define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos)
10736#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk
10737#define EXTI_EMR3_EM85_Pos (21U)
10738#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos)
10739#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk
10740#define EXTI_EMR3_EM86_Pos (22U)
10741#define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos)
10742#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk
10743#define EXTI_EMR3_EM87_Pos (23U)
10744#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos)
10745#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk
10747/******************* Bit definition for EXTI_PR3 register ********************/
10748#define EXTI_PR3_PR_Pos (18U)
10749#define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos)
10750#define EXTI_PR3_PR EXTI_PR3_PR_Msk
10751#define EXTI_PR3_PR82_Pos (18U)
10752#define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos)
10753#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk
10754#define EXTI_PR3_PR84_Pos (20U)
10755#define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos)
10756#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk
10757#define EXTI_PR3_PR85_Pos (21U)
10758#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos)
10759#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk
10760#define EXTI_PR3_PR86_Pos (22U)
10761#define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos)
10762#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk
10763/******************************************************************************/
10764/* */
10765/* FLASH */
10766/* */
10767/******************************************************************************/
10768/*
10769* @brief FLASH Global Defines
10770*/
10771#if defined(CORE_CM4)
10772#define FLASH_SIZE 0x100000UL /* 1 MB */
10773#else
10774#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
10775#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
10776 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
10777 (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
10778#endif /* CORE_CM4 */
10779#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
10780#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
10781#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
10782#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
10783#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
10784#define DUAL_BANK /* Dual-bank Flash */
10785
10786/******************* Bits definition for FLASH_ACR register **********************/
10787#define FLASH_ACR_LATENCY_Pos (0U)
10788#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
10789#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10790#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
10791#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
10792#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
10793#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
10794#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
10795#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
10796#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
10797#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
10798
10799#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
10800#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
10801#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
10802#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
10803#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
10805/* Legacy FLASH Latency defines */
10806#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
10807#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
10808#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
10809#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
10810#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
10811#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
10812#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
10813#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
10814/******************* Bits definition for FLASH_CR register ***********************/
10815#define FLASH_CR_LOCK_Pos (0U)
10816#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
10817#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10818#define FLASH_CR_PG_Pos (1U)
10819#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
10820#define FLASH_CR_PG FLASH_CR_PG_Msk
10821#define FLASH_CR_SER_Pos (2U)
10822#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
10823#define FLASH_CR_SER FLASH_CR_SER_Msk
10824#define FLASH_CR_BER_Pos (3U)
10825#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos)
10826#define FLASH_CR_BER FLASH_CR_BER_Msk
10827#define FLASH_CR_PSIZE_Pos (4U)
10828#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
10829#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10830#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
10831#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
10832#define FLASH_CR_FW_Pos (6U)
10833#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos)
10834#define FLASH_CR_FW FLASH_CR_FW_Msk
10835#define FLASH_CR_START_Pos (7U)
10836#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos)
10837#define FLASH_CR_START FLASH_CR_START_Msk
10838#define FLASH_CR_SNB_Pos (8U)
10839#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos)
10840#define FLASH_CR_SNB FLASH_CR_SNB_Msk
10841#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos)
10842#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos)
10843#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos)
10844#define FLASH_CR_CRC_EN_Pos (15U)
10845#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos)
10846#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
10847#define FLASH_CR_EOPIE_Pos (16U)
10848#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
10849#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10850#define FLASH_CR_WRPERRIE_Pos (17U)
10851#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos)
10852#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
10853#define FLASH_CR_PGSERRIE_Pos (18U)
10854#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos)
10855#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
10856#define FLASH_CR_STRBERRIE_Pos (19U)
10857#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos)
10858#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
10859#define FLASH_CR_INCERRIE_Pos (21U)
10860#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos)
10861#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
10862#define FLASH_CR_OPERRIE_Pos (22U)
10863#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos)
10864#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
10865#define FLASH_CR_RDPERRIE_Pos (23U)
10866#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos)
10867#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
10868#define FLASH_CR_RDSERRIE_Pos (24U)
10869#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos)
10870#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
10871#define FLASH_CR_SNECCERRIE_Pos (25U)
10872#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos)
10873#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
10874#define FLASH_CR_DBECCERRIE_Pos (26U)
10875#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos)
10876#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
10877#define FLASH_CR_CRCENDIE_Pos (27U)
10878#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos)
10879#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
10880#define FLASH_CR_CRCRDERRIE_Pos (28U)
10881#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
10882#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
10884/******************* Bits definition for FLASH_SR register ***********************/
10885#define FLASH_SR_BSY_Pos (0U)
10886#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
10887#define FLASH_SR_BSY FLASH_SR_BSY_Msk
10888#define FLASH_SR_WBNE_Pos (1U)
10889#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos)
10890#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
10891#define FLASH_SR_QW_Pos (2U)
10892#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos)
10893#define FLASH_SR_QW FLASH_SR_QW_Msk
10894#define FLASH_SR_CRC_BUSY_Pos (3U)
10895#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos)
10896#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
10897#define FLASH_SR_EOP_Pos (16U)
10898#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
10899#define FLASH_SR_EOP FLASH_SR_EOP_Msk
10900#define FLASH_SR_WRPERR_Pos (17U)
10901#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
10902#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10903#define FLASH_SR_PGSERR_Pos (18U)
10904#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
10905#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10906#define FLASH_SR_STRBERR_Pos (19U)
10907#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos)
10908#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
10909#define FLASH_SR_INCERR_Pos (21U)
10910#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos)
10911#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
10912#define FLASH_SR_OPERR_Pos (22U)
10913#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
10914#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
10915#define FLASH_SR_RDPERR_Pos (23U)
10916#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos)
10917#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
10918#define FLASH_SR_RDSERR_Pos (24U)
10919#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos)
10920#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
10921#define FLASH_SR_SNECCERR_Pos (25U)
10922#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos)
10923#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
10924#define FLASH_SR_DBECCERR_Pos (26U)
10925#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos)
10926#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
10927#define FLASH_SR_CRCEND_Pos (27U)
10928#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos)
10929#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
10930#define FLASH_SR_CRCRDERR_Pos (28U)
10931#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos)
10932#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
10934/******************* Bits definition for FLASH_CCR register *******************/
10935#define FLASH_CCR_CLR_EOP_Pos (16U)
10936#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos)
10937#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
10938#define FLASH_CCR_CLR_WRPERR_Pos (17U)
10939#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
10940#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
10941#define FLASH_CCR_CLR_PGSERR_Pos (18U)
10942#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
10943#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
10944#define FLASH_CCR_CLR_STRBERR_Pos (19U)
10945#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
10946#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
10947#define FLASH_CCR_CLR_INCERR_Pos (21U)
10948#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
10949#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
10950#define FLASH_CCR_CLR_OPERR_Pos (22U)
10951#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos)
10952#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
10953#define FLASH_CCR_CLR_RDPERR_Pos (23U)
10954#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
10955#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
10956#define FLASH_CCR_CLR_RDSERR_Pos (24U)
10957#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
10958#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
10959#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
10960#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
10961#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
10962#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
10963#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
10964#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
10965#define FLASH_CCR_CLR_CRCEND_Pos (27U)
10966#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
10967#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
10968#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
10969#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
10970#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
10972/******************* Bits definition for FLASH_OPTCR register *******************/
10973#define FLASH_OPTCR_OPTLOCK_Pos (0U)
10974#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
10975#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10976#define FLASH_OPTCR_OPTSTART_Pos (1U)
10977#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
10978#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
10979#define FLASH_OPTCR_MER_Pos (4U)
10980#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos)
10981#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
10982#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
10983#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
10984#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
10985#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
10986#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)
10987#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
10989/******************* Bits definition for FLASH_OPTSR register ***************/
10990#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
10991#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
10992#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
10993#define FLASH_OPTSR_BOR_LEV_Pos (2U)
10994#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
10995#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
10996#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
10997#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
10998#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
10999#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
11000#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
11001#define FLASH_OPTSR_IWDG2_SW_Pos (5U)
11002#define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos)
11003#define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk
11004#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
11005#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
11006#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
11007#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
11008#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
11009#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
11010#define FLASH_OPTSR_RDP_Pos (8U)
11011#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos)
11012#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
11013#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
11014#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
11015#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
11016#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
11017#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
11018#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
11019#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
11020#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11021#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
11022#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11023#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
11024#define FLASH_OPTSR_SECURITY_Pos (21U)
11025#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos)
11026#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
11027#define FLASH_OPTSR_BCM4_Pos (22U)
11028#define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos)
11029#define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk
11030#define FLASH_OPTSR_BCM7_Pos (23U)
11031#define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos)
11032#define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk
11033#define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
11034#define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos)
11035#define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk
11036#define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
11037#define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos)
11038#define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk
11039#define FLASH_OPTSR_IO_HSLV_Pos (29U)
11040#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
11041#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
11042#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
11043#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
11044#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
11045#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
11046#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos)
11047#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
11049/******************* Bits definition for FLASH_OPTCCR register *******************/
11050#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
11051#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
11052#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
11054/******************* Bits definition for FLASH_PRAR register *********************/
11055#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
11056#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
11057#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
11058#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
11059#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
11060#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
11061#define FLASH_PRAR_DMEP_Pos (31U)
11062#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos)
11063#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
11065/******************* Bits definition for FLASH_SCAR register *********************/
11066#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
11067#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
11068#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
11069#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
11070#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
11071#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
11072#define FLASH_SCAR_DMES_Pos (31U)
11073#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos)
11074#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
11076/******************* Bits definition for FLASH_WPSN register *********************/
11077#define FLASH_WPSN_WRPSN_Pos (0U)
11078#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos)
11079#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
11081/******************* Bits definition for FLASH_BOOT7_CUR register ****************/
11082#define FLASH_BOOT7_BCM7_ADD0_Pos (0U)
11083#define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos)
11084#define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk
11085#define FLASH_BOOT7_BCM7_ADD1_Pos (16U)
11086#define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos)
11087#define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk
11089/******************* Bits definition for FLASH_BOOT4 register ********************/
11090#define FLASH_BOOT4_BCM4_ADD0_Pos (0U)
11091#define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos)
11092#define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk
11093#define FLASH_BOOT4_BCM4_ADD1_Pos (16U)
11094#define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos)
11095#define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk
11097/******************* Bits definition for FLASH_CRCCR register ********************/
11098#define FLASH_CRCCR_CRC_SECT_Pos (0U)
11099#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)
11100#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
11101#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
11102#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
11103#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
11104#define FLASH_CRCCR_ADD_SECT_Pos (9U)
11105#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
11106#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
11107#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
11108#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
11109#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
11110#define FLASH_CRCCR_START_CRC_Pos (16U)
11111#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos)
11112#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
11113#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
11114#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
11115#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
11116#define FLASH_CRCCR_CRC_BURST_Pos (20U)
11117#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
11118#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
11119#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
11120#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
11121#define FLASH_CRCCR_ALL_BANK_Pos (22U)
11122#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
11123#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
11125/******************* Bits definition for FLASH_CRCSADD register ****************/
11126#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
11127#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
11128#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
11130/******************* Bits definition for FLASH_CRCEADD register ****************/
11131#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
11132#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
11133#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
11135/******************* Bits definition for FLASH_CRCDATA register ***************/
11136#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
11137#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
11138#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
11140/******************* Bits definition for FLASH_ECC_FA register *******************/
11141#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
11142#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
11143#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
11145/******************************************************************************/
11146/* */
11147/* Flexible Memory Controller */
11148/* */
11149/******************************************************************************/
11150/****************** Bit definition for FMC_BCR1 register *******************/
11151#define FMC_BCR1_CCLKEN_Pos (20U)
11152#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
11153#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
11154#define FMC_BCR1_WFDIS_Pos (21U)
11155#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
11156#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
11158#define FMC_BCR1_BMAP_Pos (24U)
11159#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos)
11160#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk
11161#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos)
11162#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos)
11164#define FMC_BCR1_FMCEN_Pos (31U)
11165#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos)
11166#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk
11167/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
11168#define FMC_BCRx_MBKEN_Pos (0U)
11169#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
11170#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
11171#define FMC_BCRx_MUXEN_Pos (1U)
11172#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
11173#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
11175#define FMC_BCRx_MTYP_Pos (2U)
11176#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
11177#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
11178#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
11179#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
11181#define FMC_BCRx_MWID_Pos (4U)
11182#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
11183#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
11184#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
11185#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
11187#define FMC_BCRx_FACCEN_Pos (6U)
11188#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
11189#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
11190#define FMC_BCRx_BURSTEN_Pos (8U)
11191#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
11192#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
11193#define FMC_BCRx_WAITPOL_Pos (9U)
11194#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
11195#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
11196#define FMC_BCRx_WAITCFG_Pos (11U)
11197#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
11198#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
11199#define FMC_BCRx_WREN_Pos (12U)
11200#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
11201#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
11202#define FMC_BCRx_WAITEN_Pos (13U)
11203#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
11204#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
11205#define FMC_BCRx_EXTMOD_Pos (14U)
11206#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
11207#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
11208#define FMC_BCRx_ASYNCWAIT_Pos (15U)
11209#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
11210#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
11212#define FMC_BCRx_CPSIZE_Pos (16U)
11213#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
11214#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
11215#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
11216#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
11217#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
11219#define FMC_BCRx_CBURSTRW_Pos (19U)
11220#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
11221#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
11223/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
11224#define FMC_BTRx_ADDSET_Pos (0U)
11225#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
11226#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
11227#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
11228#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
11229#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
11230#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
11232#define FMC_BTRx_ADDHLD_Pos (4U)
11233#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
11234#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
11235#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
11236#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
11237#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
11238#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
11240#define FMC_BTRx_DATAST_Pos (8U)
11241#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
11242#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
11243#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
11244#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
11245#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
11246#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
11247#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
11248#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
11249#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
11250#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
11252#define FMC_BTRx_BUSTURN_Pos (16U)
11253#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
11254#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
11255#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
11256#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
11257#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
11258#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
11260#define FMC_BTRx_CLKDIV_Pos (20U)
11261#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
11262#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
11263#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
11264#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
11265#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
11266#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
11268#define FMC_BTRx_DATLAT_Pos (24U)
11269#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
11270#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
11271#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
11272#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
11273#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
11274#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
11276#define FMC_BTRx_ACCMOD_Pos (28U)
11277#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
11278#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
11279#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
11280#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
11282/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
11283#define FMC_BWTRx_ADDSET_Pos (0U)
11284#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
11285#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
11286#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
11287#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
11288#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
11289#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
11291#define FMC_BWTRx_ADDHLD_Pos (4U)
11292#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
11293#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
11294#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
11295#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
11296#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
11297#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
11299#define FMC_BWTRx_DATAST_Pos (8U)
11300#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
11301#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
11302#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
11303#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
11304#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
11305#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
11306#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
11307#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
11308#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
11309#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
11311#define FMC_BWTRx_BUSTURN_Pos (16U)
11312#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
11313#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
11314#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
11315#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
11316#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
11317#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
11319#define FMC_BWTRx_ACCMOD_Pos (28U)
11320#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
11321#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
11322#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
11323#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
11325/****************** Bit definition for FMC_PCR register *******************/
11326#define FMC_PCR_PWAITEN_Pos (1U)
11327#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
11328#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
11329#define FMC_PCR_PBKEN_Pos (2U)
11330#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
11331#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
11333#define FMC_PCR_PWID_Pos (4U)
11334#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
11335#define FMC_PCR_PWID FMC_PCR_PWID_Msk
11336#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
11337#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
11339#define FMC_PCR_ECCEN_Pos (6U)
11340#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
11341#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
11343#define FMC_PCR_TCLR_Pos (9U)
11344#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
11345#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
11346#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
11347#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
11348#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
11349#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
11351#define FMC_PCR_TAR_Pos (13U)
11352#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
11353#define FMC_PCR_TAR FMC_PCR_TAR_Msk
11354#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
11355#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
11356#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
11357#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
11359#define FMC_PCR_ECCPS_Pos (17U)
11360#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
11361#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
11362#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
11363#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
11364#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
11366/******************* Bit definition for FMC_SR register *******************/
11367#define FMC_SR_IRS_Pos (0U)
11368#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
11369#define FMC_SR_IRS FMC_SR_IRS_Msk
11370#define FMC_SR_ILS_Pos (1U)
11371#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
11372#define FMC_SR_ILS FMC_SR_ILS_Msk
11373#define FMC_SR_IFS_Pos (2U)
11374#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
11375#define FMC_SR_IFS FMC_SR_IFS_Msk
11376#define FMC_SR_IREN_Pos (3U)
11377#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
11378#define FMC_SR_IREN FMC_SR_IREN_Msk
11379#define FMC_SR_ILEN_Pos (4U)
11380#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
11381#define FMC_SR_ILEN FMC_SR_ILEN_Msk
11382#define FMC_SR_IFEN_Pos (5U)
11383#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
11384#define FMC_SR_IFEN FMC_SR_IFEN_Msk
11385#define FMC_SR_FEMPT_Pos (6U)
11386#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
11387#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
11389/****************** Bit definition for FMC_PMEM register ******************/
11390#define FMC_PMEM_MEMSET_Pos (0U)
11391#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
11392#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
11393#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
11394#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
11395#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
11396#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
11397#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
11398#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
11399#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
11400#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
11402#define FMC_PMEM_MEMWAIT_Pos (8U)
11403#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
11404#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
11405#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
11406#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
11407#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
11408#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
11409#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
11410#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
11411#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
11412#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
11414#define FMC_PMEM_MEMHOLD_Pos (16U)
11415#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
11416#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
11417#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
11418#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
11419#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
11420#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
11421#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
11422#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
11423#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
11424#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
11426#define FMC_PMEM_MEMHIZ_Pos (24U)
11427#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
11428#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
11429#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
11430#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
11431#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
11432#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
11433#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
11434#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
11435#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
11436#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
11438/****************** Bit definition for FMC_PATT register ******************/
11439#define FMC_PATT_ATTSET_Pos (0U)
11440#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
11441#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
11442#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
11443#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
11444#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
11445#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
11446#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
11447#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
11448#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
11449#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
11451#define FMC_PATT_ATTWAIT_Pos (8U)
11452#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
11453#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
11454#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
11455#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
11456#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
11457#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
11458#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
11459#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
11460#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
11461#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
11463#define FMC_PATT_ATTHOLD_Pos (16U)
11464#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
11465#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
11466#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
11467#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
11468#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
11469#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
11470#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
11471#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
11472#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
11473#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
11475#define FMC_PATT_ATTHIZ_Pos (24U)
11476#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
11477#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
11478#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
11479#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
11480#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
11481#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
11482#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
11483#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
11484#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
11485#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
11487/****************** Bit definition for FMC_ECCR3 register ******************/
11488#define FMC_ECCR3_ECC3_Pos (0U)
11489#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
11490#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
11492/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
11493#define FMC_SDCRx_NC_Pos (0U)
11494#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos)
11495#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk
11496#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos)
11497#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos)
11499#define FMC_SDCRx_NR_Pos (2U)
11500#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos)
11501#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk
11502#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos)
11503#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos)
11505#define FMC_SDCRx_MWID_Pos (4U)
11506#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos)
11507#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk
11508#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos)
11509#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos)
11511#define FMC_SDCRx_NB_Pos (6U)
11512#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos)
11513#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk
11515#define FMC_SDCRx_CAS_Pos (7U)
11516#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos)
11517#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk
11518#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos)
11519#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos)
11521#define FMC_SDCRx_WP_Pos (9U)
11522#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos)
11523#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk
11525#define FMC_SDCRx_SDCLK_Pos (10U)
11526#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos)
11527#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk
11528#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos)
11529#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
11531#define FMC_SDCRx_RBURST_Pos (12U)
11532#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos)
11533#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk
11535#define FMC_SDCRx_RPIPE_Pos (13U)
11536#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos)
11537#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk
11538#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos)
11539#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos)
11541/****************** Bit definition for FMC_SDTRx(1,2) register ******************/
11542#define FMC_SDTRx_TMRD_Pos (0U)
11543#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos)
11544#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk
11545#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos)
11546#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos)
11547#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos)
11548#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos)
11550#define FMC_SDTRx_TXSR_Pos (4U)
11551#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos)
11552#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk
11553#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos)
11554#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos)
11555#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos)
11556#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos)
11558#define FMC_SDTRx_TRAS_Pos (8U)
11559#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos)
11560#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk
11561#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos)
11562#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos)
11563#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos)
11564#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos)
11566#define FMC_SDTRx_TRC_Pos (12U)
11567#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos)
11568#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk
11569#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos)
11570#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos)
11571#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos)
11573#define FMC_SDTRx_TWR_Pos (16U)
11574#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos)
11575#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk
11576#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos)
11577#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos)
11578#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos)
11580#define FMC_SDTRx_TRP_Pos (20U)
11581#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos)
11582#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk
11583#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos)
11584#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos)
11585#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos)
11587#define FMC_SDTRx_TRCD_Pos (24U)
11588#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos)
11589#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk
11590#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos)
11591#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos)
11592#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos)
11594/****************** Bit definition for FMC_SDCMR register ******************/
11595#define FMC_SDCMR_MODE_Pos (0U)
11596#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
11597#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
11598#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
11599#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
11600#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos)
11602#define FMC_SDCMR_CTB2_Pos (3U)
11603#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
11604#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
11606#define FMC_SDCMR_CTB1_Pos (4U)
11607#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
11608#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
11610#define FMC_SDCMR_NRFS_Pos (5U)
11611#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
11612#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
11613#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
11614#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
11615#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
11616#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
11618#define FMC_SDCMR_MRD_Pos (9U)
11619#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
11620#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
11622/****************** Bit definition for FMC_SDRTR register ******************/
11623#define FMC_SDRTR_CRE_Pos (0U)
11624#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
11625#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
11627#define FMC_SDRTR_COUNT_Pos (1U)
11628#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
11629#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
11631#define FMC_SDRTR_REIE_Pos (14U)
11632#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
11633#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
11635/****************** Bit definition for FMC_SDSR register ******************/
11636#define FMC_SDSR_RE_Pos (0U)
11637#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
11638#define FMC_SDSR_RE FMC_SDSR_RE_Msk
11640#define FMC_SDSR_MODES1_Pos (1U)
11641#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
11642#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
11643#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
11644#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
11646#define FMC_SDSR_MODES2_Pos (3U)
11647#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
11648#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
11649#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
11650#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
11652/******************************************************************************/
11653/* */
11654/* General Purpose I/O */
11655/* */
11656/******************************************************************************/
11657/****************** Bits definition for GPIO_MODER register *****************/
11658#define GPIO_MODER_MODE0_Pos (0U)
11659#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
11660#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11661#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
11662#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
11664#define GPIO_MODER_MODE1_Pos (2U)
11665#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
11666#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11667#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
11668#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
11670#define GPIO_MODER_MODE2_Pos (4U)
11671#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
11672#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11673#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
11674#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
11676#define GPIO_MODER_MODE3_Pos (6U)
11677#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
11678#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11679#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
11680#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
11682#define GPIO_MODER_MODE4_Pos (8U)
11683#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
11684#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11685#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
11686#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
11688#define GPIO_MODER_MODE5_Pos (10U)
11689#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
11690#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11691#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
11692#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
11694#define GPIO_MODER_MODE6_Pos (12U)
11695#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
11696#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11697#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
11698#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
11700#define GPIO_MODER_MODE7_Pos (14U)
11701#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
11702#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11703#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
11704#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
11706#define GPIO_MODER_MODE8_Pos (16U)
11707#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
11708#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11709#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
11710#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
11712#define GPIO_MODER_MODE9_Pos (18U)
11713#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
11714#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11715#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
11716#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
11718#define GPIO_MODER_MODE10_Pos (20U)
11719#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
11720#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11721#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
11722#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
11724#define GPIO_MODER_MODE11_Pos (22U)
11725#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
11726#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11727#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
11728#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
11730#define GPIO_MODER_MODE12_Pos (24U)
11731#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
11732#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11733#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
11734#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
11736#define GPIO_MODER_MODE13_Pos (26U)
11737#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
11738#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11739#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
11740#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
11742#define GPIO_MODER_MODE14_Pos (28U)
11743#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
11744#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11745#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
11746#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
11748#define GPIO_MODER_MODE15_Pos (30U)
11749#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
11750#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11751#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
11752#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
11754/****************** Bits definition for GPIO_OTYPER register ****************/
11755#define GPIO_OTYPER_OT0_Pos (0U)
11756#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
11757#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11758#define GPIO_OTYPER_OT1_Pos (1U)
11759#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
11760#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11761#define GPIO_OTYPER_OT2_Pos (2U)
11762#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
11763#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11764#define GPIO_OTYPER_OT3_Pos (3U)
11765#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
11766#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11767#define GPIO_OTYPER_OT4_Pos (4U)
11768#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
11769#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11770#define GPIO_OTYPER_OT5_Pos (5U)
11771#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
11772#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11773#define GPIO_OTYPER_OT6_Pos (6U)
11774#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
11775#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11776#define GPIO_OTYPER_OT7_Pos (7U)
11777#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
11778#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11779#define GPIO_OTYPER_OT8_Pos (8U)
11780#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
11781#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11782#define GPIO_OTYPER_OT9_Pos (9U)
11783#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
11784#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11785#define GPIO_OTYPER_OT10_Pos (10U)
11786#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
11787#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11788#define GPIO_OTYPER_OT11_Pos (11U)
11789#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
11790#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11791#define GPIO_OTYPER_OT12_Pos (12U)
11792#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
11793#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11794#define GPIO_OTYPER_OT13_Pos (13U)
11795#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
11796#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11797#define GPIO_OTYPER_OT14_Pos (14U)
11798#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
11799#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11800#define GPIO_OTYPER_OT15_Pos (15U)
11801#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
11802#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11803
11804/****************** Bits definition for GPIO_OSPEEDR register ***************/
11805#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11806#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
11807#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11808#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
11809#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
11811#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11812#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
11813#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11814#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
11815#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
11817#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11818#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
11819#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11820#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
11821#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
11823#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11824#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
11825#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11826#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
11827#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
11829#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11830#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
11831#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11832#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
11833#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
11835#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11836#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
11837#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11838#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
11839#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
11841#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11842#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
11843#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11844#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
11845#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
11847#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11848#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
11849#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11850#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
11851#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
11853#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11854#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
11855#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11856#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
11857#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
11859#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
11860#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
11861#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
11862#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
11863#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
11865#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
11866#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
11867#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
11868#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
11869#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
11871#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
11872#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
11873#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
11874#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
11875#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
11877#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
11878#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
11879#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
11880#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
11881#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
11883#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
11884#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
11885#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
11886#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
11887#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
11889#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
11890#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
11891#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
11892#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
11893#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
11895#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
11896#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
11897#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
11898#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
11899#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
11901/****************** Bits definition for GPIO_PUPDR register *****************/
11902#define GPIO_PUPDR_PUPD0_Pos (0U)
11903#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
11904#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
11905#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
11906#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
11908#define GPIO_PUPDR_PUPD1_Pos (2U)
11909#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
11910#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
11911#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
11912#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
11914#define GPIO_PUPDR_PUPD2_Pos (4U)
11915#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
11916#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
11917#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
11918#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
11920#define GPIO_PUPDR_PUPD3_Pos (6U)
11921#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
11922#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
11923#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
11924#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
11926#define GPIO_PUPDR_PUPD4_Pos (8U)
11927#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
11928#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
11929#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
11930#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
11932#define GPIO_PUPDR_PUPD5_Pos (10U)
11933#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
11934#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
11935#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
11936#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
11938#define GPIO_PUPDR_PUPD6_Pos (12U)
11939#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
11940#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
11941#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
11942#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
11944#define GPIO_PUPDR_PUPD7_Pos (14U)
11945#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
11946#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
11947#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
11948#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
11950#define GPIO_PUPDR_PUPD8_Pos (16U)
11951#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
11952#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
11953#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
11954#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
11956#define GPIO_PUPDR_PUPD9_Pos (18U)
11957#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
11958#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
11959#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
11960#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
11962#define GPIO_PUPDR_PUPD10_Pos (20U)
11963#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
11964#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
11965#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
11966#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
11968#define GPIO_PUPDR_PUPD11_Pos (22U)
11969#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
11970#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
11971#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
11972#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
11974#define GPIO_PUPDR_PUPD12_Pos (24U)
11975#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
11976#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
11977#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
11978#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
11980#define GPIO_PUPDR_PUPD13_Pos (26U)
11981#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
11982#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
11983#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
11984#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
11986#define GPIO_PUPDR_PUPD14_Pos (28U)
11987#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
11988#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
11989#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
11990#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
11992#define GPIO_PUPDR_PUPD15_Pos (30U)
11993#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
11994#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
11995#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
11996#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
11998/****************** Bits definition for GPIO_IDR register *******************/
11999#define GPIO_IDR_ID0_Pos (0U)
12000#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
12001#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12002#define GPIO_IDR_ID1_Pos (1U)
12003#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
12004#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12005#define GPIO_IDR_ID2_Pos (2U)
12006#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
12007#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12008#define GPIO_IDR_ID3_Pos (3U)
12009#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
12010#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12011#define GPIO_IDR_ID4_Pos (4U)
12012#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
12013#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12014#define GPIO_IDR_ID5_Pos (5U)
12015#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
12016#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12017#define GPIO_IDR_ID6_Pos (6U)
12018#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
12019#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12020#define GPIO_IDR_ID7_Pos (7U)
12021#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
12022#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12023#define GPIO_IDR_ID8_Pos (8U)
12024#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
12025#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12026#define GPIO_IDR_ID9_Pos (9U)
12027#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
12028#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12029#define GPIO_IDR_ID10_Pos (10U)
12030#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
12031#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12032#define GPIO_IDR_ID11_Pos (11U)
12033#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
12034#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12035#define GPIO_IDR_ID12_Pos (12U)
12036#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
12037#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12038#define GPIO_IDR_ID13_Pos (13U)
12039#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
12040#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12041#define GPIO_IDR_ID14_Pos (14U)
12042#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
12043#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12044#define GPIO_IDR_ID15_Pos (15U)
12045#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
12046#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12047
12048/****************** Bits definition for GPIO_ODR register *******************/
12049#define GPIO_ODR_OD0_Pos (0U)
12050#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
12051#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12052#define GPIO_ODR_OD1_Pos (1U)
12053#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
12054#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12055#define GPIO_ODR_OD2_Pos (2U)
12056#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
12057#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12058#define GPIO_ODR_OD3_Pos (3U)
12059#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
12060#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12061#define GPIO_ODR_OD4_Pos (4U)
12062#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
12063#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12064#define GPIO_ODR_OD5_Pos (5U)
12065#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
12066#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12067#define GPIO_ODR_OD6_Pos (6U)
12068#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
12069#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12070#define GPIO_ODR_OD7_Pos (7U)
12071#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
12072#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12073#define GPIO_ODR_OD8_Pos (8U)
12074#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
12075#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12076#define GPIO_ODR_OD9_Pos (9U)
12077#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
12078#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12079#define GPIO_ODR_OD10_Pos (10U)
12080#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
12081#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12082#define GPIO_ODR_OD11_Pos (11U)
12083#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
12084#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12085#define GPIO_ODR_OD12_Pos (12U)
12086#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
12087#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12088#define GPIO_ODR_OD13_Pos (13U)
12089#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
12090#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12091#define GPIO_ODR_OD14_Pos (14U)
12092#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
12093#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12094#define GPIO_ODR_OD15_Pos (15U)
12095#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
12096#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12097
12098/****************** Bits definition for GPIO_BSRR register ******************/
12099#define GPIO_BSRR_BS0_Pos (0U)
12100#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
12101#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12102#define GPIO_BSRR_BS1_Pos (1U)
12103#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
12104#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12105#define GPIO_BSRR_BS2_Pos (2U)
12106#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
12107#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12108#define GPIO_BSRR_BS3_Pos (3U)
12109#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
12110#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12111#define GPIO_BSRR_BS4_Pos (4U)
12112#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
12113#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12114#define GPIO_BSRR_BS5_Pos (5U)
12115#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
12116#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12117#define GPIO_BSRR_BS6_Pos (6U)
12118#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
12119#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12120#define GPIO_BSRR_BS7_Pos (7U)
12121#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
12122#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12123#define GPIO_BSRR_BS8_Pos (8U)
12124#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
12125#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12126#define GPIO_BSRR_BS9_Pos (9U)
12127#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
12128#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12129#define GPIO_BSRR_BS10_Pos (10U)
12130#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
12131#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12132#define GPIO_BSRR_BS11_Pos (11U)
12133#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
12134#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12135#define GPIO_BSRR_BS12_Pos (12U)
12136#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
12137#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12138#define GPIO_BSRR_BS13_Pos (13U)
12139#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
12140#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12141#define GPIO_BSRR_BS14_Pos (14U)
12142#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
12143#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12144#define GPIO_BSRR_BS15_Pos (15U)
12145#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
12146#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12147#define GPIO_BSRR_BR0_Pos (16U)
12148#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
12149#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12150#define GPIO_BSRR_BR1_Pos (17U)
12151#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
12152#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12153#define GPIO_BSRR_BR2_Pos (18U)
12154#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
12155#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12156#define GPIO_BSRR_BR3_Pos (19U)
12157#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
12158#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12159#define GPIO_BSRR_BR4_Pos (20U)
12160#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
12161#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12162#define GPIO_BSRR_BR5_Pos (21U)
12163#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
12164#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12165#define GPIO_BSRR_BR6_Pos (22U)
12166#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
12167#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12168#define GPIO_BSRR_BR7_Pos (23U)
12169#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
12170#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12171#define GPIO_BSRR_BR8_Pos (24U)
12172#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
12173#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12174#define GPIO_BSRR_BR9_Pos (25U)
12175#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
12176#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12177#define GPIO_BSRR_BR10_Pos (26U)
12178#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
12179#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12180#define GPIO_BSRR_BR11_Pos (27U)
12181#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
12182#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12183#define GPIO_BSRR_BR12_Pos (28U)
12184#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
12185#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12186#define GPIO_BSRR_BR13_Pos (29U)
12187#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
12188#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12189#define GPIO_BSRR_BR14_Pos (30U)
12190#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
12191#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12192#define GPIO_BSRR_BR15_Pos (31U)
12193#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
12194#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12195
12196/****************** Bit definition for GPIO_LCKR register *********************/
12197#define GPIO_LCKR_LCK0_Pos (0U)
12198#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
12199#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12200#define GPIO_LCKR_LCK1_Pos (1U)
12201#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
12202#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12203#define GPIO_LCKR_LCK2_Pos (2U)
12204#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
12205#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12206#define GPIO_LCKR_LCK3_Pos (3U)
12207#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
12208#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12209#define GPIO_LCKR_LCK4_Pos (4U)
12210#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
12211#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12212#define GPIO_LCKR_LCK5_Pos (5U)
12213#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
12214#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12215#define GPIO_LCKR_LCK6_Pos (6U)
12216#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
12217#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12218#define GPIO_LCKR_LCK7_Pos (7U)
12219#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
12220#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12221#define GPIO_LCKR_LCK8_Pos (8U)
12222#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
12223#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12224#define GPIO_LCKR_LCK9_Pos (9U)
12225#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
12226#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12227#define GPIO_LCKR_LCK10_Pos (10U)
12228#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
12229#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12230#define GPIO_LCKR_LCK11_Pos (11U)
12231#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
12232#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12233#define GPIO_LCKR_LCK12_Pos (12U)
12234#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
12235#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12236#define GPIO_LCKR_LCK13_Pos (13U)
12237#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
12238#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12239#define GPIO_LCKR_LCK14_Pos (14U)
12240#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
12241#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12242#define GPIO_LCKR_LCK15_Pos (15U)
12243#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
12244#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12245#define GPIO_LCKR_LCKK_Pos (16U)
12246#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
12247#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12248
12249/****************** Bit definition for GPIO_AFRL register ********************/
12250#define GPIO_AFRL_AFSEL0_Pos (0U)
12251#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
12252#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12253#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
12254#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
12255#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
12256#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
12257#define GPIO_AFRL_AFSEL1_Pos (4U)
12258#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
12259#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12260#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
12261#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
12262#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
12263#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
12264#define GPIO_AFRL_AFSEL2_Pos (8U)
12265#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
12266#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12267#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
12268#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
12269#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
12270#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
12271#define GPIO_AFRL_AFSEL3_Pos (12U)
12272#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
12273#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12274#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
12275#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
12276#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
12277#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
12278#define GPIO_AFRL_AFSEL4_Pos (16U)
12279#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
12280#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12281#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
12282#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
12283#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
12284#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
12285#define GPIO_AFRL_AFSEL5_Pos (20U)
12286#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
12287#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12288#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
12289#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
12290#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
12291#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
12292#define GPIO_AFRL_AFSEL6_Pos (24U)
12293#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
12294#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12295#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
12296#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
12297#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
12298#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
12299#define GPIO_AFRL_AFSEL7_Pos (28U)
12300#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
12301#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12302#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
12303#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
12304#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
12305#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
12307/* Legacy defines */
12308#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12309#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12310#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12311#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12312#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12313#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12314#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12315#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12316
12317/****************** Bit definition for GPIO_AFRH register ********************/
12318#define GPIO_AFRH_AFSEL8_Pos (0U)
12319#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
12320#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12321#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
12322#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
12323#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
12324#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
12325#define GPIO_AFRH_AFSEL9_Pos (4U)
12326#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
12327#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12328#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
12329#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
12330#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
12331#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
12332#define GPIO_AFRH_AFSEL10_Pos (8U)
12333#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
12334#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12335#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
12336#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
12337#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
12338#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
12339#define GPIO_AFRH_AFSEL11_Pos (12U)
12340#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
12341#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12342#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
12343#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
12344#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
12345#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
12346#define GPIO_AFRH_AFSEL12_Pos (16U)
12347#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
12348#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12349#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
12350#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
12351#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
12352#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
12353#define GPIO_AFRH_AFSEL13_Pos (20U)
12354#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
12355#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12356#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
12357#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
12358#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
12359#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
12360#define GPIO_AFRH_AFSEL14_Pos (24U)
12361#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
12362#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12363#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
12364#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
12365#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
12366#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
12367#define GPIO_AFRH_AFSEL15_Pos (28U)
12368#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
12369#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12370#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
12371#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
12372#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
12373#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
12375/* Legacy defines */
12376#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12377#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12378#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12379#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12380#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12381#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12382#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12383#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12384
12385/******************************************************************************/
12386/* */
12387/* HSEM HW Semaphore */
12388/* */
12389/******************************************************************************/
12390/******************** Bit definition for HSEM_R register ********************/
12391#define HSEM_R_PROCID_Pos (0U)
12392#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)
12393#define HSEM_R_PROCID HSEM_R_PROCID_Msk
12394#define HSEM_R_COREID_Pos (8U)
12395#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos)
12396#define HSEM_R_COREID HSEM_R_COREID_Msk
12397#define HSEM_R_LOCK_Pos (31U)
12398#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)
12399#define HSEM_R_LOCK HSEM_R_LOCK_Msk
12401/******************** Bit definition for HSEM_RLR register ******************/
12402#define HSEM_RLR_PROCID_Pos (0U)
12403#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)
12404#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk
12405#define HSEM_RLR_COREID_Pos (8U)
12406#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos)
12407#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk
12408#define HSEM_RLR_LOCK_Pos (31U)
12409#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)
12410#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk
12412/******************** Bit definition for HSEM_C1IER register *****************/
12413#define HSEM_C1IER_ISE0_Pos (0U)
12414#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)
12415#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk
12416#define HSEM_C1IER_ISE1_Pos (1U)
12417#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)
12418#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk
12419#define HSEM_C1IER_ISE2_Pos (2U)
12420#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)
12421#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk
12422#define HSEM_C1IER_ISE3_Pos (3U)
12423#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)
12424#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk
12425#define HSEM_C1IER_ISE4_Pos (4U)
12426#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)
12427#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk
12428#define HSEM_C1IER_ISE5_Pos (5U)
12429#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)
12430#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk
12431#define HSEM_C1IER_ISE6_Pos (6U)
12432#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)
12433#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk
12434#define HSEM_C1IER_ISE7_Pos (7U)
12435#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)
12436#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk
12437#define HSEM_C1IER_ISE8_Pos (8U)
12438#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)
12439#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk
12440#define HSEM_C1IER_ISE9_Pos (9U)
12441#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)
12442#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk
12443#define HSEM_C1IER_ISE10_Pos (10U)
12444#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)
12445#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk
12446#define HSEM_C1IER_ISE11_Pos (11U)
12447#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)
12448#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk
12449#define HSEM_C1IER_ISE12_Pos (12U)
12450#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)
12451#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk
12452#define HSEM_C1IER_ISE13_Pos (13U)
12453#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)
12454#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk
12455#define HSEM_C1IER_ISE14_Pos (14U)
12456#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)
12457#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
12458#define HSEM_C1IER_ISE15_Pos (15U)
12459#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)
12460#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk
12461#define HSEM_C1IER_ISE16_Pos (16U)
12462#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos)
12463#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk
12464#define HSEM_C1IER_ISE17_Pos (17U)
12465#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos)
12466#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk
12467#define HSEM_C1IER_ISE18_Pos (18U)
12468#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos)
12469#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk
12470#define HSEM_C1IER_ISE19_Pos (19U)
12471#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos)
12472#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk
12473#define HSEM_C1IER_ISE20_Pos (20U)
12474#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos)
12475#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk
12476#define HSEM_C1IER_ISE21_Pos (21U)
12477#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos)
12478#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk
12479#define HSEM_C1IER_ISE22_Pos (22U)
12480#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos)
12481#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk
12482#define HSEM_C1IER_ISE23_Pos (23U)
12483#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos)
12484#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk
12485#define HSEM_C1IER_ISE24_Pos (24U)
12486#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos)
12487#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk
12488#define HSEM_C1IER_ISE25_Pos (25U)
12489#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos)
12490#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk
12491#define HSEM_C1IER_ISE26_Pos (26U)
12492#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos)
12493#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk
12494#define HSEM_C1IER_ISE27_Pos (27U)
12495#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos)
12496#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk
12497#define HSEM_C1IER_ISE28_Pos (28U)
12498#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos)
12499#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk
12500#define HSEM_C1IER_ISE29_Pos (29U)
12501#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos)
12502#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk
12503#define HSEM_C1IER_ISE30_Pos (30U)
12504#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos)
12505#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk
12506#define HSEM_C1IER_ISE31_Pos (31U)
12507#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos)
12508#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk
12510/******************** Bit definition for HSEM_C1ICR register *****************/
12511#define HSEM_C1ICR_ISC0_Pos (0U)
12512#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)
12513#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk
12514#define HSEM_C1ICR_ISC1_Pos (1U)
12515#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)
12516#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk
12517#define HSEM_C1ICR_ISC2_Pos (2U)
12518#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)
12519#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk
12520#define HSEM_C1ICR_ISC3_Pos (3U)
12521#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)
12522#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk
12523#define HSEM_C1ICR_ISC4_Pos (4U)
12524#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)
12525#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk
12526#define HSEM_C1ICR_ISC5_Pos (5U)
12527#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)
12528#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk
12529#define HSEM_C1ICR_ISC6_Pos (6U)
12530#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)
12531#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk
12532#define HSEM_C1ICR_ISC7_Pos (7U)
12533#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)
12534#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk
12535#define HSEM_C1ICR_ISC8_Pos (8U)
12536#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)
12537#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk
12538#define HSEM_C1ICR_ISC9_Pos (9U)
12539#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)
12540#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk
12541#define HSEM_C1ICR_ISC10_Pos (10U)
12542#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)
12543#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk
12544#define HSEM_C1ICR_ISC11_Pos (11U)
12545#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)
12546#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk
12547#define HSEM_C1ICR_ISC12_Pos (12U)
12548#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)
12549#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk
12550#define HSEM_C1ICR_ISC13_Pos (13U)
12551#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)
12552#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk
12553#define HSEM_C1ICR_ISC14_Pos (14U)
12554#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)
12555#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk
12556#define HSEM_C1ICR_ISC15_Pos (15U)
12557#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)
12558#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk
12559#define HSEM_C1ICR_ISC16_Pos (16U)
12560#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos)
12561#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk
12562#define HSEM_C1ICR_ISC17_Pos (17U)
12563#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos)
12564#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk
12565#define HSEM_C1ICR_ISC18_Pos (18U)
12566#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos)
12567#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk
12568#define HSEM_C1ICR_ISC19_Pos (19U)
12569#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos)
12570#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk
12571#define HSEM_C1ICR_ISC20_Pos (20U)
12572#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos)
12573#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk
12574#define HSEM_C1ICR_ISC21_Pos (21U)
12575#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos)
12576#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk
12577#define HSEM_C1ICR_ISC22_Pos (22U)
12578#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos)
12579#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk
12580#define HSEM_C1ICR_ISC23_Pos (23U)
12581#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos)
12582#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk
12583#define HSEM_C1ICR_ISC24_Pos (24U)
12584#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos)
12585#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
12586#define HSEM_C1ICR_ISC25_Pos (25U)
12587#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos)
12588#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk
12589#define HSEM_C1ICR_ISC26_Pos (26U)
12590#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos)
12591#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk
12592#define HSEM_C1ICR_ISC27_Pos (27U)
12593#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos)
12594#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk
12595#define HSEM_C1ICR_ISC28_Pos (28U)
12596#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos)
12597#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk
12598#define HSEM_C1ICR_ISC29_Pos (29U)
12599#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos)
12600#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk
12601#define HSEM_C1ICR_ISC30_Pos (30U)
12602#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos)
12603#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk
12604#define HSEM_C1ICR_ISC31_Pos (31U)
12605#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos)
12606#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk
12608/******************** Bit definition for HSEM_C1ISR register *****************/
12609#define HSEM_C1ISR_ISF0_Pos (0U)
12610#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)
12611#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk
12612#define HSEM_C1ISR_ISF1_Pos (1U)
12613#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)
12614#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk
12615#define HSEM_C1ISR_ISF2_Pos (2U)
12616#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)
12617#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk
12618#define HSEM_C1ISR_ISF3_Pos (3U)
12619#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)
12620#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk
12621#define HSEM_C1ISR_ISF4_Pos (4U)
12622#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)
12623#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk
12624#define HSEM_C1ISR_ISF5_Pos (5U)
12625#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)
12626#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk
12627#define HSEM_C1ISR_ISF6_Pos (6U)
12628#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)
12629#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk
12630#define HSEM_C1ISR_ISF7_Pos (7U)
12631#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)
12632#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk
12633#define HSEM_C1ISR_ISF8_Pos (8U)
12634#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)
12635#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk
12636#define HSEM_C1ISR_ISF9_Pos (9U)
12637#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)
12638#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk
12639#define HSEM_C1ISR_ISF10_Pos (10U)
12640#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)
12641#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk
12642#define HSEM_C1ISR_ISF11_Pos (11U)
12643#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)
12644#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk
12645#define HSEM_C1ISR_ISF12_Pos (12U)
12646#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)
12647#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk
12648#define HSEM_C1ISR_ISF13_Pos (13U)
12649#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)
12650#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk
12651#define HSEM_C1ISR_ISF14_Pos (14U)
12652#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)
12653#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk
12654#define HSEM_C1ISR_ISF15_Pos (15U)
12655#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)
12656#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk
12657#define HSEM_C1ISR_ISF16_Pos (16U)
12658#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos)
12659#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk
12660#define HSEM_C1ISR_ISF17_Pos (17U)
12661#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos)
12662#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk
12663#define HSEM_C1ISR_ISF18_Pos (18U)
12664#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos)
12665#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk
12666#define HSEM_C1ISR_ISF19_Pos (19U)
12667#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos)
12668#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk
12669#define HSEM_C1ISR_ISF20_Pos (20U)
12670#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos)
12671#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk
12672#define HSEM_C1ISR_ISF21_Pos (21U)
12673#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos)
12674#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk
12675#define HSEM_C1ISR_ISF22_Pos (22U)
12676#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos)
12677#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk
12678#define HSEM_C1ISR_ISF23_Pos (23U)
12679#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos)
12680#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk
12681#define HSEM_C1ISR_ISF24_Pos (24U)
12682#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos)
12683#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk
12684#define HSEM_C1ISR_ISF25_Pos (25U)
12685#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos)
12686#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk
12687#define HSEM_C1ISR_ISF26_Pos (26U)
12688#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos)
12689#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk
12690#define HSEM_C1ISR_ISF27_Pos (27U)
12691#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos)
12692#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk
12693#define HSEM_C1ISR_ISF28_Pos (28U)
12694#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos)
12695#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk
12696#define HSEM_C1ISR_ISF29_Pos (29U)
12697#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos)
12698#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk
12699#define HSEM_C1ISR_ISF30_Pos (30U)
12700#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos)
12701#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk
12702#define HSEM_C1ISR_ISF31_Pos (31U)
12703#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos)
12704#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk
12706/******************** Bit definition for HSEM_C1MISR register *****************/
12707#define HSEM_C1MISR_MISF0_Pos (0U)
12708#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)
12709#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk
12710#define HSEM_C1MISR_MISF1_Pos (1U)
12711#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)
12712#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk
12713#define HSEM_C1MISR_MISF2_Pos (2U)
12714#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)
12715#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk
12716#define HSEM_C1MISR_MISF3_Pos (3U)
12717#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)
12718#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk
12719#define HSEM_C1MISR_MISF4_Pos (4U)
12720#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)
12721#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk
12722#define HSEM_C1MISR_MISF5_Pos (5U)
12723#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)
12724#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk
12725#define HSEM_C1MISR_MISF6_Pos (6U)
12726#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)
12727#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk
12728#define HSEM_C1MISR_MISF7_Pos (7U)
12729#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)
12730#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk
12731#define HSEM_C1MISR_MISF8_Pos (8U)
12732#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)
12733#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk
12734#define HSEM_C1MISR_MISF9_Pos (9U)
12735#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)
12736#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk
12737#define HSEM_C1MISR_MISF10_Pos (10U)
12738#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)
12739#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk
12740#define HSEM_C1MISR_MISF11_Pos (11U)
12741#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)
12742#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk
12743#define HSEM_C1MISR_MISF12_Pos (12U)
12744#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)
12745#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk
12746#define HSEM_C1MISR_MISF13_Pos (13U)
12747#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)
12748#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk
12749#define HSEM_C1MISR_MISF14_Pos (14U)
12750#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)
12751#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk
12752#define HSEM_C1MISR_MISF15_Pos (15U)
12753#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)
12754#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk
12755#define HSEM_C1MISR_MISF16_Pos (16U)
12756#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos)
12757#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk
12758#define HSEM_C1MISR_MISF17_Pos (17U)
12759#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos)
12760#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk
12761#define HSEM_C1MISR_MISF18_Pos (18U)
12762#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos)
12763#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk
12764#define HSEM_C1MISR_MISF19_Pos (19U)
12765#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos)
12766#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk
12767#define HSEM_C1MISR_MISF20_Pos (20U)
12768#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos)
12769#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk
12770#define HSEM_C1MISR_MISF21_Pos (21U)
12771#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos)
12772#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk
12773#define HSEM_C1MISR_MISF22_Pos (22U)
12774#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos)
12775#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk
12776#define HSEM_C1MISR_MISF23_Pos (23U)
12777#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos)
12778#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk
12779#define HSEM_C1MISR_MISF24_Pos (24U)
12780#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos)
12781#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk
12782#define HSEM_C1MISR_MISF25_Pos (25U)
12783#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos)
12784#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk
12785#define HSEM_C1MISR_MISF26_Pos (26U)
12786#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos)
12787#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk
12788#define HSEM_C1MISR_MISF27_Pos (27U)
12789#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos)
12790#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk
12791#define HSEM_C1MISR_MISF28_Pos (28U)
12792#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos)
12793#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk
12794#define HSEM_C1MISR_MISF29_Pos (29U)
12795#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos)
12796#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk
12797#define HSEM_C1MISR_MISF30_Pos (30U)
12798#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos)
12799#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk
12800#define HSEM_C1MISR_MISF31_Pos (31U)
12801#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos)
12802#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk
12804/******************** Bit definition for HSEM_C2IER register *****************/
12805#define HSEM_C2IER_ISE0_Pos (0U)
12806#define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos)
12807#define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk
12808#define HSEM_C2IER_ISE1_Pos (1U)
12809#define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos)
12810#define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk
12811#define HSEM_C2IER_ISE2_Pos (2U)
12812#define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos)
12813#define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk
12814#define HSEM_C2IER_ISE3_Pos (3U)
12815#define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos)
12816#define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk
12817#define HSEM_C2IER_ISE4_Pos (4U)
12818#define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos)
12819#define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk
12820#define HSEM_C2IER_ISE5_Pos (5U)
12821#define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos)
12822#define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk
12823#define HSEM_C2IER_ISE6_Pos (6U)
12824#define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos)
12825#define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk
12826#define HSEM_C2IER_ISE7_Pos (7U)
12827#define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos)
12828#define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk
12829#define HSEM_C2IER_ISE8_Pos (8U)
12830#define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos)
12831#define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk
12832#define HSEM_C2IER_ISE9_Pos (9U)
12833#define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos)
12834#define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk
12835#define HSEM_C2IER_ISE10_Pos (10U)
12836#define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos)
12837#define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk
12838#define HSEM_C2IER_ISE11_Pos (11U)
12839#define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos)
12840#define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk
12841#define HSEM_C2IER_ISE12_Pos (12U)
12842#define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos)
12843#define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk
12844#define HSEM_C2IER_ISE13_Pos (13U)
12845#define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos)
12846#define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk
12847#define HSEM_C2IER_ISE14_Pos (14U)
12848#define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos)
12849#define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk
12850#define HSEM_C2IER_ISE15_Pos (15U)
12851#define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos)
12852#define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk
12853#define HSEM_C2IER_ISE16_Pos (16U)
12854#define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos)
12855#define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk
12856#define HSEM_C2IER_ISE17_Pos (17U)
12857#define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos)
12858#define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk
12859#define HSEM_C2IER_ISE18_Pos (18U)
12860#define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos)
12861#define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk
12862#define HSEM_C2IER_ISE19_Pos (19U)
12863#define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos)
12864#define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk
12865#define HSEM_C2IER_ISE20_Pos (20U)
12866#define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos)
12867#define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk
12868#define HSEM_C2IER_ISE21_Pos (21U)
12869#define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos)
12870#define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk
12871#define HSEM_C2IER_ISE22_Pos (22U)
12872#define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos)
12873#define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk
12874#define HSEM_C2IER_ISE23_Pos (23U)
12875#define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos)
12876#define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk
12877#define HSEM_C2IER_ISE24_Pos (24U)
12878#define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos)
12879#define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk
12880#define HSEM_C2IER_ISE25_Pos (25U)
12881#define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos)
12882#define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk
12883#define HSEM_C2IER_ISE26_Pos (26U)
12884#define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos)
12885#define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk
12886#define HSEM_C2IER_ISE27_Pos (27U)
12887#define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos)
12888#define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk
12889#define HSEM_C2IER_ISE28_Pos (28U)
12890#define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos)
12891#define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk
12892#define HSEM_C2IER_ISE29_Pos (29U)
12893#define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos)
12894#define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk
12895#define HSEM_C2IER_ISE30_Pos (30U)
12896#define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos)
12897#define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk
12898#define HSEM_C2IER_ISE31_Pos (31U)
12899#define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos)
12900#define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk
12902/******************** Bit definition for HSEM_C2ICR register *****************/
12903#define HSEM_C2ICR_ISC0_Pos (0U)
12904#define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos)
12905#define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk
12906#define HSEM_C2ICR_ISC1_Pos (1U)
12907#define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos)
12908#define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk
12909#define HSEM_C2ICR_ISC2_Pos (2U)
12910#define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos)
12911#define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk
12912#define HSEM_C2ICR_ISC3_Pos (3U)
12913#define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos)
12914#define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk
12915#define HSEM_C2ICR_ISC4_Pos (4U)
12916#define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos)
12917#define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk
12918#define HSEM_C2ICR_ISC5_Pos (5U)
12919#define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos)
12920#define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk
12921#define HSEM_C2ICR_ISC6_Pos (6U)
12922#define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos)
12923#define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk
12924#define HSEM_C2ICR_ISC7_Pos (7U)
12925#define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos)
12926#define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk
12927#define HSEM_C2ICR_ISC8_Pos (8U)
12928#define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos)
12929#define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk
12930#define HSEM_C2ICR_ISC9_Pos (9U)
12931#define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos)
12932#define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk
12933#define HSEM_C2ICR_ISC10_Pos (10U)
12934#define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos)
12935#define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk
12936#define HSEM_C2ICR_ISC11_Pos (11U)
12937#define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos)
12938#define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk
12939#define HSEM_C2ICR_ISC12_Pos (12U)
12940#define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos)
12941#define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk
12942#define HSEM_C2ICR_ISC13_Pos (13U)
12943#define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos)
12944#define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk
12945#define HSEM_C2ICR_ISC14_Pos (14U)
12946#define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos)
12947#define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk
12948#define HSEM_C2ICR_ISC15_Pos (15U)
12949#define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos)
12950#define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk
12951#define HSEM_C2ICR_ISC16_Pos (16U)
12952#define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos)
12953#define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk
12954#define HSEM_C2ICR_ISC17_Pos (17U)
12955#define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos)
12956#define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk
12957#define HSEM_C2ICR_ISC18_Pos (18U)
12958#define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos)
12959#define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk
12960#define HSEM_C2ICR_ISC19_Pos (19U)
12961#define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos)
12962#define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk
12963#define HSEM_C2ICR_ISC20_Pos (20U)
12964#define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos)
12965#define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk
12966#define HSEM_C2ICR_ISC21_Pos (21U)
12967#define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos)
12968#define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk
12969#define HSEM_C2ICR_ISC22_Pos (22U)
12970#define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos)
12971#define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk
12972#define HSEM_C2ICR_ISC23_Pos (23U)
12973#define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos)
12974#define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk
12975#define HSEM_C2ICR_ISC24_Pos (24U)
12976#define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos)
12977#define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk
12978#define HSEM_C2ICR_ISC25_Pos (25U)
12979#define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos)
12980#define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk
12981#define HSEM_C2ICR_ISC26_Pos (26U)
12982#define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos)
12983#define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk
12984#define HSEM_C2ICR_ISC27_Pos (27U)
12985#define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos)
12986#define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk
12987#define HSEM_C2ICR_ISC28_Pos (28U)
12988#define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos)
12989#define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk
12990#define HSEM_C2ICR_ISC29_Pos (29U)
12991#define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos)
12992#define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk
12993#define HSEM_C2ICR_ISC30_Pos (30U)
12994#define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos)
12995#define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk
12996#define HSEM_C2ICR_ISC31_Pos (31U)
12997#define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos)
12998#define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk
13000/******************** Bit definition for HSEM_C2ISR register *****************/
13001#define HSEM_C2ISR_ISF0_Pos (0U)
13002#define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos)
13003#define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk
13004#define HSEM_C2ISR_ISF1_Pos (1U)
13005#define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos)
13006#define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk
13007#define HSEM_C2ISR_ISF2_Pos (2U)
13008#define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos)
13009#define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk
13010#define HSEM_C2ISR_ISF3_Pos (3U)
13011#define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos)
13012#define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk
13013#define HSEM_C2ISR_ISF4_Pos (4U)
13014#define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos)
13015#define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk
13016#define HSEM_C2ISR_ISF5_Pos (5U)
13017#define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos)
13018#define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk
13019#define HSEM_C2ISR_ISF6_Pos (6U)
13020#define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos)
13021#define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk
13022#define HSEM_C2ISR_ISF7_Pos (7U)
13023#define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos)
13024#define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk
13025#define HSEM_C2ISR_ISF8_Pos (8U)
13026#define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos)
13027#define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk
13028#define HSEM_C2ISR_ISF9_Pos (9U)
13029#define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos)
13030#define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk
13031#define HSEM_C2ISR_ISF10_Pos (10U)
13032#define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos)
13033#define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk
13034#define HSEM_C2ISR_ISF11_Pos (11U)
13035#define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos)
13036#define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk
13037#define HSEM_C2ISR_ISF12_Pos (12U)
13038#define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos)
13039#define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk
13040#define HSEM_C2ISR_ISF13_Pos (13U)
13041#define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos)
13042#define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk
13043#define HSEM_C2ISR_ISF14_Pos (14U)
13044#define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos)
13045#define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk
13046#define HSEM_C2ISR_ISF15_Pos (15U)
13047#define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos)
13048#define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk
13049#define HSEM_C2ISR_ISF16_Pos (16U)
13050#define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos)
13051#define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk
13052#define HSEM_C2ISR_ISF17_Pos (17U)
13053#define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos)
13054#define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk
13055#define HSEM_C2ISR_ISF18_Pos (18U)
13056#define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos)
13057#define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk
13058#define HSEM_C2ISR_ISF19_Pos (19U)
13059#define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos)
13060#define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk
13061#define HSEM_C2ISR_ISF20_Pos (20U)
13062#define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos)
13063#define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk
13064#define HSEM_C2ISR_ISF21_Pos (21U)
13065#define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos)
13066#define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk
13067#define HSEM_C2ISR_ISF22_Pos (22U)
13068#define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos)
13069#define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk
13070#define HSEM_C2ISR_ISF23_Pos (23U)
13071#define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos)
13072#define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk
13073#define HSEM_C2ISR_ISF24_Pos (24U)
13074#define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos)
13075#define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk
13076#define HSEM_C2ISR_ISF25_Pos (25U)
13077#define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos)
13078#define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk
13079#define HSEM_C2ISR_ISF26_Pos (26U)
13080#define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos)
13081#define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk
13082#define HSEM_C2ISR_ISF27_Pos (27U)
13083#define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos)
13084#define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk
13085#define HSEM_C2ISR_ISF28_Pos (28U)
13086#define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos)
13087#define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk
13088#define HSEM_C2ISR_ISF29_Pos (29U)
13089#define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos)
13090#define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk
13091#define HSEM_C2ISR_ISF30_Pos (30U)
13092#define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos)
13093#define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk
13094#define HSEM_C2ISR_ISF31_Pos (31U)
13095#define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos)
13096#define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk
13098/******************** Bit definition for HSEM_C2MISR register *****************/
13099#define HSEM_C2MISR_MISF0_Pos (0U)
13100#define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos)
13101#define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk
13102#define HSEM_C2MISR_MISF1_Pos (1U)
13103#define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos)
13104#define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk
13105#define HSEM_C2MISR_MISF2_Pos (2U)
13106#define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos)
13107#define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk
13108#define HSEM_C2MISR_MISF3_Pos (3U)
13109#define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos)
13110#define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk
13111#define HSEM_C2MISR_MISF4_Pos (4U)
13112#define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos)
13113#define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk
13114#define HSEM_C2MISR_MISF5_Pos (5U)
13115#define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos)
13116#define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk
13117#define HSEM_C2MISR_MISF6_Pos (6U)
13118#define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos)
13119#define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk
13120#define HSEM_C2MISR_MISF7_Pos (7U)
13121#define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos)
13122#define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk
13123#define HSEM_C2MISR_MISF8_Pos (8U)
13124#define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos)
13125#define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk
13126#define HSEM_C2MISR_MISF9_Pos (9U)
13127#define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos)
13128#define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk
13129#define HSEM_C2MISR_MISF10_Pos (10U)
13130#define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos)
13131#define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk
13132#define HSEM_C2MISR_MISF11_Pos (11U)
13133#define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos)
13134#define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk
13135#define HSEM_C2MISR_MISF12_Pos (12U)
13136#define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos)
13137#define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk
13138#define HSEM_C2MISR_MISF13_Pos (13U)
13139#define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos)
13140#define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk
13141#define HSEM_C2MISR_MISF14_Pos (14U)
13142#define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos)
13143#define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk
13144#define HSEM_C2MISR_MISF15_Pos (15U)
13145#define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos)
13146#define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk
13147#define HSEM_C2MISR_MISF16_Pos (16U)
13148#define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos)
13149#define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk
13150#define HSEM_C2MISR_MISF17_Pos (17U)
13151#define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos)
13152#define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk
13153#define HSEM_C2MISR_MISF18_Pos (18U)
13154#define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos)
13155#define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk
13156#define HSEM_C2MISR_MISF19_Pos (19U)
13157#define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos)
13158#define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk
13159#define HSEM_C2MISR_MISF20_Pos (20U)
13160#define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos)
13161#define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk
13162#define HSEM_C2MISR_MISF21_Pos (21U)
13163#define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos)
13164#define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk
13165#define HSEM_C2MISR_MISF22_Pos (22U)
13166#define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos)
13167#define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk
13168#define HSEM_C2MISR_MISF23_Pos (23U)
13169#define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos)
13170#define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk
13171#define HSEM_C2MISR_MISF24_Pos (24U)
13172#define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos)
13173#define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk
13174#define HSEM_C2MISR_MISF25_Pos (25U)
13175#define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos)
13176#define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk
13177#define HSEM_C2MISR_MISF26_Pos (26U)
13178#define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos)
13179#define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk
13180#define HSEM_C2MISR_MISF27_Pos (27U)
13181#define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos)
13182#define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk
13183#define HSEM_C2MISR_MISF28_Pos (28U)
13184#define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos)
13185#define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk
13186#define HSEM_C2MISR_MISF29_Pos (29U)
13187#define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos)
13188#define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk
13189#define HSEM_C2MISR_MISF30_Pos (30U)
13190#define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos)
13191#define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk
13192#define HSEM_C2MISR_MISF31_Pos (31U)
13193#define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos)
13194#define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk
13195/******************** Bit definition for HSEM_CR register *****************/
13196#define HSEM_CR_COREID_Pos (8U)
13197#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos)
13198#define HSEM_CR_COREID HSEM_CR_COREID_Msk
13199#define HSEM_CR_KEY_Pos (16U)
13200#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)
13201#define HSEM_CR_KEY HSEM_CR_KEY_Msk
13203/******************** Bit definition for HSEM_KEYR register *****************/
13204#define HSEM_KEYR_KEY_Pos (16U)
13205#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)
13206#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk
13208/******************************************************************************/
13209/* */
13210/* Inter-integrated Circuit Interface (I2C) */
13211/* */
13212/******************************************************************************/
13213/******************* Bit definition for I2C_CR1 register *******************/
13214#define I2C_CR1_PE_Pos (0U)
13215#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
13216#define I2C_CR1_PE I2C_CR1_PE_Msk
13217#define I2C_CR1_TXIE_Pos (1U)
13218#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
13219#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
13220#define I2C_CR1_RXIE_Pos (2U)
13221#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
13222#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
13223#define I2C_CR1_ADDRIE_Pos (3U)
13224#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
13225#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
13226#define I2C_CR1_NACKIE_Pos (4U)
13227#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
13228#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
13229#define I2C_CR1_STOPIE_Pos (5U)
13230#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
13231#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
13232#define I2C_CR1_TCIE_Pos (6U)
13233#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
13234#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
13235#define I2C_CR1_ERRIE_Pos (7U)
13236#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
13237#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
13238#define I2C_CR1_DNF_Pos (8U)
13239#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
13240#define I2C_CR1_DNF I2C_CR1_DNF_Msk
13241#define I2C_CR1_ANFOFF_Pos (12U)
13242#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
13243#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
13244#define I2C_CR1_TXDMAEN_Pos (14U)
13245#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
13246#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
13247#define I2C_CR1_RXDMAEN_Pos (15U)
13248#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
13249#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
13250#define I2C_CR1_SBC_Pos (16U)
13251#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
13252#define I2C_CR1_SBC I2C_CR1_SBC_Msk
13253#define I2C_CR1_NOSTRETCH_Pos (17U)
13254#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
13255#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
13256#define I2C_CR1_WUPEN_Pos (18U)
13257#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
13258#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
13259#define I2C_CR1_GCEN_Pos (19U)
13260#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
13261#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
13262#define I2C_CR1_SMBHEN_Pos (20U)
13263#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
13264#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
13265#define I2C_CR1_SMBDEN_Pos (21U)
13266#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
13267#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
13268#define I2C_CR1_ALERTEN_Pos (22U)
13269#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
13270#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
13271#define I2C_CR1_PECEN_Pos (23U)
13272#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
13273#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
13275/****************** Bit definition for I2C_CR2 register ********************/
13276#define I2C_CR2_SADD_Pos (0U)
13277#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
13278#define I2C_CR2_SADD I2C_CR2_SADD_Msk
13279#define I2C_CR2_RD_WRN_Pos (10U)
13280#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
13281#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
13282#define I2C_CR2_ADD10_Pos (11U)
13283#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
13284#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
13285#define I2C_CR2_HEAD10R_Pos (12U)
13286#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
13287#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
13288#define I2C_CR2_START_Pos (13U)
13289#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
13290#define I2C_CR2_START I2C_CR2_START_Msk
13291#define I2C_CR2_STOP_Pos (14U)
13292#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
13293#define I2C_CR2_STOP I2C_CR2_STOP_Msk
13294#define I2C_CR2_NACK_Pos (15U)
13295#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
13296#define I2C_CR2_NACK I2C_CR2_NACK_Msk
13297#define I2C_CR2_NBYTES_Pos (16U)
13298#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
13299#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
13300#define I2C_CR2_RELOAD_Pos (24U)
13301#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
13302#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
13303#define I2C_CR2_AUTOEND_Pos (25U)
13304#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
13305#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
13306#define I2C_CR2_PECBYTE_Pos (26U)
13307#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
13308#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
13310/******************* Bit definition for I2C_OAR1 register ******************/
13311#define I2C_OAR1_OA1_Pos (0U)
13312#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
13313#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
13314#define I2C_OAR1_OA1MODE_Pos (10U)
13315#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
13316#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
13317#define I2C_OAR1_OA1EN_Pos (15U)
13318#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
13319#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
13321/******************* Bit definition for I2C_OAR2 register ******************/
13322#define I2C_OAR2_OA2_Pos (1U)
13323#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
13324#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
13325#define I2C_OAR2_OA2MSK_Pos (8U)
13326#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
13327#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
13328#define I2C_OAR2_OA2NOMASK 0x00000000UL
13329#define I2C_OAR2_OA2MASK01_Pos (8U)
13330#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
13331#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
13332#define I2C_OAR2_OA2MASK02_Pos (9U)
13333#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
13334#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
13335#define I2C_OAR2_OA2MASK03_Pos (8U)
13336#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
13337#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
13338#define I2C_OAR2_OA2MASK04_Pos (10U)
13339#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
13340#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
13341#define I2C_OAR2_OA2MASK05_Pos (8U)
13342#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
13343#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
13344#define I2C_OAR2_OA2MASK06_Pos (9U)
13345#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
13346#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
13347#define I2C_OAR2_OA2MASK07_Pos (8U)
13348#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
13349#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
13350#define I2C_OAR2_OA2EN_Pos (15U)
13351#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
13352#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
13354/******************* Bit definition for I2C_TIMINGR register *******************/
13355#define I2C_TIMINGR_SCLL_Pos (0U)
13356#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
13357#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
13358#define I2C_TIMINGR_SCLH_Pos (8U)
13359#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
13360#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
13361#define I2C_TIMINGR_SDADEL_Pos (16U)
13362#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
13363#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
13364#define I2C_TIMINGR_SCLDEL_Pos (20U)
13365#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
13366#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
13367#define I2C_TIMINGR_PRESC_Pos (28U)
13368#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
13369#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
13371/******************* Bit definition for I2C_TIMEOUTR register *******************/
13372#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
13373#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
13374#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
13375#define I2C_TIMEOUTR_TIDLE_Pos (12U)
13376#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
13377#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
13378#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
13379#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
13380#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
13381#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
13382#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
13383#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
13384#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
13385#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
13386#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
13388/****************** Bit definition for I2C_ISR register *********************/
13389#define I2C_ISR_TXE_Pos (0U)
13390#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
13391#define I2C_ISR_TXE I2C_ISR_TXE_Msk
13392#define I2C_ISR_TXIS_Pos (1U)
13393#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
13394#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
13395#define I2C_ISR_RXNE_Pos (2U)
13396#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
13397#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
13398#define I2C_ISR_ADDR_Pos (3U)
13399#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
13400#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
13401#define I2C_ISR_NACKF_Pos (4U)
13402#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
13403#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
13404#define I2C_ISR_STOPF_Pos (5U)
13405#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
13406#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
13407#define I2C_ISR_TC_Pos (6U)
13408#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
13409#define I2C_ISR_TC I2C_ISR_TC_Msk
13410#define I2C_ISR_TCR_Pos (7U)
13411#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
13412#define I2C_ISR_TCR I2C_ISR_TCR_Msk
13413#define I2C_ISR_BERR_Pos (8U)
13414#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
13415#define I2C_ISR_BERR I2C_ISR_BERR_Msk
13416#define I2C_ISR_ARLO_Pos (9U)
13417#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
13418#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
13419#define I2C_ISR_OVR_Pos (10U)
13420#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
13421#define I2C_ISR_OVR I2C_ISR_OVR_Msk
13422#define I2C_ISR_PECERR_Pos (11U)
13423#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
13424#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
13425#define I2C_ISR_TIMEOUT_Pos (12U)
13426#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
13427#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
13428#define I2C_ISR_ALERT_Pos (13U)
13429#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
13430#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
13431#define I2C_ISR_BUSY_Pos (15U)
13432#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
13433#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
13434#define I2C_ISR_DIR_Pos (16U)
13435#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
13436#define I2C_ISR_DIR I2C_ISR_DIR_Msk
13437#define I2C_ISR_ADDCODE_Pos (17U)
13438#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
13439#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
13441/****************** Bit definition for I2C_ICR register *********************/
13442#define I2C_ICR_ADDRCF_Pos (3U)
13443#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
13444#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
13445#define I2C_ICR_NACKCF_Pos (4U)
13446#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
13447#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
13448#define I2C_ICR_STOPCF_Pos (5U)
13449#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
13450#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
13451#define I2C_ICR_BERRCF_Pos (8U)
13452#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
13453#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
13454#define I2C_ICR_ARLOCF_Pos (9U)
13455#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
13456#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
13457#define I2C_ICR_OVRCF_Pos (10U)
13458#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
13459#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
13460#define I2C_ICR_PECCF_Pos (11U)
13461#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
13462#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
13463#define I2C_ICR_TIMOUTCF_Pos (12U)
13464#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
13465#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
13466#define I2C_ICR_ALERTCF_Pos (13U)
13467#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
13468#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
13470/****************** Bit definition for I2C_PECR register *********************/
13471#define I2C_PECR_PEC_Pos (0U)
13472#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
13473#define I2C_PECR_PEC I2C_PECR_PEC_Msk
13475/****************** Bit definition for I2C_RXDR register *********************/
13476#define I2C_RXDR_RXDATA_Pos (0U)
13477#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
13478#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
13480/****************** Bit definition for I2C_TXDR register *********************/
13481#define I2C_TXDR_TXDATA_Pos (0U)
13482#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
13483#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
13485/******************************************************************************/
13486/* */
13487/* Independent WATCHDOG */
13488/* */
13489/******************************************************************************/
13490/******************* Bit definition for IWDG_KR register ********************/
13491#define IWDG_KR_KEY_Pos (0U)
13492#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
13493#define IWDG_KR_KEY IWDG_KR_KEY_Msk
13495/******************* Bit definition for IWDG_PR register ********************/
13496#define IWDG_PR_PR_Pos (0U)
13497#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
13498#define IWDG_PR_PR IWDG_PR_PR_Msk
13499#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
13500#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
13501#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
13503/******************* Bit definition for IWDG_RLR register *******************/
13504#define IWDG_RLR_RL_Pos (0U)
13505#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
13506#define IWDG_RLR_RL IWDG_RLR_RL_Msk
13508/******************* Bit definition for IWDG_SR register ********************/
13509#define IWDG_SR_PVU_Pos (0U)
13510#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
13511#define IWDG_SR_PVU IWDG_SR_PVU_Msk
13512#define IWDG_SR_RVU_Pos (1U)
13513#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
13514#define IWDG_SR_RVU IWDG_SR_RVU_Msk
13515#define IWDG_SR_WVU_Pos (2U)
13516#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
13517#define IWDG_SR_WVU IWDG_SR_WVU_Msk
13519/******************* Bit definition for IWDG_KR register ********************/
13520#define IWDG_WINR_WIN_Pos (0U)
13521#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
13522#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
13524/******************************************************************************/
13525/* */
13526/* JPEG Encoder/Decoder */
13527/* */
13528/******************************************************************************/
13529/******************** Bit definition for CONFR0 register ********************/
13530#define JPEG_CONFR0_START_Pos (0U)
13531#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos)
13532#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk
13534/******************** Bit definition for CONFR1 register ********************/
13535#define JPEG_CONFR1_NF_Pos (0U)
13536#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos)
13537#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk
13538#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos)
13539#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos)
13540#define JPEG_CONFR1_DE_Pos (3U)
13541#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos)
13542#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk
13543#define JPEG_CONFR1_COLORSPACE_Pos (4U)
13544#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)
13545#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk
13546#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)
13547#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)
13548#define JPEG_CONFR1_NS_Pos (6U)
13549#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos)
13550#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk
13551#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos)
13552#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos)
13553#define JPEG_CONFR1_HDR_Pos (8U)
13554#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos)
13555#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk
13556#define JPEG_CONFR1_YSIZE_Pos (16U)
13557#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)
13558#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk
13560/******************** Bit definition for CONFR2 register ********************/
13561#define JPEG_CONFR2_NMCU_Pos (0U)
13562#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)
13563#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk
13565/******************** Bit definition for CONFR3 register ********************/
13566#define JPEG_CONFR3_XSIZE_Pos (16U)
13567#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)
13568#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk
13570/******************** Bit definition for CONFR4 register ********************/
13571#define JPEG_CONFR4_HD_Pos (0U)
13572#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos)
13573#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk
13574#define JPEG_CONFR4_HA_Pos (1U)
13575#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos)
13576#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk
13577#define JPEG_CONFR4_QT_Pos (2U)
13578#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos)
13579#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk
13580#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos)
13581#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos)
13582#define JPEG_CONFR4_NB_Pos (4U)
13583#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos)
13584#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk
13585#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos)
13586#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos)
13587#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos)
13588#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos)
13589#define JPEG_CONFR4_VSF_Pos (8U)
13590#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos)
13591#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk
13592#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos)
13593#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos)
13594#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos)
13595#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos)
13596#define JPEG_CONFR4_HSF_Pos (12U)
13597#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos)
13598#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk
13599#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos)
13600#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos)
13601#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos)
13602#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos)
13604/******************** Bit definition for CONFR5 register ********************/
13605#define JPEG_CONFR5_HD_Pos (0U)
13606#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos)
13607#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk
13608#define JPEG_CONFR5_HA_Pos (1U)
13609#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos)
13610#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk
13611#define JPEG_CONFR5_QT_Pos (2U)
13612#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos)
13613#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk
13614#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos)
13615#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos)
13616#define JPEG_CONFR5_NB_Pos (4U)
13617#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos)
13618#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk
13619#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos)
13620#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos)
13621#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos)
13622#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos)
13623#define JPEG_CONFR5_VSF_Pos (8U)
13624#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos)
13625#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk
13626#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos)
13627#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos)
13628#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos)
13629#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos)
13630#define JPEG_CONFR5_HSF_Pos (12U)
13631#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos)
13632#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk
13633#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos)
13634#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos)
13635#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos)
13636#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos)
13638/******************** Bit definition for CONFR6 register ********************/
13639#define JPEG_CONFR6_HD_Pos (0U)
13640#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos)
13641#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk
13642#define JPEG_CONFR6_HA_Pos (1U)
13643#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos)
13644#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk
13645#define JPEG_CONFR6_QT_Pos (2U)
13646#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos)
13647#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk
13648#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos)
13649#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos)
13650#define JPEG_CONFR6_NB_Pos (4U)
13651#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos)
13652#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk
13653#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos)
13654#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos)
13655#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos)
13656#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos)
13657#define JPEG_CONFR6_VSF_Pos (8U)
13658#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos)
13659#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk
13660#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos)
13661#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos)
13662#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos)
13663#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos)
13664#define JPEG_CONFR6_HSF_Pos (12U)
13665#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos)
13666#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk
13667#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos)
13668#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos)
13669#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos)
13670#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos)
13672/******************** Bit definition for CONFR7 register ********************/
13673#define JPEG_CONFR7_HD_Pos (0U)
13674#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos)
13675#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk
13676#define JPEG_CONFR7_HA_Pos (1U)
13677#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos)
13678#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk
13679#define JPEG_CONFR7_QT_Pos (2U)
13680#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos)
13681#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk
13682#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos)
13683#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos)
13684#define JPEG_CONFR7_NB_Pos (4U)
13685#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos)
13686#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk
13687#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos)
13688#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos)
13689#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos)
13690#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos)
13691#define JPEG_CONFR7_VSF_Pos (8U)
13692#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos)
13693#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk
13694#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos)
13695#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos)
13696#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos)
13697#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos)
13698#define JPEG_CONFR7_HSF_Pos (12U)
13699#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos)
13700#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk
13701#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos)
13702#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos)
13703#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos)
13704#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos)
13706/******************** Bit definition for CR register ********************/
13707#define JPEG_CR_JCEN_Pos (0U)
13708#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos)
13709#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk
13710#define JPEG_CR_IFTIE_Pos (1U)
13711#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos)
13712#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk
13713#define JPEG_CR_IFNFIE_Pos (2U)
13714#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos)
13715#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk
13716#define JPEG_CR_OFTIE_Pos (3U)
13717#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos)
13718#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk
13719#define JPEG_CR_OFNEIE_Pos (4U)
13720#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos)
13721#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk
13722#define JPEG_CR_EOCIE_Pos (5U)
13723#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos)
13724#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk
13725#define JPEG_CR_HPDIE_Pos (6U)
13726#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos)
13727#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk
13728#define JPEG_CR_IFF_Pos (13U)
13729#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos)
13730#define JPEG_CR_IFF JPEG_CR_IFF_Msk
13731#define JPEG_CR_OFF_Pos (14U)
13732#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos)
13733#define JPEG_CR_OFF JPEG_CR_OFF_Msk
13735/******************** Bit definition for SR register ********************/
13736#define JPEG_SR_IFTF_Pos (1U)
13737#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos)
13738#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk
13739#define JPEG_SR_IFNFF_Pos (2U)
13740#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos)
13741#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk
13742#define JPEG_SR_OFTF_Pos (3U)
13743#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos)
13744#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk
13745#define JPEG_SR_OFNEF_Pos (4U)
13746#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos)
13747#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk
13748#define JPEG_SR_EOCF_Pos (5U)
13749#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos)
13750#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk
13751#define JPEG_SR_HPDF_Pos (6U)
13752#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos)
13753#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk
13754#define JPEG_SR_COF_Pos (7U)
13755#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos)
13756#define JPEG_SR_COF JPEG_SR_COF_Msk
13758/******************** Bit definition for CFR register ********************/
13759#define JPEG_CFR_CEOCF_Pos (4U)
13760#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos)
13761#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk
13762#define JPEG_CFR_CHPDF_Pos (5U)
13763#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos)
13764#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk
13766/******************** Bit definition for DIR register ********************/
13767#define JPEG_DIR_DATAIN_Pos (0U)
13768#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)
13769#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk
13771/******************** Bit definition for DOR register ********************/
13772#define JPEG_DOR_DATAOUT_Pos (0U)
13773#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos)
13774#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk
13776/******************************************************************************/
13777/* */
13778/* LCD-TFT Display Controller (LTDC) */
13779/* */
13780/******************************************************************************/
13781
13782/******************** Bit definition for LTDC_SSCR register *****************/
13783
13784#define LTDC_SSCR_VSH_Pos (0U)
13785#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
13786#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
13787#define LTDC_SSCR_HSW_Pos (16U)
13788#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
13789#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
13791/******************** Bit definition for LTDC_BPCR register *****************/
13792
13793#define LTDC_BPCR_AVBP_Pos (0U)
13794#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
13795#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
13796#define LTDC_BPCR_AHBP_Pos (16U)
13797#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
13798#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
13800/******************** Bit definition for LTDC_AWCR register *****************/
13801
13802#define LTDC_AWCR_AAH_Pos (0U)
13803#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
13804#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
13805#define LTDC_AWCR_AAW_Pos (16U)
13806#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
13807#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
13809/******************** Bit definition for LTDC_TWCR register *****************/
13810
13811#define LTDC_TWCR_TOTALH_Pos (0U)
13812#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
13813#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
13814#define LTDC_TWCR_TOTALW_Pos (16U)
13815#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
13816#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
13818/******************** Bit definition for LTDC_GCR register ******************/
13819
13820#define LTDC_GCR_LTDCEN_Pos (0U)
13821#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
13822#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
13823#define LTDC_GCR_DBW_Pos (4U)
13824#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
13825#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
13826#define LTDC_GCR_DGW_Pos (8U)
13827#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
13828#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
13829#define LTDC_GCR_DRW_Pos (12U)
13830#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
13831#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
13832#define LTDC_GCR_DEN_Pos (16U)
13833#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
13834#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
13835#define LTDC_GCR_PCPOL_Pos (28U)
13836#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
13837#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
13838#define LTDC_GCR_DEPOL_Pos (29U)
13839#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
13840#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
13841#define LTDC_GCR_VSPOL_Pos (30U)
13842#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
13843#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
13844#define LTDC_GCR_HSPOL_Pos (31U)
13845#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
13846#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
13849/******************** Bit definition for LTDC_SRCR register *****************/
13850
13851#define LTDC_SRCR_IMR_Pos (0U)
13852#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
13853#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
13854#define LTDC_SRCR_VBR_Pos (1U)
13855#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
13856#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
13858/******************** Bit definition for LTDC_BCCR register *****************/
13859
13860#define LTDC_BCCR_BCBLUE_Pos (0U)
13861#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
13862#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
13863#define LTDC_BCCR_BCGREEN_Pos (8U)
13864#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
13865#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
13866#define LTDC_BCCR_BCRED_Pos (16U)
13867#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
13868#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
13870/******************** Bit definition for LTDC_IER register ******************/
13871
13872#define LTDC_IER_LIE_Pos (0U)
13873#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
13874#define LTDC_IER_LIE LTDC_IER_LIE_Msk
13875#define LTDC_IER_FUIE_Pos (1U)
13876#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
13877#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
13878#define LTDC_IER_TERRIE_Pos (2U)
13879#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
13880#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
13881#define LTDC_IER_RRIE_Pos (3U)
13882#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
13883#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
13885/******************** Bit definition for LTDC_ISR register ******************/
13886
13887#define LTDC_ISR_LIF_Pos (0U)
13888#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
13889#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
13890#define LTDC_ISR_FUIF_Pos (1U)
13891#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
13892#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
13893#define LTDC_ISR_TERRIF_Pos (2U)
13894#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
13895#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
13896#define LTDC_ISR_RRIF_Pos (3U)
13897#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
13898#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
13900/******************** Bit definition for LTDC_ICR register ******************/
13901
13902#define LTDC_ICR_CLIF_Pos (0U)
13903#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
13904#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
13905#define LTDC_ICR_CFUIF_Pos (1U)
13906#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
13907#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
13908#define LTDC_ICR_CTERRIF_Pos (2U)
13909#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
13910#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
13911#define LTDC_ICR_CRRIF_Pos (3U)
13912#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
13913#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
13915/******************** Bit definition for LTDC_LIPCR register ****************/
13916
13917#define LTDC_LIPCR_LIPOS_Pos (0U)
13918#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
13919#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
13921/******************** Bit definition for LTDC_CPSR register *****************/
13922
13923#define LTDC_CPSR_CYPOS_Pos (0U)
13924#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
13925#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
13926#define LTDC_CPSR_CXPOS_Pos (16U)
13927#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
13928#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
13930/******************** Bit definition for LTDC_CDSR register *****************/
13931
13932#define LTDC_CDSR_VDES_Pos (0U)
13933#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
13934#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
13935#define LTDC_CDSR_HDES_Pos (1U)
13936#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
13937#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
13938#define LTDC_CDSR_VSYNCS_Pos (2U)
13939#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
13940#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
13941#define LTDC_CDSR_HSYNCS_Pos (3U)
13942#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
13943#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
13945/******************** Bit definition for LTDC_LxCR register *****************/
13946
13947#define LTDC_LxCR_LEN_Pos (0U)
13948#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
13949#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
13950#define LTDC_LxCR_COLKEN_Pos (1U)
13951#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
13952#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
13953#define LTDC_LxCR_CLUTEN_Pos (4U)
13954#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
13955#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
13957/******************** Bit definition for LTDC_LxWHPCR register **************/
13958
13959#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13960#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
13961#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
13962#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13963#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
13964#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
13966/******************** Bit definition for LTDC_LxWVPCR register **************/
13967
13968#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13969#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
13970#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
13971#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13972#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
13973#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
13975/******************** Bit definition for LTDC_LxCKCR register ***************/
13976
13977#define LTDC_LxCKCR_CKBLUE_Pos (0U)
13978#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
13979#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
13980#define LTDC_LxCKCR_CKGREEN_Pos (8U)
13981#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
13982#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
13983#define LTDC_LxCKCR_CKRED_Pos (16U)
13984#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
13985#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
13987/******************** Bit definition for LTDC_LxPFCR register ***************/
13988
13989#define LTDC_LxPFCR_PF_Pos (0U)
13990#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
13991#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
13993/******************** Bit definition for LTDC_LxCACR register ***************/
13994
13995#define LTDC_LxCACR_CONSTA_Pos (0U)
13996#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
13997#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
13999/******************** Bit definition for LTDC_LxDCCR register ***************/
14000
14001#define LTDC_LxDCCR_DCBLUE_Pos (0U)
14002#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
14003#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
14004#define LTDC_LxDCCR_DCGREEN_Pos (8U)
14005#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
14006#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
14007#define LTDC_LxDCCR_DCRED_Pos (16U)
14008#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
14009#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
14010#define LTDC_LxDCCR_DCALPHA_Pos (24U)
14011#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
14012#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
14014/******************** Bit definition for LTDC_LxBFCR register ***************/
14015
14016#define LTDC_LxBFCR_BF2_Pos (0U)
14017#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
14018#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
14019#define LTDC_LxBFCR_BF1_Pos (8U)
14020#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
14021#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
14023/******************** Bit definition for LTDC_LxCFBAR register **************/
14024
14025#define LTDC_LxCFBAR_CFBADD_Pos (0U)
14026#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
14027#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
14029/******************** Bit definition for LTDC_LxCFBLR register **************/
14030
14031#define LTDC_LxCFBLR_CFBLL_Pos (0U)
14032#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
14033#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
14034#define LTDC_LxCFBLR_CFBP_Pos (16U)
14035#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
14036#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
14038/******************** Bit definition for LTDC_LxCFBLNR register *************/
14039
14040#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
14041#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
14042#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
14044/******************** Bit definition for LTDC_LxCLUTWR register *************/
14045
14046#define LTDC_LxCLUTWR_BLUE_Pos (0U)
14047#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
14048#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
14049#define LTDC_LxCLUTWR_GREEN_Pos (8U)
14050#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
14051#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
14052#define LTDC_LxCLUTWR_RED_Pos (16U)
14053#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
14054#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
14055#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
14056#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
14057#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
14059/******************************************************************************/
14060/* */
14061/* MDMA */
14062/* */
14063/******************************************************************************/
14064/******************** Bit definition for MDMA_GISR0 register ****************/
14065#define MDMA_GISR0_GIF0_Pos (0U)
14066#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos)
14067#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk
14068#define MDMA_GISR0_GIF1_Pos (1U)
14069#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos)
14070#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk
14071#define MDMA_GISR0_GIF2_Pos (2U)
14072#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos)
14073#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk
14074#define MDMA_GISR0_GIF3_Pos (3U)
14075#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos)
14076#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk
14077#define MDMA_GISR0_GIF4_Pos (4U)
14078#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos)
14079#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk
14080#define MDMA_GISR0_GIF5_Pos (5U)
14081#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos)
14082#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk
14083#define MDMA_GISR0_GIF6_Pos (6U)
14084#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos)
14085#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk
14086#define MDMA_GISR0_GIF7_Pos (7U)
14087#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos)
14088#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk
14089#define MDMA_GISR0_GIF8_Pos (8U)
14090#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos)
14091#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk
14092#define MDMA_GISR0_GIF9_Pos (9U)
14093#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos)
14094#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk
14095#define MDMA_GISR0_GIF10_Pos (10U)
14096#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos)
14097#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk
14098#define MDMA_GISR0_GIF11_Pos (11U)
14099#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos)
14100#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk
14101#define MDMA_GISR0_GIF12_Pos (12U)
14102#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos)
14103#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk
14104#define MDMA_GISR0_GIF13_Pos (13U)
14105#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos)
14106#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk
14107#define MDMA_GISR0_GIF14_Pos (14U)
14108#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos)
14109#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk
14110#define MDMA_GISR0_GIF15_Pos (15U)
14111#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos)
14112#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk
14114/******************** Bit definition for MDMA_CxISR register ****************/
14115#define MDMA_CISR_TEIF_Pos (0U)
14116#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos)
14117#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk
14118#define MDMA_CISR_CTCIF_Pos (1U)
14119#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos)
14120#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk
14121#define MDMA_CISR_BRTIF_Pos (2U)
14122#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos)
14123#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk
14124#define MDMA_CISR_BTIF_Pos (3U)
14125#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos)
14126#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk
14127#define MDMA_CISR_TCIF_Pos (4U)
14128#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
14129#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk
14130#define MDMA_CISR_CRQA_Pos (16U)
14131#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos)
14132#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk
14134/******************** Bit definition for MDMA_CxIFCR register ****************/
14135#define MDMA_CIFCR_CTEIF_Pos (0U)
14136#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos)
14137#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk
14138#define MDMA_CIFCR_CCTCIF_Pos (1U)
14139#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
14140#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk
14141#define MDMA_CIFCR_CBRTIF_Pos (2U)
14142#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
14143#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk
14144#define MDMA_CIFCR_CBTIF_Pos (3U)
14145#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos)
14146#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk
14147#define MDMA_CIFCR_CLTCIF_Pos (4U)
14148#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
14149#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk
14151/******************** Bit definition for MDMA_CxESR register ****************/
14152#define MDMA_CESR_TEA_Pos (0U)
14153#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos)
14154#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk
14155#define MDMA_CESR_TED_Pos (7U)
14156#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos)
14157#define MDMA_CESR_TED MDMA_CESR_TED_Msk
14158#define MDMA_CESR_TELD_Pos (8U)
14159#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos)
14160#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk
14161#define MDMA_CESR_TEMD_Pos (9U)
14162#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos)
14163#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk
14164#define MDMA_CESR_ASE_Pos (10U)
14165#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos)
14166#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk
14167#define MDMA_CESR_BSE_Pos (11U)
14168#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos)
14169#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk
14171/******************** Bit definition for MDMA_CxCR register ****************/
14172#define MDMA_CCR_EN_Pos (0U)
14173#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos)
14174#define MDMA_CCR_EN MDMA_CCR_EN_Msk
14175#define MDMA_CCR_TEIE_Pos (1U)
14176#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos)
14177#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk
14178#define MDMA_CCR_CTCIE_Pos (2U)
14179#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos)
14180#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk
14181#define MDMA_CCR_BRTIE_Pos (3U)
14182#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos)
14183#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk
14184#define MDMA_CCR_BTIE_Pos (4U)
14185#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos)
14186#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk
14187#define MDMA_CCR_TCIE_Pos (5U)
14188#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos)
14189#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk
14190#define MDMA_CCR_PL_Pos (6U)
14191#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos)
14192#define MDMA_CCR_PL MDMA_CCR_PL_Msk
14193#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos)
14194#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos)
14195#define MDMA_CCR_BEX_Pos (12U)
14196#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos)
14197#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk
14198#define MDMA_CCR_HEX_Pos (13U)
14199#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos)
14200#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk
14201#define MDMA_CCR_WEX_Pos (14U)
14202#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos)
14203#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk
14204#define MDMA_CCR_SWRQ_Pos (16U)
14205#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos)
14206#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk
14208/******************** Bit definition for MDMA_CxTCR register ****************/
14209#define MDMA_CTCR_SINC_Pos (0U)
14210#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos)
14211#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk
14212#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos)
14213#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos)
14214#define MDMA_CTCR_DINC_Pos (2U)
14215#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos)
14216#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk
14217#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos)
14218#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos)
14219#define MDMA_CTCR_SSIZE_Pos (4U)
14220#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos)
14221#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk
14222#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos)
14223#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos)
14224#define MDMA_CTCR_DSIZE_Pos (6U)
14225#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos)
14226#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk
14227#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos)
14228#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos)
14229#define MDMA_CTCR_SINCOS_Pos (8U)
14230#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos)
14231#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk
14232#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos)
14233#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos)
14234#define MDMA_CTCR_DINCOS_Pos (10U)
14235#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos)
14236#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk
14237#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos)
14238#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos)
14239#define MDMA_CTCR_SBURST_Pos (12U)
14240#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos)
14241#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk
14242#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos)
14243#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos)
14244#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos)
14245#define MDMA_CTCR_DBURST_Pos (15U)
14246#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos)
14247#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk
14248#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos)
14249#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos)
14250#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos)
14251#define MDMA_CTCR_TLEN_Pos (18U)
14252#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos)
14253#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk
14254#define MDMA_CTCR_PKE_Pos (25U)
14255#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos)
14256#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
14257#define MDMA_CTCR_PAM_Pos (26U)
14258#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos)
14259#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk
14260#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos)
14261#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos)
14262#define MDMA_CTCR_TRGM_Pos (28U)
14263#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos)
14264#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk
14265#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos)
14266#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos)
14267#define MDMA_CTCR_SWRM_Pos (30U)
14268#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos)
14269#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk
14270#define MDMA_CTCR_BWM_Pos (31U)
14271#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos)
14272#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk
14274/******************** Bit definition for MDMA_CxBNDTR register ****************/
14275#define MDMA_CBNDTR_BNDT_Pos (0U)
14276#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
14277#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk
14278#define MDMA_CBNDTR_BRSUM_Pos (18U)
14279#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
14280#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk
14281#define MDMA_CBNDTR_BRDUM_Pos (19U)
14282#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
14283#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk
14284#define MDMA_CBNDTR_BRC_Pos (20U)
14285#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
14286#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk
14288/******************** Bit definition for MDMA_CxSAR register ****************/
14289#define MDMA_CSAR_SAR_Pos (0U)
14290#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
14291#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk
14293/******************** Bit definition for MDMA_CxDAR register ****************/
14294#define MDMA_CDAR_DAR_Pos (0U)
14295#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
14296#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk
14298/******************** Bit definition for MDMA_CxBRUR ************************/
14299#define MDMA_CBRUR_SUV_Pos (0U)
14300#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
14301#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk
14302#define MDMA_CBRUR_DUV_Pos (16U)
14303#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
14304#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk
14306/******************** Bit definition for MDMA_CxLAR *************************/
14307#define MDMA_CLAR_LAR_Pos (0U)
14308#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
14309#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk
14311/******************** Bit definition for MDMA_CxTBR) ************************/
14312#define MDMA_CTBR_TSEL_Pos (0U)
14313#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos)
14314#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk
14315#define MDMA_CTBR_SBUS_Pos (16U)
14316#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos)
14317#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk
14318#define MDMA_CTBR_DBUS_Pos (17U)
14319#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos)
14320#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk
14322/******************** Bit definition for MDMA_CxMAR) ************************/
14323#define MDMA_CMAR_MAR_Pos (0U)
14324#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
14325#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk
14327/******************** Bit definition for MDMA_CxMDR) ************************/
14328#define MDMA_CMDR_MDR_Pos (0U)
14329#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
14330#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk
14332/******************************************************************************/
14333/* */
14334/* Operational Amplifier (OPAMP) */
14335/* */
14336/******************************************************************************/
14337/********************* Bit definition for OPAMPx_CSR register ***************/
14338#define OPAMP_CSR_OPAMPxEN_Pos (0U)
14339#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
14340#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
14341#define OPAMP_CSR_FORCEVP_Pos (1U)
14342#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
14343#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
14345#define OPAMP_CSR_VPSEL_Pos (2U)
14346#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
14347#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
14348#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
14349#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
14351#define OPAMP_CSR_VMSEL_Pos (5U)
14352#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
14353#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
14354#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
14355#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
14357#define OPAMP_CSR_OPAHSM_Pos (8U)
14358#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos)
14359#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk
14360#define OPAMP_CSR_CALON_Pos (11U)
14361#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
14362#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
14364#define OPAMP_CSR_CALSEL_Pos (12U)
14365#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
14366#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
14367#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
14368#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
14370#define OPAMP_CSR_PGGAIN_Pos (14U)
14371#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
14372#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
14373#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
14374#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
14375#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
14376#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
14378#define OPAMP_CSR_USERTRIM_Pos (18U)
14379#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
14380#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
14381#define OPAMP_CSR_TSTREF_Pos (29U)
14382#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
14383#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
14384#define OPAMP_CSR_CALOUT_Pos (30U)
14385#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
14386#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
14388/********************* Bit definition for OPAMP1_CSR register ***************/
14389#define OPAMP1_CSR_OPAEN_Pos (0U)
14390#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
14391#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
14392#define OPAMP1_CSR_FORCEVP_Pos (1U)
14393#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
14394#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
14396#define OPAMP1_CSR_VPSEL_Pos (2U)
14397#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
14398#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
14399#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
14400#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
14402#define OPAMP1_CSR_VMSEL_Pos (5U)
14403#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
14404#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
14405#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
14406#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
14408#define OPAMP1_CSR_OPAHSM_Pos (8U)
14409#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
14410#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk
14411#define OPAMP1_CSR_CALON_Pos (11U)
14412#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
14413#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
14415#define OPAMP1_CSR_CALSEL_Pos (12U)
14416#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
14417#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
14418#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
14419#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
14421#define OPAMP1_CSR_PGGAIN_Pos (14U)
14422#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
14423#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
14424#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
14425#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
14426#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
14427#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
14429#define OPAMP1_CSR_USERTRIM_Pos (18U)
14430#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
14431#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
14432#define OPAMP1_CSR_TSTREF_Pos (29U)
14433#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
14434#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
14435#define OPAMP1_CSR_CALOUT_Pos (30U)
14436#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
14437#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
14439/********************* Bit definition for OPAMP2_CSR register ***************/
14440#define OPAMP2_CSR_OPAEN_Pos (0U)
14441#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
14442#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
14443#define OPAMP2_CSR_FORCEVP_Pos (1U)
14444#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
14445#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
14447#define OPAMP2_CSR_VPSEL_Pos (2U)
14448#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
14449#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
14450#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
14451#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
14453#define OPAMP2_CSR_VMSEL_Pos (5U)
14454#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
14455#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
14456#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
14457#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
14459#define OPAMP2_CSR_OPAHSM_Pos (8U)
14460#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
14461#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk
14462#define OPAMP2_CSR_CALON_Pos (11U)
14463#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
14464#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
14466#define OPAMP2_CSR_CALSEL_Pos (12U)
14467#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
14468#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
14469#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
14470#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
14472#define OPAMP2_CSR_PGGAIN_Pos (14U)
14473#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
14474#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
14475#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
14476#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
14477#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
14478#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
14480#define OPAMP2_CSR_USERTRIM_Pos (18U)
14481#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
14482#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
14483#define OPAMP2_CSR_TSTREF_Pos (29U)
14484#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
14485#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
14486#define OPAMP2_CSR_CALOUT_Pos (30U)
14487#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
14488#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
14490/******************* Bit definition for OPAMP_OTR register ******************/
14491#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
14492#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
14493#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
14494#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
14495#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
14496#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
14498/******************* Bit definition for OPAMP1_OTR register ******************/
14499#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
14500#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
14501#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
14502#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
14503#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
14504#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
14506/******************* Bit definition for OPAMP2_OTR register ******************/
14507#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
14508#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
14509#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
14510#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
14511#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
14512#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
14514/******************* Bit definition for OPAMP_HSOTR register ****************/
14515#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
14516#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
14517#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk
14518#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
14519#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
14520#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk
14522/******************* Bit definition for OPAMP1_HSOTR register ****************/
14523#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
14524#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
14525#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
14526#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
14527#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
14528#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
14530/******************* Bit definition for OPAMP2_HSOTR register ****************/
14531#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
14532#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
14533#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
14534#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
14535#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
14536#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
14538/******************************************************************************/
14539/* */
14540/* Power Control */
14541/* */
14542/******************************************************************************/
14543/************************* NUMBER OF POWER DOMAINS **************************/
14544#define POWER_DOMAINS_NUMBER 3U
14546/******************** Bit definition for PWR_CR1 register *******************/
14547#define PWR_CR1_ALS_Pos (17U)
14548#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos)
14549#define PWR_CR1_ALS PWR_CR1_ALS_Msk
14550#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos)
14551#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos)
14552#define PWR_CR1_AVDEN_Pos (16U)
14553#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos)
14554#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk
14555#define PWR_CR1_SVOS_Pos (14U)
14556#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos)
14557#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk
14558#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos)
14559#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos)
14560#define PWR_CR1_FLPS_Pos (9U)
14561#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos)
14562#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk
14563#define PWR_CR1_DBP_Pos (8U)
14564#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
14565#define PWR_CR1_DBP PWR_CR1_DBP_Msk
14566#define PWR_CR1_PLS_Pos (5U)
14567#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
14568#define PWR_CR1_PLS PWR_CR1_PLS_Msk
14569#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
14570#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
14571#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
14572#define PWR_CR1_PVDEN_Pos (4U)
14573#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos)
14574#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk
14575#define PWR_CR1_LPDS_Pos (0U)
14576#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
14577#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
14580#define PWR_CR1_PLS_LEV0 (0UL)
14581#define PWR_CR1_PLS_LEV1_Pos (5U)
14582#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
14583#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
14584#define PWR_CR1_PLS_LEV2_Pos (6U)
14585#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
14586#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
14587#define PWR_CR1_PLS_LEV3_Pos (5U)
14588#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
14589#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
14590#define PWR_CR1_PLS_LEV4_Pos (7U)
14591#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
14592#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
14593#define PWR_CR1_PLS_LEV5_Pos (5U)
14594#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
14595#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
14596#define PWR_CR1_PLS_LEV6_Pos (6U)
14597#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
14598#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
14599#define PWR_CR1_PLS_LEV7_Pos (5U)
14600#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
14601#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
14604#define PWR_CR1_ALS_LEV0 (0UL)
14605#define PWR_CR1_ALS_LEV1_Pos (17U)
14606#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos)
14607#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk
14608#define PWR_CR1_ALS_LEV2_Pos (18U)
14609#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos)
14610#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk
14611#define PWR_CR1_ALS_LEV3_Pos (17U)
14612#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos)
14613#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk
14615/******************** Bit definition for PWR_CSR1 register ******************/
14616#define PWR_CSR1_AVDO_Pos (16U)
14617#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos)
14618#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk
14619#define PWR_CSR1_ACTVOS_Pos (14U)
14620#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos)
14621#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk
14622#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos)
14623#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos)
14624#define PWR_CSR1_ACTVOSRDY_Pos (13U)
14625#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
14626#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk
14627#define PWR_CSR1_PVDO_Pos (4U)
14628#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
14629#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
14631/******************** Bit definition for PWR_CR2 register *******************/
14632#define PWR_CR2_TEMPH_Pos (23U)
14633#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos)
14634#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk
14635#define PWR_CR2_TEMPL_Pos (22U)
14636#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos)
14637#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk
14638#define PWR_CR2_VBATH_Pos (21U)
14639#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos)
14640#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk
14641#define PWR_CR2_VBATL_Pos (20U)
14642#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos)
14643#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk
14644#define PWR_CR2_BRRDY_Pos (16U)
14645#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos)
14646#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk
14647#define PWR_CR2_MONEN_Pos (4U)
14648#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos)
14649#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk
14650#define PWR_CR2_BREN_Pos (0U)
14651#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos)
14652#define PWR_CR2_BREN PWR_CR2_BREN_Msk
14654/******************** Bit definition for PWR_CR3 register *******************/
14655#define PWR_CR3_USB33RDY_Pos (26U)
14656#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos)
14657#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk
14658#define PWR_CR3_USBREGEN_Pos (25U)
14659#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos)
14660#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk
14661#define PWR_CR3_USB33DEN_Pos (24U)
14662#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos)
14663#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk
14664#define PWR_CR3_SMPSEXTRDY_Pos (16U)
14665#define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)
14666#define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk
14667#define PWR_CR3_VBRS_Pos (9U)
14668#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos)
14669#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk
14670#define PWR_CR3_VBE_Pos (8U)
14671#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos)
14672#define PWR_CR3_VBE PWR_CR3_VBE_Msk
14673#define PWR_CR3_SMPSLEVEL_Pos (4U)
14674#define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos)
14675#define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk
14676#define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos)
14677#define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos)
14678#define PWR_CR3_SMPSEXTHP_Pos (3U)
14679#define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos)
14680#define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk
14681#define PWR_CR3_SMPSEN_Pos (2U)
14682#define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos)
14683#define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk
14684#define PWR_CR3_LDOEN_Pos (1U)
14685#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos)
14686#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk
14687#define PWR_CR3_BYPASS_Pos (0U)
14688#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos)
14689#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk
14691/******************** Bit definition for PWR_CPUCR register *****************/
14692#define PWR_CPUCR_RUN_D3_Pos (11U)
14693#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos)
14694#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk
14695#define PWR_CPUCR_HOLD2_Pos (10U)
14696#define PWR_CPUCR_HOLD2_Msk (0x1UL << PWR_CPUCR_HOLD2_Pos)
14697#define PWR_CPUCR_HOLD2 PWR_CPUCR_HOLD2_Msk
14698#define PWR_CPUCR_CSSF_Pos (9U)
14699#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos)
14700#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk
14701#define PWR_CPUCR_SBF_D2_Pos (8U)
14702#define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos)
14703#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk
14704#define PWR_CPUCR_SBF_D1_Pos (7U)
14705#define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos)
14706#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk
14707#define PWR_CPUCR_SBF_Pos (6U)
14708#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos)
14709#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk
14710#define PWR_CPUCR_STOPF_Pos (5U)
14711#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos)
14712#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk
14713#define PWR_CPUCR_HOLD2F_Pos (4U)
14714#define PWR_CPUCR_HOLD2F_Msk (0x1UL << PWR_CPUCR_HOLD2F_Pos)
14715#define PWR_CPUCR_HOLD2F PWR_CPUCR_HOLD2F_Msk
14716#define PWR_CPUCR_PDDS_D3_Pos (2U)
14717#define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos)
14718#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk
14719#define PWR_CPUCR_PDDS_D2_Pos (1U)
14720#define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos)
14721#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk
14722#define PWR_CPUCR_PDDS_D1_Pos (0U)
14723#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos)
14724#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk
14726/******************** Bit definition for PWR_CPU2CR register ****************/
14727#define PWR_CPU2CR_RUN_D3_Pos (11U)
14728#define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos)
14729#define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk
14730#define PWR_CPU2CR_HOLD1_Pos (10U)
14731#define PWR_CPU2CR_HOLD1_Msk (0x1UL << PWR_CPU2CR_HOLD1_Pos)
14732#define PWR_CPU2CR_HOLD1 PWR_CPU2CR_HOLD1_Msk
14733#define PWR_CPU2CR_CSSF_Pos (9U)
14734#define PWR_CPU2CR_CSSF_Msk (0x1UL << PWR_CPU2CR_CSSF_Pos)
14735#define PWR_CPU2CR_CSSF PWR_CPU2CR_CSSF_Msk
14736#define PWR_CPU2CR_SBF_D2_Pos (8U)
14737#define PWR_CPU2CR_SBF_D2_Msk (0x1UL << PWR_CPU2CR_SBF_D2_Pos)
14738#define PWR_CPU2CR_SBF_D2 PWR_CPU2CR_SBF_D2_Msk
14739#define PWR_CPU2CR_SBF_D1_Pos (7U)
14740#define PWR_CPU2CR_SBF_D1_Msk (0x1UL << PWR_CPU2CR_SBF_D1_Pos)
14741#define PWR_CPU2CR_SBF_D1 PWR_CPU2CR_SBF_D1_Msk
14742#define PWR_CPU2CR_SBF_Pos (6U)
14743#define PWR_CPU2CR_SBF_Msk (0x1UL << PWR_CPU2CR_SBF_Pos)
14744#define PWR_CPU2CR_SBF PWR_CPU2CR_SBF_Msk
14745#define PWR_CPU2CR_STOPF_Pos (5U)
14746#define PWR_CPU2CR_STOPF_Msk (0x1UL << PWR_CPU2CR_STOPF_Pos)
14747#define PWR_CPU2CR_STOPF PWR_CPU2CR_STOPF_Msk
14748#define PWR_CPU2CR_HOLD1F_Pos (4U)
14749#define PWR_CPU2CR_HOLD1F_Msk (0x1UL << PWR_CPU2CR_HOLD1F_Pos)
14750#define PWR_CPU2CR_HOLD1F PWR_CPU2CR_HOLD1F_Msk
14751#define PWR_CPU2CR_PDDS_D3_Pos (2U)
14752#define PWR_CPU2CR_PDDS_D3_Msk (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)
14753#define PWR_CPU2CR_PDDS_D3 PWR_CPU2CR_PDDS_D3_Msk
14754#define PWR_CPU2CR_PDDS_D2_Pos (1U)
14755#define PWR_CPU2CR_PDDS_D2_Msk (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)
14756#define PWR_CPU2CR_PDDS_D2 PWR_CPU2CR_PDDS_D2_Msk
14757#define PWR_CPU2CR_PDDS_D1_Pos (0U)
14758#define PWR_CPU2CR_PDDS_D1_Msk (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)
14759#define PWR_CPU2CR_PDDS_D1 PWR_CPU2CR_PDDS_D1_Msk
14762/******************** Bit definition for PWR_D3CR register ******************/
14763#define PWR_D3CR_VOS_Pos (14U)
14764#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos)
14765#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk
14766#define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos)
14767#define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos)
14768#define PWR_D3CR_VOSRDY_Pos (13U)
14769#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos)
14770#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk
14772/****************** Bit definition for PWR_WKUPCR register ******************/
14773#define PWR_WKUPCR_WKUPC6_Pos (5U)
14774#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
14775#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk
14776#define PWR_WKUPCR_WKUPC5_Pos (4U)
14777#define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos)
14778#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk
14779#define PWR_WKUPCR_WKUPC4_Pos (3U)
14780#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
14781#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk
14782#define PWR_WKUPCR_WKUPC3_Pos (2U)
14783#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos)
14784#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk
14785#define PWR_WKUPCR_WKUPC2_Pos (1U)
14786#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
14787#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk
14788#define PWR_WKUPCR_WKUPC1_Pos (0U)
14789#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
14790#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk
14792/******************** Bit definition for PWR_WKUPFR register ****************/
14793#define PWR_WKUPFR_WKUPF6_Pos (5U)
14794#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
14795#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk
14796#define PWR_WKUPFR_WKUPF5_Pos (4U)
14797#define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos)
14798#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk
14799#define PWR_WKUPFR_WKUPF4_Pos (3U)
14800#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
14801#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk
14802#define PWR_WKUPFR_WKUPF3_Pos (2U)
14803#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos)
14804#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk
14805#define PWR_WKUPFR_WKUPF2_Pos (1U)
14806#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
14807#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk
14808#define PWR_WKUPFR_WKUPF1_Pos (0U)
14809#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
14810#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk
14812/****************** Bit definition for PWR_WKUPEPR register *****************/
14813#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
14814#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14815#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk
14816#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14817#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
14818#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
14819#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
14820#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk
14821#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
14822#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
14823#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
14824#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14825#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk
14826#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14827#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
14828#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
14829#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
14830#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk
14831#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
14832#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
14833#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
14834#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14835#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk
14836#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14837#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
14838#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
14839#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14840#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk
14841#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14842#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
14843#define PWR_WKUPEPR_WKUPP6_Pos (13U)
14844#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
14845#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk
14846#define PWR_WKUPEPR_WKUPP5_Pos (12U)
14847#define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)
14848#define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk
14849#define PWR_WKUPEPR_WKUPP4_Pos (11U)
14850#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
14851#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk
14852#define PWR_WKUPEPR_WKUPP3_Pos (10U)
14853#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)
14854#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk
14855#define PWR_WKUPEPR_WKUPP2_Pos (9U)
14856#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
14857#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk
14858#define PWR_WKUPEPR_WKUPP1_Pos (8U)
14859#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
14860#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk
14861#define PWR_WKUPEPR_WKUPEN6_Pos (5U)
14862#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
14863#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk
14864#define PWR_WKUPEPR_WKUPEN5_Pos (4U)
14865#define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)
14866#define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk
14867#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
14868#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
14869#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk
14870#define PWR_WKUPEPR_WKUPEN3_Pos (2U)
14871#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)
14872#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk
14873#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
14874#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
14875#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk
14876#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
14877#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
14878#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk
14879#define PWR_WKUPEPR_WKUPEN_Pos (0U)
14880#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
14881#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk
14883/******************************************************************************/
14884/* */
14885/* Reset and Clock Control */
14886/* */
14887/******************************************************************************/
14888/******************************* RCC VERSION ********************************/
14889#define RCC_VER_X
14890
14891/******************** Bit definition for RCC_CR register ********************/
14892#define RCC_CR_HSION_Pos (0U)
14893#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
14894#define RCC_CR_HSION RCC_CR_HSION_Msk
14895#define RCC_CR_HSIKERON_Pos (1U)
14896#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
14897#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
14898#define RCC_CR_HSIRDY_Pos (2U)
14899#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
14900#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
14901#define RCC_CR_HSIDIV_Pos (3U)
14902#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos)
14903#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk
14904#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos)
14905#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos)
14906#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos)
14907#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos)
14909#define RCC_CR_HSIDIVF_Pos (5U)
14910#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
14911#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
14912#define RCC_CR_CSION_Pos (7U)
14913#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos)
14914#define RCC_CR_CSION RCC_CR_CSION_Msk
14915#define RCC_CR_CSIRDY_Pos (8U)
14916#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos)
14917#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk
14918#define RCC_CR_CSIKERON_Pos (9U)
14919#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos)
14920#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk
14921#define RCC_CR_HSI48ON_Pos (12U)
14922#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos)
14923#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk
14924#define RCC_CR_HSI48RDY_Pos (13U)
14925#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos)
14926#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk
14928#define RCC_CR_D1CKRDY_Pos (14U)
14929#define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos)
14930#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk
14931#define RCC_CR_D2CKRDY_Pos (15U)
14932#define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos)
14933#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk
14935#define RCC_CR_HSEON_Pos (16U)
14936#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
14937#define RCC_CR_HSEON RCC_CR_HSEON_Msk
14938#define RCC_CR_HSERDY_Pos (17U)
14939#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
14940#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
14941#define RCC_CR_HSEBYP_Pos (18U)
14942#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
14943#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
14944#define RCC_CR_CSSHSEON_Pos (19U)
14945#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
14946#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
14949#define RCC_CR_PLL1ON_Pos (24U)
14950#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos)
14951#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk
14952#define RCC_CR_PLL1RDY_Pos (25U)
14953#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos)
14954#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk
14955#define RCC_CR_PLL2ON_Pos (26U)
14956#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
14957#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
14958#define RCC_CR_PLL2RDY_Pos (27U)
14959#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
14960#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
14961#define RCC_CR_PLL3ON_Pos (28U)
14962#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
14963#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
14964#define RCC_CR_PLL3RDY_Pos (29U)
14965#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
14966#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
14968/*Legacy */
14969#define RCC_CR_PLLON_Pos (24U)
14970#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
14971#define RCC_CR_PLLON RCC_CR_PLLON_Msk
14972#define RCC_CR_PLLRDY_Pos (25U)
14973#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
14974#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
14976/******************** Bit definition for RCC_HSICFGR register ***************/
14978#define RCC_HSICFGR_HSICAL_Pos (0U)
14979#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
14980#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk
14981#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos)
14982#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos)
14983#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos)
14984#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos)
14985#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos)
14986#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos)
14987#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos)
14988#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos)
14989#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos)
14990#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos)
14991#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos)
14992#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos)
14995#define RCC_HSICFGR_HSITRIM_Pos (24U)
14996#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
14997#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk
14998#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
14999#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
15000#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
15001#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
15002#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
15003#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
15004#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
15007/******************** Bit definition for RCC_CRRCR register *****************/
15008
15010#define RCC_CRRCR_HSI48CAL_Pos (0U)
15011#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
15012#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
15013#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
15014#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
15015#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
15016#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
15017#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
15018#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
15019#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
15020#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
15021#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
15022#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
15025/******************** Bit definition for RCC_CSICFGR register *****************/
15027#define RCC_CSICFGR_CSICAL_Pos (0U)
15028#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
15029#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk
15030#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos)
15031#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos)
15032#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos)
15033#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos)
15034#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos)
15035#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos)
15036#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos)
15037#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos)
15040#define RCC_CSICFGR_CSITRIM_Pos (24U)
15041#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
15042#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk
15043#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
15044#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
15045#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
15046#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
15047#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
15048#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
15050/******************** Bit definition for RCC_CFGR register ******************/
15052#define RCC_CFGR_SW_Pos (0U)
15053#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)
15054#define RCC_CFGR_SW RCC_CFGR_SW_Msk
15055#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
15056#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
15057#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)
15059#define RCC_CFGR_SW_HSI (0x00000000UL)
15060#define RCC_CFGR_SW_CSI (0x00000001UL)
15061#define RCC_CFGR_SW_HSE (0x00000002UL)
15062#define RCC_CFGR_SW_PLL1 (0x00000003UL)
15065#define RCC_CFGR_SWS_Pos (3U)
15066#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)
15067#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
15068#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
15069#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
15070#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)
15072#define RCC_CFGR_SWS_HSI (0x00000000UL)
15073#define RCC_CFGR_SWS_CSI (0x00000008UL)
15074#define RCC_CFGR_SWS_HSE (0x00000010UL)
15075#define RCC_CFGR_SWS_PLL1 (0x00000018UL)
15077#define RCC_CFGR_STOPWUCK_Pos (6U)
15078#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
15079#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
15081#define RCC_CFGR_STOPKERWUCK_Pos (7U)
15082#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
15083#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk
15086#define RCC_CFGR_RTCPRE_Pos (8U)
15087#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
15088#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
15089#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos)
15090#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos)
15091#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos)
15092#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos)
15093#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
15094#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos)
15097#define RCC_CFGR_HRTIMSEL_Pos (14U)
15098#define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
15099#define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk
15102#define RCC_CFGR_TIMPRE_Pos (15U)
15103#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
15104#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk
15107#define RCC_CFGR_MCO1_Pos (22U)
15108#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
15109#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
15110#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
15111#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
15112#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos)
15114#define RCC_CFGR_MCO1PRE_Pos (18U)
15115#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
15116#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
15117#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
15118#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
15119#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
15120#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos)
15122#define RCC_CFGR_MCO2PRE_Pos (25U)
15123#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
15124#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
15125#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
15126#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
15127#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
15128#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos)
15130#define RCC_CFGR_MCO2_Pos (29U)
15131#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
15132#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
15133#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
15134#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
15135#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos)
15137/******************** Bit definition for RCC_D1CFGR register ******************/
15139#define RCC_D1CFGR_HPRE_Pos (0U)
15140#define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos)
15141#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk
15142#define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos)
15143#define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos)
15144#define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos)
15145#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos)
15148#define RCC_D1CFGR_HPRE_DIV1 (0U)
15149#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
15150#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos)
15151#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk
15152#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
15153#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos)
15154#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk
15155#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
15156#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos)
15157#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk
15158#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
15159#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos)
15160#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk
15161#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
15162#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos)
15163#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk
15164#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
15165#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos)
15166#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk
15167#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
15168#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos)
15169#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk
15170#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
15171#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos)
15172#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk
15175#define RCC_D1CFGR_D1PPRE_Pos (4U)
15176#define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos)
15177#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk
15178#define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos)
15179#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos)
15180#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos)
15182#define RCC_D1CFGR_D1PPRE_DIV1 (0U)
15183#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
15184#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos)
15185#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk
15186#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
15187#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos)
15188#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk
15189#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
15190#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos)
15191#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk
15192#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
15193#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos)
15194#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk
15196#define RCC_D1CFGR_D1CPRE_Pos (8U)
15197#define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos)
15198#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk
15199#define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos)
15200#define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos)
15201#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos)
15202#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos)
15204#define RCC_D1CFGR_D1CPRE_DIV1 (0U)
15205#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
15206#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos)
15207#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk
15208#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
15209#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos)
15210#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk
15211#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
15212#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos)
15213#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk
15214#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
15215#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos)
15216#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk
15217#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
15218#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos)
15219#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk
15220#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
15221#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos)
15222#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk
15223#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
15224#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos)
15225#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk
15226#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
15227#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos)
15228#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk
15230/******************** Bit definition for RCC_D2CFGR register ******************/
15232#define RCC_D2CFGR_D2PPRE1_Pos (4U)
15233#define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos)
15234#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk
15235#define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos)
15236#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos)
15237#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos)
15239#define RCC_D2CFGR_D2PPRE1_DIV1 (0U)
15240#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
15241#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos)
15242#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk
15243#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
15244#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos)
15245#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk
15246#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
15247#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos)
15248#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk
15249#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
15250#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos)
15251#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk
15254#define RCC_D2CFGR_D2PPRE2_Pos (8U)
15255#define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos)
15256#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk
15257#define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos)
15258#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos)
15259#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos)
15261#define RCC_D2CFGR_D2PPRE2_DIV1 (0U)
15262#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
15263#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos)
15264#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk
15265#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
15266#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos)
15267#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk
15268#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
15269#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos)
15270#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk
15271#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
15272#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos)
15273#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk
15275/******************** Bit definition for RCC_D3CFGR register ******************/
15277#define RCC_D3CFGR_D3PPRE_Pos (4U)
15278#define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos)
15279#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk
15280#define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos)
15281#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos)
15282#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos)
15284#define RCC_D3CFGR_D3PPRE_DIV1 (0U)
15285#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
15286#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos)
15287#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk
15288#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
15289#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos)
15290#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk
15291#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
15292#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos)
15293#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk
15294#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
15295#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos)
15296#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk
15298/******************** Bit definition for RCC_PLLCKSELR register *************/
15299
15300#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
15301#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
15302#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
15303
15304#define RCC_PLLCKSELR_PLLSRC_HSI (0U)
15305#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
15306#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
15307#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk
15308#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
15309#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
15310#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk
15311#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
15312#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
15313#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk
15315#define RCC_PLLCKSELR_DIVM1_Pos (4U)
15316#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
15317#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
15318#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
15319#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
15320#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
15321#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
15322#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
15323#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
15325#define RCC_PLLCKSELR_DIVM2_Pos (12U)
15326#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
15327#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
15328#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
15329#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
15330#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
15331#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
15332#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
15333#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
15335#define RCC_PLLCKSELR_DIVM3_Pos (20U)
15336#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
15337#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
15338#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
15339#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
15340#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
15341#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
15342#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
15343#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
15345/******************** Bit definition for RCC_PLLCFGR register ***************/
15346
15347#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
15348#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
15349#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
15350#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
15351#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
15352#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
15353#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
15354#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
15355#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
15356#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
15357#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
15358#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
15359#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
15361#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
15362#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
15363#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
15364#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
15365#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
15366#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
15367#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
15368#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
15369#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
15370#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
15371#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
15372#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
15373#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
15375#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
15376#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
15377#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
15378#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
15379#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
15380#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
15381#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
15382#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
15383#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
15384#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
15385#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
15386#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
15387#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
15389#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
15390#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
15391#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
15392#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
15393#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
15394#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
15395#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
15396#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
15397#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
15398
15399#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
15400#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
15401#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
15402#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
15403#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
15404#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
15405#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
15406#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
15407#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
15408
15409#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
15410#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
15411#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
15412#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
15413#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
15414#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
15415#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
15416#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
15417#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
15418
15419
15420/******************** Bit definition for RCC_PLL1DIVR register ***************/
15421#define RCC_PLL1DIVR_N1_Pos (0U)
15422#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
15423#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
15424#define RCC_PLL1DIVR_P1_Pos (9U)
15425#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos)
15426#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
15427#define RCC_PLL1DIVR_Q1_Pos (16U)
15428#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
15429#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
15430#define RCC_PLL1DIVR_R1_Pos (24U)
15431#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos)
15432#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
15433
15434/******************** Bit definition for RCC_PLL1FRACR register ***************/
15435#define RCC_PLL1FRACR_FRACN1_Pos (3U)
15436#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
15437#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
15438
15439/******************** Bit definition for RCC_PLL2DIVR register ***************/
15440#define RCC_PLL2DIVR_N2_Pos (0U)
15441#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
15442#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
15443#define RCC_PLL2DIVR_P2_Pos (9U)
15444#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos)
15445#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
15446#define RCC_PLL2DIVR_Q2_Pos (16U)
15447#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
15448#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
15449#define RCC_PLL2DIVR_R2_Pos (24U)
15450#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos)
15451#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
15452
15453/******************** Bit definition for RCC_PLL2FRACR register ***************/
15454#define RCC_PLL2FRACR_FRACN2_Pos (3U)
15455#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
15456#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
15457
15458/******************** Bit definition for RCC_PLL3DIVR register ***************/
15459#define RCC_PLL3DIVR_N3_Pos (0U)
15460#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
15461#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
15462#define RCC_PLL3DIVR_P3_Pos (9U)
15463#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos)
15464#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
15465#define RCC_PLL3DIVR_Q3_Pos (16U)
15466#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
15467#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
15468#define RCC_PLL3DIVR_R3_Pos (24U)
15469#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos)
15470#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
15471
15472/******************** Bit definition for RCC_PLL3FRACR register ***************/
15473#define RCC_PLL3FRACR_FRACN3_Pos (3U)
15474#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
15475#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
15476
15477/******************** Bit definition for RCC_D1CCIPR register ***************/
15478#define RCC_D1CCIPR_FMCSEL_Pos (0U)
15479#define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos)
15480#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
15481#define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos)
15482#define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos)
15483#define RCC_D1CCIPR_QSPISEL_Pos (4U)
15484#define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos)
15485#define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
15486#define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos)
15487#define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos)
15488#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
15489#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos)
15490#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
15491#define RCC_D1CCIPR_CKPERSEL_Pos (28U)
15492#define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos)
15493#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
15494#define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos)
15495#define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos)
15497/******************** Bit definition for RCC_D2CCIP1R register ***************/
15498#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
15499#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15500#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
15501#define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15502#define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15503#define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos)
15505#define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
15506#define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos)
15507#define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
15508#define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos)
15509#define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos)
15510#define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos)
15512#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
15513#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15514#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
15515#define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15516#define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15517#define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos)
15519#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
15520#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15521#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
15522#define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15523#define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15524#define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos)
15526#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
15527#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15528#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
15529#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15530#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
15532#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
15533#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos)
15534#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
15535
15536#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
15537#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15538#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
15539#define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15540#define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos)
15542#define RCC_D2CCIP1R_SWPSEL_Pos (31U)
15543#define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos)
15544#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
15545
15546/******************** Bit definition for RCC_D2CCIP2R register ***************/
15547#define RCC_D2CCIP2R_USART16SEL_Pos (3U)
15548#define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos)
15549#define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
15550#define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos)
15551#define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos)
15552#define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos)
15554#define RCC_D2CCIP2R_USART28SEL_Pos (0U)
15555#define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos)
15556#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
15557#define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos)
15558#define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos)
15559#define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos)
15561#define RCC_D2CCIP2R_RNGSEL_Pos (8U)
15562#define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos)
15563#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
15564#define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos)
15565#define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos)
15567#define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
15568#define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos)
15569#define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
15570#define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos)
15571#define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos)
15573#define RCC_D2CCIP2R_USBSEL_Pos (20U)
15574#define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos)
15575#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
15576#define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos)
15577#define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos)
15579#define RCC_D2CCIP2R_CECSEL_Pos (22U)
15580#define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos)
15581#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
15582#define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos)
15583#define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos)
15585#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
15586#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15587#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
15588#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15589#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15590#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
15592/******************** Bit definition for RCC_D3CCIPR register ***************/
15593#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
15594#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15595#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
15596#define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15597#define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15598#define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos)
15600#define RCC_D3CCIPR_I2C4SEL_Pos (8U)
15601#define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos)
15602#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
15603#define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos)
15604#define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos)
15606#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
15607#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15608#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
15609#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15610#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15611#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
15613#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
15614#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15615#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
15616#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15617#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15618#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
15620#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
15621#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15622#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
15623#define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15624#define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15625#define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos)
15627#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
15628#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15629#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
15630#define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15631#define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15632#define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos)
15634#define RCC_D3CCIPR_ADCSEL_Pos (16U)
15635#define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos)
15636#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
15637#define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos)
15638#define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos)
15640#define RCC_D3CCIPR_SPI6SEL_Pos (28U)
15641#define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos)
15642#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
15643#define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos)
15644#define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos)
15645#define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos)
15646/******************** Bit definition for RCC_CIER register ******************/
15647#define RCC_CIER_LSIRDYIE_Pos (0U)
15648#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
15649#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
15650#define RCC_CIER_LSERDYIE_Pos (1U)
15651#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
15652#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
15653#define RCC_CIER_HSIRDYIE_Pos (2U)
15654#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
15655#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
15656#define RCC_CIER_HSERDYIE_Pos (3U)
15657#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
15658#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
15659#define RCC_CIER_CSIRDYIE_Pos (4U)
15660#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos)
15661#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
15662#define RCC_CIER_HSI48RDYIE_Pos (5U)
15663#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
15664#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
15665#define RCC_CIER_PLL1RDYIE_Pos (6U)
15666#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
15667#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
15668#define RCC_CIER_PLL2RDYIE_Pos (7U)
15669#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
15670#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
15671#define RCC_CIER_PLL3RDYIE_Pos (8U)
15672#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
15673#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
15674#define RCC_CIER_LSECSSIE_Pos (9U)
15675#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
15676#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
15677
15678/******************** Bit definition for RCC_CIFR register ******************/
15679#define RCC_CIFR_LSIRDYF_Pos (0U)
15680#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
15681#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
15682#define RCC_CIFR_LSERDYF_Pos (1U)
15683#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
15684#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
15685#define RCC_CIFR_HSIRDYF_Pos (2U)
15686#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
15687#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
15688#define RCC_CIFR_HSERDYF_Pos (3U)
15689#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
15690#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
15691#define RCC_CIFR_CSIRDYF_Pos (4U)
15692#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos)
15693#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
15694#define RCC_CIFR_HSI48RDYF_Pos (5U)
15695#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
15696#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
15697#define RCC_CIFR_PLLRDYF_Pos (6U)
15698#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
15699#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
15700#define RCC_CIFR_PLL2RDYF_Pos (7U)
15701#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
15702#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
15703#define RCC_CIFR_PLL3RDYF_Pos (8U)
15704#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
15705#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
15706#define RCC_CIFR_LSECSSF_Pos (9U)
15707#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
15708#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
15709#define RCC_CIFR_HSECSSF_Pos (10U)
15710#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos)
15711#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
15712
15713/******************** Bit definition for RCC_CICR register ******************/
15714#define RCC_CICR_LSIRDYC_Pos (0U)
15715#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
15716#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
15717#define RCC_CICR_LSERDYC_Pos (1U)
15718#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
15719#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
15720#define RCC_CICR_HSIRDYC_Pos (2U)
15721#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
15722#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
15723#define RCC_CICR_HSERDYC_Pos (3U)
15724#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
15725#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
15726#define RCC_CICR_CSIRDYC_Pos (4U)
15727#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos)
15728#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
15729#define RCC_CICR_HSI48RDYC_Pos (5U)
15730#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
15731#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
15732#define RCC_CICR_PLLRDYC_Pos (6U)
15733#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
15734#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
15735#define RCC_CICR_PLL2RDYC_Pos (7U)
15736#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos)
15737#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
15738#define RCC_CICR_PLL3RDYC_Pos (8U)
15739#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos)
15740#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
15741#define RCC_CICR_LSECSSC_Pos (9U)
15742#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
15743#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
15744#define RCC_CICR_HSECSSC_Pos (10U)
15745#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos)
15746#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
15747
15748/******************** Bit definition for RCC_BDCR register ******************/
15749#define RCC_BDCR_LSEON_Pos (0U)
15750#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
15751#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
15752#define RCC_BDCR_LSERDY_Pos (1U)
15753#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
15754#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
15755#define RCC_BDCR_LSEBYP_Pos (2U)
15756#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
15757#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
15758
15759#define RCC_BDCR_LSEDRV_Pos (3U)
15760#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
15761#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
15762#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
15763#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
15765#define RCC_BDCR_LSECSSON_Pos (5U)
15766#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
15767#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
15768#define RCC_BDCR_LSECSSD_Pos (6U)
15769#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
15770#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
15771
15772#define RCC_BDCR_RTCSEL_Pos (8U)
15773#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
15774#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
15775#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
15776#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
15778#define RCC_BDCR_RTCEN_Pos (15U)
15779#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
15780#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
15781#define RCC_BDCR_BDRST_Pos (16U)
15782#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
15783#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
15784/******************** Bit definition for RCC_CSR register *******************/
15785#define RCC_CSR_LSION_Pos (0U)
15786#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
15787#define RCC_CSR_LSION RCC_CSR_LSION_Msk
15788#define RCC_CSR_LSIRDY_Pos (1U)
15789#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
15790#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
15791
15792
15793/******************** Bit definition for RCC_AHB3ENR register **************/
15794#define RCC_AHB3ENR_MDMAEN_Pos (0U)
15795#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
15796#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
15797#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
15798#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
15799#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
15800#define RCC_AHB3ENR_JPGDECEN_Pos (5U)
15801#define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)
15802#define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
15803#define RCC_AHB3ENR_FMCEN_Pos (12U)
15804#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
15805#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
15806#define RCC_AHB3ENR_QSPIEN_Pos (14U)
15807#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
15808#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
15809#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
15810#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
15811#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
15812#define RCC_AHB3ENR_FLASHEN_Pos (8U)
15813#define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)
15814#define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
15815#define RCC_AHB3ENR_DTCM1EN_Pos (28U)
15816#define RCC_AHB3ENR_DTCM1EN_Msk (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)
15817#define RCC_AHB3ENR_DTCM1EN RCC_AHB3ENR_DTCM1EN_Msk
15818#define RCC_AHB3ENR_DTCM2EN_Pos (29U)
15819#define RCC_AHB3ENR_DTCM2EN_Msk (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)
15820#define RCC_AHB3ENR_DTCM2EN RCC_AHB3ENR_DTCM2EN_Msk
15821#define RCC_AHB3ENR_ITCMEN_Pos (30U)
15822#define RCC_AHB3ENR_ITCMEN_Msk (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)
15823#define RCC_AHB3ENR_ITCMEN RCC_AHB3ENR_ITCMEN_Msk
15824#define RCC_AHB3ENR_AXISRAMEN_Pos (31U)
15825#define RCC_AHB3ENR_AXISRAMEN_Msk (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)
15826#define RCC_AHB3ENR_AXISRAMEN RCC_AHB3ENR_AXISRAMEN_Msk
15827
15828/* Legacy define */
15829#define RCC_AHB3ENR_D1SRAM1EN_Pos RCC_AHB3ENR_AXISRAMEN_Pos
15830#define RCC_AHB3ENR_D1SRAM1EN_Msk RCC_AHB3ENR_AXISRAMEN_Msk
15831#define RCC_AHB3ENR_D1SRAM1EN RCC_AHB3ENR_AXISRAMEN
15832
15833/******************** Bit definition for RCC_AHB1ENR register ***************/
15834#define RCC_AHB1ENR_DMA1EN_Pos (0U)
15835#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
15836#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
15837#define RCC_AHB1ENR_DMA2EN_Pos (1U)
15838#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
15839#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
15840#define RCC_AHB1ENR_ADC12EN_Pos (5U)
15841#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
15842#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
15843#define RCC_AHB1ENR_ARTEN_Pos (14U)
15844#define RCC_AHB1ENR_ARTEN_Msk (0x1UL << RCC_AHB1ENR_ARTEN_Pos)
15845#define RCC_AHB1ENR_ARTEN RCC_AHB1ENR_ARTEN_Msk
15846#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
15847#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)
15848#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
15849#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
15850#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)
15851#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
15852#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
15853#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)
15854#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
15855#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
15856#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
15857#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
15858#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
15859#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
15860#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
15861#define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
15862#define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)
15863#define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
15864#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
15865#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos)
15866#define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
15867
15868/* Legacy define */
15869#define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
15870#define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
15871#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
15872#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
15873#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
15874#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
15875
15876
15877/******************** Bit definition for RCC_AHB2ENR register ***************/
15878#define RCC_AHB2ENR_DCMIEN_Pos (0U)
15879#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
15880#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
15881#define RCC_AHB2ENR_RNGEN_Pos (6U)
15882#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
15883#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
15884#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
15885#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
15886#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
15887#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
15888#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)
15889#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
15890#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
15891#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)
15892#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
15893#define RCC_AHB2ENR_SRAM3EN_Pos (31U)
15894#define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)
15895#define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
15896
15897/* Legacy define */
15898#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
15899#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
15900#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
15901#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
15902#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
15903#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
15904#define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
15905#define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
15906#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
15907
15908/******************** Bit definition for RCC_AHB4ENR register ******************/
15909#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
15910#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
15911#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
15912#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
15913#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
15914#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
15915#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
15916#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
15917#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
15918#define RCC_AHB4ENR_GPIODEN_Pos (3U)
15919#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
15920#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
15921#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
15922#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
15923#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
15924#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
15925#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
15926#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
15927#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
15928#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
15929#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
15930#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
15931#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
15932#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
15933#define RCC_AHB4ENR_GPIOIEN_Pos (8U)
15934#define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)
15935#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
15936#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
15937#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
15938#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
15939#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
15940#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
15941#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
15942#define RCC_AHB4ENR_CRCEN_Pos (19U)
15943#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos)
15944#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
15945#define RCC_AHB4ENR_BDMAEN_Pos (21U)
15946#define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)
15947#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
15948#define RCC_AHB4ENR_ADC3EN_Pos (24U)
15949#define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)
15950#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
15951#define RCC_AHB4ENR_HSEMEN_Pos (25U)
15952#define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)
15953#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
15954#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
15955#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
15956#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
15957
15958/******************** Bit definition for RCC_APB3ENR register ******************/
15959#define RCC_APB3ENR_LTDCEN_Pos (3U)
15960#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos)
15961#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
15962#define RCC_APB3ENR_WWDG1EN_Pos (6U)
15963#define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos)
15964#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
15965
15966/******************** Bit definition for RCC_APB1LENR register ******************/
15967
15968#define RCC_APB1LENR_TIM2EN_Pos (0U)
15969#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
15970#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
15971#define RCC_APB1LENR_TIM3EN_Pos (1U)
15972#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
15973#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
15974#define RCC_APB1LENR_TIM4EN_Pos (2U)
15975#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
15976#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
15977#define RCC_APB1LENR_TIM5EN_Pos (3U)
15978#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
15979#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
15980#define RCC_APB1LENR_TIM6EN_Pos (4U)
15981#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
15982#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
15983#define RCC_APB1LENR_TIM7EN_Pos (5U)
15984#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
15985#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
15986#define RCC_APB1LENR_TIM12EN_Pos (6U)
15987#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
15988#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
15989#define RCC_APB1LENR_TIM13EN_Pos (7U)
15990#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
15991#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
15992#define RCC_APB1LENR_TIM14EN_Pos (8U)
15993#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
15994#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
15995#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
15996#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
15997#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
15998
15999#define RCC_APB1LENR_WWDG2EN_Pos (11U)
16000#define RCC_APB1LENR_WWDG2EN_Msk (0x1UL << RCC_APB1LENR_WWDG2EN_Pos)
16001#define RCC_APB1LENR_WWDG2EN RCC_APB1LENR_WWDG2EN_Msk
16002
16003#define RCC_APB1LENR_SPI2EN_Pos (14U)
16004#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
16005#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
16006#define RCC_APB1LENR_SPI3EN_Pos (15U)
16007#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
16008#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
16009#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
16010#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
16011#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
16012#define RCC_APB1LENR_USART2EN_Pos (17U)
16013#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos)
16014#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
16015#define RCC_APB1LENR_USART3EN_Pos (18U)
16016#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos)
16017#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
16018#define RCC_APB1LENR_UART4EN_Pos (19U)
16019#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos)
16020#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
16021#define RCC_APB1LENR_UART5EN_Pos (20U)
16022#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos)
16023#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
16024#define RCC_APB1LENR_I2C1EN_Pos (21U)
16025#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
16026#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
16027#define RCC_APB1LENR_I2C2EN_Pos (22U)
16028#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
16029#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
16030#define RCC_APB1LENR_I2C3EN_Pos (23U)
16031#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
16032#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
16033#define RCC_APB1LENR_CECEN_Pos (27U)
16034#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos)
16035#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
16036#define RCC_APB1LENR_DAC12EN_Pos (29U)
16037#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
16038#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
16039#define RCC_APB1LENR_UART7EN_Pos (30U)
16040#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos)
16041#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
16042#define RCC_APB1LENR_UART8EN_Pos (31U)
16043#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos)
16044#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
16045
16046/* Legacy define */
16047#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
16048#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
16049#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
16050/******************** Bit definition for RCC_APB1HENR register ******************/
16051#define RCC_APB1HENR_CRSEN_Pos (1U)
16052#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos)
16053#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
16054#define RCC_APB1HENR_SWPMIEN_Pos (2U)
16055#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
16056#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
16057#define RCC_APB1HENR_OPAMPEN_Pos (4U)
16058#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
16059#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
16060#define RCC_APB1HENR_MDIOSEN_Pos (5U)
16061#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
16062#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
16063#define RCC_APB1HENR_FDCANEN_Pos (8U)
16064#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
16065#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
16066
16067/******************** Bit definition for RCC_APB2ENR register ******************/
16068#define RCC_APB2ENR_TIM1EN_Pos (0U)
16069#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
16070#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
16071#define RCC_APB2ENR_TIM8EN_Pos (1U)
16072#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
16073#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
16074#define RCC_APB2ENR_USART1EN_Pos (4U)
16075#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
16076#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
16077#define RCC_APB2ENR_USART6EN_Pos (5U)
16078#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
16079#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
16080#define RCC_APB2ENR_SPI1EN_Pos (12U)
16081#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
16082#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
16083#define RCC_APB2ENR_SPI4EN_Pos (13U)
16084#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
16085#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
16086#define RCC_APB2ENR_TIM15EN_Pos (16U)
16087#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
16088#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
16089#define RCC_APB2ENR_TIM16EN_Pos (17U)
16090#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
16091#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
16092#define RCC_APB2ENR_TIM17EN_Pos (18U)
16093#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
16094#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
16095#define RCC_APB2ENR_SPI5EN_Pos (20U)
16096#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
16097#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
16098#define RCC_APB2ENR_SAI1EN_Pos (22U)
16099#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
16100#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
16101#define RCC_APB2ENR_SAI2EN_Pos (23U)
16102#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
16103#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
16104#define RCC_APB2ENR_SAI3EN_Pos (24U)
16105#define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos)
16106#define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
16107#define RCC_APB2ENR_DFSDM1EN_Pos (28U)
16108#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
16109#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
16110#define RCC_APB2ENR_HRTIMEN_Pos (29U)
16111#define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos)
16112#define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
16113
16114/******************** Bit definition for RCC_APB4ENR register ******************/
16115#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
16116#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
16117#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
16118#define RCC_APB4ENR_LPUART1EN_Pos (3U)
16119#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
16120#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
16121#define RCC_APB4ENR_SPI6EN_Pos (5U)
16122#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
16123#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
16124#define RCC_APB4ENR_I2C4EN_Pos (7U)
16125#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
16126#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
16127#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
16128#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
16129#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
16130#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
16131#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
16132#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
16133#define RCC_APB4ENR_LPTIM4EN_Pos (11U)
16134#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)
16135#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
16136#define RCC_APB4ENR_LPTIM5EN_Pos (12U)
16137#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)
16138#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
16139#define RCC_APB4ENR_COMP12EN_Pos (14U)
16140#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
16141#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
16142#define RCC_APB4ENR_VREFEN_Pos (15U)
16143#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos)
16144#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
16145#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
16146#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
16147#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
16148#define RCC_APB4ENR_SAI4EN_Pos (21U)
16149#define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos)
16150#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
16151
16152
16153/******************** Bit definition for RCC_AHB3RSTR register ***************/
16154#define RCC_AHB3RSTR_MDMARST_Pos (0U)
16155#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
16156#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
16157#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
16158#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
16159#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
16160#define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
16161#define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)
16162#define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
16163#define RCC_AHB3RSTR_FMCRST_Pos (12U)
16164#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
16165#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
16166#define RCC_AHB3RSTR_QSPIRST_Pos (14U)
16167#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
16168#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
16169#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
16170#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
16171#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
16172
16173
16174/******************** Bit definition for RCC_AHB1RSTR register ***************/
16175#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
16176#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
16177#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
16178#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
16179#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
16180#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
16181#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
16182#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
16183#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
16184#define RCC_AHB1RSTR_ARTRST_Pos (14U)
16185#define RCC_AHB1RSTR_ARTRST_Msk (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)
16186#define RCC_AHB1RSTR_ARTRST RCC_AHB1RSTR_ARTRST_Msk
16187#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
16188#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)
16189#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
16190#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
16191#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
16192#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
16193#define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
16194#define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos)
16195#define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
16196
16197/* Legacy define */
16198#define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
16199#define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
16200#define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
16201
16202/******************** Bit definition for RCC_AHB2RSTR register ***************/
16203#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
16204#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
16205#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
16206#define RCC_AHB2RSTR_RNGRST_Pos (6U)
16207#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
16208#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
16209#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
16210#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
16211#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
16212
16213/******************** Bit definition for RCC_AHB4RSTR register ******************/
16214#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
16215#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
16216#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
16217#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
16218#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
16219#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
16220#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
16221#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
16222#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
16223#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
16224#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
16225#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
16226#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
16227#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
16228#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
16229#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
16230#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
16231#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
16232#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
16233#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
16234#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
16235#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
16236#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
16237#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
16238#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
16239#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)
16240#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
16241#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
16242#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
16243#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
16244#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
16245#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
16246#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
16247#define RCC_AHB4RSTR_CRCRST_Pos (19U)
16248#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)
16249#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
16250#define RCC_AHB4RSTR_BDMARST_Pos (21U)
16251#define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)
16252#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
16253#define RCC_AHB4RSTR_ADC3RST_Pos (24U)
16254#define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)
16255#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
16256#define RCC_AHB4RSTR_HSEMRST_Pos (25U)
16257#define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
16258#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
16259
16260
16261/******************** Bit definition for RCC_APB3RSTR register ******************/
16262#define RCC_APB3RSTR_LTDCRST_Pos (3U)
16263#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos)
16264#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
16265
16266/******************** Bit definition for RCC_APB1LRSTR register ******************/
16267
16268#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
16269#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
16270#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
16271#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
16272#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
16273#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
16274#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
16275#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
16276#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
16277#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
16278#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
16279#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
16280#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
16281#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
16282#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
16283#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
16284#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
16285#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
16286#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
16287#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
16288#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
16289#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
16290#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
16291#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
16292#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
16293#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
16294#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
16295#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
16296#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
16297#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
16298#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
16299#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
16300#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
16301#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
16302#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
16303#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
16304#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
16305#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
16306#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
16307#define RCC_APB1LRSTR_USART2RST_Pos (17U)
16308#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
16309#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
16310#define RCC_APB1LRSTR_USART3RST_Pos (18U)
16311#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
16312#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
16313#define RCC_APB1LRSTR_UART4RST_Pos (19U)
16314#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
16315#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
16316#define RCC_APB1LRSTR_UART5RST_Pos (20U)
16317#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
16318#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
16319#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
16320#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
16321#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
16322#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
16323#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
16324#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
16325#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
16326#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
16327#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
16328#define RCC_APB1LRSTR_CECRST_Pos (27U)
16329#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
16330#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
16331#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
16332#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
16333#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
16334#define RCC_APB1LRSTR_UART7RST_Pos (30U)
16335#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
16336#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
16337#define RCC_APB1LRSTR_UART8RST_Pos (31U)
16338#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
16339#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
16340
16341/* Legacy define */
16342#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
16343#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
16344#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
16345/******************** Bit definition for RCC_APB1HRSTR register ******************/
16346#define RCC_APB1HRSTR_CRSRST_Pos (1U)
16347#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
16348#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
16349#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
16350#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
16351#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
16352#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
16353#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
16354#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
16355#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
16356#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
16357#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
16358#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
16359#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
16360#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
16361
16362/******************** Bit definition for RCC_APB2RSTR register ******************/
16363#define RCC_APB2RSTR_TIM1RST_Pos (0U)
16364#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
16365#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
16366#define RCC_APB2RSTR_TIM8RST_Pos (1U)
16367#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
16368#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
16369#define RCC_APB2RSTR_USART1RST_Pos (4U)
16370#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
16371#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
16372#define RCC_APB2RSTR_USART6RST_Pos (5U)
16373#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
16374#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
16375#define RCC_APB2RSTR_SPI1RST_Pos (12U)
16376#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
16377#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
16378#define RCC_APB2RSTR_SPI4RST_Pos (13U)
16379#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
16380#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
16381#define RCC_APB2RSTR_TIM15RST_Pos (16U)
16382#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
16383#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
16384#define RCC_APB2RSTR_TIM16RST_Pos (17U)
16385#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
16386#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
16387#define RCC_APB2RSTR_TIM17RST_Pos (18U)
16388#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
16389#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
16390#define RCC_APB2RSTR_SPI5RST_Pos (20U)
16391#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
16392#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
16393#define RCC_APB2RSTR_SAI1RST_Pos (22U)
16394#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
16395#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
16396#define RCC_APB2RSTR_SAI2RST_Pos (23U)
16397#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
16398#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
16399#define RCC_APB2RSTR_SAI3RST_Pos (24U)
16400#define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos)
16401#define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
16402#define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
16403#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
16404#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
16405#define RCC_APB2RSTR_HRTIMRST_Pos (29U)
16406#define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos)
16407#define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
16408
16409/******************** Bit definition for RCC_APB4RSTR register ******************/
16410#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
16411#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
16412#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
16413#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
16414#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
16415#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
16416#define RCC_APB4RSTR_SPI6RST_Pos (5U)
16417#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
16418#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
16419#define RCC_APB4RSTR_I2C4RST_Pos (7U)
16420#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
16421#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
16422#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
16423#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
16424#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
16425#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
16426#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
16427#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
16428#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
16429#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)
16430#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
16431#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
16432#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)
16433#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
16434#define RCC_APB4RSTR_COMP12RST_Pos (14U)
16435#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
16436#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
16437#define RCC_APB4RSTR_VREFRST_Pos (15U)
16438#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
16439#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
16440#define RCC_APB4RSTR_SAI4RST_Pos (21U)
16441#define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos)
16442#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
16443
16444
16445/******************** Bit definition for RCC_GCR register ********************/
16446#define RCC_GCR_WW1RSC_Pos (0U)
16447#define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos)
16448#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
16449#define RCC_GCR_WW2RSC_Pos (1U)
16450#define RCC_GCR_WW2RSC_Msk (0x1UL << RCC_GCR_WW2RSC_Pos)
16451#define RCC_GCR_WW2RSC RCC_GCR_WW2RSC_Msk
16452#define RCC_GCR_BOOT_C1_Pos (2U)
16453#define RCC_GCR_BOOT_C1_Msk (0x1UL << RCC_GCR_BOOT_C1_Pos)
16454#define RCC_GCR_BOOT_C1 RCC_GCR_BOOT_C1_Msk
16455#define RCC_GCR_BOOT_C2_Pos (3U)
16456#define RCC_GCR_BOOT_C2_Msk (0x1UL << RCC_GCR_BOOT_C2_Pos)
16457#define RCC_GCR_BOOT_C2 RCC_GCR_BOOT_C2_Msk
16458
16459/******************** Bit definition for RCC_D3AMR register ********************/
16460#define RCC_D3AMR_BDMAAMEN_Pos (0U)
16461#define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos)
16462#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
16463#define RCC_D3AMR_LPUART1AMEN_Pos (3U)
16464#define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos)
16465#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
16466#define RCC_D3AMR_SPI6AMEN_Pos (5U)
16467#define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos)
16468#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
16469#define RCC_D3AMR_I2C4AMEN_Pos (7U)
16470#define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos)
16471#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
16472#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
16473#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos)
16474#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
16475#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
16476#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos)
16477#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
16478#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
16479#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos)
16480#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
16481#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
16482#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos)
16483#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
16484#define RCC_D3AMR_COMP12AMEN_Pos (14U)
16485#define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos)
16486#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
16487#define RCC_D3AMR_VREFAMEN_Pos (15U)
16488#define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos)
16489#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
16490#define RCC_D3AMR_RTCAMEN_Pos (16U)
16491#define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos)
16492#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
16493#define RCC_D3AMR_CRCAMEN_Pos (19U)
16494#define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos)
16495#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
16496#define RCC_D3AMR_SAI4AMEN_Pos (21U)
16497#define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos)
16498#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
16499#define RCC_D3AMR_ADC3AMEN_Pos (24U)
16500#define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos)
16501#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
16502
16503
16504#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
16505#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos)
16506#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
16507#define RCC_D3AMR_SRAM4AMEN_Pos (29U)
16508#define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos)
16509#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
16510/******************** Bit definition for RCC_AHB3LPENR register **************/
16511#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
16512#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
16513#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
16514#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
16515#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
16516#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
16517#define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
16518#define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)
16519#define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
16520#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
16521#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
16522#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
16523#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
16524#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
16525#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
16526#define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
16527#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
16528#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
16529#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
16530#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
16531#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
16532#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
16533#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
16534#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
16535#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
16536#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
16537#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
16538#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
16539#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
16540#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
16541#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
16542#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)
16543#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
16544
16545
16546/******************** Bit definition for RCC_AHB1LPENR register ***************/
16547#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
16548#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
16549#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
16550#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
16551#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
16552#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
16553#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
16554#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
16555#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
16556#define RCC_AHB1LPENR_ARTLPEN_Pos (14U)
16557#define RCC_AHB1LPENR_ARTLPEN_Msk (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos)
16558#define RCC_AHB1LPENR_ARTLPEN RCC_AHB1LPENR_ARTLPEN_Msk
16559#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
16560#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos)
16561#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
16562#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
16563#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos)
16564#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
16565#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
16566#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos)
16567#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
16568#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
16569#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
16570#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
16571#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
16572#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
16573#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
16574#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
16575#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos)
16576#define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
16577#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
16578#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos)
16579#define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
16580
16581/* Legacy define */
16582#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
16583#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
16584#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
16585#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
16586#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
16587#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
16588
16589/******************** Bit definition for RCC_AHB2LPENR register ***************/
16590#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
16591#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
16592#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
16593#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
16594#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
16595#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
16596#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
16597#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
16598#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
16599#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
16600#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)
16601#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
16602#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
16603#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)
16604#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
16605#define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
16606#define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos)
16607#define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
16608
16609/* Legacy define */
16610#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
16611#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
16612#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
16613#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
16614#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
16615#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
16616#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
16617#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
16618#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
16619
16620/******************** Bit definition for RCC_AHB4LPENR register ******************/
16621#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
16622#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
16623#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
16624#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
16625#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
16626#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
16627#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
16628#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
16629#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
16630#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
16631#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
16632#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
16633#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
16634#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
16635#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
16636#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
16637#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
16638#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
16639#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
16640#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
16641#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
16642#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
16643#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
16644#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
16645#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
16646#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos)
16647#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
16648#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
16649#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
16650#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
16651#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
16652#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
16653#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
16654#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
16655#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)
16656#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
16657#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
16658#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos)
16659#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
16660#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
16661#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos)
16662#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
16663#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
16664#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
16665#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
16666#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
16667#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos)
16668#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
16669
16670/* Legacy define */
16671#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
16672#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
16673#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
16674/******************** Bit definition for RCC_APB3LPENR register ******************/
16675#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
16676#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos)
16677#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
16678#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
16679#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos)
16680#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
16681
16682/******************** Bit definition for RCC_APB1LLPENR register ******************/
16683
16684#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
16685#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
16686#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
16687#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
16688#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
16689#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
16690#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
16691#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
16692#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
16693#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
16694#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
16695#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
16696#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
16697#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
16698#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
16699#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
16700#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
16701#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
16702#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
16703#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
16704#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
16705#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
16706#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
16707#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
16708#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
16709#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
16710#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
16711#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
16712#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
16713#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
16714
16715#define RCC_APB1LLPENR_WWDG2LPEN_Pos (11U)
16716#define RCC_APB1LLPENR_WWDG2LPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos)
16717#define RCC_APB1LLPENR_WWDG2LPEN RCC_APB1LLPENR_WWDG2LPEN_Msk
16718
16719#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
16720#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
16721#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
16722#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
16723#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
16724#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
16725#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
16726#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
16727#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
16728#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
16729#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
16730#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
16731#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
16732#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
16733#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
16734#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
16735#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
16736#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
16737#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
16738#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
16739#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
16740#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
16741#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
16742#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
16743#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
16744#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
16745#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
16746#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
16747#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
16748#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
16749#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
16750#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
16751#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
16752#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
16753#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
16754#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
16755#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
16756#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
16757#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
16758#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
16759#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
16760#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
16761
16762/* Legacy define */
16763#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
16764#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
16765#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
16766/******************** Bit definition for RCC_APB1HLPENR register ******************/
16767#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
16768#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
16769#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
16770#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
16771#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
16772#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
16773#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
16774#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
16775#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
16776#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
16777#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
16778#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
16779#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
16780#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
16781#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
16782
16783/******************** Bit definition for RCC_APB2LPENR register ******************/
16784#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
16785#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
16786#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
16787#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
16788#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
16789#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
16790#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
16791#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
16792#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
16793#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
16794#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
16795#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
16796#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
16797#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
16798#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
16799#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
16800#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
16801#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
16802#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
16803#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
16804#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
16805#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
16806#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
16807#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
16808#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
16809#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
16810#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
16811#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
16812#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
16813#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
16814#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
16815#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
16816#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
16817#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
16818#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
16819#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
16820#define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
16821#define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos)
16822#define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
16823#define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
16824#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
16825#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
16826#define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
16827#define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos)
16828#define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
16829
16830/******************** Bit definition for RCC_APB4LPENR register ******************/
16831#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
16832#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
16833#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
16834#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
16835#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
16836#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
16837#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
16838#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
16839#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
16840#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
16841#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
16842#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
16843#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
16844#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
16845#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
16846#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
16847#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
16848#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
16849#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
16850#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos)
16851#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
16852#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
16853#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos)
16854#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
16855#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
16856#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
16857#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
16858#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
16859#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
16860#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
16861#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
16862#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
16863#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
16864#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
16865#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos)
16866#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
16867
16868
16869/******************** Bit definition for RCC_RSR register *******************/
16870#define RCC_RSR_RMVF_Pos (16U)
16871#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos)
16872#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
16873#define RCC_RSR_C1RSTF_Pos (17U)
16874#define RCC_RSR_C1RSTF_Msk (0x1UL << RCC_RSR_C1RSTF_Pos)
16875#define RCC_RSR_C1RSTF RCC_RSR_C1RSTF_Msk
16876#define RCC_RSR_D1RSTF_Pos (19U)
16877#define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos)
16878#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
16879#define RCC_RSR_D2RSTF_Pos (20U)
16880#define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos)
16881#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
16882#define RCC_RSR_BORRSTF_Pos (21U)
16883#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos)
16884#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
16885#define RCC_RSR_PINRSTF_Pos (22U)
16886#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos)
16887#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
16888#define RCC_RSR_PORRSTF_Pos (23U)
16889#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos)
16890#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
16891#define RCC_RSR_SFT1RSTF_Pos (24U)
16892#define RCC_RSR_SFT1RSTF_Msk (0x1UL << RCC_RSR_SFT1RSTF_Pos)
16893#define RCC_RSR_SFT1RSTF RCC_RSR_SFT1RSTF_Msk
16894#define RCC_RSR_IWDG1RSTF_Pos (26U)
16895#define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos)
16896#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
16897#define RCC_RSR_WWDG1RSTF_Pos (28U)
16898#define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos)
16899#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
16900
16901#define RCC_RSR_WWDG2RSTF_Pos (29U)
16902#define RCC_RSR_WWDG2RSTF_Msk (0x1UL << RCC_RSR_WWDG2RSTF_Pos)
16903#define RCC_RSR_WWDG2RSTF RCC_RSR_WWDG2RSTF_Msk
16904#define RCC_RSR_IWDG2RSTF_Pos (27U)
16905#define RCC_RSR_IWDG2RSTF_Msk (0x1UL << RCC_RSR_IWDG2RSTF_Pos)
16906#define RCC_RSR_IWDG2RSTF RCC_RSR_IWDG2RSTF_Msk
16907#define RCC_RSR_SFT2RSTF_Pos (25U)
16908#define RCC_RSR_SFT2RSTF_Msk (0x1UL << RCC_RSR_SFT2RSTF_Pos)
16909#define RCC_RSR_SFT2RSTF RCC_RSR_SFT2RSTF_Msk
16910#define RCC_RSR_C2RSTF_Pos (18U)
16911#define RCC_RSR_C2RSTF_Msk (0x1UL << RCC_RSR_C2RSTF_Pos)
16912#define RCC_RSR_C2RSTF RCC_RSR_C2RSTF_Msk
16913#define RCC_RSR_LPWR1RSTF_Pos (30U)
16914#define RCC_RSR_LPWR1RSTF_Msk (0x1UL << RCC_RSR_LPWR1RSTF_Pos)
16915#define RCC_RSR_LPWR1RSTF RCC_RSR_LPWR1RSTF_Msk
16916#define RCC_RSR_LPWR2RSTF_Pos (31U)
16917#define RCC_RSR_LPWR2RSTF_Msk (0x1UL << RCC_RSR_LPWR2RSTF_Pos)
16918#define RCC_RSR_LPWR2RSTF RCC_RSR_LPWR2RSTF_Msk
16919
16920
16921/******************************************************************************/
16922/* */
16923/* RNG */
16924/* */
16925/******************************************************************************/
16926/******************** Bits definition for RNG_CR register *******************/
16927#define RNG_CR_RNGEN_Pos (2U)
16928#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
16929#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
16930#define RNG_CR_IE_Pos (3U)
16931#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
16932#define RNG_CR_IE RNG_CR_IE_Msk
16933#define RNG_CR_CED_Pos (5U)
16934#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)
16935#define RNG_CR_CED RNG_CR_CED_Msk
16936
16937/******************** Bits definition for RNG_SR register *******************/
16938#define RNG_SR_DRDY_Pos (0U)
16939#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
16940#define RNG_SR_DRDY RNG_SR_DRDY_Msk
16941#define RNG_SR_CECS_Pos (1U)
16942#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
16943#define RNG_SR_CECS RNG_SR_CECS_Msk
16944#define RNG_SR_SECS_Pos (2U)
16945#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
16946#define RNG_SR_SECS RNG_SR_SECS_Msk
16947#define RNG_SR_CEIS_Pos (5U)
16948#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
16949#define RNG_SR_CEIS RNG_SR_CEIS_Msk
16950#define RNG_SR_SEIS_Pos (6U)
16951#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
16952#define RNG_SR_SEIS RNG_SR_SEIS_Msk
16953
16954/******************************************************************************/
16955/* */
16956/* Real-Time Clock (RTC) */
16957/* */
16958/******************************************************************************/
16959/******************** Bits definition for RTC_TR register *******************/
16960#define RTC_TR_PM_Pos (22U)
16961#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
16962#define RTC_TR_PM RTC_TR_PM_Msk
16963#define RTC_TR_HT_Pos (20U)
16964#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
16965#define RTC_TR_HT RTC_TR_HT_Msk
16966#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
16967#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
16968#define RTC_TR_HU_Pos (16U)
16969#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
16970#define RTC_TR_HU RTC_TR_HU_Msk
16971#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
16972#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
16973#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
16974#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
16975#define RTC_TR_MNT_Pos (12U)
16976#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
16977#define RTC_TR_MNT RTC_TR_MNT_Msk
16978#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
16979#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
16980#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
16981#define RTC_TR_MNU_Pos (8U)
16982#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
16983#define RTC_TR_MNU RTC_TR_MNU_Msk
16984#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
16985#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
16986#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
16987#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
16988#define RTC_TR_ST_Pos (4U)
16989#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
16990#define RTC_TR_ST RTC_TR_ST_Msk
16991#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
16992#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
16993#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
16994#define RTC_TR_SU_Pos (0U)
16995#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
16996#define RTC_TR_SU RTC_TR_SU_Msk
16997#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
16998#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
16999#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
17000#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
17002/******************** Bits definition for RTC_DR register *******************/
17003#define RTC_DR_YT_Pos (20U)
17004#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
17005#define RTC_DR_YT RTC_DR_YT_Msk
17006#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
17007#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
17008#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
17009#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
17010#define RTC_DR_YU_Pos (16U)
17011#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
17012#define RTC_DR_YU RTC_DR_YU_Msk
17013#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
17014#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
17015#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
17016#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
17017#define RTC_DR_WDU_Pos (13U)
17018#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
17019#define RTC_DR_WDU RTC_DR_WDU_Msk
17020#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
17021#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
17022#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
17023#define RTC_DR_MT_Pos (12U)
17024#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
17025#define RTC_DR_MT RTC_DR_MT_Msk
17026#define RTC_DR_MU_Pos (8U)
17027#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
17028#define RTC_DR_MU RTC_DR_MU_Msk
17029#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
17030#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
17031#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
17032#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
17033#define RTC_DR_DT_Pos (4U)
17034#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
17035#define RTC_DR_DT RTC_DR_DT_Msk
17036#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
17037#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
17038#define RTC_DR_DU_Pos (0U)
17039#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
17040#define RTC_DR_DU RTC_DR_DU_Msk
17041#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
17042#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
17043#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
17044#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
17046/******************** Bits definition for RTC_CR register *******************/
17047#define RTC_CR_ITSE_Pos (24U)
17048#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
17049#define RTC_CR_ITSE RTC_CR_ITSE_Msk
17050#define RTC_CR_COE_Pos (23U)
17051#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
17052#define RTC_CR_COE RTC_CR_COE_Msk
17053#define RTC_CR_OSEL_Pos (21U)
17054#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
17055#define RTC_CR_OSEL RTC_CR_OSEL_Msk
17056#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
17057#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
17058#define RTC_CR_POL_Pos (20U)
17059#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
17060#define RTC_CR_POL RTC_CR_POL_Msk
17061#define RTC_CR_COSEL_Pos (19U)
17062#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
17063#define RTC_CR_COSEL RTC_CR_COSEL_Msk
17064#define RTC_CR_BKP_Pos (18U)
17065#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
17066#define RTC_CR_BKP RTC_CR_BKP_Msk
17067#define RTC_CR_SUB1H_Pos (17U)
17068#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
17069#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
17070#define RTC_CR_ADD1H_Pos (16U)
17071#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
17072#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
17073#define RTC_CR_TSIE_Pos (15U)
17074#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
17075#define RTC_CR_TSIE RTC_CR_TSIE_Msk
17076#define RTC_CR_WUTIE_Pos (14U)
17077#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
17078#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
17079#define RTC_CR_ALRBIE_Pos (13U)
17080#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
17081#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
17082#define RTC_CR_ALRAIE_Pos (12U)
17083#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
17084#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
17085#define RTC_CR_TSE_Pos (11U)
17086#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
17087#define RTC_CR_TSE RTC_CR_TSE_Msk
17088#define RTC_CR_WUTE_Pos (10U)
17089#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
17090#define RTC_CR_WUTE RTC_CR_WUTE_Msk
17091#define RTC_CR_ALRBE_Pos (9U)
17092#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
17093#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
17094#define RTC_CR_ALRAE_Pos (8U)
17095#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
17096#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
17097#define RTC_CR_FMT_Pos (6U)
17098#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
17099#define RTC_CR_FMT RTC_CR_FMT_Msk
17100#define RTC_CR_BYPSHAD_Pos (5U)
17101#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
17102#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
17103#define RTC_CR_REFCKON_Pos (4U)
17104#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
17105#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
17106#define RTC_CR_TSEDGE_Pos (3U)
17107#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
17108#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
17109#define RTC_CR_WUCKSEL_Pos (0U)
17110#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
17111#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
17112#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
17113#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
17114#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
17116/******************** Bits definition for RTC_ISR register ******************/
17117#define RTC_ISR_ITSF_Pos (17U)
17118#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
17119#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
17120#define RTC_ISR_RECALPF_Pos (16U)
17121#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
17122#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
17123#define RTC_ISR_TAMP3F_Pos (15U)
17124#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
17125#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
17126#define RTC_ISR_TAMP2F_Pos (14U)
17127#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
17128#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
17129#define RTC_ISR_TAMP1F_Pos (13U)
17130#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
17131#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
17132#define RTC_ISR_TSOVF_Pos (12U)
17133#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
17134#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
17135#define RTC_ISR_TSF_Pos (11U)
17136#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
17137#define RTC_ISR_TSF RTC_ISR_TSF_Msk
17138#define RTC_ISR_WUTF_Pos (10U)
17139#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
17140#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
17141#define RTC_ISR_ALRBF_Pos (9U)
17142#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
17143#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
17144#define RTC_ISR_ALRAF_Pos (8U)
17145#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
17146#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
17147#define RTC_ISR_INIT_Pos (7U)
17148#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
17149#define RTC_ISR_INIT RTC_ISR_INIT_Msk
17150#define RTC_ISR_INITF_Pos (6U)
17151#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
17152#define RTC_ISR_INITF RTC_ISR_INITF_Msk
17153#define RTC_ISR_RSF_Pos (5U)
17154#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
17155#define RTC_ISR_RSF RTC_ISR_RSF_Msk
17156#define RTC_ISR_INITS_Pos (4U)
17157#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
17158#define RTC_ISR_INITS RTC_ISR_INITS_Msk
17159#define RTC_ISR_SHPF_Pos (3U)
17160#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
17161#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
17162#define RTC_ISR_WUTWF_Pos (2U)
17163#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
17164#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
17165#define RTC_ISR_ALRBWF_Pos (1U)
17166#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
17167#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
17168#define RTC_ISR_ALRAWF_Pos (0U)
17169#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
17170#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
17171
17172/******************** Bits definition for RTC_PRER register *****************/
17173#define RTC_PRER_PREDIV_A_Pos (16U)
17174#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
17175#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
17176#define RTC_PRER_PREDIV_S_Pos (0U)
17177#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
17178#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
17179
17180/******************** Bits definition for RTC_WUTR register *****************/
17181#define RTC_WUTR_WUT_Pos (0U)
17182#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
17183#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
17184
17185/******************** Bits definition for RTC_ALRMAR register ***************/
17186#define RTC_ALRMAR_MSK4_Pos (31U)
17187#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
17188#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
17189#define RTC_ALRMAR_WDSEL_Pos (30U)
17190#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
17191#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
17192#define RTC_ALRMAR_DT_Pos (28U)
17193#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
17194#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
17195#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
17196#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
17197#define RTC_ALRMAR_DU_Pos (24U)
17198#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
17199#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
17200#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
17201#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
17202#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
17203#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
17204#define RTC_ALRMAR_MSK3_Pos (23U)
17205#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
17206#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
17207#define RTC_ALRMAR_PM_Pos (22U)
17208#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
17209#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
17210#define RTC_ALRMAR_HT_Pos (20U)
17211#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
17212#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
17213#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
17214#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
17215#define RTC_ALRMAR_HU_Pos (16U)
17216#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
17217#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
17218#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
17219#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
17220#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
17221#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
17222#define RTC_ALRMAR_MSK2_Pos (15U)
17223#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
17224#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
17225#define RTC_ALRMAR_MNT_Pos (12U)
17226#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
17227#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
17228#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
17229#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
17230#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
17231#define RTC_ALRMAR_MNU_Pos (8U)
17232#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
17233#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
17234#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
17235#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
17236#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
17237#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
17238#define RTC_ALRMAR_MSK1_Pos (7U)
17239#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
17240#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
17241#define RTC_ALRMAR_ST_Pos (4U)
17242#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
17243#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
17244#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
17245#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
17246#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
17247#define RTC_ALRMAR_SU_Pos (0U)
17248#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
17249#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
17250#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
17251#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
17252#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
17253#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
17255/******************** Bits definition for RTC_ALRMBR register ***************/
17256#define RTC_ALRMBR_MSK4_Pos (31U)
17257#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
17258#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
17259#define RTC_ALRMBR_WDSEL_Pos (30U)
17260#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
17261#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
17262#define RTC_ALRMBR_DT_Pos (28U)
17263#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
17264#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
17265#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
17266#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
17267#define RTC_ALRMBR_DU_Pos (24U)
17268#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
17269#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
17270#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
17271#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
17272#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
17273#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
17274#define RTC_ALRMBR_MSK3_Pos (23U)
17275#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
17276#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
17277#define RTC_ALRMBR_PM_Pos (22U)
17278#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
17279#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
17280#define RTC_ALRMBR_HT_Pos (20U)
17281#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
17282#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
17283#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
17284#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
17285#define RTC_ALRMBR_HU_Pos (16U)
17286#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
17287#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
17288#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
17289#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
17290#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
17291#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
17292#define RTC_ALRMBR_MSK2_Pos (15U)
17293#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
17294#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
17295#define RTC_ALRMBR_MNT_Pos (12U)
17296#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
17297#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
17298#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
17299#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
17300#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
17301#define RTC_ALRMBR_MNU_Pos (8U)
17302#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
17303#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
17304#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
17305#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
17306#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
17307#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
17308#define RTC_ALRMBR_MSK1_Pos (7U)
17309#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
17310#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
17311#define RTC_ALRMBR_ST_Pos (4U)
17312#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
17313#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
17314#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
17315#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
17316#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
17317#define RTC_ALRMBR_SU_Pos (0U)
17318#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
17319#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
17320#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
17321#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
17322#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
17323#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
17325/******************** Bits definition for RTC_WPR register ******************/
17326#define RTC_WPR_KEY_Pos (0U)
17327#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
17328#define RTC_WPR_KEY RTC_WPR_KEY_Msk
17329
17330/******************** Bits definition for RTC_SSR register ******************/
17331#define RTC_SSR_SS_Pos (0U)
17332#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
17333#define RTC_SSR_SS RTC_SSR_SS_Msk
17334
17335/******************** Bits definition for RTC_SHIFTR register ***************/
17336#define RTC_SHIFTR_SUBFS_Pos (0U)
17337#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
17338#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
17339#define RTC_SHIFTR_ADD1S_Pos (31U)
17340#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
17341#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
17342
17343/******************** Bits definition for RTC_TSTR register *****************/
17344#define RTC_TSTR_PM_Pos (22U)
17345#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
17346#define RTC_TSTR_PM RTC_TSTR_PM_Msk
17347#define RTC_TSTR_HT_Pos (20U)
17348#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
17349#define RTC_TSTR_HT RTC_TSTR_HT_Msk
17350#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
17351#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
17352#define RTC_TSTR_HU_Pos (16U)
17353#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
17354#define RTC_TSTR_HU RTC_TSTR_HU_Msk
17355#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
17356#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
17357#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
17358#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
17359#define RTC_TSTR_MNT_Pos (12U)
17360#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
17361#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
17362#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
17363#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
17364#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
17365#define RTC_TSTR_MNU_Pos (8U)
17366#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
17367#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
17368#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
17369#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
17370#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
17371#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
17372#define RTC_TSTR_ST_Pos (4U)
17373#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
17374#define RTC_TSTR_ST RTC_TSTR_ST_Msk
17375#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
17376#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
17377#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
17378#define RTC_TSTR_SU_Pos (0U)
17379#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
17380#define RTC_TSTR_SU RTC_TSTR_SU_Msk
17381#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
17382#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
17383#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
17384#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
17386/******************** Bits definition for RTC_TSDR register *****************/
17387#define RTC_TSDR_WDU_Pos (13U)
17388#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
17389#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
17390#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
17391#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
17392#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
17393#define RTC_TSDR_MT_Pos (12U)
17394#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
17395#define RTC_TSDR_MT RTC_TSDR_MT_Msk
17396#define RTC_TSDR_MU_Pos (8U)
17397#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
17398#define RTC_TSDR_MU RTC_TSDR_MU_Msk
17399#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
17400#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
17401#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
17402#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
17403#define RTC_TSDR_DT_Pos (4U)
17404#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
17405#define RTC_TSDR_DT RTC_TSDR_DT_Msk
17406#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
17407#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
17408#define RTC_TSDR_DU_Pos (0U)
17409#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
17410#define RTC_TSDR_DU RTC_TSDR_DU_Msk
17411#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
17412#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
17413#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
17414#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
17416/******************** Bits definition for RTC_TSSSR register ****************/
17417#define RTC_TSSSR_SS_Pos (0U)
17418#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
17419#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
17420
17421/******************** Bits definition for RTC_CALR register *****************/
17422#define RTC_CALR_CALP_Pos (15U)
17423#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
17424#define RTC_CALR_CALP RTC_CALR_CALP_Msk
17425#define RTC_CALR_CALW8_Pos (14U)
17426#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
17427#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
17428#define RTC_CALR_CALW16_Pos (13U)
17429#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
17430#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
17431#define RTC_CALR_CALM_Pos (0U)
17432#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
17433#define RTC_CALR_CALM RTC_CALR_CALM_Msk
17434#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
17435#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
17436#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
17437#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
17438#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
17439#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
17440#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
17441#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
17442#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
17444/******************** Bits definition for RTC_TAMPCR register ***************/
17445#define RTC_TAMPCR_TAMP3MF_Pos (24U)
17446#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
17447#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
17448#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
17449#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
17450#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
17451#define RTC_TAMPCR_TAMP3IE_Pos (22U)
17452#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
17453#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
17454#define RTC_TAMPCR_TAMP2MF_Pos (21U)
17455#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
17456#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
17457#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
17458#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
17459#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
17460#define RTC_TAMPCR_TAMP2IE_Pos (19U)
17461#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
17462#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
17463#define RTC_TAMPCR_TAMP1MF_Pos (18U)
17464#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
17465#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
17466#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
17467#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
17468#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
17469#define RTC_TAMPCR_TAMP1IE_Pos (16U)
17470#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
17471#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
17472#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
17473#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
17474#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
17475#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
17476#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
17477#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
17478#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
17479#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
17480#define RTC_TAMPCR_TAMPFLT_Pos (11U)
17481#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
17482#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
17483#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
17484#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
17485#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
17486#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
17487#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
17488#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
17489#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
17490#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
17491#define RTC_TAMPCR_TAMPTS_Pos (7U)
17492#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
17493#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
17494#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
17495#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
17496#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
17497#define RTC_TAMPCR_TAMP3E_Pos (5U)
17498#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
17499#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
17500#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
17501#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
17502#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
17503#define RTC_TAMPCR_TAMP2E_Pos (3U)
17504#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
17505#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
17506#define RTC_TAMPCR_TAMPIE_Pos (2U)
17507#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
17508#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
17509#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
17510#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
17511#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
17512#define RTC_TAMPCR_TAMP1E_Pos (0U)
17513#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
17514#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
17515
17516/******************** Bits definition for RTC_ALRMASSR register *************/
17517#define RTC_ALRMASSR_MASKSS_Pos (24U)
17518#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
17519#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
17520#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
17521#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
17522#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
17523#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
17524#define RTC_ALRMASSR_SS_Pos (0U)
17525#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
17526#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
17527
17528/******************** Bits definition for RTC_ALRMBSSR register *************/
17529#define RTC_ALRMBSSR_MASKSS_Pos (24U)
17530#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
17531#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
17532#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
17533#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
17534#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
17535#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
17536#define RTC_ALRMBSSR_SS_Pos (0U)
17537#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
17538#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
17539
17540/******************** Bits definition for RTC_OR register *******************/
17541#define RTC_OR_OUT_RMP_Pos (1U)
17542#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
17543#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
17544#define RTC_OR_ALARMOUTTYPE_Pos (0U)
17545#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
17546#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
17547
17548/******************** Bits definition for RTC_BKP0R register ****************/
17549#define RTC_BKP0R_Pos (0U)
17550#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
17551#define RTC_BKP0R RTC_BKP0R_Msk
17552
17553/******************** Bits definition for RTC_BKP1R register ****************/
17554#define RTC_BKP1R_Pos (0U)
17555#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
17556#define RTC_BKP1R RTC_BKP1R_Msk
17557
17558/******************** Bits definition for RTC_BKP2R register ****************/
17559#define RTC_BKP2R_Pos (0U)
17560#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
17561#define RTC_BKP2R RTC_BKP2R_Msk
17562
17563/******************** Bits definition for RTC_BKP3R register ****************/
17564#define RTC_BKP3R_Pos (0U)
17565#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
17566#define RTC_BKP3R RTC_BKP3R_Msk
17567
17568/******************** Bits definition for RTC_BKP4R register ****************/
17569#define RTC_BKP4R_Pos (0U)
17570#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
17571#define RTC_BKP4R RTC_BKP4R_Msk
17572
17573/******************** Bits definition for RTC_BKP5R register ****************/
17574#define RTC_BKP5R_Pos (0U)
17575#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
17576#define RTC_BKP5R RTC_BKP5R_Msk
17577
17578/******************** Bits definition for RTC_BKP6R register ****************/
17579#define RTC_BKP6R_Pos (0U)
17580#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
17581#define RTC_BKP6R RTC_BKP6R_Msk
17582
17583/******************** Bits definition for RTC_BKP7R register ****************/
17584#define RTC_BKP7R_Pos (0U)
17585#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
17586#define RTC_BKP7R RTC_BKP7R_Msk
17587
17588/******************** Bits definition for RTC_BKP8R register ****************/
17589#define RTC_BKP8R_Pos (0U)
17590#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
17591#define RTC_BKP8R RTC_BKP8R_Msk
17592
17593/******************** Bits definition for RTC_BKP9R register ****************/
17594#define RTC_BKP9R_Pos (0U)
17595#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
17596#define RTC_BKP9R RTC_BKP9R_Msk
17597
17598/******************** Bits definition for RTC_BKP10R register ***************/
17599#define RTC_BKP10R_Pos (0U)
17600#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
17601#define RTC_BKP10R RTC_BKP10R_Msk
17602
17603/******************** Bits definition for RTC_BKP11R register ***************/
17604#define RTC_BKP11R_Pos (0U)
17605#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
17606#define RTC_BKP11R RTC_BKP11R_Msk
17607
17608/******************** Bits definition for RTC_BKP12R register ***************/
17609#define RTC_BKP12R_Pos (0U)
17610#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
17611#define RTC_BKP12R RTC_BKP12R_Msk
17612
17613/******************** Bits definition for RTC_BKP13R register ***************/
17614#define RTC_BKP13R_Pos (0U)
17615#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
17616#define RTC_BKP13R RTC_BKP13R_Msk
17617
17618/******************** Bits definition for RTC_BKP14R register ***************/
17619#define RTC_BKP14R_Pos (0U)
17620#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
17621#define RTC_BKP14R RTC_BKP14R_Msk
17622
17623/******************** Bits definition for RTC_BKP15R register ***************/
17624#define RTC_BKP15R_Pos (0U)
17625#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
17626#define RTC_BKP15R RTC_BKP15R_Msk
17627
17628/******************** Bits definition for RTC_BKP16R register ***************/
17629#define RTC_BKP16R_Pos (0U)
17630#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
17631#define RTC_BKP16R RTC_BKP16R_Msk
17632
17633/******************** Bits definition for RTC_BKP17R register ***************/
17634#define RTC_BKP17R_Pos (0U)
17635#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
17636#define RTC_BKP17R RTC_BKP17R_Msk
17637
17638/******************** Bits definition for RTC_BKP18R register ***************/
17639#define RTC_BKP18R_Pos (0U)
17640#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
17641#define RTC_BKP18R RTC_BKP18R_Msk
17642
17643/******************** Bits definition for RTC_BKP19R register ***************/
17644#define RTC_BKP19R_Pos (0U)
17645#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
17646#define RTC_BKP19R RTC_BKP19R_Msk
17647
17648/******************** Bits definition for RTC_BKP20R register ***************/
17649#define RTC_BKP20R_Pos (0U)
17650#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
17651#define RTC_BKP20R RTC_BKP20R_Msk
17652
17653/******************** Bits definition for RTC_BKP21R register ***************/
17654#define RTC_BKP21R_Pos (0U)
17655#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
17656#define RTC_BKP21R RTC_BKP21R_Msk
17657
17658/******************** Bits definition for RTC_BKP22R register ***************/
17659#define RTC_BKP22R_Pos (0U)
17660#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
17661#define RTC_BKP22R RTC_BKP22R_Msk
17662
17663/******************** Bits definition for RTC_BKP23R register ***************/
17664#define RTC_BKP23R_Pos (0U)
17665#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
17666#define RTC_BKP23R RTC_BKP23R_Msk
17667
17668/******************** Bits definition for RTC_BKP24R register ***************/
17669#define RTC_BKP24R_Pos (0U)
17670#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
17671#define RTC_BKP24R RTC_BKP24R_Msk
17672
17673/******************** Bits definition for RTC_BKP25R register ***************/
17674#define RTC_BKP25R_Pos (0U)
17675#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
17676#define RTC_BKP25R RTC_BKP25R_Msk
17677
17678/******************** Bits definition for RTC_BKP26R register ***************/
17679#define RTC_BKP26R_Pos (0U)
17680#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
17681#define RTC_BKP26R RTC_BKP26R_Msk
17682
17683/******************** Bits definition for RTC_BKP27R register ***************/
17684#define RTC_BKP27R_Pos (0U)
17685#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
17686#define RTC_BKP27R RTC_BKP27R_Msk
17687
17688/******************** Bits definition for RTC_BKP28R register ***************/
17689#define RTC_BKP28R_Pos (0U)
17690#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
17691#define RTC_BKP28R RTC_BKP28R_Msk
17692
17693/******************** Bits definition for RTC_BKP29R register ***************/
17694#define RTC_BKP29R_Pos (0U)
17695#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
17696#define RTC_BKP29R RTC_BKP29R_Msk
17697
17698/******************** Bits definition for RTC_BKP30R register ***************/
17699#define RTC_BKP30R_Pos (0U)
17700#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
17701#define RTC_BKP30R RTC_BKP30R_Msk
17702
17703/******************** Bits definition for RTC_BKP31R register ***************/
17704#define RTC_BKP31R_Pos (0U)
17705#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
17706#define RTC_BKP31R RTC_BKP31R_Msk
17707
17708/******************** Number of backup registers ******************************/
17709#define RTC_BKP_NUMBER_Pos (5U)
17710#define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos)
17711#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
17712
17713/******************************************************************************/
17714/* */
17715/* SPDIF-RX Interface */
17716/* */
17717/******************************************************************************/
17718/******************** Bit definition for SPDIF_CR register ******************/
17719#define SPDIFRX_CR_SPDIFEN_Pos (0U)
17720#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
17721#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
17722#define SPDIFRX_CR_RXDMAEN_Pos (2U)
17723#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
17724#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
17725#define SPDIFRX_CR_RXSTEO_Pos (3U)
17726#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
17727#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
17728#define SPDIFRX_CR_DRFMT_Pos (4U)
17729#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
17730#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
17731#define SPDIFRX_CR_PMSK_Pos (6U)
17732#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
17733#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
17734#define SPDIFRX_CR_VMSK_Pos (7U)
17735#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
17736#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
17737#define SPDIFRX_CR_CUMSK_Pos (8U)
17738#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
17739#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
17740#define SPDIFRX_CR_PTMSK_Pos (9U)
17741#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
17742#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
17743#define SPDIFRX_CR_CBDMAEN_Pos (10U)
17744#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
17745#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
17746#define SPDIFRX_CR_CHSEL_Pos (11U)
17747#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
17748#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
17749#define SPDIFRX_CR_NBTR_Pos (12U)
17750#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
17751#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
17752#define SPDIFRX_CR_WFA_Pos (14U)
17753#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
17754#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
17755#define SPDIFRX_CR_INSEL_Pos (16U)
17756#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
17757#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
17758#define SPDIFRX_CR_CKSEN_Pos (20U)
17759#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos)
17760#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk
17761#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
17762#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
17763#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk
17765/******************* Bit definition for SPDIFRX_IMR register *******************/
17766#define SPDIFRX_IMR_RXNEIE_Pos (0U)
17767#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
17768#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
17769#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
17770#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
17771#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
17772#define SPDIFRX_IMR_PERRIE_Pos (2U)
17773#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
17774#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
17775#define SPDIFRX_IMR_OVRIE_Pos (3U)
17776#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
17777#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
17778#define SPDIFRX_IMR_SBLKIE_Pos (4U)
17779#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
17780#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
17781#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
17782#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
17783#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
17784#define SPDIFRX_IMR_IFEIE_Pos (6U)
17785#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
17786#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
17788/******************* Bit definition for SPDIFRX_SR register *******************/
17789#define SPDIFRX_SR_RXNE_Pos (0U)
17790#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
17791#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
17792#define SPDIFRX_SR_CSRNE_Pos (1U)
17793#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
17794#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
17795#define SPDIFRX_SR_PERR_Pos (2U)
17796#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
17797#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
17798#define SPDIFRX_SR_OVR_Pos (3U)
17799#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
17800#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
17801#define SPDIFRX_SR_SBD_Pos (4U)
17802#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
17803#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
17804#define SPDIFRX_SR_SYNCD_Pos (5U)
17805#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
17806#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
17807#define SPDIFRX_SR_FERR_Pos (6U)
17808#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
17809#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
17810#define SPDIFRX_SR_SERR_Pos (7U)
17811#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
17812#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
17813#define SPDIFRX_SR_TERR_Pos (8U)
17814#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
17815#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
17816#define SPDIFRX_SR_WIDTH5_Pos (16U)
17817#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
17818#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
17820/******************* Bit definition for SPDIFRX_IFCR register *******************/
17821#define SPDIFRX_IFCR_PERRCF_Pos (2U)
17822#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
17823#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
17824#define SPDIFRX_IFCR_OVRCF_Pos (3U)
17825#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
17826#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
17827#define SPDIFRX_IFCR_SBDCF_Pos (4U)
17828#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
17829#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
17830#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
17831#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
17832#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
17834/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
17835#define SPDIFRX_DR0_DR_Pos (0U)
17836#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
17837#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
17838#define SPDIFRX_DR0_PE_Pos (24U)
17839#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
17840#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
17841#define SPDIFRX_DR0_V_Pos (25U)
17842#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
17843#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
17844#define SPDIFRX_DR0_U_Pos (26U)
17845#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
17846#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
17847#define SPDIFRX_DR0_C_Pos (27U)
17848#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
17849#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
17850#define SPDIFRX_DR0_PT_Pos (28U)
17851#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
17852#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
17854/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
17855#define SPDIFRX_DR1_DR_Pos (8U)
17856#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
17857#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
17858#define SPDIFRX_DR1_PT_Pos (4U)
17859#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
17860#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
17861#define SPDIFRX_DR1_C_Pos (3U)
17862#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
17863#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
17864#define SPDIFRX_DR1_U_Pos (2U)
17865#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
17866#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
17867#define SPDIFRX_DR1_V_Pos (1U)
17868#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
17869#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
17870#define SPDIFRX_DR1_PE_Pos (0U)
17871#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
17872#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
17874/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
17875#define SPDIFRX_DR1_DRNL1_Pos (16U)
17876#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
17877#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
17878#define SPDIFRX_DR1_DRNL2_Pos (0U)
17879#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
17880#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
17882/******************* Bit definition for SPDIFRX_CSR register *******************/
17883#define SPDIFRX_CSR_USR_Pos (0U)
17884#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
17885#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
17886#define SPDIFRX_CSR_CS_Pos (16U)
17887#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
17888#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
17889#define SPDIFRX_CSR_SOB_Pos (24U)
17890#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
17891#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
17893/******************* Bit definition for SPDIFRX_DIR register *******************/
17894#define SPDIFRX_DIR_THI_Pos (0U)
17895#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
17896#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
17897#define SPDIFRX_DIR_TLO_Pos (16U)
17898#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
17899#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
17901/******************* Bit definition for SPDIFRX_VERR register *******************/
17902#define SPDIFRX_VERR_MINREV_Pos (0U)
17903#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos)
17904#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk
17905#define SPDIFRX_VERR_MAJREV_Pos (4U)
17906#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
17907#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk
17909/******************* Bit definition for SPDIFRX_IDR register *******************/
17910#define SPDIFRX_IDR_ID_Pos (0U)
17911#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
17912#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk
17914/******************* Bit definition for SPDIFRX_SIDR register *******************/
17915#define SPDIFRX_SIDR_SID_Pos (0U)
17916#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
17917#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk
17919/******************************************************************************/
17920/* */
17921/* Serial Audio Interface */
17922/* */
17923/******************************************************************************/
17924/******************************* SAI VERSION ********************************/
17925#define SAI_VER_V2_X
17926
17927/******************** Bit definition for SAI_GCR register *******************/
17928#define SAI_GCR_SYNCIN_Pos (0U)
17929#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
17930#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
17931#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
17932#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
17934#define SAI_GCR_SYNCOUT_Pos (4U)
17935#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
17936#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
17937#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
17938#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
17940/******************* Bit definition for SAI_xCR1 register *******************/
17941#define SAI_xCR1_MODE_Pos (0U)
17942#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
17943#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
17944#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
17945#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
17947#define SAI_xCR1_PRTCFG_Pos (2U)
17948#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
17949#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
17950#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
17951#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
17953#define SAI_xCR1_DS_Pos (5U)
17954#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
17955#define SAI_xCR1_DS SAI_xCR1_DS_Msk
17956#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
17957#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
17958#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
17960#define SAI_xCR1_LSBFIRST_Pos (8U)
17961#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
17962#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
17963#define SAI_xCR1_CKSTR_Pos (9U)
17964#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
17965#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
17967#define SAI_xCR1_SYNCEN_Pos (10U)
17968#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
17969#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
17970#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
17971#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
17973#define SAI_xCR1_MONO_Pos (12U)
17974#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
17975#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
17976#define SAI_xCR1_OUTDRIV_Pos (13U)
17977#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
17978#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
17979#define SAI_xCR1_SAIEN_Pos (16U)
17980#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
17981#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
17982#define SAI_xCR1_DMAEN_Pos (17U)
17983#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
17984#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
17985#define SAI_xCR1_NODIV_Pos (19U)
17986#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
17987#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
17989#define SAI_xCR1_MCKDIV_Pos (20U)
17990#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
17991#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
17992#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos)
17993#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos)
17994#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos)
17995#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos)
17996#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos)
17997#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos)
17999#define SAI_xCR1_MCKEN_Pos (27U)
18000#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
18001#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
18003#define SAI_xCR1_OSR_Pos (26U)
18004#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
18005#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
18007/* Legacy define */
18008#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
18009
18010/******************* Bit definition for SAI_xCR2 register *******************/
18011#define SAI_xCR2_FTH_Pos (0U)
18012#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
18013#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
18014#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
18015#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
18016#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
18018#define SAI_xCR2_FFLUSH_Pos (3U)
18019#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
18020#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
18021#define SAI_xCR2_TRIS_Pos (4U)
18022#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
18023#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
18024#define SAI_xCR2_MUTE_Pos (5U)
18025#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
18026#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
18027#define SAI_xCR2_MUTEVAL_Pos (6U)
18028#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
18029#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
18031#define SAI_xCR2_MUTECNT_Pos (7U)
18032#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
18033#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
18034#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
18035#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
18036#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
18037#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
18038#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
18039#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
18041#define SAI_xCR2_CPL_Pos (13U)
18042#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
18043#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
18045#define SAI_xCR2_COMP_Pos (14U)
18046#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
18047#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
18048#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
18049#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
18051/****************** Bit definition for SAI_xFRCR register *******************/
18052#define SAI_xFRCR_FRL_Pos (0U)
18053#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
18054#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
18055#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
18056#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
18057#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
18058#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
18059#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
18060#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
18061#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
18062#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
18064#define SAI_xFRCR_FSALL_Pos (8U)
18065#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
18066#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
18067#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
18068#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
18069#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
18070#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
18071#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
18072#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
18073#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
18075#define SAI_xFRCR_FSDEF_Pos (16U)
18076#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
18077#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
18078#define SAI_xFRCR_FSPOL_Pos (17U)
18079#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
18080#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
18081#define SAI_xFRCR_FSOFF_Pos (18U)
18082#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
18083#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
18085/* Legacy define */
18086#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
18087
18088/****************** Bit definition for SAI_xSLOTR register *******************/
18089#define SAI_xSLOTR_FBOFF_Pos (0U)
18090#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
18091#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
18092#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
18093#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
18094#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
18095#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
18096#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
18098#define SAI_xSLOTR_SLOTSZ_Pos (6U)
18099#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
18100#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
18101#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
18102#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
18104#define SAI_xSLOTR_NBSLOT_Pos (8U)
18105#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
18106#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
18107#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
18108#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
18109#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
18110#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
18112#define SAI_xSLOTR_SLOTEN_Pos (16U)
18113#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
18114#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
18116/******************* Bit definition for SAI_xIMR register *******************/
18117#define SAI_xIMR_OVRUDRIE_Pos (0U)
18118#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
18119#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
18120#define SAI_xIMR_MUTEDETIE_Pos (1U)
18121#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
18122#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
18123#define SAI_xIMR_WCKCFGIE_Pos (2U)
18124#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
18125#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
18126#define SAI_xIMR_FREQIE_Pos (3U)
18127#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
18128#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
18129#define SAI_xIMR_CNRDYIE_Pos (4U)
18130#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
18131#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
18132#define SAI_xIMR_AFSDETIE_Pos (5U)
18133#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
18134#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
18135#define SAI_xIMR_LFSDETIE_Pos (6U)
18136#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
18137#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
18139/******************** Bit definition for SAI_xSR register *******************/
18140#define SAI_xSR_OVRUDR_Pos (0U)
18141#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
18142#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
18143#define SAI_xSR_MUTEDET_Pos (1U)
18144#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
18145#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
18146#define SAI_xSR_WCKCFG_Pos (2U)
18147#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
18148#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
18149#define SAI_xSR_FREQ_Pos (3U)
18150#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
18151#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
18152#define SAI_xSR_CNRDY_Pos (4U)
18153#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
18154#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
18155#define SAI_xSR_AFSDET_Pos (5U)
18156#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
18157#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
18158#define SAI_xSR_LFSDET_Pos (6U)
18159#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
18160#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
18162#define SAI_xSR_FLVL_Pos (16U)
18163#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
18164#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
18165#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
18166#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
18167#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
18169/****************** Bit definition for SAI_xCLRFR register ******************/
18170#define SAI_xCLRFR_COVRUDR_Pos (0U)
18171#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
18172#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
18173#define SAI_xCLRFR_CMUTEDET_Pos (1U)
18174#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
18175#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
18176#define SAI_xCLRFR_CWCKCFG_Pos (2U)
18177#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
18178#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
18179#define SAI_xCLRFR_CFREQ_Pos (3U)
18180#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
18181#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
18182#define SAI_xCLRFR_CCNRDY_Pos (4U)
18183#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
18184#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
18185#define SAI_xCLRFR_CAFSDET_Pos (5U)
18186#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
18187#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
18188#define SAI_xCLRFR_CLFSDET_Pos (6U)
18189#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
18190#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
18192/****************** Bit definition for SAI_xDR register *********************/
18193#define SAI_xDR_DATA_Pos (0U)
18194#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
18195#define SAI_xDR_DATA SAI_xDR_DATA_Msk
18196
18197/******************* Bit definition for SAI_PDMCR register ******************/
18198#define SAI_PDMCR_PDMEN_Pos (0U)
18199#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
18200#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
18202#define SAI_PDMCR_MICNBR_Pos (4U)
18203#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
18204#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
18205#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
18206#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
18208#define SAI_PDMCR_CKEN1_Pos (8U)
18209#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
18210#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
18211#define SAI_PDMCR_CKEN2_Pos (9U)
18212#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
18213#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
18214#define SAI_PDMCR_CKEN3_Pos (10U)
18215#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
18216#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
18217#define SAI_PDMCR_CKEN4_Pos (11U)
18218#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
18219#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
18221/****************** Bit definition for SAI_PDMDLY register ******************/
18222#define SAI_PDMDLY_DLYM1L_Pos (0U)
18223#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
18224#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
18225#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
18226#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
18227#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
18229#define SAI_PDMDLY_DLYM1R_Pos (4U)
18230#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
18231#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
18232#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
18233#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
18234#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
18236#define SAI_PDMDLY_DLYM2L_Pos (8U)
18237#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
18238#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
18239#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
18240#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
18241#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
18243#define SAI_PDMDLY_DLYM2R_Pos (12U)
18244#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
18245#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
18246#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
18247#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
18248#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
18250#define SAI_PDMDLY_DLYM3L_Pos (16U)
18251#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
18252#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
18253#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
18254#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
18255#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
18257#define SAI_PDMDLY_DLYM3R_Pos (20U)
18258#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
18259#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
18260#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
18261#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
18262#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
18264#define SAI_PDMDLY_DLYM4L_Pos (24U)
18265#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
18266#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
18267#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
18268#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
18269#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
18271#define SAI_PDMDLY_DLYM4R_Pos (28U)
18272#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
18273#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
18274#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
18275#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
18276#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
18278/******************************************************************************/
18279/* */
18280/* SDMMC Interface */
18281/* */
18282/******************************************************************************/
18283/****************** Bit definition for SDMMC_POWER register ******************/
18284#define SDMMC_POWER_PWRCTRL_Pos (0U)
18285#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
18286#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
18287#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
18288#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
18289#define SDMMC_POWER_VSWITCH_Pos (2U)
18290#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos)
18291#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk
18292#define SDMMC_POWER_VSWITCHEN_Pos (3U)
18293#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
18294#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk
18295#define SDMMC_POWER_DIRPOL_Pos (4U)
18296#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos)
18297#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk
18299/****************** Bit definition for SDMMC_CLKCR register ******************/
18300#define SDMMC_CLKCR_CLKDIV_Pos (0U)
18301#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
18302#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
18303#define SDMMC_CLKCR_PWRSAV_Pos (12U)
18304#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
18305#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
18307#define SDMMC_CLKCR_WIDBUS_Pos (14U)
18308#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
18309#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
18310#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
18311#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
18313#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
18314#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
18315#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
18316#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
18317#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
18318#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
18319#define SDMMC_CLKCR_DDR_Pos (18U)
18320#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos)
18321#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk
18322#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
18323#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
18324#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk
18325#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
18326#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
18327#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk
18328#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
18329#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
18331/******************* Bit definition for SDMMC_ARG register *******************/
18332#define SDMMC_ARG_CMDARG_Pos (0U)
18333#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
18334#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
18336/******************* Bit definition for SDMMC_CMD register *******************/
18337#define SDMMC_CMD_CMDINDEX_Pos (0U)
18338#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
18339#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
18340#define SDMMC_CMD_CMDTRANS_Pos (6U)
18341#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
18342#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk
18343#define SDMMC_CMD_CMDSTOP_Pos (7U)
18344#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
18345#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk
18347#define SDMMC_CMD_WAITRESP_Pos (8U)
18348#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
18349#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
18350#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
18351#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
18353#define SDMMC_CMD_WAITINT_Pos (10U)
18354#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
18355#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
18356#define SDMMC_CMD_WAITPEND_Pos (11U)
18357#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
18358#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
18359#define SDMMC_CMD_CPSMEN_Pos (12U)
18360#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
18361#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
18362#define SDMMC_CMD_DTHOLD_Pos (13U)
18363#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos)
18364#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk
18365#define SDMMC_CMD_BOOTMODE_Pos (14U)
18366#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
18367#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk
18368#define SDMMC_CMD_BOOTEN_Pos (15U)
18369#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos)
18370#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk
18371#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
18372#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
18373#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk
18375/***************** Bit definition for SDMMC_RESPCMD register *****************/
18376#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
18377#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
18378#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
18380/****************** Bit definition for SDMMC_RESP0 register ******************/
18381#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
18382#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
18383#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
18385/****************** Bit definition for SDMMC_RESP1 register ******************/
18386#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
18387#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
18388#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
18390/****************** Bit definition for SDMMC_RESP2 register ******************/
18391#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
18392#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
18393#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
18395/****************** Bit definition for SDMMC_RESP3 register ******************/
18396#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
18397#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
18398#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
18400/****************** Bit definition for SDMMC_RESP4 register ******************/
18401#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
18402#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
18403#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
18405/****************** Bit definition for SDMMC_DTIMER register *****************/
18406#define SDMMC_DTIMER_DATATIME_Pos (0U)
18407#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
18408#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
18410/****************** Bit definition for SDMMC_DLEN register *******************/
18411#define SDMMC_DLEN_DATALENGTH_Pos (0U)
18412#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
18413#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
18415/****************** Bit definition for SDMMC_DCTRL register ******************/
18416#define SDMMC_DCTRL_DTEN_Pos (0U)
18417#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
18418#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
18419#define SDMMC_DCTRL_DTDIR_Pos (1U)
18420#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
18421#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
18422#define SDMMC_DCTRL_DTMODE_Pos (2U)
18423#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
18424#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
18425#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
18426#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
18428#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
18429#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18430#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
18431#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18432#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18433#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18434#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
18436#define SDMMC_DCTRL_RWSTART_Pos (8U)
18437#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
18438#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
18439#define SDMMC_DCTRL_RWSTOP_Pos (9U)
18440#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
18441#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
18442#define SDMMC_DCTRL_RWMOD_Pos (10U)
18443#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
18444#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
18445#define SDMMC_DCTRL_SDIOEN_Pos (11U)
18446#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
18447#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
18448#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
18449#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
18450#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk
18451#define SDMMC_DCTRL_FIFORST_Pos (13U)
18452#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
18453#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk
18455/****************** Bit definition for SDMMC_DCOUNT register *****************/
18456#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
18457#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
18458#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
18460/****************** Bit definition for SDMMC_STA register ********************/
18461#define SDMMC_STA_CCRCFAIL_Pos (0U)
18462#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
18463#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
18464#define SDMMC_STA_DCRCFAIL_Pos (1U)
18465#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
18466#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
18467#define SDMMC_STA_CTIMEOUT_Pos (2U)
18468#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
18469#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
18470#define SDMMC_STA_DTIMEOUT_Pos (3U)
18471#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
18472#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
18473#define SDMMC_STA_TXUNDERR_Pos (4U)
18474#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
18475#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
18476#define SDMMC_STA_RXOVERR_Pos (5U)
18477#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
18478#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
18479#define SDMMC_STA_CMDREND_Pos (6U)
18480#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
18481#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
18482#define SDMMC_STA_CMDSENT_Pos (7U)
18483#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
18484#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
18485#define SDMMC_STA_DATAEND_Pos (8U)
18486#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
18487#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
18488#define SDMMC_STA_DHOLD_Pos (9U)
18489#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos)
18490#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk
18491#define SDMMC_STA_DBCKEND_Pos (10U)
18492#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
18493#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
18494#define SDMMC_STA_DABORT_Pos (11U)
18495#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos)
18496#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk
18497#define SDMMC_STA_DPSMACT_Pos (12U)
18498#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos)
18499#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk
18500#define SDMMC_STA_CPSMACT_Pos (13U)
18501#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos)
18502#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk
18503#define SDMMC_STA_TXFIFOHE_Pos (14U)
18504#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
18505#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
18506#define SDMMC_STA_RXFIFOHF_Pos (15U)
18507#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
18508#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
18509#define SDMMC_STA_TXFIFOF_Pos (16U)
18510#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
18511#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
18512#define SDMMC_STA_RXFIFOF_Pos (17U)
18513#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
18514#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
18515#define SDMMC_STA_TXFIFOE_Pos (18U)
18516#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
18517#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
18518#define SDMMC_STA_RXFIFOE_Pos (19U)
18519#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
18520#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
18521#define SDMMC_STA_BUSYD0_Pos (20U)
18522#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos)
18523#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk
18524#define SDMMC_STA_BUSYD0END_Pos (21U)
18525#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos)
18526#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk
18527#define SDMMC_STA_SDIOIT_Pos (22U)
18528#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
18529#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
18530#define SDMMC_STA_ACKFAIL_Pos (23U)
18531#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos)
18532#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk
18533#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
18534#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
18535#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk
18536#define SDMMC_STA_VSWEND_Pos (25U)
18537#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos)
18538#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk
18539#define SDMMC_STA_CKSTOP_Pos (26U)
18540#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos)
18541#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk
18542#define SDMMC_STA_IDMATE_Pos (27U)
18543#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos)
18544#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk
18545#define SDMMC_STA_IDMABTC_Pos (28U)
18546#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos)
18547#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk
18549/******************* Bit definition for SDMMC_ICR register *******************/
18550#define SDMMC_ICR_CCRCFAILC_Pos (0U)
18551#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
18552#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
18553#define SDMMC_ICR_DCRCFAILC_Pos (1U)
18554#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
18555#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
18556#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
18557#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
18558#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
18559#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
18560#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
18561#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
18562#define SDMMC_ICR_TXUNDERRC_Pos (4U)
18563#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
18564#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
18565#define SDMMC_ICR_RXOVERRC_Pos (5U)
18566#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
18567#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
18568#define SDMMC_ICR_CMDRENDC_Pos (6U)
18569#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
18570#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
18571#define SDMMC_ICR_CMDSENTC_Pos (7U)
18572#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
18573#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
18574#define SDMMC_ICR_DATAENDC_Pos (8U)
18575#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
18576#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
18577#define SDMMC_ICR_DHOLDC_Pos (9U)
18578#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos)
18579#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk
18580#define SDMMC_ICR_DBCKENDC_Pos (10U)
18581#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
18582#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
18583#define SDMMC_ICR_DABORTC_Pos (11U)
18584#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos)
18585#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk
18586#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
18587#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
18588#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk
18589#define SDMMC_ICR_SDIOITC_Pos (22U)
18590#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
18591#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
18592#define SDMMC_ICR_ACKFAILC_Pos (23U)
18593#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
18594#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk
18595#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
18596#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
18597#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk
18598#define SDMMC_ICR_VSWENDC_Pos (25U)
18599#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos)
18600#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk
18601#define SDMMC_ICR_CKSTOPC_Pos (26U)
18602#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
18603#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk
18604#define SDMMC_ICR_IDMATEC_Pos (27U)
18605#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos)
18606#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk
18607#define SDMMC_ICR_IDMABTCC_Pos (28U)
18608#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
18609#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk
18611/****************** Bit definition for SDMMC_MASK register *******************/
18612#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
18613#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
18614#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
18615#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
18616#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
18617#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
18618#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
18619#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
18620#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
18621#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
18622#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
18623#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
18624#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
18625#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
18626#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
18627#define SDMMC_MASK_RXOVERRIE_Pos (5U)
18628#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
18629#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
18630#define SDMMC_MASK_CMDRENDIE_Pos (6U)
18631#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
18632#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
18633#define SDMMC_MASK_CMDSENTIE_Pos (7U)
18634#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
18635#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
18636#define SDMMC_MASK_DATAENDIE_Pos (8U)
18637#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
18638#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
18639#define SDMMC_MASK_DHOLDIE_Pos (9U)
18640#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
18641#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk
18642#define SDMMC_MASK_DBCKENDIE_Pos (10U)
18643#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
18644#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
18645#define SDMMC_MASK_DABORTIE_Pos (11U)
18646#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos)
18647#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk
18649#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
18650#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
18651#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
18652#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
18653#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
18654#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
18656#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
18657#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
18658#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
18659#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
18660#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
18661#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
18663#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
18664#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
18665#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk
18666#define SDMMC_MASK_SDIOITIE_Pos (22U)
18667#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
18668#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
18669#define SDMMC_MASK_ACKFAILIE_Pos (23U)
18670#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
18671#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk
18672#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
18673#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
18674#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk
18675#define SDMMC_MASK_VSWENDIE_Pos (25U)
18676#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
18677#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk
18678#define SDMMC_MASK_CKSTOPIE_Pos (26U)
18679#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
18680#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk
18681#define SDMMC_MASK_IDMABTCIE_Pos (28U)
18682#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
18683#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk
18685/***************** Bit definition for SDMMC_ACKTIME register *****************/
18686#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
18687#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
18688#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk
18690/****************** Bit definition for SDMMC_FIFO register *******************/
18691#define SDMMC_FIFO_FIFODATA_Pos (0U)
18692#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
18693#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
18695/****************** Bit definition for SDMMC_IDMACTRL register ****************/
18696#define SDMMC_IDMA_IDMAEN_Pos (0U)
18697#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
18698#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk
18699#define SDMMC_IDMA_IDMABMODE_Pos (1U)
18700#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
18701#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk
18702#define SDMMC_IDMA_IDMABACT_Pos (2U)
18703#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
18704#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk
18706/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
18707#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
18708#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
18709#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk
18711/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
18712#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU)
18714/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
18715#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU)
18717/******************************************************************************/
18718/* */
18719/* Delay Block Interface (DLYB) */
18720/* */
18721/******************************************************************************/
18722/******************* Bit definition for DLYB_CR register ********************/
18723#define DLYB_CR_DEN_Pos (0U)
18724#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos)
18725#define DLYB_CR_DEN DLYB_CR_DEN_Msk
18726#define DLYB_CR_SEN_Pos (1U)
18727#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos)
18728#define DLYB_CR_SEN DLYB_CR_SEN_Msk
18731/******************* Bit definition for DLYB_CFGR register ********************/
18732#define DLYB_CFGR_SEL_Pos (0U)
18733#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos)
18734#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk
18735#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos)
18736#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos)
18737#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos)
18738#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos)
18740#define DLYB_CFGR_UNIT_Pos (8U)
18741#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos)
18742#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk
18743#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos)
18744#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos)
18745#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos)
18746#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos)
18747#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos)
18748#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos)
18749#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos)
18751#define DLYB_CFGR_LNG_Pos (16U)
18752#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos)
18753#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk
18754#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos)
18755#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos)
18756#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos)
18757#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos)
18758#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos)
18759#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos)
18760#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos)
18761#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos)
18762#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos)
18763#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos)
18764#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos)
18765#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos)
18767#define DLYB_CFGR_LNGF_Pos (31U)
18768#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos)
18769#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk
18771/******************************************************************************/
18772/* */
18773/* Serial Peripheral Interface (SPI/I2S) */
18774/* */
18775/******************************************************************************/
18776/******************* Bit definition for SPI_CR1 register ********************/
18777#define SPI_CR1_SPE_Pos (0U)
18778#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
18779#define SPI_CR1_SPE SPI_CR1_SPE_Msk
18780#define SPI_CR1_MASRX_Pos (8U)
18781#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos)
18782#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk
18783#define SPI_CR1_CSTART_Pos (9U)
18784#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos)
18785#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk
18786#define SPI_CR1_CSUSP_Pos (10U)
18787#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos)
18788#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk
18789#define SPI_CR1_HDDIR_Pos (11U)
18790#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos)
18791#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk
18792#define SPI_CR1_SSI_Pos (12U)
18793#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
18794#define SPI_CR1_SSI SPI_CR1_SSI_Msk
18795#define SPI_CR1_CRC33_17_Pos (13U)
18796#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos)
18797#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk
18798#define SPI_CR1_RCRCINI_Pos (14U)
18799#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos)
18800#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk
18801#define SPI_CR1_TCRCINI_Pos (15U)
18802#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos)
18803#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk
18804#define SPI_CR1_IOLOCK_Pos (16U)
18805#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos)
18806#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk
18808/******************* Bit definition for SPI_CR2 register ********************/
18809#define SPI_CR2_TSER_Pos (16U)
18810#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos)
18811#define SPI_CR2_TSER SPI_CR2_TSER_Msk
18812#define SPI_CR2_TSIZE_Pos (0U)
18813#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos)
18814#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk
18816/******************* Bit definition for SPI_CFG1 register ********************/
18817#define SPI_CFG1_DSIZE_Pos (0U)
18818#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos)
18819#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk
18820#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos)
18821#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos)
18822#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos)
18823#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos)
18824#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos)
18826#define SPI_CFG1_FTHLV_Pos (5U)
18827#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos)
18828#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk
18829#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos)
18830#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos)
18831#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos)
18832#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos)
18834#define SPI_CFG1_UDRCFG_Pos (9U)
18835#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos)
18836#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk
18837#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos)
18838#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos)
18841#define SPI_CFG1_UDRDET_Pos (11U)
18842#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
18843#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk
18844#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos)
18845#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos)
18847#define SPI_CFG1_RXDMAEN_Pos (14U)
18848#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos)
18849#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk
18850#define SPI_CFG1_TXDMAEN_Pos (15U)
18851#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos)
18852#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk
18854#define SPI_CFG1_CRCSIZE_Pos (16U)
18855#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
18856#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk
18857#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos)
18858#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos)
18859#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos)
18860#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos)
18861#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos)
18863#define SPI_CFG1_CRCEN_Pos (22U)
18864#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos)
18865#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk
18867#define SPI_CFG1_MBR_Pos (28U)
18868#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos)
18869#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk
18870#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos)
18871#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos)
18872#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos)
18874/******************* Bit definition for SPI_CFG2 register ********************/
18875#define SPI_CFG2_MSSI_Pos (0U)
18876#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos)
18877#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk
18878#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos)
18879#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos)
18880#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos)
18881#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos)
18883#define SPI_CFG2_MIDI_Pos (4U)
18884#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos)
18885#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk
18886#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos)
18887#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos)
18888#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos)
18889#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos)
18891#define SPI_CFG2_IOSWP_Pos (15U)
18892#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos)
18893#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk
18895#define SPI_CFG2_COMM_Pos (17U)
18896#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos)
18897#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk
18898#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos)
18899#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos)
18901#define SPI_CFG2_SP_Pos (19U)
18902#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos)
18903#define SPI_CFG2_SP SPI_CFG2_SP_Msk
18904#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos)
18905#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos)
18906#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos)
18908#define SPI_CFG2_MASTER_Pos (22U)
18909#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos)
18910#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk
18911#define SPI_CFG2_LSBFRST_Pos (23U)
18912#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos)
18913#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk
18914#define SPI_CFG2_CPHA_Pos (24U)
18915#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos)
18916#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk
18917#define SPI_CFG2_CPOL_Pos (25U)
18918#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos)
18919#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk
18920#define SPI_CFG2_SSM_Pos (26U)
18921#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos)
18922#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk
18924#define SPI_CFG2_SSIOP_Pos (28U)
18925#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos)
18926#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk
18927#define SPI_CFG2_SSOE_Pos (29U)
18928#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos)
18929#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk
18930#define SPI_CFG2_SSOM_Pos (30U)
18931#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos)
18932#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk
18934#define SPI_CFG2_AFCNTR_Pos (31U)
18935#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos)
18936#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk
18938/******************* Bit definition for SPI_IER register ********************/
18939#define SPI_IER_RXPIE_Pos (0U)
18940#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos)
18941#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk
18942#define SPI_IER_TXPIE_Pos (1U)
18943#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos)
18944#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk
18945#define SPI_IER_DXPIE_Pos (2U)
18946#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos)
18947#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk
18948#define SPI_IER_EOTIE_Pos (3U)
18949#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos)
18950#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk
18951#define SPI_IER_TXTFIE_Pos (4U)
18952#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos)
18953#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk
18954#define SPI_IER_UDRIE_Pos (5U)
18955#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos)
18956#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk
18957#define SPI_IER_OVRIE_Pos (6U)
18958#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos)
18959#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk
18960#define SPI_IER_CRCEIE_Pos (7U)
18961#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos)
18962#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk
18963#define SPI_IER_TIFREIE_Pos (8U)
18964#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos)
18965#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk
18966#define SPI_IER_MODFIE_Pos (9U)
18967#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos)
18968#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk
18969#define SPI_IER_TSERFIE_Pos (10U)
18970#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
18971#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk
18973/******************* Bit definition for SPI_SR register ********************/
18974#define SPI_SR_RXP_Pos (0U)
18975#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos)
18976#define SPI_SR_RXP SPI_SR_RXP_Msk
18977#define SPI_SR_TXP_Pos (1U)
18978#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos)
18979#define SPI_SR_TXP SPI_SR_TXP_Msk
18980#define SPI_SR_DXP_Pos (2U)
18981#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos)
18982#define SPI_SR_DXP SPI_SR_DXP_Msk
18983#define SPI_SR_EOT_Pos (3U)
18984#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos)
18985#define SPI_SR_EOT SPI_SR_EOT_Msk
18986#define SPI_SR_TXTF_Pos (4U)
18987#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos)
18988#define SPI_SR_TXTF SPI_SR_TXTF_Msk
18989#define SPI_SR_UDR_Pos (5U)
18990#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
18991#define SPI_SR_UDR SPI_SR_UDR_Msk
18992#define SPI_SR_OVR_Pos (6U)
18993#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
18994#define SPI_SR_OVR SPI_SR_OVR_Msk
18995#define SPI_SR_CRCE_Pos (7U)
18996#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos)
18997#define SPI_SR_CRCE SPI_SR_CRCE_Msk
18998#define SPI_SR_TIFRE_Pos (8U)
18999#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos)
19000#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk
19001#define SPI_SR_MODF_Pos (9U)
19002#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
19003#define SPI_SR_MODF SPI_SR_MODF_Msk
19004#define SPI_SR_TSERF_Pos (10U)
19005#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos)
19006#define SPI_SR_TSERF SPI_SR_TSERF_Msk
19007#define SPI_SR_SUSP_Pos (11U)
19008#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos)
19009#define SPI_SR_SUSP SPI_SR_SUSP_Msk
19010#define SPI_SR_TXC_Pos (12U)
19011#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos)
19012#define SPI_SR_TXC SPI_SR_TXC_Msk
19013#define SPI_SR_RXPLVL_Pos (13U)
19014#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos)
19015#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk
19016#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos)
19017#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos)
19018#define SPI_SR_RXWNE_Pos (15U)
19019#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos)
19020#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk
19021#define SPI_SR_CTSIZE_Pos (16U)
19022#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos)
19023#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk
19025/******************* Bit definition for SPI_IFCR register ********************/
19026#define SPI_IFCR_EOTC_Pos (3U)
19027#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos)
19028#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk
19029#define SPI_IFCR_TXTFC_Pos (4U)
19030#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos)
19031#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk
19032#define SPI_IFCR_UDRC_Pos (5U)
19033#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos)
19034#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk
19035#define SPI_IFCR_OVRC_Pos (6U)
19036#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos)
19037#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk
19038#define SPI_IFCR_CRCEC_Pos (7U)
19039#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos)
19040#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk
19041#define SPI_IFCR_TIFREC_Pos (8U)
19042#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos)
19043#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk
19044#define SPI_IFCR_MODFC_Pos (9U)
19045#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos)
19046#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk
19047#define SPI_IFCR_TSERFC_Pos (10U)
19048#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos)
19049#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk
19050#define SPI_IFCR_SUSPC_Pos (11U)
19051#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos)
19052#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk
19054/******************* Bit definition for SPI_TXDR register ********************/
19055#define SPI_TXDR_TXDR_Pos (0U)
19056#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
19057#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
19058
19059/******************* Bit definition for SPI_RXDR register ********************/
19060#define SPI_RXDR_RXDR_Pos (0U)
19061#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
19062#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
19063
19064/******************* Bit definition for SPI_CRCPOLY register ********************/
19065#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
19066#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
19067#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
19068
19069/******************* Bit definition for SPI_TXCRC register ********************/
19070#define SPI_TXCRC_TXCRC_Pos (0U)
19071#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
19072#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
19073
19074/******************* Bit definition for SPI_RXCRC register ********************/
19075#define SPI_RXCRC_RXCRC_Pos (0U)
19076#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
19077#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
19078
19079/******************* Bit definition for SPI_UDRDR register ********************/
19080#define SPI_UDRDR_UDRDR_Pos (0U)
19081#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
19082#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
19083
19084/****************** Bit definition for SPI_I2SCFGR register *****************/
19085#define SPI_I2SCFGR_I2SMOD_Pos (0U)
19086#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
19087#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
19088#define SPI_I2SCFGR_I2SCFG_Pos (1U)
19089#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
19090#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
19091#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
19092#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
19093#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
19094#define SPI_I2SCFGR_I2SSTD_Pos (4U)
19095#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
19096#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
19097#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
19098#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
19099#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
19100#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
19101#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
19102#define SPI_I2SCFGR_DATLEN_Pos (8U)
19103#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
19104#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
19105#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
19106#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
19107#define SPI_I2SCFGR_CHLEN_Pos (10U)
19108#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
19109#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
19110#define SPI_I2SCFGR_CKPOL_Pos (11U)
19111#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
19112#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
19113#define SPI_I2SCFGR_FIXCH_Pos (12U)
19114#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
19115#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk
19116#define SPI_I2SCFGR_WSINV_Pos (13U)
19117#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos)
19118#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk
19119#define SPI_I2SCFGR_DATFMT_Pos (14U)
19120#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
19121#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk
19122#define SPI_I2SCFGR_I2SDIV_Pos (16U)
19123#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
19124#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk
19125#define SPI_I2SCFGR_ODD_Pos (24U)
19126#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos)
19127#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk
19128#define SPI_I2SCFGR_MCKOE_Pos (25U)
19129#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
19130#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk
19133/******************************************************************************/
19134/* */
19135/* QUADSPI */
19136/* */
19137/******************************************************************************/
19138/***************** Bit definition for QUADSPI_CR register *******************/
19139#define QUADSPI_CR_EN_Pos (0U)
19140#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
19141#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
19142#define QUADSPI_CR_ABORT_Pos (1U)
19143#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
19144#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
19145#define QUADSPI_CR_DMAEN_Pos (2U)
19146#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
19147#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
19148#define QUADSPI_CR_TCEN_Pos (3U)
19149#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
19150#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
19151#define QUADSPI_CR_SSHIFT_Pos (4U)
19152#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
19153#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
19154#define QUADSPI_CR_DFM_Pos (6U)
19155#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
19156#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
19157#define QUADSPI_CR_FSEL_Pos (7U)
19158#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
19159#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
19160#define QUADSPI_CR_FTHRES_Pos (8U)
19161#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
19162#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
19163#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos)
19164#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos)
19165#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos)
19166#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos)
19167#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
19168#define QUADSPI_CR_TEIE_Pos (16U)
19169#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
19170#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
19171#define QUADSPI_CR_TCIE_Pos (17U)
19172#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
19173#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
19174#define QUADSPI_CR_FTIE_Pos (18U)
19175#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
19176#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
19177#define QUADSPI_CR_SMIE_Pos (19U)
19178#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
19179#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
19180#define QUADSPI_CR_TOIE_Pos (20U)
19181#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
19182#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
19183#define QUADSPI_CR_APMS_Pos (22U)
19184#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
19185#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
19186#define QUADSPI_CR_PMM_Pos (23U)
19187#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
19188#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
19189#define QUADSPI_CR_PRESCALER_Pos (24U)
19190#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
19191#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
19192#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
19193#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
19194#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
19195#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
19196#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
19197#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
19198#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
19199#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
19201/***************** Bit definition for QUADSPI_DCR register ******************/
19202#define QUADSPI_DCR_CKMODE_Pos (0U)
19203#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
19204#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
19205#define QUADSPI_DCR_CSHT_Pos (8U)
19206#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
19207#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
19208#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
19209#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
19210#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
19211#define QUADSPI_DCR_FSIZE_Pos (16U)
19212#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
19213#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
19214#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
19215#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
19216#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
19217#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
19218#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
19220/****************** Bit definition for QUADSPI_SR register *******************/
19221#define QUADSPI_SR_TEF_Pos (0U)
19222#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
19223#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
19224#define QUADSPI_SR_TCF_Pos (1U)
19225#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
19226#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
19227#define QUADSPI_SR_FTF_Pos (2U)
19228#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
19229#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
19230#define QUADSPI_SR_SMF_Pos (3U)
19231#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
19232#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
19233#define QUADSPI_SR_TOF_Pos (4U)
19234#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
19235#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
19236#define QUADSPI_SR_BUSY_Pos (5U)
19237#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
19238#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
19239#define QUADSPI_SR_FLEVEL_Pos (8U)
19240#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
19241#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
19242#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
19243#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
19244#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
19245#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
19246#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
19247#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
19249/****************** Bit definition for QUADSPI_FCR register ******************/
19250#define QUADSPI_FCR_CTEF_Pos (0U)
19251#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
19252#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
19253#define QUADSPI_FCR_CTCF_Pos (1U)
19254#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
19255#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
19256#define QUADSPI_FCR_CSMF_Pos (3U)
19257#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
19258#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
19259#define QUADSPI_FCR_CTOF_Pos (4U)
19260#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
19261#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
19263/****************** Bit definition for QUADSPI_DLR register ******************/
19264#define QUADSPI_DLR_DL_Pos (0U)
19265#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
19266#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
19268/****************** Bit definition for QUADSPI_CCR register ******************/
19269#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
19270#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
19271#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
19272#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
19273#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
19274#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
19275#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
19276#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
19277#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
19278#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
19279#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
19280#define QUADSPI_CCR_IMODE_Pos (8U)
19281#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
19282#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
19283#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
19284#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
19285#define QUADSPI_CCR_ADMODE_Pos (10U)
19286#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
19287#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
19288#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
19289#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
19290#define QUADSPI_CCR_ADSIZE_Pos (12U)
19291#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
19292#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
19293#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
19294#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
19295#define QUADSPI_CCR_ABMODE_Pos (14U)
19296#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
19297#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
19298#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
19299#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
19300#define QUADSPI_CCR_ABSIZE_Pos (16U)
19301#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
19302#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
19303#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
19304#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
19305#define QUADSPI_CCR_DCYC_Pos (18U)
19306#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
19307#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
19308#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
19309#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
19310#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
19311#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
19312#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
19313#define QUADSPI_CCR_DMODE_Pos (24U)
19314#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
19315#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
19316#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
19317#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
19318#define QUADSPI_CCR_FMODE_Pos (26U)
19319#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
19320#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
19321#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
19322#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
19323#define QUADSPI_CCR_SIOO_Pos (28U)
19324#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
19325#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
19326#define QUADSPI_CCR_DHHC_Pos (30U)
19327#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
19328#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
19329#define QUADSPI_CCR_DDRM_Pos (31U)
19330#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
19331#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
19333/****************** Bit definition for QUADSPI_AR register *******************/
19334#define QUADSPI_AR_ADDRESS_Pos (0U)
19335#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
19336#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
19338/****************** Bit definition for QUADSPI_ABR register ******************/
19339#define QUADSPI_ABR_ALTERNATE_Pos (0U)
19340#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
19341#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
19343/****************** Bit definition for QUADSPI_DR register *******************/
19344#define QUADSPI_DR_DATA_Pos (0U)
19345#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
19346#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
19348/****************** Bit definition for QUADSPI_PSMKR register ****************/
19349#define QUADSPI_PSMKR_MASK_Pos (0U)
19350#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
19351#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
19353/****************** Bit definition for QUADSPI_PSMAR register ****************/
19354#define QUADSPI_PSMAR_MATCH_Pos (0U)
19355#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
19356#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
19358/****************** Bit definition for QUADSPI_PIR register *****************/
19359#define QUADSPI_PIR_INTERVAL_Pos (0U)
19360#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
19361#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
19363/****************** Bit definition for QUADSPI_LPTR register *****************/
19364#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
19365#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
19366#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
19368/******************************************************************************/
19369/* */
19370/* SYSCFG */
19371/* */
19372/******************************************************************************/
19373
19374/****************** Bit definition for SYSCFG_PMCR register ******************/
19375#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
19376#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
19377#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk
19378#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
19379#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
19380#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk
19381#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
19382#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
19383#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk
19384#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
19385#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
19386#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk
19387#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
19388#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
19389#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk
19390#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
19391#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
19392#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk
19393#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
19394#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
19395#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk
19396#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
19397#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
19398#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk
19399#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
19400#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)
19401#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk
19403#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
19404#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos)
19405#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk
19407#define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
19408#define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19409#define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk
19410#define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19411#define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19412#define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)
19413#define SYSCFG_PMCR_PA0SO_Pos (24U)
19414#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
19415#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk
19416#define SYSCFG_PMCR_PA1SO_Pos (25U)
19417#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
19418#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk
19419#define SYSCFG_PMCR_PC2SO_Pos (26U)
19420#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
19421#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk
19422#define SYSCFG_PMCR_PC3SO_Pos (27U)
19423#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
19424#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk
19426/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
19427#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
19428#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
19429#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
19430#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
19431#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
19432#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
19433#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
19434#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
19435#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
19436#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
19437#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
19438#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
19442#define SYSCFG_EXTICR1_EXTI0_PA (0U)
19443#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
19444#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
19445#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
19446#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
19447#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
19448#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
19449#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
19450#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U)
19451#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U)
19452#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU)
19457#define SYSCFG_EXTICR1_EXTI1_PA (0U)
19458#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
19459#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
19460#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
19461#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
19462#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
19463#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
19464#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
19465#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U)
19466#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U)
19467#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U)
19471#define SYSCFG_EXTICR1_EXTI2_PA (0U)
19472#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
19473#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
19474#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
19475#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
19476#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
19477#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
19478#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U)
19479#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U)
19480#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U)
19481#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U)
19486#define SYSCFG_EXTICR1_EXTI3_PA (0U)
19487#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
19488#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
19489#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
19490#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
19491#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
19492#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
19493#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U)
19494#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U)
19495#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U)
19496#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U)
19498/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
19499#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
19500#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
19501#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
19502#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
19503#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
19504#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
19505#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
19506#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
19507#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
19508#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
19509#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
19510#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
19514#define SYSCFG_EXTICR2_EXTI4_PA (0U)
19515#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
19516#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
19517#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
19518#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
19519#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
19520#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
19521#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
19522#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U)
19523#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U)
19524#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU)
19528#define SYSCFG_EXTICR2_EXTI5_PA (0U)
19529#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
19530#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
19531#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
19532#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
19533#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
19534#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
19535#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U)
19536#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U)
19537#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U)
19538#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U)
19542#define SYSCFG_EXTICR2_EXTI6_PA (0U)
19543#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
19544#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
19545#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
19546#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
19547#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
19548#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
19549#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U)
19550#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U)
19551#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U)
19552#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U)
19557#define SYSCFG_EXTICR2_EXTI7_PA (0U)
19558#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
19559#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
19560#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
19561#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
19562#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
19563#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
19564#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U)
19565#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U)
19566#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U)
19567#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U)
19569/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
19570#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
19571#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
19572#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
19573#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
19574#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
19575#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
19576#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
19577#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
19578#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
19579#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
19580#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
19581#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
19586#define SYSCFG_EXTICR3_EXTI8_PA (0U)
19587#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
19588#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
19589#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
19590#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
19591#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
19592#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
19593#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U)
19594#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U)
19595#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U)
19596#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU)
19601#define SYSCFG_EXTICR3_EXTI9_PA (0U)
19602#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
19603#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
19604#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
19605#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
19606#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
19607#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
19608#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U)
19609#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U)
19610#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U)
19611#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U)
19616#define SYSCFG_EXTICR3_EXTI10_PA (0U)
19617#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
19618#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
19619#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
19620#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
19621#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
19622#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
19623#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U)
19624#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U)
19625#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U)
19626#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U)
19631#define SYSCFG_EXTICR3_EXTI11_PA (0U)
19632#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
19633#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
19634#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
19635#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
19636#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
19637#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)
19638#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U)
19639#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U)
19640#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U)
19641#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U)
19643/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
19644#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
19645#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
19646#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
19647#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
19648#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
19649#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
19650#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
19651#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
19652#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
19653#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
19654#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
19655#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
19659#define SYSCFG_EXTICR4_EXTI12_PA (0U)
19660#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
19661#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
19662#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
19663#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
19664#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
19665#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
19666#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U)
19667#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U)
19668#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U)
19669#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU)
19673#define SYSCFG_EXTICR4_EXTI13_PA (0U)
19674#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
19675#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
19676#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
19677#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
19678#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
19679#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
19680#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U)
19681#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U)
19682#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U)
19683#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U)
19687#define SYSCFG_EXTICR4_EXTI14_PA (0U)
19688#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
19689#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
19690#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
19691#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
19692#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
19693#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
19694#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U)
19695#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U)
19696#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U)
19697#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U)
19701#define SYSCFG_EXTICR4_EXTI15_PA (0U)
19702#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
19703#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
19704#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
19705#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
19706#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
19707#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)
19708#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U)
19709#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U)
19710#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U)
19711#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U)
19713/****************** Bit definition for SYSCFG_CFGR register ******************/
19714#define SYSCFG_CFGR_CM4L_Pos (0U)
19715#define SYSCFG_CFGR_CM4L_Msk (0x1UL << SYSCFG_CFGR_CM4L_Pos)
19716#define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk
19717#define SYSCFG_CFGR_PVDL_Pos (2U)
19718#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos)
19719#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk
19720#define SYSCFG_CFGR_FLASHL_Pos (3U)
19721#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
19722#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk
19723#define SYSCFG_CFGR_CM7L_Pos (6U)
19724#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos)
19725#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk
19726#define SYSCFG_CFGR_BKRAML_Pos (7U)
19727#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos)
19728#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk
19729#define SYSCFG_CFGR_SRAM4L_Pos (9U)
19730#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)
19731#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk
19732#define SYSCFG_CFGR_SRAM3L_Pos (10U)
19733#define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)
19734#define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk
19735#define SYSCFG_CFGR_SRAM2L_Pos (11U)
19736#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)
19737#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk
19738#define SYSCFG_CFGR_SRAM1L_Pos (12U)
19739#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)
19740#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk
19741#define SYSCFG_CFGR_DTCML_Pos (13U)
19742#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos)
19743#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk
19744#define SYSCFG_CFGR_ITCML_Pos (14U)
19745#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos)
19746#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk
19747#define SYSCFG_CFGR_AXISRAML_Pos (15U)
19748#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)
19749#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk
19751/****************** Bit definition for SYSCFG_CCCSR register ******************/
19752#define SYSCFG_CCCSR_EN_Pos (0U)
19753#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos)
19754#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk
19755#define SYSCFG_CCCSR_CS_Pos (1U)
19756#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos)
19757#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk
19758#define SYSCFG_CCCSR_READY_Pos (8U)
19759#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos)
19760#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk
19761#define SYSCFG_CCCSR_HSLV_Pos (16U)
19762#define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos)
19763#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk
19765/****************** Bit definition for SYSCFG_CCVR register *******************/
19766#define SYSCFG_CCVR_NCV_Pos (0U)
19767#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos)
19768#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk
19769#define SYSCFG_CCVR_PCV_Pos (4U)
19770#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos)
19771#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk
19773/****************** Bit definition for SYSCFG_CCCR register *******************/
19774#define SYSCFG_CCCR_NCC_Pos (0U)
19775#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos)
19776#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk
19777#define SYSCFG_CCCR_PCC_Pos (4U)
19778#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos)
19779#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk
19780/****************** Bit definition for SYSCFG_PWRCR register *******************/
19781#define SYSCFG_PWRCR_ODEN_Pos (0U)
19782#define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos)
19783#define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk
19785/****************** Bit definition for SYSCFG_PKGR register *******************/
19786#define SYSCFG_PKGR_PKG_Pos (0U)
19787#define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos)
19788#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk
19790/****************** Bit definition for SYSCFG_UR0 register *******************/
19791#define SYSCFG_UR0_BKS_Pos (0U)
19792#define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos)
19793#define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk
19794#define SYSCFG_UR0_RDP_Pos (16U)
19795#define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos)
19796#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk
19798/****************** Bit definition for SYSCFG_UR1 register *******************/
19799#define SYSCFG_UR1_BCM4_Pos (0U)
19800#define SYSCFG_UR1_BCM4_Msk (0x1UL << SYSCFG_UR1_BCM4_Pos)
19801#define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk
19802#define SYSCFG_UR1_BCM7_Pos (16U)
19803#define SYSCFG_UR1_BCM7_Msk (0x1UL << SYSCFG_UR1_BCM7_Pos)
19804#define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk
19805/****************** Bit definition for SYSCFG_UR2 register *******************/
19806#define SYSCFG_UR2_BORH_Pos (0U)
19807#define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos)
19808#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk
19809#define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos)
19810#define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos)
19811#define SYSCFG_UR2_BCM7_ADD0_Pos (16U)
19812#define SYSCFG_UR2_BCM7_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos)
19813#define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk
19814/****************** Bit definition for SYSCFG_UR3 register *******************/
19815#define SYSCFG_UR3_BCM7_ADD1_Pos (0U)
19816#define SYSCFG_UR3_BCM7_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos)
19817#define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk
19819#define SYSCFG_UR3_BCM4_ADD0_Pos (16U)
19820#define SYSCFG_UR3_BCM4_ADD0_Msk (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos)
19821#define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk
19823/****************** Bit definition for SYSCFG_UR4 register *******************/
19824
19825#define SYSCFG_UR4_BCM4_ADD1_Pos (0U)
19826#define SYSCFG_UR4_BCM4_ADD1_Msk (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos)
19827#define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk
19829#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
19830#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)
19831#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk
19833/****************** Bit definition for SYSCFG_UR5 register *******************/
19834#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
19835#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)
19836#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk
19837#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
19838#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)
19839#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk
19841/****************** Bit definition for SYSCFG_UR6 register *******************/
19842#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
19843#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos)
19844#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk
19845#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
19846#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos)
19847#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk
19849/****************** Bit definition for SYSCFG_UR7 register *******************/
19850#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
19851#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos)
19852#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk
19853#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
19854#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos)
19855#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk
19857/****************** Bit definition for SYSCFG_UR8 register *******************/
19858#define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
19859#define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)
19860#define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk
19861#define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
19862#define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)
19863#define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk
19865/****************** Bit definition for SYSCFG_UR9 register *******************/
19866#define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
19867#define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)
19868#define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk
19869#define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
19870#define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos)
19871#define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk
19873/****************** Bit definition for SYSCFG_UR10 register *******************/
19874#define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
19875#define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos)
19876#define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk
19877#define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
19878#define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos)
19879#define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk
19881/****************** Bit definition for SYSCFG_UR11 register *******************/
19882#define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
19883#define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos)
19884#define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk
19885#define SYSCFG_UR11_IWDG1M_Pos (16U)
19886#define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos)
19887#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk
19889/****************** Bit definition for SYSCFG_UR12 register *******************/
19890#define SYSCFG_UR12_IWDG2M_Pos (0U)
19891#define SYSCFG_UR12_IWDG2M_Msk (0x1UL << SYSCFG_UR12_IWDG2M_Pos)
19892#define SYSCFG_UR12_IWDG2M SYSCFG_UR12_IWDG2M_Msk
19894#define SYSCFG_UR12_SECURE_Pos (16U)
19895#define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos)
19896#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk
19898/****************** Bit definition for SYSCFG_UR13 register *******************/
19899#define SYSCFG_UR13_SDRS_Pos (0U)
19900#define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos)
19901#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk
19902#define SYSCFG_UR13_D1SBRST_Pos (16U)
19903#define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos)
19904#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk
19906/****************** Bit definition for SYSCFG_UR14 register *******************/
19907#define SYSCFG_UR14_D1STPRST_Pos (0U)
19908#define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos)
19909#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk
19910#define SYSCFG_UR14_D2SBRST_Pos (16U)
19911#define SYSCFG_UR14_D2SBRST_Msk (0x1UL << SYSCFG_UR14_D2SBRST_Pos)
19912#define SYSCFG_UR14_D2SBRST SYSCFG_UR14_D2SBRST_Msk
19914/****************** Bit definition for SYSCFG_UR15 register *******************/
19915#define SYSCFG_UR15_D2STPRST_Pos (0U)
19916#define SYSCFG_UR15_D2STPRST_Msk (0x1UL << SYSCFG_UR15_D2STPRST_Pos)
19917#define SYSCFG_UR15_D2STPRST SYSCFG_UR15_D2STPRST_Msk
19918#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
19919#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)
19920#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk
19922/****************** Bit definition for SYSCFG_UR16 register *******************/
19923#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
19924#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)
19925#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk
19926#define SYSCFG_UR16_PKP_Pos (16U)
19927#define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos)
19928#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk
19930/****************** Bit definition for SYSCFG_UR17 register *******************/
19931#define SYSCFG_UR17_IOHSLV_Pos (0U)
19932#define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos)
19933#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk
19936/******************************************************************************/
19937/* */
19938/* TIM */
19939/* */
19940/******************************************************************************/
19941#define TIM_BREAK_INPUT_SUPPORT
19943/******************* Bit definition for TIM_CR1 register ********************/
19944#define TIM_CR1_CEN_Pos (0U)
19945#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
19946#define TIM_CR1_CEN TIM_CR1_CEN_Msk
19947#define TIM_CR1_UDIS_Pos (1U)
19948#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
19949#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
19950#define TIM_CR1_URS_Pos (2U)
19951#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
19952#define TIM_CR1_URS TIM_CR1_URS_Msk
19953#define TIM_CR1_OPM_Pos (3U)
19954#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
19955#define TIM_CR1_OPM TIM_CR1_OPM_Msk
19956#define TIM_CR1_DIR_Pos (4U)
19957#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
19958#define TIM_CR1_DIR TIM_CR1_DIR_Msk
19960#define TIM_CR1_CMS_Pos (5U)
19961#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
19962#define TIM_CR1_CMS TIM_CR1_CMS_Msk
19963#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
19964#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
19966#define TIM_CR1_ARPE_Pos (7U)
19967#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
19968#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
19970#define TIM_CR1_CKD_Pos (8U)
19971#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
19972#define TIM_CR1_CKD TIM_CR1_CKD_Msk
19973#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
19974#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
19976#define TIM_CR1_UIFREMAP_Pos (11U)
19977#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
19978#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
19980/******************* Bit definition for TIM_CR2 register ********************/
19981#define TIM_CR2_CCPC_Pos (0U)
19982#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
19983#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
19984#define TIM_CR2_CCUS_Pos (2U)
19985#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
19986#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
19987#define TIM_CR2_CCDS_Pos (3U)
19988#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
19989#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
19991#define TIM_CR2_MMS_Pos (4U)
19992#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
19993#define TIM_CR2_MMS TIM_CR2_MMS_Msk
19994#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
19995#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
19996#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
19998#define TIM_CR2_TI1S_Pos (7U)
19999#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
20000#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
20001#define TIM_CR2_OIS1_Pos (8U)
20002#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
20003#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
20004#define TIM_CR2_OIS1N_Pos (9U)
20005#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
20006#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
20007#define TIM_CR2_OIS2_Pos (10U)
20008#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
20009#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
20010#define TIM_CR2_OIS2N_Pos (11U)
20011#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
20012#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
20013#define TIM_CR2_OIS3_Pos (12U)
20014#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
20015#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
20016#define TIM_CR2_OIS3N_Pos (13U)
20017#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
20018#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
20019#define TIM_CR2_OIS4_Pos (14U)
20020#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
20021#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
20022#define TIM_CR2_OIS5_Pos (16U)
20023#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
20024#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
20025#define TIM_CR2_OIS6_Pos (18U)
20026#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
20027#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
20029#define TIM_CR2_MMS2_Pos (20U)
20030#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
20031#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
20032#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
20033#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
20034#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
20035#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
20037/******************* Bit definition for TIM_SMCR register *******************/
20038#define TIM_SMCR_SMS_Pos (0U)
20039#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
20040#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
20041#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
20042#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
20043#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
20044#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
20046#define TIM_SMCR_TS_Pos (4U)
20047#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
20048#define TIM_SMCR_TS TIM_SMCR_TS_Msk
20049#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
20050#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
20051#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
20052#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
20053#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
20055#define TIM_SMCR_MSM_Pos (7U)
20056#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
20057#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
20059#define TIM_SMCR_ETF_Pos (8U)
20060#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
20061#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
20062#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
20063#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
20064#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
20065#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
20067#define TIM_SMCR_ETPS_Pos (12U)
20068#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
20069#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
20070#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
20071#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
20073#define TIM_SMCR_ECE_Pos (14U)
20074#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
20075#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
20076#define TIM_SMCR_ETP_Pos (15U)
20077#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
20078#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
20080/******************* Bit definition for TIM_DIER register *******************/
20081#define TIM_DIER_UIE_Pos (0U)
20082#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
20083#define TIM_DIER_UIE TIM_DIER_UIE_Msk
20084#define TIM_DIER_CC1IE_Pos (1U)
20085#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
20086#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
20087#define TIM_DIER_CC2IE_Pos (2U)
20088#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
20089#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
20090#define TIM_DIER_CC3IE_Pos (3U)
20091#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
20092#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
20093#define TIM_DIER_CC4IE_Pos (4U)
20094#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
20095#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
20096#define TIM_DIER_COMIE_Pos (5U)
20097#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
20098#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
20099#define TIM_DIER_TIE_Pos (6U)
20100#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
20101#define TIM_DIER_TIE TIM_DIER_TIE_Msk
20102#define TIM_DIER_BIE_Pos (7U)
20103#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
20104#define TIM_DIER_BIE TIM_DIER_BIE_Msk
20105#define TIM_DIER_UDE_Pos (8U)
20106#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
20107#define TIM_DIER_UDE TIM_DIER_UDE_Msk
20108#define TIM_DIER_CC1DE_Pos (9U)
20109#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
20110#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
20111#define TIM_DIER_CC2DE_Pos (10U)
20112#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
20113#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
20114#define TIM_DIER_CC3DE_Pos (11U)
20115#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
20116#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
20117#define TIM_DIER_CC4DE_Pos (12U)
20118#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
20119#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
20120#define TIM_DIER_COMDE_Pos (13U)
20121#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
20122#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
20123#define TIM_DIER_TDE_Pos (14U)
20124#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
20125#define TIM_DIER_TDE TIM_DIER_TDE_Msk
20127/******************** Bit definition for TIM_SR register ********************/
20128#define TIM_SR_UIF_Pos (0U)
20129#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
20130#define TIM_SR_UIF TIM_SR_UIF_Msk
20131#define TIM_SR_CC1IF_Pos (1U)
20132#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
20133#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
20134#define TIM_SR_CC2IF_Pos (2U)
20135#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
20136#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
20137#define TIM_SR_CC3IF_Pos (3U)
20138#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
20139#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
20140#define TIM_SR_CC4IF_Pos (4U)
20141#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
20142#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
20143#define TIM_SR_COMIF_Pos (5U)
20144#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
20145#define TIM_SR_COMIF TIM_SR_COMIF_Msk
20146#define TIM_SR_TIF_Pos (6U)
20147#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
20148#define TIM_SR_TIF TIM_SR_TIF_Msk
20149#define TIM_SR_BIF_Pos (7U)
20150#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
20151#define TIM_SR_BIF TIM_SR_BIF_Msk
20152#define TIM_SR_B2IF_Pos (8U)
20153#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
20154#define TIM_SR_B2IF TIM_SR_B2IF_Msk
20155#define TIM_SR_CC1OF_Pos (9U)
20156#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
20157#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
20158#define TIM_SR_CC2OF_Pos (10U)
20159#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
20160#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
20161#define TIM_SR_CC3OF_Pos (11U)
20162#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
20163#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
20164#define TIM_SR_CC4OF_Pos (12U)
20165#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
20166#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
20167#define TIM_SR_CC5IF_Pos (16U)
20168#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
20169#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
20170#define TIM_SR_CC6IF_Pos (17U)
20171#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
20172#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
20173#define TIM_SR_SBIF_Pos (13U)
20174#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
20175#define TIM_SR_SBIF TIM_SR_SBIF_Msk
20177/******************* Bit definition for TIM_EGR register ********************/
20178#define TIM_EGR_UG_Pos (0U)
20179#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
20180#define TIM_EGR_UG TIM_EGR_UG_Msk
20181#define TIM_EGR_CC1G_Pos (1U)
20182#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
20183#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
20184#define TIM_EGR_CC2G_Pos (2U)
20185#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
20186#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
20187#define TIM_EGR_CC3G_Pos (3U)
20188#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
20189#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
20190#define TIM_EGR_CC4G_Pos (4U)
20191#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
20192#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
20193#define TIM_EGR_COMG_Pos (5U)
20194#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
20195#define TIM_EGR_COMG TIM_EGR_COMG_Msk
20196#define TIM_EGR_TG_Pos (6U)
20197#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
20198#define TIM_EGR_TG TIM_EGR_TG_Msk
20199#define TIM_EGR_BG_Pos (7U)
20200#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
20201#define TIM_EGR_BG TIM_EGR_BG_Msk
20202#define TIM_EGR_B2G_Pos (8U)
20203#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
20204#define TIM_EGR_B2G TIM_EGR_B2G_Msk
20207/****************** Bit definition for TIM_CCMR1 register *******************/
20208#define TIM_CCMR1_CC1S_Pos (0U)
20209#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
20210#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
20211#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
20212#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
20214#define TIM_CCMR1_OC1FE_Pos (2U)
20215#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
20216#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
20217#define TIM_CCMR1_OC1PE_Pos (3U)
20218#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
20219#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
20221#define TIM_CCMR1_OC1M_Pos (4U)
20222#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
20223#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
20224#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
20225#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
20226#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
20227#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
20229#define TIM_CCMR1_OC1CE_Pos (7U)
20230#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
20231#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
20233#define TIM_CCMR1_CC2S_Pos (8U)
20234#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
20235#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
20236#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
20237#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
20239#define TIM_CCMR1_OC2FE_Pos (10U)
20240#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
20241#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
20242#define TIM_CCMR1_OC2PE_Pos (11U)
20243#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
20244#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
20246#define TIM_CCMR1_OC2M_Pos (12U)
20247#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
20248#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
20249#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
20250#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
20251#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
20252#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
20254#define TIM_CCMR1_OC2CE_Pos (15U)
20255#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
20256#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
20258/*----------------------------------------------------------------------------*/
20259
20260#define TIM_CCMR1_IC1PSC_Pos (2U)
20261#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
20262#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
20263#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
20264#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
20266#define TIM_CCMR1_IC1F_Pos (4U)
20267#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
20268#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
20269#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
20270#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
20271#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
20272#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
20274#define TIM_CCMR1_IC2PSC_Pos (10U)
20275#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
20276#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
20277#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
20278#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
20280#define TIM_CCMR1_IC2F_Pos (12U)
20281#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
20282#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
20283#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
20284#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
20285#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
20286#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
20288/****************** Bit definition for TIM_CCMR2 register *******************/
20289#define TIM_CCMR2_CC3S_Pos (0U)
20290#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
20291#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
20292#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
20293#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
20295#define TIM_CCMR2_OC3FE_Pos (2U)
20296#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
20297#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
20298#define TIM_CCMR2_OC3PE_Pos (3U)
20299#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
20300#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
20302#define TIM_CCMR2_OC3M_Pos (4U)
20303#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
20304#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
20305#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
20306#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
20307#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
20308#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
20310#define TIM_CCMR2_OC3CE_Pos (7U)
20311#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
20312#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
20314#define TIM_CCMR2_CC4S_Pos (8U)
20315#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
20316#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
20317#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
20318#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
20320#define TIM_CCMR2_OC4FE_Pos (10U)
20321#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
20322#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
20323#define TIM_CCMR2_OC4PE_Pos (11U)
20324#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
20325#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
20327#define TIM_CCMR2_OC4M_Pos (12U)
20328#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
20329#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
20330#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
20331#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
20332#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
20333#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
20335#define TIM_CCMR2_OC4CE_Pos (15U)
20336#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
20337#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
20339/*----------------------------------------------------------------------------*/
20340
20341#define TIM_CCMR2_IC3PSC_Pos (2U)
20342#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
20343#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
20344#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
20345#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
20347#define TIM_CCMR2_IC3F_Pos (4U)
20348#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
20349#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
20350#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
20351#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
20352#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
20353#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
20355#define TIM_CCMR2_IC4PSC_Pos (10U)
20356#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
20357#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
20358#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
20359#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
20361#define TIM_CCMR2_IC4F_Pos (12U)
20362#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
20363#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
20364#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
20365#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
20366#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
20367#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
20369/******************* Bit definition for TIM_CCER register *******************/
20370#define TIM_CCER_CC1E_Pos (0U)
20371#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
20372#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
20373#define TIM_CCER_CC1P_Pos (1U)
20374#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
20375#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
20376#define TIM_CCER_CC1NE_Pos (2U)
20377#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
20378#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
20379#define TIM_CCER_CC1NP_Pos (3U)
20380#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
20381#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
20382#define TIM_CCER_CC2E_Pos (4U)
20383#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
20384#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
20385#define TIM_CCER_CC2P_Pos (5U)
20386#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
20387#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
20388#define TIM_CCER_CC2NE_Pos (6U)
20389#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
20390#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
20391#define TIM_CCER_CC2NP_Pos (7U)
20392#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
20393#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
20394#define TIM_CCER_CC3E_Pos (8U)
20395#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
20396#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
20397#define TIM_CCER_CC3P_Pos (9U)
20398#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
20399#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
20400#define TIM_CCER_CC3NE_Pos (10U)
20401#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
20402#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
20403#define TIM_CCER_CC3NP_Pos (11U)
20404#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
20405#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
20406#define TIM_CCER_CC4E_Pos (12U)
20407#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
20408#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
20409#define TIM_CCER_CC4P_Pos (13U)
20410#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
20411#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
20412#define TIM_CCER_CC4NP_Pos (15U)
20413#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
20414#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
20415#define TIM_CCER_CC5E_Pos (16U)
20416#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
20417#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
20418#define TIM_CCER_CC5P_Pos (17U)
20419#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
20420#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
20421#define TIM_CCER_CC6E_Pos (20U)
20422#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
20423#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
20424#define TIM_CCER_CC6P_Pos (21U)
20425#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
20426#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
20427/******************* Bit definition for TIM_CNT register ********************/
20428#define TIM_CNT_CNT_Pos (0U)
20429#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
20430#define TIM_CNT_CNT TIM_CNT_CNT_Msk
20431#define TIM_CNT_UIFCPY_Pos (31U)
20432#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
20433#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
20434/******************* Bit definition for TIM_PSC register ********************/
20435#define TIM_PSC_PSC_Pos (0U)
20436#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
20437#define TIM_PSC_PSC TIM_PSC_PSC_Msk
20439/******************* Bit definition for TIM_ARR register ********************/
20440#define TIM_ARR_ARR_Pos (0U)
20441#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
20442#define TIM_ARR_ARR TIM_ARR_ARR_Msk
20444/******************* Bit definition for TIM_RCR register ********************/
20445#define TIM_RCR_REP_Pos (0U)
20446#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
20447#define TIM_RCR_REP TIM_RCR_REP_Msk
20449/******************* Bit definition for TIM_CCR1 register *******************/
20450#define TIM_CCR1_CCR1_Pos (0U)
20451#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
20452#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
20454/******************* Bit definition for TIM_CCR2 register *******************/
20455#define TIM_CCR2_CCR2_Pos (0U)
20456#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
20457#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
20459/******************* Bit definition for TIM_CCR3 register *******************/
20460#define TIM_CCR3_CCR3_Pos (0U)
20461#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
20462#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
20464/******************* Bit definition for TIM_CCR4 register *******************/
20465#define TIM_CCR4_CCR4_Pos (0U)
20466#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
20467#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
20469/******************* Bit definition for TIM_CCR5 register *******************/
20470#define TIM_CCR5_CCR5_Pos (0U)
20471#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
20472#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
20473#define TIM_CCR5_GC5C1_Pos (29U)
20474#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
20475#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
20476#define TIM_CCR5_GC5C2_Pos (30U)
20477#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
20478#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
20479#define TIM_CCR5_GC5C3_Pos (31U)
20480#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
20481#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
20483/******************* Bit definition for TIM_CCR6 register *******************/
20484#define TIM_CCR6_CCR6_Pos (0U)
20485#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
20486#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
20488/******************* Bit definition for TIM_BDTR register *******************/
20489#define TIM_BDTR_DTG_Pos (0U)
20490#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
20491#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
20492#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
20493#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
20494#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
20495#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
20496#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
20497#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
20498#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
20499#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
20501#define TIM_BDTR_LOCK_Pos (8U)
20502#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
20503#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
20504#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
20505#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
20507#define TIM_BDTR_OSSI_Pos (10U)
20508#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
20509#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
20510#define TIM_BDTR_OSSR_Pos (11U)
20511#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
20512#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
20513#define TIM_BDTR_BKE_Pos (12U)
20514#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
20515#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
20516#define TIM_BDTR_BKP_Pos (13U)
20517#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
20518#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
20519#define TIM_BDTR_AOE_Pos (14U)
20520#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
20521#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
20522#define TIM_BDTR_MOE_Pos (15U)
20523#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
20524#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
20526#define TIM_BDTR_BKF_Pos (16U)
20527#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
20528#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
20529#define TIM_BDTR_BK2F_Pos (20U)
20530#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
20531#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
20533#define TIM_BDTR_BK2E_Pos (24U)
20534#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
20535#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
20536#define TIM_BDTR_BK2P_Pos (25U)
20537#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
20538#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
20540/******************* Bit definition for TIM_DCR register ********************/
20541#define TIM_DCR_DBA_Pos (0U)
20542#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
20543#define TIM_DCR_DBA TIM_DCR_DBA_Msk
20544#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
20545#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
20546#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
20547#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
20548#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
20550#define TIM_DCR_DBL_Pos (8U)
20551#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
20552#define TIM_DCR_DBL TIM_DCR_DBL_Msk
20553#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
20554#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
20555#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
20556#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
20557#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
20559/******************* Bit definition for TIM_DMAR register *******************/
20560#define TIM_DMAR_DMAB_Pos (0U)
20561#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
20562#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
20564/****************** Bit definition for TIM_CCMR3 register *******************/
20565#define TIM_CCMR3_OC5FE_Pos (2U)
20566#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
20567#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
20568#define TIM_CCMR3_OC5PE_Pos (3U)
20569#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
20570#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
20572#define TIM_CCMR3_OC5M_Pos (4U)
20573#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
20574#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
20575#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos)
20576#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos)
20577#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos)
20578#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
20580#define TIM_CCMR3_OC5CE_Pos (7U)
20581#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
20582#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
20584#define TIM_CCMR3_OC6FE_Pos (10U)
20585#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
20586#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
20587#define TIM_CCMR3_OC6PE_Pos (11U)
20588#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
20589#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
20591#define TIM_CCMR3_OC6M_Pos (12U)
20592#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
20593#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
20594#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos)
20595#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos)
20596#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos)
20597#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
20599#define TIM_CCMR3_OC6CE_Pos (15U)
20600#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
20601#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
20602/******************* Bit definition for TIM1_AF1 register *********************/
20603#define TIM1_AF1_BKINE_Pos (0U)
20604#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
20605#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
20606#define TIM1_AF1_BKCMP1E_Pos (1U)
20607#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
20608#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
20609#define TIM1_AF1_BKCMP2E_Pos (2U)
20610#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
20611#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
20612#define TIM1_AF1_BKDF1BK0E_Pos (8U)
20613#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
20614#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk
20615#define TIM1_AF1_BKINP_Pos (9U)
20616#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
20617#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
20618#define TIM1_AF1_BKCMP1P_Pos (10U)
20619#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
20620#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
20621#define TIM1_AF1_BKCMP2P_Pos (11U)
20622#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
20623#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
20625#define TIM1_AF1_ETRSEL_Pos (14U)
20626#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
20627#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
20628#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
20629#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
20630#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
20631#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
20633/******************* Bit definition for TIM1_AF2 register *********************/
20634#define TIM1_AF2_BK2INE_Pos (0U)
20635#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
20636#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
20637#define TIM1_AF2_BK2CMP1E_Pos (1U)
20638#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
20639#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
20640#define TIM1_AF2_BK2CMP2E_Pos (2U)
20641#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
20642#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
20643#define TIM1_AF2_BK2DFBK1E_Pos (8U)
20644#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
20645#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk
20646#define TIM1_AF2_BK2INP_Pos (9U)
20647#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
20648#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
20649#define TIM1_AF2_BK2CMP1P_Pos (10U)
20650#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
20651#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
20652#define TIM1_AF2_BK2CMP2P_Pos (11U)
20653#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
20654#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
20656/******************* Bit definition for TIM_TISEL register *********************/
20657#define TIM_TISEL_TI1SEL_Pos (0U)
20658#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
20659#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
20660#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
20661#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
20662#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
20663#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
20665#define TIM_TISEL_TI2SEL_Pos (8U)
20666#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
20667#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
20668#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
20669#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
20670#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
20671#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
20673#define TIM_TISEL_TI3SEL_Pos (16U)
20674#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
20675#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
20676#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
20677#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
20678#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
20679#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
20681#define TIM_TISEL_TI4SEL_Pos (24U)
20682#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
20683#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
20684#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
20685#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
20686#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
20687#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
20689/******************* Bit definition for TIM8_AF1 register *********************/
20690#define TIM8_AF1_BKINE_Pos (0U)
20691#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
20692#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
20693#define TIM8_AF1_BKCMP1E_Pos (1U)
20694#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos)
20695#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk
20696#define TIM8_AF1_BKCMP2E_Pos (2U)
20697#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos)
20698#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk
20699#define TIM8_AF1_BKDFBK2E_Pos (8U)
20700#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
20701#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk
20702#define TIM8_AF1_BKINP_Pos (9U)
20703#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
20704#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
20705#define TIM8_AF1_BKCMP1P_Pos (10U)
20706#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos)
20707#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk
20708#define TIM8_AF1_BKCMP2P_Pos (11U)
20709#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos)
20710#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk
20712#define TIM8_AF1_ETRSEL_Pos (14U)
20713#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos)
20714#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk
20715#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos)
20716#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos)
20717#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos)
20718#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos)
20719/******************* Bit definition for TIM8_AF2 register *********************/
20720#define TIM8_AF2_BK2INE_Pos (0U)
20721#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
20722#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
20723#define TIM8_AF2_BK2CMP1E_Pos (1U)
20724#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
20725#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk
20726#define TIM8_AF2_BK2CMP2E_Pos (2U)
20727#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
20728#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk
20729#define TIM8_AF2_BK2DFBK3E_Pos (8U)
20730#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
20731#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk
20732#define TIM8_AF2_BK2INP_Pos (9U)
20733#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
20734#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
20735#define TIM8_AF2_BK2CMP1P_Pos (10U)
20736#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
20737#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk
20738#define TIM8_AF2_BK2CMP2P_Pos (11U)
20739#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
20740#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk
20742/******************* Bit definition for TIM2_AF1 register *********************/
20743#define TIM2_AF1_ETRSEL_Pos (14U)
20744#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)
20745#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk
20746#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos)
20747#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos)
20748#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos)
20749#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos)
20751/******************* Bit definition for TIM3_AF1 register *********************/
20752#define TIM3_AF1_ETRSEL_Pos (14U)
20753#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)
20754#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk
20755#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)
20756#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)
20757#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)
20758#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)
20760/******************* Bit definition for TIM5_AF1 register *********************/
20761#define TIM5_AF1_ETRSEL_Pos (14U)
20762#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos)
20763#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk
20764#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos)
20765#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos)
20766#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos)
20767#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos)
20769/******************* Bit definition for TIM15_AF1 register *********************/
20770#define TIM15_AF1_BKINE_Pos (0U)
20771#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos)
20772#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk
20773#define TIM15_AF1_BKCMP1E_Pos (1U)
20774#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos)
20775#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk
20776#define TIM15_AF1_BKCMP2E_Pos (2U)
20777#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos)
20778#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk
20779#define TIM15_AF1_BKDF1BK2E_Pos (8U)
20780#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
20781#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk
20782#define TIM15_AF1_BKINP_Pos (9U)
20783#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos)
20784#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk
20785#define TIM15_AF1_BKCMP1P_Pos (10U)
20786#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos)
20787#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk
20788#define TIM15_AF1_BKCMP2P_Pos (11U)
20789#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
20790#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk
20792/******************* Bit definition for TIM16_ register *********************/
20793#define TIM16_AF1_BKINE_Pos (0U)
20794#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)
20795#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk
20796#define TIM16_AF1_BKCMP1E_Pos (1U)
20797#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)
20798#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk
20799#define TIM16_AF1_BKCMP2E_Pos (2U)
20800#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)
20801#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk
20802#define TIM16_AF1_BKDF1BK2E_Pos (8U)
20803#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
20804#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk
20805#define TIM16_AF1_BKINP_Pos (9U)
20806#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)
20807#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk
20808#define TIM16_AF1_BKCMP1P_Pos (10U)
20809#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)
20810#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk
20811#define TIM16_AF1_BKCMP2P_Pos (11U)
20812#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)
20813#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk
20815/******************* Bit definition for TIM17_AF1 register *********************/
20816#define TIM17_AF1_BKINE_Pos (0U)
20817#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)
20818#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk
20819#define TIM17_AF1_BKCMP1E_Pos (1U)
20820#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)
20821#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk
20822#define TIM17_AF1_BKCMP2E_Pos (2U)
20823#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)
20824#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk
20825#define TIM17_AF1_BKDF1BK2E_Pos (8U)
20826#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
20827#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk
20828#define TIM17_AF1_BKINP_Pos (9U)
20829#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)
20830#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk
20831#define TIM17_AF1_BKCMP1P_Pos (10U)
20832#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)
20833#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk
20834#define TIM17_AF1_BKCMP2P_Pos (11U)
20835#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)
20836#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk
20838/******************************************************************************/
20839/* */
20840/* Low Power Timer (LPTTIM) */
20841/* */
20842/******************************************************************************/
20843/****************** Bit definition for LPTIM_ISR register *******************/
20844#define LPTIM_ISR_CMPM_Pos (0U)
20845#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
20846#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
20847#define LPTIM_ISR_ARRM_Pos (1U)
20848#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
20849#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
20850#define LPTIM_ISR_EXTTRIG_Pos (2U)
20851#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
20852#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
20853#define LPTIM_ISR_CMPOK_Pos (3U)
20854#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
20855#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
20856#define LPTIM_ISR_ARROK_Pos (4U)
20857#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
20858#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
20859#define LPTIM_ISR_UP_Pos (5U)
20860#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
20861#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
20862#define LPTIM_ISR_DOWN_Pos (6U)
20863#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
20864#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
20866/****************** Bit definition for LPTIM_ICR register *******************/
20867#define LPTIM_ICR_CMPMCF_Pos (0U)
20868#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
20869#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
20870#define LPTIM_ICR_ARRMCF_Pos (1U)
20871#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
20872#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
20873#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
20874#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
20875#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
20876#define LPTIM_ICR_CMPOKCF_Pos (3U)
20877#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
20878#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
20879#define LPTIM_ICR_ARROKCF_Pos (4U)
20880#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
20881#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
20882#define LPTIM_ICR_UPCF_Pos (5U)
20883#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
20884#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
20885#define LPTIM_ICR_DOWNCF_Pos (6U)
20886#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
20887#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
20889/****************** Bit definition for LPTIM_IER register ********************/
20890#define LPTIM_IER_CMPMIE_Pos (0U)
20891#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
20892#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
20893#define LPTIM_IER_ARRMIE_Pos (1U)
20894#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
20895#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
20896#define LPTIM_IER_EXTTRIGIE_Pos (2U)
20897#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
20898#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
20899#define LPTIM_IER_CMPOKIE_Pos (3U)
20900#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
20901#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
20902#define LPTIM_IER_ARROKIE_Pos (4U)
20903#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
20904#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
20905#define LPTIM_IER_UPIE_Pos (5U)
20906#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
20907#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
20908#define LPTIM_IER_DOWNIE_Pos (6U)
20909#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
20910#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
20912/****************** Bit definition for LPTIM_CFGR register *******************/
20913#define LPTIM_CFGR_CKSEL_Pos (0U)
20914#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
20915#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
20917#define LPTIM_CFGR_CKPOL_Pos (1U)
20918#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
20919#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
20920#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
20921#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
20923#define LPTIM_CFGR_CKFLT_Pos (3U)
20924#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
20925#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
20926#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
20927#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
20929#define LPTIM_CFGR_TRGFLT_Pos (6U)
20930#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
20931#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
20932#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
20933#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
20935#define LPTIM_CFGR_PRESC_Pos (9U)
20936#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
20937#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
20938#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
20939#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
20940#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
20942#define LPTIM_CFGR_TRIGSEL_Pos (13U)
20943#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
20944#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
20945#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
20946#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
20947#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
20949#define LPTIM_CFGR_TRIGEN_Pos (17U)
20950#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
20951#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
20952#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
20953#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
20955#define LPTIM_CFGR_TIMOUT_Pos (19U)
20956#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
20957#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
20958#define LPTIM_CFGR_WAVE_Pos (20U)
20959#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
20960#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
20961#define LPTIM_CFGR_WAVPOL_Pos (21U)
20962#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
20963#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
20964#define LPTIM_CFGR_PRELOAD_Pos (22U)
20965#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
20966#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
20967#define LPTIM_CFGR_COUNTMODE_Pos (23U)
20968#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
20969#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
20970#define LPTIM_CFGR_ENC_Pos (24U)
20971#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
20972#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
20974/****************** Bit definition for LPTIM_CR register ********************/
20975#define LPTIM_CR_ENABLE_Pos (0U)
20976#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
20977#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
20978#define LPTIM_CR_SNGSTRT_Pos (1U)
20979#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
20980#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
20981#define LPTIM_CR_CNTSTRT_Pos (2U)
20982#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
20983#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
20984#define LPTIM_CR_COUNTRST_Pos (3U)
20985#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
20986#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
20987#define LPTIM_CR_RSTARE_Pos (4U)
20988#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
20989#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
20992/****************** Bit definition for LPTIM_CMP register *******************/
20993#define LPTIM_CMP_CMP_Pos (0U)
20994#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
20995#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
20997/****************** Bit definition for LPTIM_ARR register *******************/
20998#define LPTIM_ARR_ARR_Pos (0U)
20999#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
21000#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
21002/****************** Bit definition for LPTIM_CNT register *******************/
21003#define LPTIM_CNT_CNT_Pos (0U)
21004#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
21005#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
21007/****************** Bit definition for LPTIM_CFGR2 register *****************/
21008#define LPTIM_CFGR2_IN1SEL_Pos (0U)
21009#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
21010#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk
21011#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
21012#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
21013#define LPTIM_CFGR2_IN2SEL_Pos (4U)
21014#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
21015#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk
21016#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
21017#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
21019/******************************************************************************/
21020/* */
21021/* Analog Comparators (COMP) */
21022/* */
21023/******************************************************************************/
21024
21025/******************* Bit definition for COMP_SR register ********************/
21026#define COMP_SR_C1VAL_Pos (0U)
21027#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos)
21028#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
21029#define COMP_SR_C2VAL_Pos (1U)
21030#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos)
21031#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
21032#define COMP_SR_C1IF_Pos (16U)
21033#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos)
21034#define COMP_SR_C1IF COMP_SR_C1IF_Msk
21035#define COMP_SR_C2IF_Pos (17U)
21036#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos)
21037#define COMP_SR_C2IF COMP_SR_C2IF_Msk
21038/******************* Bit definition for COMP_ICFR register ********************/
21039#define COMP_ICFR_C1IF_Pos (16U)
21040#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos)
21041#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
21042#define COMP_ICFR_C2IF_Pos (17U)
21043#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos)
21044#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
21045/******************* Bit definition for COMP_OR register ********************/
21046#define COMP_OR_AFOPA6_Pos (0U)
21047#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos)
21048#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
21049#define COMP_OR_AFOPA8_Pos (1U)
21050#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos)
21051#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
21052#define COMP_OR_AFOPB12_Pos (2U)
21053#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos)
21054#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
21055#define COMP_OR_AFOPE6_Pos (3U)
21056#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos)
21057#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
21058#define COMP_OR_AFOPE15_Pos (4U)
21059#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos)
21060#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
21061#define COMP_OR_AFOPG2_Pos (5U)
21062#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos)
21063#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
21064#define COMP_OR_AFOPG3_Pos (6U)
21065#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos)
21066#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
21067#define COMP_OR_AFOPG4_Pos (7U)
21068#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos)
21069#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
21070#define COMP_OR_AFOPI1_Pos (8U)
21071#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos)
21072#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
21073#define COMP_OR_AFOPI4_Pos (9U)
21074#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos)
21075#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
21076#define COMP_OR_AFOPK2_Pos (10U)
21077#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos)
21078#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
21079
21081#define COMP_CFGRx_EN_Pos (0U)
21082#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos)
21083#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk
21084#define COMP_CFGRx_BRGEN_Pos (1U)
21085#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos)
21086#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk
21087#define COMP_CFGRx_SCALEN_Pos (2U)
21088#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos)
21089#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk
21090#define COMP_CFGRx_POLARITY_Pos (3U)
21091#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos)
21092#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk
21093#define COMP_CFGRx_WINMODE_Pos (4U)
21094#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos)
21095#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk
21096#define COMP_CFGRx_ITEN_Pos (6U)
21097#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos)
21098#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk
21099#define COMP_CFGRx_HYST_Pos (8U)
21100#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos)
21101#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk
21102#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos)
21103#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos)
21104#define COMP_CFGRx_PWRMODE_Pos (12U)
21105#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos)
21106#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk
21107#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos)
21108#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos)
21109#define COMP_CFGRx_INMSEL_Pos (16U)
21110#define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos)
21111#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk
21112#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos)
21113#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos)
21114#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos)
21115#define COMP_CFGRx_INPSEL_Pos (20U)
21116#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos)
21117#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk
21118#define COMP_CFGRx_BLANKING_Pos (24U)
21119#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos)
21120#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk
21121#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos)
21122#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos)
21123#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos)
21124#define COMP_CFGRx_LOCK_Pos (31U)
21125#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos)
21126#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk
21129/******************************************************************************/
21130/* */
21131/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
21132/* */
21133/******************************************************************************/
21134/****************** Bit definition for USART_CR1 register *******************/
21135#define USART_CR1_UE_Pos (0U)
21136#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
21137#define USART_CR1_UE USART_CR1_UE_Msk
21138#define USART_CR1_UESM_Pos (1U)
21139#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
21140#define USART_CR1_UESM USART_CR1_UESM_Msk
21141#define USART_CR1_RE_Pos (2U)
21142#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
21143#define USART_CR1_RE USART_CR1_RE_Msk
21144#define USART_CR1_TE_Pos (3U)
21145#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
21146#define USART_CR1_TE USART_CR1_TE_Msk
21147#define USART_CR1_IDLEIE_Pos (4U)
21148#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
21149#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
21150#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
21151#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
21152#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk
21153#define USART_CR1_TCIE_Pos (6U)
21154#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
21155#define USART_CR1_TCIE USART_CR1_TCIE_Msk
21156#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
21157#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
21158#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk
21159#define USART_CR1_PEIE_Pos (8U)
21160#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
21161#define USART_CR1_PEIE USART_CR1_PEIE_Msk
21162#define USART_CR1_PS_Pos (9U)
21163#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
21164#define USART_CR1_PS USART_CR1_PS_Msk
21165#define USART_CR1_PCE_Pos (10U)
21166#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
21167#define USART_CR1_PCE USART_CR1_PCE_Msk
21168#define USART_CR1_WAKE_Pos (11U)
21169#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
21170#define USART_CR1_WAKE USART_CR1_WAKE_Msk
21171#define USART_CR1_M_Pos (12U)
21172#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
21173#define USART_CR1_M USART_CR1_M_Msk
21174#define USART_CR1_M0_Pos (12U)
21175#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
21176#define USART_CR1_M0 USART_CR1_M0_Msk
21177#define USART_CR1_MME_Pos (13U)
21178#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
21179#define USART_CR1_MME USART_CR1_MME_Msk
21180#define USART_CR1_CMIE_Pos (14U)
21181#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
21182#define USART_CR1_CMIE USART_CR1_CMIE_Msk
21183#define USART_CR1_OVER8_Pos (15U)
21184#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
21185#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
21186#define USART_CR1_DEDT_Pos (16U)
21187#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
21188#define USART_CR1_DEDT USART_CR1_DEDT_Msk
21189#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
21190#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
21191#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
21192#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
21193#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
21194#define USART_CR1_DEAT_Pos (21U)
21195#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
21196#define USART_CR1_DEAT USART_CR1_DEAT_Msk
21197#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
21198#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
21199#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
21200#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
21201#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
21202#define USART_CR1_RTOIE_Pos (26U)
21203#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
21204#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
21205#define USART_CR1_EOBIE_Pos (27U)
21206#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
21207#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
21208#define USART_CR1_M1_Pos (28U)
21209#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
21210#define USART_CR1_M1 USART_CR1_M1_Msk
21211#define USART_CR1_FIFOEN_Pos (29U)
21212#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
21213#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
21214#define USART_CR1_TXFEIE_Pos (30U)
21215#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
21216#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
21217#define USART_CR1_RXFFIE_Pos (31U)
21218#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
21219#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
21221/* Legacy define */
21222#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
21223#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
21224
21225/****************** Bit definition for USART_CR2 register *******************/
21226#define USART_CR2_SLVEN_Pos (0U)
21227#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
21228#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
21229#define USART_CR2_DIS_NSS_Pos (3U)
21230#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
21231#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
21232#define USART_CR2_ADDM7_Pos (4U)
21233#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
21234#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
21235#define USART_CR2_LBDL_Pos (5U)
21236#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
21237#define USART_CR2_LBDL USART_CR2_LBDL_Msk
21238#define USART_CR2_LBDIE_Pos (6U)
21239#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
21240#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
21241#define USART_CR2_LBCL_Pos (8U)
21242#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
21243#define USART_CR2_LBCL USART_CR2_LBCL_Msk
21244#define USART_CR2_CPHA_Pos (9U)
21245#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
21246#define USART_CR2_CPHA USART_CR2_CPHA_Msk
21247#define USART_CR2_CPOL_Pos (10U)
21248#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
21249#define USART_CR2_CPOL USART_CR2_CPOL_Msk
21250#define USART_CR2_CLKEN_Pos (11U)
21251#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
21252#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
21253#define USART_CR2_STOP_Pos (12U)
21254#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
21255#define USART_CR2_STOP USART_CR2_STOP_Msk
21256#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
21257#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
21258#define USART_CR2_LINEN_Pos (14U)
21259#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
21260#define USART_CR2_LINEN USART_CR2_LINEN_Msk
21261#define USART_CR2_SWAP_Pos (15U)
21262#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
21263#define USART_CR2_SWAP USART_CR2_SWAP_Msk
21264#define USART_CR2_RXINV_Pos (16U)
21265#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
21266#define USART_CR2_RXINV USART_CR2_RXINV_Msk
21267#define USART_CR2_TXINV_Pos (17U)
21268#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
21269#define USART_CR2_TXINV USART_CR2_TXINV_Msk
21270#define USART_CR2_DATAINV_Pos (18U)
21271#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
21272#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
21273#define USART_CR2_MSBFIRST_Pos (19U)
21274#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
21275#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
21276#define USART_CR2_ABREN_Pos (20U)
21277#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
21278#define USART_CR2_ABREN USART_CR2_ABREN_Msk
21279#define USART_CR2_ABRMODE_Pos (21U)
21280#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
21281#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
21282#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
21283#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
21284#define USART_CR2_RTOEN_Pos (23U)
21285#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
21286#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
21287#define USART_CR2_ADD_Pos (24U)
21288#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
21289#define USART_CR2_ADD USART_CR2_ADD_Msk
21291/****************** Bit definition for USART_CR3 register *******************/
21292#define USART_CR3_EIE_Pos (0U)
21293#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
21294#define USART_CR3_EIE USART_CR3_EIE_Msk
21295#define USART_CR3_IREN_Pos (1U)
21296#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
21297#define USART_CR3_IREN USART_CR3_IREN_Msk
21298#define USART_CR3_IRLP_Pos (2U)
21299#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
21300#define USART_CR3_IRLP USART_CR3_IRLP_Msk
21301#define USART_CR3_HDSEL_Pos (3U)
21302#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
21303#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
21304#define USART_CR3_NACK_Pos (4U)
21305#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
21306#define USART_CR3_NACK USART_CR3_NACK_Msk
21307#define USART_CR3_SCEN_Pos (5U)
21308#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
21309#define USART_CR3_SCEN USART_CR3_SCEN_Msk
21310#define USART_CR3_DMAR_Pos (6U)
21311#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
21312#define USART_CR3_DMAR USART_CR3_DMAR_Msk
21313#define USART_CR3_DMAT_Pos (7U)
21314#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
21315#define USART_CR3_DMAT USART_CR3_DMAT_Msk
21316#define USART_CR3_RTSE_Pos (8U)
21317#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
21318#define USART_CR3_RTSE USART_CR3_RTSE_Msk
21319#define USART_CR3_CTSE_Pos (9U)
21320#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
21321#define USART_CR3_CTSE USART_CR3_CTSE_Msk
21322#define USART_CR3_CTSIE_Pos (10U)
21323#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
21324#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
21325#define USART_CR3_ONEBIT_Pos (11U)
21326#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
21327#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
21328#define USART_CR3_OVRDIS_Pos (12U)
21329#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
21330#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
21331#define USART_CR3_DDRE_Pos (13U)
21332#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
21333#define USART_CR3_DDRE USART_CR3_DDRE_Msk
21334#define USART_CR3_DEM_Pos (14U)
21335#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
21336#define USART_CR3_DEM USART_CR3_DEM_Msk
21337#define USART_CR3_DEP_Pos (15U)
21338#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
21339#define USART_CR3_DEP USART_CR3_DEP_Msk
21340#define USART_CR3_SCARCNT_Pos (17U)
21341#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
21342#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
21343#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
21344#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
21345#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
21346#define USART_CR3_WUS_Pos (20U)
21347#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
21348#define USART_CR3_WUS USART_CR3_WUS_Msk
21349#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
21350#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
21351#define USART_CR3_WUFIE_Pos (22U)
21352#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
21353#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
21354#define USART_CR3_TXFTIE_Pos (23U)
21355#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
21356#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
21357#define USART_CR3_TCBGTIE_Pos (24U)
21358#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
21359#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
21360#define USART_CR3_RXFTCFG_Pos (25U)
21361#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
21362#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
21363#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
21364#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
21365#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
21366#define USART_CR3_RXFTIE_Pos (28U)
21367#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
21368#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
21369#define USART_CR3_TXFTCFG_Pos (29U)
21370#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
21371#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
21372#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
21373#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
21374#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
21376/****************** Bit definition for USART_BRR register *******************/
21377#define USART_BRR_DIV_FRACTION_Pos (0U)
21378#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
21379#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
21380#define USART_BRR_DIV_MANTISSA_Pos (4U)
21381#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
21382#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
21384/****************** Bit definition for USART_GTPR register ******************/
21385#define USART_GTPR_PSC_Pos (0U)
21386#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
21387#define USART_GTPR_PSC USART_GTPR_PSC_Msk
21388#define USART_GTPR_GT_Pos (8U)
21389#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
21390#define USART_GTPR_GT USART_GTPR_GT_Msk
21392/******************* Bit definition for USART_RTOR register *****************/
21393#define USART_RTOR_RTO_Pos (0U)
21394#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
21395#define USART_RTOR_RTO USART_RTOR_RTO_Msk
21396#define USART_RTOR_BLEN_Pos (24U)
21397#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
21398#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
21400/******************* Bit definition for USART_RQR register ******************/
21401#define USART_RQR_ABRRQ_Pos (0U)
21402#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
21403#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
21404#define USART_RQR_SBKRQ_Pos (1U)
21405#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
21406#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
21407#define USART_RQR_MMRQ_Pos (2U)
21408#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
21409#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
21410#define USART_RQR_RXFRQ_Pos (3U)
21411#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
21412#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
21413#define USART_RQR_TXFRQ_Pos (4U)
21414#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
21415#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
21417/******************* Bit definition for USART_ISR register ******************/
21418#define USART_ISR_PE_Pos (0U)
21419#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
21420#define USART_ISR_PE USART_ISR_PE_Msk
21421#define USART_ISR_FE_Pos (1U)
21422#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
21423#define USART_ISR_FE USART_ISR_FE_Msk
21424#define USART_ISR_NE_Pos (2U)
21425#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
21426#define USART_ISR_NE USART_ISR_NE_Msk
21427#define USART_ISR_ORE_Pos (3U)
21428#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
21429#define USART_ISR_ORE USART_ISR_ORE_Msk
21430#define USART_ISR_IDLE_Pos (4U)
21431#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
21432#define USART_ISR_IDLE USART_ISR_IDLE_Msk
21433#define USART_ISR_RXNE_RXFNE_Pos (5U)
21434#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
21435#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk
21436#define USART_ISR_TC_Pos (6U)
21437#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
21438#define USART_ISR_TC USART_ISR_TC_Msk
21439#define USART_ISR_TXE_TXFNF_Pos (7U)
21440#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)
21441#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk
21442#define USART_ISR_LBDF_Pos (8U)
21443#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
21444#define USART_ISR_LBDF USART_ISR_LBDF_Msk
21445#define USART_ISR_CTSIF_Pos (9U)
21446#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
21447#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
21448#define USART_ISR_CTS_Pos (10U)
21449#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
21450#define USART_ISR_CTS USART_ISR_CTS_Msk
21451#define USART_ISR_RTOF_Pos (11U)
21452#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
21453#define USART_ISR_RTOF USART_ISR_RTOF_Msk
21454#define USART_ISR_EOBF_Pos (12U)
21455#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
21456#define USART_ISR_EOBF USART_ISR_EOBF_Msk
21457#define USART_ISR_UDR_Pos (13U)
21458#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
21459#define USART_ISR_UDR USART_ISR_UDR_Msk
21460#define USART_ISR_ABRE_Pos (14U)
21461#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
21462#define USART_ISR_ABRE USART_ISR_ABRE_Msk
21463#define USART_ISR_ABRF_Pos (15U)
21464#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
21465#define USART_ISR_ABRF USART_ISR_ABRF_Msk
21466#define USART_ISR_BUSY_Pos (16U)
21467#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
21468#define USART_ISR_BUSY USART_ISR_BUSY_Msk
21469#define USART_ISR_CMF_Pos (17U)
21470#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
21471#define USART_ISR_CMF USART_ISR_CMF_Msk
21472#define USART_ISR_SBKF_Pos (18U)
21473#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
21474#define USART_ISR_SBKF USART_ISR_SBKF_Msk
21475#define USART_ISR_RWU_Pos (19U)
21476#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
21477#define USART_ISR_RWU USART_ISR_RWU_Msk
21478#define USART_ISR_WUF_Pos (20U)
21479#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
21480#define USART_ISR_WUF USART_ISR_WUF_Msk
21481#define USART_ISR_TEACK_Pos (21U)
21482#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
21483#define USART_ISR_TEACK USART_ISR_TEACK_Msk
21484#define USART_ISR_REACK_Pos (22U)
21485#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
21486#define USART_ISR_REACK USART_ISR_REACK_Msk
21487#define USART_ISR_TXFE_Pos (23U)
21488#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
21489#define USART_ISR_TXFE USART_ISR_TXFE_Msk
21490#define USART_ISR_RXFF_Pos (24U)
21491#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
21492#define USART_ISR_RXFF USART_ISR_RXFF_Msk
21493#define USART_ISR_TCBGT_Pos (25U)
21494#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
21495#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
21496#define USART_ISR_RXFT_Pos (26U)
21497#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
21498#define USART_ISR_RXFT USART_ISR_RXFT_Msk
21499#define USART_ISR_TXFT_Pos (27U)
21500#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
21501#define USART_ISR_TXFT USART_ISR_TXFT_Msk
21503/******************* Bit definition for USART_ICR register ******************/
21504#define USART_ICR_PECF_Pos (0U)
21505#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
21506#define USART_ICR_PECF USART_ICR_PECF_Msk
21507#define USART_ICR_FECF_Pos (1U)
21508#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
21509#define USART_ICR_FECF USART_ICR_FECF_Msk
21510#define USART_ICR_NECF_Pos (2U)
21511#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
21512#define USART_ICR_NECF USART_ICR_NECF_Msk
21513#define USART_ICR_ORECF_Pos (3U)
21514#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
21515#define USART_ICR_ORECF USART_ICR_ORECF_Msk
21516#define USART_ICR_IDLECF_Pos (4U)
21517#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
21518#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
21519#define USART_ICR_TXFECF_Pos (5U)
21520#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
21521#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
21522#define USART_ICR_TCCF_Pos (6U)
21523#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
21524#define USART_ICR_TCCF USART_ICR_TCCF_Msk
21525#define USART_ICR_TCBGTCF_Pos (7U)
21526#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
21527#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
21528#define USART_ICR_LBDCF_Pos (8U)
21529#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
21530#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
21531#define USART_ICR_CTSCF_Pos (9U)
21532#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
21533#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
21534#define USART_ICR_RTOCF_Pos (11U)
21535#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
21536#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
21537#define USART_ICR_EOBCF_Pos (12U)
21538#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
21539#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
21540#define USART_ICR_UDRCF_Pos (13U)
21541#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
21542#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
21543#define USART_ICR_CMCF_Pos (17U)
21544#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
21545#define USART_ICR_CMCF USART_ICR_CMCF_Msk
21546#define USART_ICR_WUCF_Pos (20U)
21547#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
21548#define USART_ICR_WUCF USART_ICR_WUCF_Msk
21550/******************* Bit definition for USART_RDR register ******************/
21551#define USART_RDR_RDR_Pos (0U)
21552#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
21553#define USART_RDR_RDR USART_RDR_RDR_Msk
21555/******************* Bit definition for USART_TDR register ******************/
21556#define USART_TDR_TDR_Pos (0U)
21557#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
21558#define USART_TDR_TDR USART_TDR_TDR_Msk
21560/******************* Bit definition for USART_PRESC register ******************/
21561#define USART_PRESC_PRESCALER_Pos (0U)
21562#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
21563#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
21564#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
21565#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
21566#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
21567#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
21569/******************************************************************************/
21570/* */
21571/* Single Wire Protocol Master Interface (SWPMI) */
21572/* */
21573/******************************************************************************/
21574
21575/******************* Bit definition for SWPMI_CR register ********************/
21576#define SWPMI_CR_RXDMA_Pos (0U)
21577#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
21578#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
21579#define SWPMI_CR_TXDMA_Pos (1U)
21580#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
21581#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
21582#define SWPMI_CR_RXMODE_Pos (2U)
21583#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
21584#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
21585#define SWPMI_CR_TXMODE_Pos (3U)
21586#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
21587#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
21588#define SWPMI_CR_LPBK_Pos (4U)
21589#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
21590#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
21591#define SWPMI_CR_SWPACT_Pos (5U)
21592#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
21593#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
21594#define SWPMI_CR_DEACT_Pos (10U)
21595#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
21596#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
21597#define SWPMI_CR_SWPEN_Pos (11U)
21598#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos)
21599#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk
21601/******************* Bit definition for SWPMI_BRR register ********************/
21602#define SWPMI_BRR_BR_Pos (0U)
21603#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos)
21604#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
21606/******************* Bit definition for SWPMI_ISR register ********************/
21607#define SWPMI_ISR_RXBFF_Pos (0U)
21608#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
21609#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
21610#define SWPMI_ISR_TXBEF_Pos (1U)
21611#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
21612#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
21613#define SWPMI_ISR_RXBERF_Pos (2U)
21614#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
21615#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
21616#define SWPMI_ISR_RXOVRF_Pos (3U)
21617#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
21618#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
21619#define SWPMI_ISR_TXUNRF_Pos (4U)
21620#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
21621#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
21622#define SWPMI_ISR_RXNE_Pos (5U)
21623#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
21624#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
21625#define SWPMI_ISR_TXE_Pos (6U)
21626#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
21627#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
21628#define SWPMI_ISR_TCF_Pos (7U)
21629#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
21630#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
21631#define SWPMI_ISR_SRF_Pos (8U)
21632#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
21633#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
21634#define SWPMI_ISR_SUSP_Pos (9U)
21635#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
21636#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
21637#define SWPMI_ISR_DEACTF_Pos (10U)
21638#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
21639#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
21640#define SWPMI_ISR_RDYF_Pos (11U)
21641#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos)
21642#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk
21644/******************* Bit definition for SWPMI_ICR register ********************/
21645#define SWPMI_ICR_CRXBFF_Pos (0U)
21646#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
21647#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
21648#define SWPMI_ICR_CTXBEF_Pos (1U)
21649#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
21650#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
21651#define SWPMI_ICR_CRXBERF_Pos (2U)
21652#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
21653#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
21654#define SWPMI_ICR_CRXOVRF_Pos (3U)
21655#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
21656#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
21657#define SWPMI_ICR_CTXUNRF_Pos (4U)
21658#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
21659#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
21660#define SWPMI_ICR_CTCF_Pos (7U)
21661#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
21662#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
21663#define SWPMI_ICR_CSRF_Pos (8U)
21664#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
21665#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
21666#define SWPMI_ICR_CRDYF_Pos (11U)
21667#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos)
21668#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk
21670/******************* Bit definition for SWPMI_IER register ********************/
21671#define SWPMI_IER_RXBFIE_Pos (0U)
21672#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
21673#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
21674#define SWPMI_IER_TXBEIE_Pos (1U)
21675#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
21676#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
21677#define SWPMI_IER_RXBERIE_Pos (2U)
21678#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
21679#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
21680#define SWPMI_IER_RXOVRIE_Pos (3U)
21681#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
21682#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
21683#define SWPMI_IER_TXUNRIE_Pos (4U)
21684#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
21685#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
21686#define SWPMI_IER_RIE_Pos (5U)
21687#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
21688#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
21689#define SWPMI_IER_TIE_Pos (6U)
21690#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
21691#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
21692#define SWPMI_IER_TCIE_Pos (7U)
21693#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
21694#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
21695#define SWPMI_IER_SRIE_Pos (8U)
21696#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
21697#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
21698#define SWPMI_IER_RDYIE_Pos (11U)
21699#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos)
21700#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk
21702/******************* Bit definition for SWPMI_RFL register ********************/
21703#define SWPMI_RFL_RFL_Pos (0U)
21704#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
21705#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
21706#define SWPMI_RFL_RFL_0_1 (0x00000003U)
21708/******************* Bit definition for SWPMI_TDR register ********************/
21709#define SWPMI_TDR_TD_Pos (0U)
21710#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
21711#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
21713/******************* Bit definition for SWPMI_RDR register ********************/
21714#define SWPMI_RDR_RD_Pos (0U)
21715#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
21716#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
21719/******************* Bit definition for SWPMI_OR register ********************/
21720#define SWPMI_OR_TBYP_Pos (0U)
21721#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
21722#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
21723#define SWPMI_OR_CLASS_Pos (1U)
21724#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
21725#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
21727/******************************************************************************/
21728/* */
21729/* Window WATCHDOG */
21730/* */
21731/******************************************************************************/
21732/******************* Bit definition for WWDG_CR register ********************/
21733#define WWDG_CR_T_Pos (0U)
21734#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
21735#define WWDG_CR_T WWDG_CR_T_Msk
21736#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
21737#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
21738#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
21739#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
21740#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
21741#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
21742#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
21744#define WWDG_CR_WDGA_Pos (7U)
21745#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
21746#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
21748/******************* Bit definition for WWDG_CFR register *******************/
21749#define WWDG_CFR_W_Pos (0U)
21750#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
21751#define WWDG_CFR_W WWDG_CFR_W_Msk
21752#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
21753#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
21754#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
21755#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
21756#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
21757#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
21758#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
21760#define WWDG_CFR_EWI_Pos (9U)
21761#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
21762#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
21764#define WWDG_CFR_WDGTB_Pos (11U)
21765#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
21766#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
21767#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
21768#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
21769#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
21771/******************* Bit definition for WWDG_SR register ********************/
21772#define WWDG_SR_EWIF_Pos (0U)
21773#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
21774#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
21777/******************************************************************************/
21778/* */
21779/* DBG */
21780/* */
21781/******************************************************************************/
21782/********************************* DEVICE ID ********************************/
21783#define STM32H7_DEV_ID 0x450UL
21784
21785/******************** Bit definition for DBGMCU_IDCODE register *************/
21786#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
21787#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
21788#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
21789#define DBGMCU_IDCODE_REV_ID_Pos (16U)
21790#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
21791#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
21792
21793/******************** Bit definition for DBGMCU_CR register *****************/
21794#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
21795#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos)
21796#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
21797#define DBGMCU_CR_DBG_STOPD1_Pos (1U)
21798#define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)
21799#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
21800#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
21801#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos)
21802#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
21803#define DBGMCU_CR_DBG_SLEEPD2_Pos (3U)
21804#define DBGMCU_CR_DBG_SLEEPD2_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos)
21805#define DBGMCU_CR_DBG_SLEEPD2 DBGMCU_CR_DBG_SLEEPD2_Msk
21806#define DBGMCU_CR_DBG_STOPD2_Pos (4U)
21807#define DBGMCU_CR_DBG_STOPD2_Msk (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)
21808#define DBGMCU_CR_DBG_STOPD2 DBGMCU_CR_DBG_STOPD2_Msk
21809#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
21810#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos)
21811#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
21812#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
21813#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
21814#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
21815#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
21816#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)
21817#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
21818#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
21819#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)
21820#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
21821#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
21822#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
21823#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
21824
21825/******************** Bit definition for APB3FZ1 register ************/
21826#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
21827#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
21828#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
21829/******************** Bit definition for APB3FZ2 register ************/
21830#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos (6U)
21831#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos)
21832#define DBGMCU_APB3FZ2_DBG_WWDG1 DBGMCU_APB3FZ2_DBG_WWDG1_Msk
21833/******************** Bit definition for APB1LFZ1 register ************/
21834#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
21835#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
21836#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
21837#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
21838#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
21839#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
21840#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
21841#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
21842#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
21843#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
21844#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
21845#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
21846#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
21847#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
21848#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
21849#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
21850#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
21851#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
21852#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
21853#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
21854#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
21855#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
21856#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
21857#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
21858#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
21859#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
21860#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
21861#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
21862#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
21863#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
21864#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos (11U)
21865#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos)
21866#define DBGMCU_APB1LFZ1_DBG_WWDG2 DBGMCU_APB1LFZ1_DBG_WWDG2_Msk
21867#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
21868#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
21869#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
21870#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
21871#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
21872#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
21873#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
21874#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
21875#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
21876
21877/******************** Bit definition for APB1LFZ2 register ************/
21878#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos (0U)
21879#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos)
21880#define DBGMCU_APB1LFZ2_DBG_TIM2 DBGMCU_APB1LFZ2_DBG_TIM2_Msk
21881#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos (1U)
21882#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos)
21883#define DBGMCU_APB1LFZ2_DBG_TIM3 DBGMCU_APB1LFZ2_DBG_TIM3_Msk
21884#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos (2U)
21885#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos)
21886#define DBGMCU_APB1LFZ2_DBG_TIM4 DBGMCU_APB1LFZ2_DBG_TIM4_Msk
21887#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos (3U)
21888#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos)
21889#define DBGMCU_APB1LFZ2_DBG_TIM5 DBGMCU_APB1LFZ2_DBG_TIM5_Msk
21890#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos (4U)
21891#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos)
21892#define DBGMCU_APB1LFZ2_DBG_TIM6 DBGMCU_APB1LFZ2_DBG_TIM6_Msk
21893#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos (5U)
21894#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos)
21895#define DBGMCU_APB1LFZ2_DBG_TIM7 DBGMCU_APB1LFZ2_DBG_TIM7_Msk
21896#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos (6U)
21897#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos)
21898#define DBGMCU_APB1LFZ2_DBG_TIM12 DBGMCU_APB1LFZ2_DBG_TIM12_Msk
21899#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos (7U)
21900#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos)
21901#define DBGMCU_APB1LFZ2_DBG_TIM13 DBGMCU_APB1LFZ2_DBG_TIM13_Msk
21902#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos (8U)
21903#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos)
21904#define DBGMCU_APB1LFZ2_DBG_TIM14 DBGMCU_APB1LFZ2_DBG_TIM14_Msk
21905#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos (9U)
21906#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos)
21907#define DBGMCU_APB1LFZ2_DBG_LPTIM1 DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk
21908#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos (11U)
21909#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos)
21910#define DBGMCU_APB1LFZ2_DBG_WWDG2 DBGMCU_APB1LFZ2_DBG_WWDG2_Msk
21911#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos (21U)
21912#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos)
21913#define DBGMCU_APB1LFZ2_DBG_I2C1 DBGMCU_APB1LFZ2_DBG_I2C1_Msk
21914#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos (22U)
21915#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos)
21916#define DBGMCU_APB1LFZ2_DBG_I2C2 DBGMCU_APB1LFZ2_DBG_I2C2_Msk
21917#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos (23U)
21918#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos)
21919#define DBGMCU_APB1LFZ2_DBG_I2C3 DBGMCU_APB1LFZ2_DBG_I2C3_Msk
21920/******************** Bit definition for APB1HFZ1 register ************/
21921#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
21922#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos)
21923#define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
21924/******************** Bit definition for APB1HFZ2 register ************/
21925#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos (8U)
21926#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos)
21927#define DBGMCU_APB1HFZ2_DBG_FDCAN DBGMCU_APB1HFZ2_DBG_FDCAN_Msk
21928
21929/******************** Bit definition for APB2FZ1 register ************/
21930#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
21931#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
21932#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
21933#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
21934#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
21935#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
21936#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
21937#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
21938#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
21939#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
21940#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
21941#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
21942#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
21943#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
21944#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
21945#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
21946#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos)
21947#define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
21948
21949/******************** Bit definition for APB2FZ2 register ************/
21950#define DBGMCU_APB2FZ2_DBG_TIM1_Pos (0U)
21951#define DBGMCU_APB2FZ2_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos)
21952#define DBGMCU_APB2FZ2_DBG_TIM1 DBGMCU_APB2FZ2_DBG_TIM1_Msk
21953#define DBGMCU_APB2FZ2_DBG_TIM8_Pos (1U)
21954#define DBGMCU_APB2FZ2_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos)
21955#define DBGMCU_APB2FZ2_DBG_TIM8 DBGMCU_APB2FZ2_DBG_TIM8_Msk
21956#define DBGMCU_APB2FZ2_DBG_TIM15_Pos (16U)
21957#define DBGMCU_APB2FZ2_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos)
21958#define DBGMCU_APB2FZ2_DBG_TIM15 DBGMCU_APB2FZ2_DBG_TIM15_Msk
21959#define DBGMCU_APB2FZ2_DBG_TIM16_Pos (17U)
21960#define DBGMCU_APB2FZ2_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos)
21961#define DBGMCU_APB2FZ2_DBG_TIM16 DBGMCU_APB2FZ2_DBG_TIM16_Msk
21962#define DBGMCU_APB2FZ2_DBG_TIM17_Pos (18U)
21963#define DBGMCU_APB2FZ2_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos)
21964#define DBGMCU_APB2FZ2_DBG_TIM17 DBGMCU_APB2FZ2_DBG_TIM17_Msk
21965#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos (29U)
21966#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos)
21967#define DBGMCU_APB2FZ2_DBG_HRTIM DBGMCU_APB2FZ2_DBG_HRTIM_Msk
21968/******************** Bit definition for APB4FZ1 register ************/
21969#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
21970#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
21971#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
21972#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
21973#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
21974#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
21975#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
21976#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
21977#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
21978#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
21979#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos)
21980#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
21981#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
21982#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos)
21983#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
21984#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
21985#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
21986#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
21987#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
21988#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
21989#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
21990#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos (19U)
21991#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos)
21992#define DBGMCU_APB4FZ1_DBG_IWDG2 DBGMCU_APB4FZ1_DBG_IWDG2_Msk
21993/******************** Bit definition for APB4FZ2 register ************/
21994#define DBGMCU_APB4FZ2_DBG_I2C4_Pos (7U)
21995#define DBGMCU_APB4FZ2_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos)
21996#define DBGMCU_APB4FZ2_DBG_I2C4 DBGMCU_APB4FZ2_DBG_I2C4_Msk
21997#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos (9U)
21998#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos)
21999#define DBGMCU_APB4FZ2_DBG_LPTIM2 DBGMCU_APB4FZ2_DBG_LPTIM2_Msk
22000#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos (10U)
22001#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos)
22002#define DBGMCU_APB4FZ2_DBG_LPTIM3 DBGMCU_APB4FZ2_DBG_LPTIM3_Msk
22003#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos (11U)
22004#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos)
22005#define DBGMCU_APB4FZ2_DBG_LPTIM4 DBGMCU_APB4FZ2_DBG_LPTIM4_Msk
22006#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos (12U)
22007#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos)
22008#define DBGMCU_APB4FZ2_DBG_LPTIM5 DBGMCU_APB4FZ2_DBG_LPTIM5_Msk
22009#define DBGMCU_APB4FZ2_DBG_RTC_Pos (16U)
22010#define DBGMCU_APB4FZ2_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos)
22011#define DBGMCU_APB4FZ2_DBG_RTC DBGMCU_APB4FZ2_DBG_RTC_Msk
22012#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos (18U)
22013#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos)
22014#define DBGMCU_APB4FZ2_DBG_IWDG1 DBGMCU_APB4FZ2_DBG_IWDG1_Msk
22015#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos (19U)
22016#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos)
22017#define DBGMCU_APB4FZ2_DBG_IWDG2 DBGMCU_APB4FZ2_DBG_IWDG2_Msk
22018/******************************************************************************/
22019/* */
22020/* High Resolution Timer (HRTIM) */
22021/* */
22022/******************************************************************************/
22023/******************** Master Timer control register ***************************/
22024#define HRTIM_MCR_CK_PSC_Pos (0U)
22025#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos)
22026#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk
22027#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos)
22028#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos)
22029#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos)
22031#define HRTIM_MCR_CONT_Pos (3U)
22032#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos)
22033#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk
22034#define HRTIM_MCR_RETRIG_Pos (4U)
22035#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos)
22036#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk
22037#define HRTIM_MCR_HALF_Pos (5U)
22038#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos)
22039#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk
22041#define HRTIM_MCR_SYNC_IN_Pos (8U)
22042#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos)
22043#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk
22044#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos)
22045#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos)
22046#define HRTIM_MCR_SYNCRSTM_Pos (10U)
22047#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)
22048#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk
22049#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
22050#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)
22051#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk
22052#define HRTIM_MCR_SYNC_OUT_Pos (12U)
22053#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)
22054#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk
22055#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)
22056#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)
22057#define HRTIM_MCR_SYNC_SRC_Pos (14U)
22058#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)
22059#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk
22060#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)
22061#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)
22063#define HRTIM_MCR_MCEN_Pos (16U)
22064#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos)
22065#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk
22066#define HRTIM_MCR_TACEN_Pos (17U)
22067#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos)
22068#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk
22069#define HRTIM_MCR_TBCEN_Pos (18U)
22070#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos)
22071#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk
22072#define HRTIM_MCR_TCCEN_Pos (19U)
22073#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos)
22074#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk
22075#define HRTIM_MCR_TDCEN_Pos (20U)
22076#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos)
22077#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk
22078#define HRTIM_MCR_TECEN_Pos (21U)
22079#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos)
22080#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk
22082#define HRTIM_MCR_DACSYNC_Pos (25U)
22083#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos)
22084#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk
22085#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos)
22086#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos)
22088#define HRTIM_MCR_PREEN_Pos (27U)
22089#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos)
22090#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk
22091#define HRTIM_MCR_MREPU_Pos (29U)
22092#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos)
22093#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk
22095#define HRTIM_MCR_BRSTDMA_Pos (30U)
22096#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos)
22097#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk
22098#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos)
22099#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos)
22101/******************** Master Timer Interrupt status register ******************/
22102#define HRTIM_MISR_MCMP1_Pos (0U)
22103#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos)
22104#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk
22105#define HRTIM_MISR_MCMP2_Pos (1U)
22106#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos)
22107#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk
22108#define HRTIM_MISR_MCMP3_Pos (2U)
22109#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos)
22110#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk
22111#define HRTIM_MISR_MCMP4_Pos (3U)
22112#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos)
22113#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk
22114#define HRTIM_MISR_MREP_Pos (4U)
22115#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos)
22116#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk
22117#define HRTIM_MISR_SYNC_Pos (5U)
22118#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos)
22119#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk
22120#define HRTIM_MISR_MUPD_Pos (6U)
22121#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos)
22122#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk
22124/******************** Master Timer Interrupt clear register *******************/
22125#define HRTIM_MICR_MCMP1_Pos (0U)
22126#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos)
22127#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk
22128#define HRTIM_MICR_MCMP2_Pos (1U)
22129#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos)
22130#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk
22131#define HRTIM_MICR_MCMP3_Pos (2U)
22132#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos)
22133#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk
22134#define HRTIM_MICR_MCMP4_Pos (3U)
22135#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos)
22136#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk
22137#define HRTIM_MICR_MREP_Pos (4U)
22138#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos)
22139#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk
22140#define HRTIM_MICR_SYNC_Pos (5U)
22141#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos)
22142#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk
22143#define HRTIM_MICR_MUPD_Pos (6U)
22144#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos)
22145#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk
22147/******************** Master Timer DMA/Interrupt enable register **************/
22148#define HRTIM_MDIER_MCMP1IE_Pos (0U)
22149#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)
22150#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk
22151#define HRTIM_MDIER_MCMP2IE_Pos (1U)
22152#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)
22153#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk
22154#define HRTIM_MDIER_MCMP3IE_Pos (2U)
22155#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)
22156#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk
22157#define HRTIM_MDIER_MCMP4IE_Pos (3U)
22158#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)
22159#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk
22160#define HRTIM_MDIER_MREPIE_Pos (4U)
22161#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos)
22162#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk
22163#define HRTIM_MDIER_SYNCIE_Pos (5U)
22164#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos)
22165#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk
22166#define HRTIM_MDIER_MUPDIE_Pos (6U)
22167#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos)
22168#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk
22170#define HRTIM_MDIER_MCMP1DE_Pos (16U)
22171#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)
22172#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk
22173#define HRTIM_MDIER_MCMP2DE_Pos (17U)
22174#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)
22175#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk
22176#define HRTIM_MDIER_MCMP3DE_Pos (18U)
22177#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)
22178#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk
22179#define HRTIM_MDIER_MCMP4DE_Pos (19U)
22180#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)
22181#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk
22182#define HRTIM_MDIER_MREPDE_Pos (20U)
22183#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos)
22184#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk
22185#define HRTIM_MDIER_SYNCDE_Pos (21U)
22186#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos)
22187#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk
22188#define HRTIM_MDIER_MUPDDE_Pos (22U)
22189#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos)
22190#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk
22192/******************* Bit definition for HRTIM_MCNTR register ****************/
22193#define HRTIM_MCNTR_MCNTR_Pos (0U)
22194#define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)
22195#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk
22197/******************* Bit definition for HRTIM_MPER register *****************/
22198#define HRTIM_MPER_MPER_Pos (0U)
22199#define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos)
22200#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk
22202/******************* Bit definition for HRTIM_MREP register *****************/
22203#define HRTIM_MREP_MREP_Pos (0U)
22204#define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos)
22205#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk
22207/******************* Bit definition for HRTIM_MCMP1R register *****************/
22208#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
22209#define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)
22210#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk
22212/******************* Bit definition for HRTIM_MCMP2R register *****************/
22213#define HRTIM_MCMP1R_MCMP2R_Pos (0U)
22214#define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)
22215#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk
22217/******************* Bit definition for HRTIM_MCMP3R register *****************/
22218#define HRTIM_MCMP1R_MCMP3R_Pos (0U)
22219#define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)
22220#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk
22222/******************* Bit definition for HRTIM_MCMP4R register *****************/
22223#define HRTIM_MCMP1R_MCMP4R_Pos (0U)
22224#define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)
22225#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk
22227/******************** Slave control register **********************************/
22228#define HRTIM_TIMCR_CK_PSC_Pos (0U)
22229#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)
22230#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk
22231#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)
22232#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)
22233#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)
22235#define HRTIM_TIMCR_CONT_Pos (3U)
22236#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos)
22237#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk
22238#define HRTIM_TIMCR_RETRIG_Pos (4U)
22239#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos)
22240#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk
22241#define HRTIM_TIMCR_HALF_Pos (5U)
22242#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos)
22243#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk
22244#define HRTIM_TIMCR_PSHPLL_Pos (6U)
22245#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)
22246#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk
22248#define HRTIM_TIMCR_SYNCRST_Pos (10U)
22249#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)
22250#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk
22251#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
22252#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)
22253#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk
22255#define HRTIM_TIMCR_DELCMP2_Pos (12U)
22256#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)
22257#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk
22258#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)
22259#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)
22260#define HRTIM_TIMCR_DELCMP4_Pos (14U)
22261#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)
22262#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk
22263#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)
22264#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)
22266#define HRTIM_TIMCR_TREPU_Pos (17U)
22267#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos)
22268#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk
22269#define HRTIM_TIMCR_TRSTU_Pos (18U)
22270#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos)
22271#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk
22272#define HRTIM_TIMCR_TAU_Pos (19U)
22273#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos)
22274#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk
22275#define HRTIM_TIMCR_TBU_Pos (20U)
22276#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos)
22277#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk
22278#define HRTIM_TIMCR_TCU_Pos (21U)
22279#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos)
22280#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk
22281#define HRTIM_TIMCR_TDU_Pos (22U)
22282#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos)
22283#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk
22284#define HRTIM_TIMCR_TEU_Pos (23U)
22285#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos)
22286#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk
22287#define HRTIM_TIMCR_MSTU_Pos (24U)
22288#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos)
22289#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk
22291#define HRTIM_TIMCR_DACSYNC_Pos (25U)
22292#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)
22293#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk
22294#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)
22295#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)
22296#define HRTIM_TIMCR_PREEN_Pos (27U)
22297#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos)
22298#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk
22300#define HRTIM_TIMCR_UPDGAT_Pos (28U)
22301#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)
22302#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk
22303#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)
22304#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)
22305#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)
22306#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)
22308/******************** Slave Interrupt status register **************************/
22309#define HRTIM_TIMISR_CMP1_Pos (0U)
22310#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos)
22311#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk
22312#define HRTIM_TIMISR_CMP2_Pos (1U)
22313#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos)
22314#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk
22315#define HRTIM_TIMISR_CMP3_Pos (2U)
22316#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos)
22317#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk
22318#define HRTIM_TIMISR_CMP4_Pos (3U)
22319#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos)
22320#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk
22321#define HRTIM_TIMISR_REP_Pos (4U)
22322#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos)
22323#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk
22324#define HRTIM_TIMISR_UPD_Pos (6U)
22325#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos)
22326#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk
22327#define HRTIM_TIMISR_CPT1_Pos (7U)
22328#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos)
22329#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk
22330#define HRTIM_TIMISR_CPT2_Pos (8U)
22331#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos)
22332#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk
22333#define HRTIM_TIMISR_SET1_Pos (9U)
22334#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos)
22335#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk
22336#define HRTIM_TIMISR_RST1_Pos (10U)
22337#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos)
22338#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk
22339#define HRTIM_TIMISR_SET2_Pos (11U)
22340#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos)
22341#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk
22342#define HRTIM_TIMISR_RST2_Pos (12U)
22343#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos)
22344#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk
22345#define HRTIM_TIMISR_RST_Pos (13U)
22346#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos)
22347#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk
22348#define HRTIM_TIMISR_DLYPRT_Pos (14U)
22349#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)
22350#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk
22351#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
22352#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)
22353#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk
22354#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
22355#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)
22356#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk
22357#define HRTIM_TIMISR_O1STAT_Pos (18U)
22358#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos)
22359#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk
22360#define HRTIM_TIMISR_O2STAT_Pos (19U)
22361#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos)
22362#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk
22363#define HRTIM_TIMISR_O1CPY_Pos (20U)
22364#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos)
22365#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk
22366#define HRTIM_TIMISR_O2CPY_Pos (21U)
22367#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos)
22368#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk
22370/******************** Slave Interrupt clear register **************************/
22371#define HRTIM_TIMICR_CMP1C_Pos (0U)
22372#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos)
22373#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk
22374#define HRTIM_TIMICR_CMP2C_Pos (1U)
22375#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos)
22376#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk
22377#define HRTIM_TIMICR_CMP3C_Pos (2U)
22378#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos)
22379#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk
22380#define HRTIM_TIMICR_CMP4C_Pos (3U)
22381#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos)
22382#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk
22383#define HRTIM_TIMICR_REPC_Pos (4U)
22384#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos)
22385#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk
22386#define HRTIM_TIMICR_UPDC_Pos (6U)
22387#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos)
22388#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk
22389#define HRTIM_TIMICR_CPT1C_Pos (7U)
22390#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos)
22391#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk
22392#define HRTIM_TIMICR_CPT2C_Pos (8U)
22393#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos)
22394#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk
22395#define HRTIM_TIMICR_SET1C_Pos (9U)
22396#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos)
22397#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk
22398#define HRTIM_TIMICR_RST1C_Pos (10U)
22399#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos)
22400#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk
22401#define HRTIM_TIMICR_SET2C_Pos (11U)
22402#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos)
22403#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk
22404#define HRTIM_TIMICR_RST2C_Pos (12U)
22405#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos)
22406#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk
22407#define HRTIM_TIMICR_RSTC_Pos (13U)
22408#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos)
22409#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk
22410#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
22411#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)
22412#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk
22414/******************** Slave DMA/Interrupt enable register *********************/
22415#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
22416#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)
22417#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk
22418#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
22419#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)
22420#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk
22421#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
22422#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)
22423#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk
22424#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
22425#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)
22426#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk
22427#define HRTIM_TIMDIER_REPIE_Pos (4U)
22428#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos)
22429#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk
22430#define HRTIM_TIMDIER_UPDIE_Pos (6U)
22431#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)
22432#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk
22433#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
22434#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)
22435#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk
22436#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
22437#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)
22438#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk
22439#define HRTIM_TIMDIER_SET1IE_Pos (9U)
22440#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)
22441#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk
22442#define HRTIM_TIMDIER_RST1IE_Pos (10U)
22443#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)
22444#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk
22445#define HRTIM_TIMDIER_SET2IE_Pos (11U)
22446#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)
22447#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk
22448#define HRTIM_TIMDIER_RST2IE_Pos (12U)
22449#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)
22450#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk
22451#define HRTIM_TIMDIER_RSTIE_Pos (13U)
22452#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)
22453#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk
22454#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
22455#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)
22456#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk
22458#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
22459#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)
22460#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk
22461#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
22462#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)
22463#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk
22464#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
22465#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)
22466#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk
22467#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
22468#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)
22469#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk
22470#define HRTIM_TIMDIER_REPDE_Pos (20U)
22471#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos)
22472#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk
22473#define HRTIM_TIMDIER_UPDDE_Pos (22U)
22474#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)
22475#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk
22476#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
22477#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)
22478#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk
22479#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
22480#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)
22481#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk
22482#define HRTIM_TIMDIER_SET1DE_Pos (25U)
22483#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)
22484#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk
22485#define HRTIM_TIMDIER_RST1DE_Pos (26U)
22486#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)
22487#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk
22488#define HRTIM_TIMDIER_SET2DE_Pos (27U)
22489#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)
22490#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk
22491#define HRTIM_TIMDIER_RST2DE_Pos (28U)
22492#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)
22493#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk
22494#define HRTIM_TIMDIER_RSTDE_Pos (29U)
22495#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)
22496#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk
22497#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
22498#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)
22499#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk
22501/****************** Bit definition for HRTIM_CNTR register ****************/
22502#define HRTIM_CNTR_CNTR_Pos (0U)
22503#define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)
22504#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk
22506/******************* Bit definition for HRTIM_PER register *****************/
22507#define HRTIM_PER_PER_Pos (0U)
22508#define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos)
22509#define HRTIM_PER_PER HRTIM_PER_PER_Msk
22511/******************* Bit definition for HRTIM_REP register *****************/
22512#define HRTIM_REP_REP_Pos (0U)
22513#define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos)
22514#define HRTIM_REP_REP HRTIM_REP_REP_Msk
22516/******************* Bit definition for HRTIM_CMP1R register *****************/
22517#define HRTIM_CMP1R_CMP1R_Pos (0U)
22518#define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)
22519#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk
22521/******************* Bit definition for HRTIM_CMP1CR register *****************/
22522#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
22523#define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)
22524#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk
22526/******************* Bit definition for HRTIM_CMP2R register *****************/
22527#define HRTIM_CMP2R_CMP2R_Pos (0U)
22528#define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)
22529#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk
22531/******************* Bit definition for HRTIM_CMP3R register *****************/
22532#define HRTIM_CMP3R_CMP3R_Pos (0U)
22533#define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)
22534#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk
22536/******************* Bit definition for HRTIM_CMP4R register *****************/
22537#define HRTIM_CMP4R_CMP4R_Pos (0U)
22538#define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)
22539#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk
22541/******************* Bit definition for HRTIM_CPT1R register ****************/
22542#define HRTIM_CPT1R_CPT1R_Pos (0U)
22543#define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)
22544#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk
22546/******************* Bit definition for HRTIM_CPT2R register ****************/
22547#define HRTIM_CPT2R_CPT2R_Pos (0U)
22548#define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)
22549#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk
22551/******************** Bit definition for Slave Deadtime register **************/
22552#define HRTIM_DTR_DTR_Pos (0U)
22553#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos)
22554#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk
22555#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos)
22556#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos)
22557#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos)
22558#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos)
22559#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos)
22560#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos)
22561#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos)
22562#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos)
22563#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos)
22564#define HRTIM_DTR_SDTR_Pos (9U)
22565#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos)
22566#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk
22567#define HRTIM_DTR_DTPRSC_Pos (10U)
22568#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos)
22569#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk
22570#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos)
22571#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos)
22572#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos)
22573#define HRTIM_DTR_DTRSLK_Pos (14U)
22574#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos)
22575#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk
22576#define HRTIM_DTR_DTRLK_Pos (15U)
22577#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos)
22578#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk
22579#define HRTIM_DTR_DTF_Pos (16U)
22580#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos)
22581#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk
22582#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos)
22583#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos)
22584#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos)
22585#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos)
22586#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos)
22587#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos)
22588#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos)
22589#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos)
22590#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos)
22591#define HRTIM_DTR_SDTF_Pos (25U)
22592#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos)
22593#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk
22594#define HRTIM_DTR_DTFSLK_Pos (30U)
22595#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos)
22596#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk
22597#define HRTIM_DTR_DTFLK_Pos (31U)
22598#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos)
22599#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk
22601/**** Bit definition for Slave Output 1 set register **************************/
22602#define HRTIM_SET1R_SST_Pos (0U)
22603#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos)
22604#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk
22605#define HRTIM_SET1R_RESYNC_Pos (1U)
22606#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos)
22607#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk
22608#define HRTIM_SET1R_PER_Pos (2U)
22609#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos)
22610#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk
22611#define HRTIM_SET1R_CMP1_Pos (3U)
22612#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos)
22613#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk
22614#define HRTIM_SET1R_CMP2_Pos (4U)
22615#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos)
22616#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk
22617#define HRTIM_SET1R_CMP3_Pos (5U)
22618#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos)
22619#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk
22620#define HRTIM_SET1R_CMP4_Pos (6U)
22621#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos)
22622#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk
22624#define HRTIM_SET1R_MSTPER_Pos (7U)
22625#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos)
22626#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk
22627#define HRTIM_SET1R_MSTCMP1_Pos (8U)
22628#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)
22629#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk
22630#define HRTIM_SET1R_MSTCMP2_Pos (9U)
22631#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)
22632#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk
22633#define HRTIM_SET1R_MSTCMP3_Pos (10U)
22634#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)
22635#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk
22636#define HRTIM_SET1R_MSTCMP4_Pos (11U)
22637#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)
22638#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk
22640#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
22641#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)
22642#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk
22643#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
22644#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)
22645#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk
22646#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
22647#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)
22648#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk
22649#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
22650#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)
22651#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk
22652#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
22653#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)
22654#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk
22655#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
22656#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)
22657#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk
22658#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
22659#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)
22660#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk
22661#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
22662#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)
22663#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk
22664#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
22665#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)
22666#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk
22668#define HRTIM_SET1R_EXTVNT1_Pos (21U)
22669#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)
22670#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk
22671#define HRTIM_SET1R_EXTVNT2_Pos (22U)
22672#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)
22673#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk
22674#define HRTIM_SET1R_EXTVNT3_Pos (23U)
22675#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)
22676#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk
22677#define HRTIM_SET1R_EXTVNT4_Pos (24U)
22678#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)
22679#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk
22680#define HRTIM_SET1R_EXTVNT5_Pos (25U)
22681#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)
22682#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk
22683#define HRTIM_SET1R_EXTVNT6_Pos (26U)
22684#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)
22685#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk
22686#define HRTIM_SET1R_EXTVNT7_Pos (27U)
22687#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)
22688#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk
22689#define HRTIM_SET1R_EXTVNT8_Pos (28U)
22690#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)
22691#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk
22692#define HRTIM_SET1R_EXTVNT9_Pos (29U)
22693#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)
22694#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk
22695#define HRTIM_SET1R_EXTVNT10_Pos (30U)
22696#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)
22697#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk
22699#define HRTIM_SET1R_UPDATE_Pos (31U)
22700#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos)
22701#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk
22703/**** Bit definition for Slave Output 1 reset register ************************/
22704#define HRTIM_RST1R_SRT_Pos (0U)
22705#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos)
22706#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk
22707#define HRTIM_RST1R_RESYNC_Pos (1U)
22708#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos)
22709#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk
22710#define HRTIM_RST1R_PER_Pos (2U)
22711#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos)
22712#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk
22713#define HRTIM_RST1R_CMP1_Pos (3U)
22714#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos)
22715#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk
22716#define HRTIM_RST1R_CMP2_Pos (4U)
22717#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos)
22718#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk
22719#define HRTIM_RST1R_CMP3_Pos (5U)
22720#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos)
22721#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk
22722#define HRTIM_RST1R_CMP4_Pos (6U)
22723#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos)
22724#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk
22726#define HRTIM_RST1R_MSTPER_Pos (7U)
22727#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos)
22728#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk
22729#define HRTIM_RST1R_MSTCMP1_Pos (8U)
22730#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)
22731#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk
22732#define HRTIM_RST1R_MSTCMP2_Pos (9U)
22733#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)
22734#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk
22735#define HRTIM_RST1R_MSTCMP3_Pos (10U)
22736#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)
22737#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk
22738#define HRTIM_RST1R_MSTCMP4_Pos (11U)
22739#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)
22740#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk
22742#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
22743#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)
22744#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk
22745#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
22746#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)
22747#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk
22748#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
22749#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)
22750#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk
22751#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
22752#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)
22753#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk
22754#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
22755#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)
22756#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk
22757#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
22758#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)
22759#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk
22760#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
22761#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)
22762#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk
22763#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
22764#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)
22765#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk
22766#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
22767#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)
22768#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk
22770#define HRTIM_RST1R_EXTVNT1_Pos (21U)
22771#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)
22772#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk
22773#define HRTIM_RST1R_EXTVNT2_Pos (22U)
22774#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)
22775#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk
22776#define HRTIM_RST1R_EXTVNT3_Pos (23U)
22777#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)
22778#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk
22779#define HRTIM_RST1R_EXTVNT4_Pos (24U)
22780#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)
22781#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk
22782#define HRTIM_RST1R_EXTVNT5_Pos (25U)
22783#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)
22784#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk
22785#define HRTIM_RST1R_EXTVNT6_Pos (26U)
22786#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)
22787#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk
22788#define HRTIM_RST1R_EXTVNT7_Pos (27U)
22789#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)
22790#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk
22791#define HRTIM_RST1R_EXTVNT8_Pos (28U)
22792#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)
22793#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk
22794#define HRTIM_RST1R_EXTVNT9_Pos (29U)
22795#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)
22796#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk
22797#define HRTIM_RST1R_EXTVNT10_Pos (30U)
22798#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)
22799#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk
22801#define HRTIM_RST1R_UPDATE_Pos (31U)
22802#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos)
22803#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk
22806/**** Bit definition for Slave Output 2 set register **************************/
22807#define HRTIM_SET2R_SST_Pos (0U)
22808#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos)
22809#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk
22810#define HRTIM_SET2R_RESYNC_Pos (1U)
22811#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos)
22812#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk
22813#define HRTIM_SET2R_PER_Pos (2U)
22814#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos)
22815#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk
22816#define HRTIM_SET2R_CMP1_Pos (3U)
22817#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos)
22818#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk
22819#define HRTIM_SET2R_CMP2_Pos (4U)
22820#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos)
22821#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk
22822#define HRTIM_SET2R_CMP3_Pos (5U)
22823#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos)
22824#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk
22825#define HRTIM_SET2R_CMP4_Pos (6U)
22826#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos)
22827#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk
22829#define HRTIM_SET2R_MSTPER_Pos (7U)
22830#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos)
22831#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk
22832#define HRTIM_SET2R_MSTCMP1_Pos (8U)
22833#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)
22834#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk
22835#define HRTIM_SET2R_MSTCMP2_Pos (9U)
22836#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)
22837#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk
22838#define HRTIM_SET2R_MSTCMP3_Pos (10U)
22839#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)
22840#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk
22841#define HRTIM_SET2R_MSTCMP4_Pos (11U)
22842#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)
22843#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk
22845#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
22846#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)
22847#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk
22848#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
22849#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)
22850#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk
22851#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
22852#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)
22853#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk
22854#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
22855#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)
22856#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk
22857#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
22858#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)
22859#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk
22860#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
22861#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)
22862#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk
22863#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
22864#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)
22865#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk
22866#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
22867#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)
22868#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk
22869#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
22870#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)
22871#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk
22873#define HRTIM_SET2R_EXTVNT1_Pos (21U)
22874#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)
22875#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk
22876#define HRTIM_SET2R_EXTVNT2_Pos (22U)
22877#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)
22878#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk
22879#define HRTIM_SET2R_EXTVNT3_Pos (23U)
22880#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)
22881#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk
22882#define HRTIM_SET2R_EXTVNT4_Pos (24U)
22883#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)
22884#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk
22885#define HRTIM_SET2R_EXTVNT5_Pos (25U)
22886#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)
22887#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk
22888#define HRTIM_SET2R_EXTVNT6_Pos (26U)
22889#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)
22890#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk
22891#define HRTIM_SET2R_EXTVNT7_Pos (27U)
22892#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)
22893#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk
22894#define HRTIM_SET2R_EXTVNT8_Pos (28U)
22895#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)
22896#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk
22897#define HRTIM_SET2R_EXTVNT9_Pos (29U)
22898#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)
22899#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk
22900#define HRTIM_SET2R_EXTVNT10_Pos (30U)
22901#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)
22902#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk
22904#define HRTIM_SET2R_UPDATE_Pos (31U)
22905#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos)
22906#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk
22908/**** Bit definition for Slave Output 2 reset register ************************/
22909#define HRTIM_RST2R_SRT_Pos (0U)
22910#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos)
22911#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk
22912#define HRTIM_RST2R_RESYNC_Pos (1U)
22913#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos)
22914#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk
22915#define HRTIM_RST2R_PER_Pos (2U)
22916#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos)
22917#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk
22918#define HRTIM_RST2R_CMP1_Pos (3U)
22919#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos)
22920#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk
22921#define HRTIM_RST2R_CMP2_Pos (4U)
22922#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos)
22923#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk
22924#define HRTIM_RST2R_CMP3_Pos (5U)
22925#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos)
22926#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk
22927#define HRTIM_RST2R_CMP4_Pos (6U)
22928#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos)
22929#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk
22931#define HRTIM_RST2R_MSTPER_Pos (7U)
22932#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos)
22933#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk
22934#define HRTIM_RST2R_MSTCMP1_Pos (8U)
22935#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)
22936#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk
22937#define HRTIM_RST2R_MSTCMP2_Pos (9U)
22938#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)
22939#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk
22940#define HRTIM_RST2R_MSTCMP3_Pos (10U)
22941#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)
22942#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk
22943#define HRTIM_RST2R_MSTCMP4_Pos (11U)
22944#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)
22945#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk
22947#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
22948#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)
22949#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk
22950#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
22951#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)
22952#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk
22953#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
22954#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)
22955#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk
22956#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
22957#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)
22958#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk
22959#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
22960#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)
22961#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk
22962#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
22963#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)
22964#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk
22965#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
22966#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)
22967#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk
22968#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
22969#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)
22970#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk
22971#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
22972#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)
22973#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk
22975#define HRTIM_RST2R_EXTVNT1_Pos (21U)
22976#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)
22977#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk
22978#define HRTIM_RST2R_EXTVNT2_Pos (22U)
22979#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)
22980#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk
22981#define HRTIM_RST2R_EXTVNT3_Pos (23U)
22982#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)
22983#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk
22984#define HRTIM_RST2R_EXTVNT4_Pos (24U)
22985#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)
22986#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk
22987#define HRTIM_RST2R_EXTVNT5_Pos (25U)
22988#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)
22989#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk
22990#define HRTIM_RST2R_EXTVNT6_Pos (26U)
22991#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)
22992#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk
22993#define HRTIM_RST2R_EXTVNT7_Pos (27U)
22994#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)
22995#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk
22996#define HRTIM_RST2R_EXTVNT8_Pos (28U)
22997#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)
22998#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk
22999#define HRTIM_RST2R_EXTVNT9_Pos (29U)
23000#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)
23001#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk
23002#define HRTIM_RST2R_EXTVNT10_Pos (30U)
23003#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)
23004#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk
23006#define HRTIM_RST2R_UPDATE_Pos (31U)
23007#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos)
23008#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk
23010/**** Bit definition for Slave external event filtering register 1 ***********/
23011#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
23012#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)
23013#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk
23014#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
23015#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)
23016#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk
23017#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)
23018#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)
23019#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)
23020#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)
23022#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
23023#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)
23024#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk
23025#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
23026#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)
23027#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk
23028#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)
23029#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)
23030#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)
23031#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)
23033#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
23034#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)
23035#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk
23036#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
23037#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)
23038#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk
23039#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)
23040#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)
23041#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)
23042#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)
23044#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
23045#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)
23046#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk
23047#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
23048#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)
23049#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk
23050#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)
23051#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)
23052#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)
23053#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)
23055#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
23056#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)
23057#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk
23058#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
23059#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)
23060#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk
23061#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)
23062#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)
23063#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)
23064#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)
23066/**** Bit definition for Slave external event filtering register 2 ***********/
23067#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
23068#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)
23069#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk
23070#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
23071#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)
23072#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk
23073#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)
23074#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)
23075#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)
23076#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)
23078#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
23079#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)
23080#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk
23081#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
23082#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)
23083#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk
23084#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)
23085#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)
23086#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)
23087#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)
23089#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
23090#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)
23091#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk
23092#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
23093#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)
23094#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk
23095#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)
23096#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)
23097#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)
23098#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)
23100#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
23101#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)
23102#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk
23103#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
23104#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)
23105#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk
23106#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)
23107#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)
23108#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)
23109#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)
23111#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
23112#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)
23113#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk
23114#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
23115#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)
23116#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk
23117#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)
23118#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)
23119#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)
23120#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)
23122/**** Bit definition for Slave Timer reset register ***************************/
23123#define HRTIM_RSTR_UPDATE_Pos (1U)
23124#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos)
23125#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk
23126#define HRTIM_RSTR_CMP2_Pos (2U)
23127#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos)
23128#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk
23129#define HRTIM_RSTR_CMP4_Pos (3U)
23130#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos)
23131#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk
23133#define HRTIM_RSTR_MSTPER_Pos (4U)
23134#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos)
23135#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk
23136#define HRTIM_RSTR_MSTCMP1_Pos (5U)
23137#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)
23138#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk
23139#define HRTIM_RSTR_MSTCMP2_Pos (6U)
23140#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)
23141#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk
23142#define HRTIM_RSTR_MSTCMP3_Pos (7U)
23143#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)
23144#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk
23145#define HRTIM_RSTR_MSTCMP4_Pos (8U)
23146#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)
23147#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk
23149#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
23150#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)
23151#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk
23152#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
23153#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)
23154#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk
23155#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
23156#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)
23157#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk
23158#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
23159#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)
23160#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk
23161#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
23162#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)
23163#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk
23164#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
23165#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)
23166#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk
23167#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
23168#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)
23169#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk
23170#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
23171#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)
23172#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk
23173#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
23174#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)
23175#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk
23176#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
23177#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)
23178#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk
23180/* Slave Timer A reset enable bits upon other slave timers events */
23181#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
23182#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)
23183#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk
23184#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
23185#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)
23186#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk
23187#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
23188#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)
23189#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk
23191#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
23192#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)
23193#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk
23194#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
23195#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)
23196#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk
23197#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
23198#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)
23199#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk
23201#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
23202#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)
23203#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk
23204#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
23205#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)
23206#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk
23207#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
23208#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)
23209#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk
23211#define HRTIM_RSTR_TIMECMP1_Pos (28U)
23212#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)
23213#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk
23214#define HRTIM_RSTR_TIMECMP2_Pos (29U)
23215#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)
23216#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk
23217#define HRTIM_RSTR_TIMECMP4_Pos (30U)
23218#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)
23219#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk
23221/* Slave Timer B reset enable bits upon other slave timers events */
23222#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
23223#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)
23224#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk
23225#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
23226#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)
23227#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk
23228#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
23229#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)
23230#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk
23232#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
23233#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)
23234#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk
23235#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
23236#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)
23237#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk
23238#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
23239#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)
23240#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk
23242#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
23243#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)
23244#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk
23245#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
23246#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)
23247#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk
23248#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
23249#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)
23250#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk
23252#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
23253#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)
23254#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk
23255#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
23256#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)
23257#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk
23258#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
23259#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)
23260#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk
23262/* Slave Timer C reset enable bits upon other slave timers events */
23263#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
23264#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)
23265#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk
23266#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
23267#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)
23268#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk
23269#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
23270#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)
23271#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk
23273#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
23274#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)
23275#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk
23276#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
23277#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)
23278#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk
23279#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
23280#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)
23281#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk
23283#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
23284#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)
23285#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk
23286#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
23287#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)
23288#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk
23289#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
23290#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)
23291#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk
23293#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
23294#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)
23295#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk
23296#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
23297#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)
23298#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk
23299#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
23300#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)
23301#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk
23303/* Slave Timer D reset enable bits upon other slave timers events */
23304#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
23305#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)
23306#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk
23307#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
23308#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)
23309#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk
23310#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
23311#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)
23312#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk
23314#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
23315#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)
23316#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk
23317#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
23318#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)
23319#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk
23320#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
23321#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)
23322#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk
23324#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
23325#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)
23326#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk
23327#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
23328#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)
23329#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk
23330#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
23331#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)
23332#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk
23334#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
23335#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)
23336#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk
23337#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
23338#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)
23339#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk
23340#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
23341#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)
23342#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk
23344/* Slave Timer E reset enable bits upon other slave timers events */
23345#define HRTIM_RSTER_TIMACMP1_Pos (19U)
23346#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)
23347#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk
23348#define HRTIM_RSTER_TIMACMP2_Pos (20U)
23349#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)
23350#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk
23351#define HRTIM_RSTER_TIMACMP4_Pos (21U)
23352#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)
23353#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk
23355#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
23356#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)
23357#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk
23358#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
23359#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)
23360#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk
23361#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
23362#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)
23363#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk
23365#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
23366#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)
23367#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk
23368#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
23369#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)
23370#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk
23371#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
23372#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)
23373#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk
23375#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
23376#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)
23377#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk
23378#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
23379#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)
23380#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk
23381#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
23382#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)
23383#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk
23385/**** Bit definition for Slave Timer Chopper register *************************/
23386#define HRTIM_CHPR_CARFRQ_Pos (0U)
23387#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos)
23388#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk
23389#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos)
23390#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos)
23391#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos)
23392#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos)
23394#define HRTIM_CHPR_CARDTY_Pos (4U)
23395#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos)
23396#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk
23397#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos)
23398#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos)
23399#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos)
23401#define HRTIM_CHPR_STRPW_Pos (7U)
23402#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos)
23403#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk
23404#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos)
23405#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos)
23406#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos)
23407#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos)
23409/**** Bit definition for Slave Timer Capture 1 control register ***************/
23410#define HRTIM_CPT1CR_SWCPT_Pos (0U)
23411#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)
23412#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk
23413#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
23414#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)
23415#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk
23416#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
23417#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)
23418#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk
23419#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
23420#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)
23421#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk
23422#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
23423#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)
23424#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk
23425#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
23426#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)
23427#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk
23428#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
23429#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)
23430#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk
23431#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
23432#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)
23433#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk
23434#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
23435#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)
23436#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk
23437#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
23438#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)
23439#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk
23440#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
23441#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)
23442#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk
23443#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
23444#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)
23445#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk
23447#define HRTIM_CPT1CR_TA1SET_Pos (12U)
23448#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)
23449#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk
23450#define HRTIM_CPT1CR_TA1RST_Pos (13U)
23451#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)
23452#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk
23453#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
23454#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)
23455#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk
23456#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
23457#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)
23458#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk
23460#define HRTIM_CPT1CR_TB1SET_Pos (16U)
23461#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)
23462#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk
23463#define HRTIM_CPT1CR_TB1RST_Pos (17U)
23464#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)
23465#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk
23466#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
23467#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)
23468#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk
23469#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
23470#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)
23471#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk
23473#define HRTIM_CPT1CR_TC1SET_Pos (20U)
23474#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)
23475#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk
23476#define HRTIM_CPT1CR_TC1RST_Pos (21U)
23477#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)
23478#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk
23479#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
23480#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)
23481#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk
23482#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
23483#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)
23484#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk
23486#define HRTIM_CPT1CR_TD1SET_Pos (24U)
23487#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)
23488#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk
23489#define HRTIM_CPT1CR_TD1RST_Pos (25U)
23490#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)
23491#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk
23492#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
23493#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)
23494#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk
23495#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
23496#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)
23497#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk
23499#define HRTIM_CPT1CR_TE1SET_Pos (28U)
23500#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)
23501#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk
23502#define HRTIM_CPT1CR_TE1RST_Pos (29U)
23503#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)
23504#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk
23505#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
23506#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)
23507#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk
23508#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
23509#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)
23510#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk
23512/**** Bit definition for Slave Timer Capture 2 control register ***************/
23513#define HRTIM_CPT2CR_SWCPT_Pos (0U)
23514#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)
23515#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk
23516#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
23517#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)
23518#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk
23519#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
23520#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)
23521#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk
23522#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
23523#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)
23524#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk
23525#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
23526#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)
23527#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk
23528#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
23529#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)
23530#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk
23531#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
23532#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)
23533#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk
23534#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
23535#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)
23536#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk
23537#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
23538#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)
23539#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk
23540#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
23541#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)
23542#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk
23543#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
23544#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)
23545#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk
23546#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
23547#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)
23548#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk
23550#define HRTIM_CPT2CR_TA1SET_Pos (12U)
23551#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)
23552#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk
23553#define HRTIM_CPT2CR_TA1RST_Pos (13U)
23554#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)
23555#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk
23556#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
23557#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)
23558#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk
23559#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
23560#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)
23561#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk
23563#define HRTIM_CPT2CR_TB1SET_Pos (16U)
23564#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)
23565#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk
23566#define HRTIM_CPT2CR_TB1RST_Pos (17U)
23567#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)
23568#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk
23569#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
23570#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)
23571#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk
23572#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
23573#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)
23574#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk
23576#define HRTIM_CPT2CR_TC1SET_Pos (20U)
23577#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)
23578#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk
23579#define HRTIM_CPT2CR_TC1RST_Pos (21U)
23580#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)
23581#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk
23582#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
23583#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)
23584#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk
23585#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
23586#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)
23587#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk
23589#define HRTIM_CPT2CR_TD1SET_Pos (24U)
23590#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)
23591#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk
23592#define HRTIM_CPT2CR_TD1RST_Pos (25U)
23593#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)
23594#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk
23595#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
23596#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)
23597#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk
23598#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
23599#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)
23600#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk
23602#define HRTIM_CPT2CR_TE1SET_Pos (28U)
23603#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)
23604#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk
23605#define HRTIM_CPT2CR_TE1RST_Pos (29U)
23606#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)
23607#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk
23608#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
23609#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)
23610#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk
23611#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
23612#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)
23613#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk
23615/**** Bit definition for Slave Timer Output register **************************/
23616#define HRTIM_OUTR_POL1_Pos (1U)
23617#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos)
23618#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk
23619#define HRTIM_OUTR_IDLM1_Pos (2U)
23620#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos)
23621#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk
23622#define HRTIM_OUTR_IDLES1_Pos (3U)
23623#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos)
23624#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk
23625#define HRTIM_OUTR_FAULT1_Pos (4U)
23626#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos)
23627#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk
23628#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos)
23629#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos)
23630#define HRTIM_OUTR_CHP1_Pos (6U)
23631#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos)
23632#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk
23633#define HRTIM_OUTR_DIDL1_Pos (7U)
23634#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos)
23635#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk
23637#define HRTIM_OUTR_DTEN_Pos (8U)
23638#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos)
23639#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk
23640#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
23641#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)
23642#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk
23643#define HRTIM_OUTR_DLYPRT_Pos (10U)
23644#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos)
23645#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk
23646#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos)
23647#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos)
23648#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos)
23650#define HRTIM_OUTR_POL2_Pos (17U)
23651#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos)
23652#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk
23653#define HRTIM_OUTR_IDLM2_Pos (18U)
23654#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos)
23655#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk
23656#define HRTIM_OUTR_IDLES2_Pos (19U)
23657#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos)
23658#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk
23659#define HRTIM_OUTR_FAULT2_Pos (20U)
23660#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos)
23661#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk
23662#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos)
23663#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos)
23664#define HRTIM_OUTR_CHP2_Pos (22U)
23665#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos)
23666#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk
23667#define HRTIM_OUTR_DIDL2_Pos (23U)
23668#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos)
23669#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk
23671/**** Bit definition for Slave Timer Fault register ***************************/
23672#define HRTIM_FLTR_FLT1EN_Pos (0U)
23673#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos)
23674#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk
23675#define HRTIM_FLTR_FLT2EN_Pos (1U)
23676#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos)
23677#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk
23678#define HRTIM_FLTR_FLT3EN_Pos (2U)
23679#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos)
23680#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk
23681#define HRTIM_FLTR_FLT4EN_Pos (3U)
23682#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos)
23683#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk
23684#define HRTIM_FLTR_FLT5EN_Pos (4U)
23685#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos)
23686#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk
23687#define HRTIM_FLTR_FLTLCK_Pos (31U)
23688#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos)
23689#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk
23691/**** Bit definition for Common HRTIM Timer control register 1 ****************/
23692#define HRTIM_CR1_MUDIS_Pos (0U)
23693#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos)
23694#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk
23695#define HRTIM_CR1_TAUDIS_Pos (1U)
23696#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos)
23697#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk
23698#define HRTIM_CR1_TBUDIS_Pos (2U)
23699#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos)
23700#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk
23701#define HRTIM_CR1_TCUDIS_Pos (3U)
23702#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos)
23703#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk
23704#define HRTIM_CR1_TDUDIS_Pos (4U)
23705#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos)
23706#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk
23707#define HRTIM_CR1_TEUDIS_Pos (5U)
23708#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos)
23709#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk
23710#define HRTIM_CR1_ADC1USRC_Pos (16U)
23711#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos)
23712#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk
23713#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos)
23714#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos)
23715#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos)
23716#define HRTIM_CR1_ADC2USRC_Pos (19U)
23717#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos)
23718#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk
23719#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos)
23720#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos)
23721#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos)
23722#define HRTIM_CR1_ADC3USRC_Pos (22U)
23723#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos)
23724#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk
23725#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos)
23726#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos)
23727#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos)
23728#define HRTIM_CR1_ADC4USRC_Pos (25U)
23729#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos)
23730#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk
23731#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos)
23732#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos)
23733#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos)
23735/**** Bit definition for Common HRTIM Timer control register 2 ****************/
23736#define HRTIM_CR2_MSWU_Pos (0U)
23737#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos)
23738#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk
23739#define HRTIM_CR2_TASWU_Pos (1U)
23740#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos)
23741#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk
23742#define HRTIM_CR2_TBSWU_Pos (2U)
23743#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos)
23744#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk
23745#define HRTIM_CR2_TCSWU_Pos (3U)
23746#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos)
23747#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk
23748#define HRTIM_CR2_TDSWU_Pos (4U)
23749#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos)
23750#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk
23751#define HRTIM_CR2_TESWU_Pos (5U)
23752#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos)
23753#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk
23754#define HRTIM_CR2_MRST_Pos (8U)
23755#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos)
23756#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk
23757#define HRTIM_CR2_TARST_Pos (9U)
23758#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos)
23759#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk
23760#define HRTIM_CR2_TBRST_Pos (10U)
23761#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos)
23762#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk
23763#define HRTIM_CR2_TCRST_Pos (11U)
23764#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos)
23765#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk
23766#define HRTIM_CR2_TDRST_Pos (12U)
23767#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos)
23768#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk
23769#define HRTIM_CR2_TERST_Pos (13U)
23770#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos)
23771#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk
23773/**** Bit definition for Common HRTIM Timer interrupt status register *********/
23774#define HRTIM_ISR_FLT1_Pos (0U)
23775#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos)
23776#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk
23777#define HRTIM_ISR_FLT2_Pos (1U)
23778#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos)
23779#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk
23780#define HRTIM_ISR_FLT3_Pos (2U)
23781#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos)
23782#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk
23783#define HRTIM_ISR_FLT4_Pos (3U)
23784#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos)
23785#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk
23786#define HRTIM_ISR_FLT5_Pos (4U)
23787#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos)
23788#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk
23789#define HRTIM_ISR_SYSFLT_Pos (5U)
23790#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos)
23791#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk
23792#define HRTIM_ISR_BMPER_Pos (17U)
23793#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos)
23794#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk
23796/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
23797#define HRTIM_ICR_FLT1C_Pos (0U)
23798#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos)
23799#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk
23800#define HRTIM_ICR_FLT2C_Pos (1U)
23801#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos)
23802#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk
23803#define HRTIM_ICR_FLT3C_Pos (2U)
23804#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos)
23805#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk
23806#define HRTIM_ICR_FLT4C_Pos (3U)
23807#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos)
23808#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk
23809#define HRTIM_ICR_FLT5C_Pos (4U)
23810#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos)
23811#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk
23812#define HRTIM_ICR_SYSFLTC_Pos (5U)
23813#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos)
23814#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk
23815#define HRTIM_ICR_BMPERC_Pos (17U)
23816#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos)
23817#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk
23819/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
23820#define HRTIM_IER_FLT1_Pos (0U)
23821#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos)
23822#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk
23823#define HRTIM_IER_FLT2_Pos (1U)
23824#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos)
23825#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk
23826#define HRTIM_IER_FLT3_Pos (2U)
23827#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos)
23828#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk
23829#define HRTIM_IER_FLT4_Pos (3U)
23830#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos)
23831#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk
23832#define HRTIM_IER_FLT5_Pos (4U)
23833#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos)
23834#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk
23835#define HRTIM_IER_SYSFLT_Pos (5U)
23836#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos)
23837#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk
23838#define HRTIM_IER_BMPER_Pos (17U)
23839#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos)
23840#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk
23842/**** Bit definition for Common HRTIM Timer output enable register ************/
23843#define HRTIM_OENR_TA1OEN_Pos (0U)
23844#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos)
23845#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk
23846#define HRTIM_OENR_TA2OEN_Pos (1U)
23847#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos)
23848#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk
23849#define HRTIM_OENR_TB1OEN_Pos (2U)
23850#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos)
23851#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk
23852#define HRTIM_OENR_TB2OEN_Pos (3U)
23853#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos)
23854#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk
23855#define HRTIM_OENR_TC1OEN_Pos (4U)
23856#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos)
23857#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk
23858#define HRTIM_OENR_TC2OEN_Pos (5U)
23859#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos)
23860#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk
23861#define HRTIM_OENR_TD1OEN_Pos (6U)
23862#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos)
23863#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk
23864#define HRTIM_OENR_TD2OEN_Pos (7U)
23865#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos)
23866#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk
23867#define HRTIM_OENR_TE1OEN_Pos (8U)
23868#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos)
23869#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk
23870#define HRTIM_OENR_TE2OEN_Pos (9U)
23871#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos)
23872#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk
23874/**** Bit definition for Common HRTIM Timer output disable register ***********/
23875#define HRTIM_ODISR_TA1ODIS_Pos (0U)
23876#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)
23877#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk
23878#define HRTIM_ODISR_TA2ODIS_Pos (1U)
23879#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)
23880#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk
23881#define HRTIM_ODISR_TB1ODIS_Pos (2U)
23882#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)
23883#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk
23884#define HRTIM_ODISR_TB2ODIS_Pos (3U)
23885#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)
23886#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk
23887#define HRTIM_ODISR_TC1ODIS_Pos (4U)
23888#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)
23889#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk
23890#define HRTIM_ODISR_TC2ODIS_Pos (5U)
23891#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)
23892#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk
23893#define HRTIM_ODISR_TD1ODIS_Pos (6U)
23894#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)
23895#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk
23896#define HRTIM_ODISR_TD2ODIS_Pos (7U)
23897#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)
23898#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk
23899#define HRTIM_ODISR_TE1ODIS_Pos (8U)
23900#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)
23901#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk
23902#define HRTIM_ODISR_TE2ODIS_Pos (9U)
23903#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)
23904#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk
23906/**** Bit definition for Common HRTIM Timer output disable status register *****/
23907#define HRTIM_ODSR_TA1ODS_Pos (0U)
23908#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos)
23909#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk
23910#define HRTIM_ODSR_TA2ODS_Pos (1U)
23911#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos)
23912#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk
23913#define HRTIM_ODSR_TB1ODS_Pos (2U)
23914#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos)
23915#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk
23916#define HRTIM_ODSR_TB2ODS_Pos (3U)
23917#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos)
23918#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk
23919#define HRTIM_ODSR_TC1ODS_Pos (4U)
23920#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos)
23921#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk
23922#define HRTIM_ODSR_TC2ODS_Pos (5U)
23923#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos)
23924#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk
23925#define HRTIM_ODSR_TD1ODS_Pos (6U)
23926#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos)
23927#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk
23928#define HRTIM_ODSR_TD2ODS_Pos (7U)
23929#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos)
23930#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk
23931#define HRTIM_ODSR_TE1ODS_Pos (8U)
23932#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos)
23933#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk
23934#define HRTIM_ODSR_TE2ODS_Pos (9U)
23935#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos)
23936#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk
23938/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
23939#define HRTIM_BMCR_BME_Pos (0U)
23940#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos)
23941#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk
23942#define HRTIM_BMCR_BMOM_Pos (1U)
23943#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos)
23944#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk
23945#define HRTIM_BMCR_BMCLK_Pos (2U)
23946#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos)
23947#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk
23948#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos)
23949#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos)
23950#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos)
23951#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos)
23952#define HRTIM_BMCR_BMPRSC_Pos (6U)
23953#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos)
23954#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk
23955#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos)
23956#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos)
23957#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos)
23958#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos)
23959#define HRTIM_BMCR_BMPREN_Pos (10U)
23960#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos)
23961#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk
23962#define HRTIM_BMCR_MTBM_Pos (16U)
23963#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos)
23964#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk
23965#define HRTIM_BMCR_TABM_Pos (17U)
23966#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos)
23967#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk
23968#define HRTIM_BMCR_TBBM_Pos (18U)
23969#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos)
23970#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk
23971#define HRTIM_BMCR_TCBM_Pos (19U)
23972#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos)
23973#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk
23974#define HRTIM_BMCR_TDBM_Pos (20U)
23975#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos)
23976#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk
23977#define HRTIM_BMCR_TEBM_Pos (21U)
23978#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos)
23979#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk
23980#define HRTIM_BMCR_BMSTAT_Pos (31U)
23981#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos)
23982#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk
23984/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
23985#define HRTIM_BMTRGR_SW_Pos (0U)
23986#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos)
23987#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk
23988#define HRTIM_BMTRGR_MSTRST_Pos (1U)
23989#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)
23990#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk
23991#define HRTIM_BMTRGR_MSTREP_Pos (2U)
23992#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)
23993#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk
23994#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
23995#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)
23996#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk
23997#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
23998#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)
23999#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk
24000#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
24001#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)
24002#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk
24003#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
24004#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)
24005#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk
24006#define HRTIM_BMTRGR_TARST_Pos (7U)
24007#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos)
24008#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk
24009#define HRTIM_BMTRGR_TAREP_Pos (8U)
24010#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos)
24011#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk
24012#define HRTIM_BMTRGR_TACMP1_Pos (9U)
24013#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)
24014#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk
24015#define HRTIM_BMTRGR_TACMP2_Pos (10U)
24016#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)
24017#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk
24018#define HRTIM_BMTRGR_TBRST_Pos (11U)
24019#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos)
24020#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk
24021#define HRTIM_BMTRGR_TBREP_Pos (12U)
24022#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos)
24023#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk
24024#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
24025#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)
24026#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk
24027#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
24028#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)
24029#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk
24030#define HRTIM_BMTRGR_TCRST_Pos (15U)
24031#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos)
24032#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk
24033#define HRTIM_BMTRGR_TCREP_Pos (16U)
24034#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos)
24035#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk
24036#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
24037#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)
24038#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk
24039#define HRTIM_BMTRGR_TCCMP2_Pos (18U)
24040#define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)
24041#define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk
24042#define HRTIM_BMTRGR_TDRST_Pos (19U)
24043#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos)
24044#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk
24045#define HRTIM_BMTRGR_TDREP_Pos (20U)
24046#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos)
24047#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk
24048#define HRTIM_BMTRGR_TDCMP1_Pos (21U)
24049#define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)
24050#define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk
24051#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
24052#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)
24053#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk
24054#define HRTIM_BMTRGR_TERST_Pos (23U)
24055#define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos)
24056#define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk
24057#define HRTIM_BMTRGR_TEREP_Pos (24U)
24058#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos)
24059#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk
24060#define HRTIM_BMTRGR_TECMP1_Pos (25U)
24061#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)
24062#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk
24063#define HRTIM_BMTRGR_TECMP2_Pos (26U)
24064#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)
24065#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk
24066#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
24067#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)
24068#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk
24069#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
24070#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)
24071#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk
24072#define HRTIM_BMTRGR_EEV7_Pos (29U)
24073#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos)
24074#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk
24075#define HRTIM_BMTRGR_EEV8_Pos (30U)
24076#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos)
24077#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk
24078#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
24079#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)
24080#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk
24082/******************* Bit definition for HRTIM_BMCMPR register ***************/
24083#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
24084#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)
24085#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk
24087/******************* Bit definition for HRTIM_BMPER register ****************/
24088#define HRTIM_BMPER_BMPER_Pos (0U)
24089#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)
24090#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk
24092/******************* Bit definition for HRTIM_EECR1 register ****************/
24093#define HRTIM_EECR1_EE1SRC_Pos (0U)
24094#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos)
24095#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk
24096#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos)
24097#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos)
24098#define HRTIM_EECR1_EE1POL_Pos (2U)
24099#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos)
24100#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk
24101#define HRTIM_EECR1_EE1SNS_Pos (3U)
24102#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos)
24103#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk
24104#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos)
24105#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos)
24106#define HRTIM_EECR1_EE1FAST_Pos (5U)
24107#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos)
24108#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk
24110#define HRTIM_EECR1_EE2SRC_Pos (6U)
24111#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos)
24112#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk
24113#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos)
24114#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos)
24115#define HRTIM_EECR1_EE2POL_Pos (8U)
24116#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos)
24117#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk
24118#define HRTIM_EECR1_EE2SNS_Pos (9U)
24119#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos)
24120#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk
24121#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos)
24122#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos)
24123#define HRTIM_EECR1_EE2FAST_Pos (11U)
24124#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos)
24125#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk
24127#define HRTIM_EECR1_EE3SRC_Pos (12U)
24128#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos)
24129#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk
24130#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos)
24131#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos)
24132#define HRTIM_EECR1_EE3POL_Pos (14U)
24133#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos)
24134#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk
24135#define HRTIM_EECR1_EE3SNS_Pos (15U)
24136#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos)
24137#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk
24138#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos)
24139#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos)
24140#define HRTIM_EECR1_EE3FAST_Pos (17U)
24141#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos)
24142#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk
24144#define HRTIM_EECR1_EE4SRC_Pos (18U)
24145#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos)
24146#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk
24147#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos)
24148#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos)
24149#define HRTIM_EECR1_EE4POL_Pos (20U)
24150#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos)
24151#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk
24152#define HRTIM_EECR1_EE4SNS_Pos (21U)
24153#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos)
24154#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk
24155#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos)
24156#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos)
24157#define HRTIM_EECR1_EE4FAST_Pos (23U)
24158#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos)
24159#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk
24161#define HRTIM_EECR1_EE5SRC_Pos (24U)
24162#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos)
24163#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk
24164#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos)
24165#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos)
24166#define HRTIM_EECR1_EE5POL_Pos (26U)
24167#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos)
24168#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk
24169#define HRTIM_EECR1_EE5SNS_Pos (27U)
24170#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos)
24171#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk
24172#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos)
24173#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos)
24174#define HRTIM_EECR1_EE5FAST_Pos (29U)
24175#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos)
24176#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk
24178/******************* Bit definition for HRTIM_EECR2 register ****************/
24179#define HRTIM_EECR2_EE6SRC_Pos (0U)
24180#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos)
24181#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk
24182#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos)
24183#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos)
24184#define HRTIM_EECR2_EE6POL_Pos (2U)
24185#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos)
24186#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk
24187#define HRTIM_EECR2_EE6SNS_Pos (3U)
24188#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos)
24189#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk
24190#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos)
24191#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos)
24193#define HRTIM_EECR2_EE7SRC_Pos (6U)
24194#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos)
24195#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk
24196#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos)
24197#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos)
24198#define HRTIM_EECR2_EE7POL_Pos (8U)
24199#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos)
24200#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk
24201#define HRTIM_EECR2_EE7SNS_Pos (9U)
24202#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos)
24203#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk
24204#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos)
24205#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos)
24207#define HRTIM_EECR2_EE8SRC_Pos (12U)
24208#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos)
24209#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk
24210#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos)
24211#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos)
24212#define HRTIM_EECR2_EE8POL_Pos (14U)
24213#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos)
24214#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk
24215#define HRTIM_EECR2_EE8SNS_Pos (15U)
24216#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos)
24217#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk
24218#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos)
24219#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos)
24221#define HRTIM_EECR2_EE9SRC_Pos (18U)
24222#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos)
24223#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk
24224#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos)
24225#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos)
24226#define HRTIM_EECR2_EE9POL_Pos (20U)
24227#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos)
24228#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk
24229#define HRTIM_EECR2_EE9SNS_Pos (21U)
24230#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos)
24231#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk
24232#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos)
24233#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos)
24235#define HRTIM_EECR2_EE10SRC_Pos (24U)
24236#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos)
24237#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk
24238#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos)
24239#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos)
24240#define HRTIM_EECR2_EE10POL_Pos (26U)
24241#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos)
24242#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk
24243#define HRTIM_EECR2_EE10SNS_Pos (27U)
24244#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos)
24245#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk
24246#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos)
24247#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos)
24249/******************* Bit definition for HRTIM_EECR3 register ****************/
24250#define HRTIM_EECR3_EE6F_Pos (0U)
24251#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos)
24252#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk
24253#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos)
24254#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos)
24255#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos)
24256#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos)
24257#define HRTIM_EECR3_EE7F_Pos (6U)
24258#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos)
24259#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk
24260#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos)
24261#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos)
24262#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos)
24263#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos)
24264#define HRTIM_EECR3_EE8F_Pos (12U)
24265#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos)
24266#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk
24267#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos)
24268#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos)
24269#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos)
24270#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos)
24271#define HRTIM_EECR3_EE9F_Pos (18U)
24272#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos)
24273#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk
24274#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos)
24275#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos)
24276#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos)
24277#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos)
24278#define HRTIM_EECR3_EE10F_Pos (24U)
24279#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos)
24280#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk
24281#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos)
24282#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos)
24283#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos)
24284#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos)
24285#define HRTIM_EECR3_EEVSD_Pos (30U)
24286#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos)
24287#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk
24288#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos)
24289#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos)
24291/******************* Bit definition for HRTIM_ADC1R register ****************/
24292#define HRTIM_ADC1R_AD1MC1_Pos (0U)
24293#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)
24294#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk
24295#define HRTIM_ADC1R_AD1MC2_Pos (1U)
24296#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)
24297#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk
24298#define HRTIM_ADC1R_AD1MC3_Pos (2U)
24299#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)
24300#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk
24301#define HRTIM_ADC1R_AD1MC4_Pos (3U)
24302#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)
24303#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk
24304#define HRTIM_ADC1R_AD1MPER_Pos (4U)
24305#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)
24306#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk
24307#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
24308#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)
24309#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk
24310#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
24311#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)
24312#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk
24313#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
24314#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)
24315#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk
24316#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
24317#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)
24318#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk
24319#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
24320#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)
24321#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk
24322#define HRTIM_ADC1R_AD1TAC2_Pos (10U)
24323#define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)
24324#define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk
24325#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
24326#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)
24327#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk
24328#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
24329#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)
24330#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk
24331#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
24332#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)
24333#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk
24334#define HRTIM_ADC1R_AD1TARST_Pos (14U)
24335#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)
24336#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk
24337#define HRTIM_ADC1R_AD1TBC2_Pos (15U)
24338#define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)
24339#define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk
24340#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
24341#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)
24342#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk
24343#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
24344#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)
24345#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk
24346#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
24347#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)
24348#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk
24349#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
24350#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)
24351#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk
24352#define HRTIM_ADC1R_AD1TCC2_Pos (20U)
24353#define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)
24354#define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk
24355#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
24356#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)
24357#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk
24358#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
24359#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)
24360#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk
24361#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
24362#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)
24363#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk
24364#define HRTIM_ADC1R_AD1TDC2_Pos (24U)
24365#define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)
24366#define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk
24367#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
24368#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)
24369#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk
24370#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
24371#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)
24372#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk
24373#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
24374#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)
24375#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk
24376#define HRTIM_ADC1R_AD1TEC2_Pos (28U)
24377#define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)
24378#define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk
24379#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
24380#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)
24381#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk
24382#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
24383#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)
24384#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk
24385#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
24386#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)
24387#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk
24389/******************* Bit definition for HRTIM_ADC2R register ****************/
24390#define HRTIM_ADC2R_AD2MC1_Pos (0U)
24391#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)
24392#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk
24393#define HRTIM_ADC2R_AD2MC2_Pos (1U)
24394#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)
24395#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk
24396#define HRTIM_ADC2R_AD2MC3_Pos (2U)
24397#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)
24398#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk
24399#define HRTIM_ADC2R_AD2MC4_Pos (3U)
24400#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)
24401#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk
24402#define HRTIM_ADC2R_AD2MPER_Pos (4U)
24403#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)
24404#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk
24405#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
24406#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)
24407#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk
24408#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
24409#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)
24410#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk
24411#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
24412#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)
24413#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk
24414#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
24415#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)
24416#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk
24417#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
24418#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)
24419#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk
24420#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
24421#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)
24422#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk
24423#define HRTIM_ADC2R_AD2TAC3_Pos (11U)
24424#define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)
24425#define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk
24426#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
24427#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)
24428#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk
24429#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
24430#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)
24431#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk
24432#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
24433#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)
24434#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk
24435#define HRTIM_ADC2R_AD2TBC3_Pos (15U)
24436#define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)
24437#define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk
24438#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
24439#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)
24440#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk
24441#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
24442#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)
24443#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk
24444#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
24445#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)
24446#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk
24447#define HRTIM_ADC2R_AD2TCC3_Pos (19U)
24448#define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)
24449#define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk
24450#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
24451#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)
24452#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk
24453#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
24454#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)
24455#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk
24456#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
24457#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)
24458#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk
24459#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
24460#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)
24461#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk
24462#define HRTIM_ADC2R_AD2TDC3_Pos (24U)
24463#define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)
24464#define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk
24465#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
24466#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)
24467#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk
24468#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
24469#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)
24470#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk
24471#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
24472#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)
24473#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk
24474#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
24475#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)
24476#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk
24477#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
24478#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)
24479#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk
24480#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
24481#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)
24482#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk
24483#define HRTIM_ADC2R_AD2TERST_Pos (31U)
24484#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)
24485#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk
24487/******************* Bit definition for HRTIM_ADC3R register ****************/
24488#define HRTIM_ADC3R_AD3MC1_Pos (0U)
24489#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)
24490#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk
24491#define HRTIM_ADC3R_AD3MC2_Pos (1U)
24492#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)
24493#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk
24494#define HRTIM_ADC3R_AD3MC3_Pos (2U)
24495#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)
24496#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk
24497#define HRTIM_ADC3R_AD3MC4_Pos (3U)
24498#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)
24499#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk
24500#define HRTIM_ADC3R_AD3MPER_Pos (4U)
24501#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)
24502#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk
24503#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
24504#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)
24505#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk
24506#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
24507#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)
24508#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk
24509#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
24510#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)
24511#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk
24512#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
24513#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)
24514#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk
24515#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
24516#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)
24517#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk
24518#define HRTIM_ADC3R_AD3TAC2_Pos (10U)
24519#define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)
24520#define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk
24521#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
24522#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)
24523#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk
24524#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
24525#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)
24526#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk
24527#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
24528#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)
24529#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk
24530#define HRTIM_ADC3R_AD3TARST_Pos (14U)
24531#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)
24532#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk
24533#define HRTIM_ADC3R_AD3TBC2_Pos (15U)
24534#define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)
24535#define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk
24536#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
24537#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)
24538#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk
24539#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
24540#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)
24541#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk
24542#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
24543#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)
24544#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk
24545#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
24546#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)
24547#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk
24548#define HRTIM_ADC3R_AD3TCC2_Pos (20U)
24549#define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)
24550#define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk
24551#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
24552#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)
24553#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk
24554#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
24555#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)
24556#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk
24557#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
24558#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)
24559#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk
24560#define HRTIM_ADC3R_AD3TDC2_Pos (24U)
24561#define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)
24562#define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk
24563#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
24564#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)
24565#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk
24566#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
24567#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)
24568#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk
24569#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
24570#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)
24571#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk
24572#define HRTIM_ADC3R_AD3TEC2_Pos (28U)
24573#define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)
24574#define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk
24575#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
24576#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)
24577#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk
24578#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
24579#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)
24580#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk
24581#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
24582#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)
24583#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk
24585/******************* Bit definition for HRTIM_ADC4R register ****************/
24586#define HRTIM_ADC4R_AD4MC1_Pos (0U)
24587#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)
24588#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk
24589#define HRTIM_ADC4R_AD4MC2_Pos (1U)
24590#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)
24591#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk
24592#define HRTIM_ADC4R_AD4MC3_Pos (2U)
24593#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)
24594#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk
24595#define HRTIM_ADC4R_AD4MC4_Pos (3U)
24596#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)
24597#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk
24598#define HRTIM_ADC4R_AD4MPER_Pos (4U)
24599#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)
24600#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk
24601#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
24602#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)
24603#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk
24604#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
24605#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)
24606#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk
24607#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
24608#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)
24609#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk
24610#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
24611#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)
24612#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk
24613#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
24614#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)
24615#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk
24616#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
24617#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)
24618#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk
24619#define HRTIM_ADC4R_AD4TAC3_Pos (11U)
24620#define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)
24621#define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk
24622#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
24623#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)
24624#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk
24625#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
24626#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)
24627#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk
24628#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
24629#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)
24630#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk
24631#define HRTIM_ADC4R_AD4TBC3_Pos (15U)
24632#define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)
24633#define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk
24634#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
24635#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)
24636#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk
24637#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
24638#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)
24639#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk
24640#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
24641#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)
24642#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk
24643#define HRTIM_ADC4R_AD4TCC3_Pos (19U)
24644#define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)
24645#define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk
24646#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
24647#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)
24648#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk
24649#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
24650#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)
24651#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk
24652#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
24653#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)
24654#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk
24655#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
24656#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)
24657#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk
24658#define HRTIM_ADC4R_AD4TDC3_Pos (24U)
24659#define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)
24660#define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk
24661#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
24662#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)
24663#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk
24664#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
24665#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)
24666#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk
24667#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
24668#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)
24669#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk
24670#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
24671#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)
24672#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk
24673#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
24674#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)
24675#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk
24676#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
24677#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)
24678#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk
24679#define HRTIM_ADC4R_AD4TERST_Pos (31U)
24680#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)
24681#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk
24683/******************* Bit definition for HRTIM_FLTINR1 register ***************/
24684#define HRTIM_FLTINR1_FLT1E_Pos (0U)
24685#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)
24686#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk
24687#define HRTIM_FLTINR1_FLT1P_Pos (1U)
24688#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)
24689#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk
24690#define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
24691#define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)
24692#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk
24693#define HRTIM_FLTINR1_FLT1F_Pos (3U)
24694#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)
24695#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk
24696#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)
24697#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)
24698#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)
24699#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)
24700#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
24701#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)
24702#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk
24704#define HRTIM_FLTINR1_FLT2E_Pos (8U)
24705#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)
24706#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk
24707#define HRTIM_FLTINR1_FLT2P_Pos (9U)
24708#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)
24709#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk
24710#define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
24711#define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)
24712#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk
24713#define HRTIM_FLTINR1_FLT2F_Pos (11U)
24714#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)
24715#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk
24716#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)
24717#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)
24718#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)
24719#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)
24720#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
24721#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)
24722#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk
24724#define HRTIM_FLTINR1_FLT3E_Pos (16U)
24725#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)
24726#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk
24727#define HRTIM_FLTINR1_FLT3P_Pos (17U)
24728#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)
24729#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk
24730#define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
24731#define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)
24732#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk
24733#define HRTIM_FLTINR1_FLT3F_Pos (19U)
24734#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)
24735#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk
24736#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)
24737#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)
24738#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)
24739#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)
24740#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
24741#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)
24742#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk
24744#define HRTIM_FLTINR1_FLT4E_Pos (24U)
24745#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)
24746#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk
24747#define HRTIM_FLTINR1_FLT4P_Pos (25U)
24748#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)
24749#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk
24750#define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
24751#define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)
24752#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk
24753#define HRTIM_FLTINR1_FLT4F_Pos (27U)
24754#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)
24755#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk
24756#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)
24757#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)
24758#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)
24759#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)
24760#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
24761#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)
24762#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk
24764/******************* Bit definition for HRTIM_FLTINR2 register ***************/
24765#define HRTIM_FLTINR2_FLT5E_Pos (0U)
24766#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)
24767#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk
24768#define HRTIM_FLTINR2_FLT5P_Pos (1U)
24769#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)
24770#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk
24771#define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
24772#define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)
24773#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk
24774#define HRTIM_FLTINR2_FLT5F_Pos (3U)
24775#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)
24776#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk
24777#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)
24778#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)
24779#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)
24780#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)
24781#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
24782#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)
24783#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk
24784#define HRTIM_FLTINR2_FLTSD_Pos (24U)
24785#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)
24786#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk
24787#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)
24788#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)
24790/******************* Bit definition for HRTIM_BDMUPR register ***************/
24791#define HRTIM_BDMUPR_MCR_Pos (0U)
24792#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos)
24793#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk
24794#define HRTIM_BDMUPR_MICR_Pos (1U)
24795#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos)
24796#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk
24797#define HRTIM_BDMUPR_MDIER_Pos (2U)
24798#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos)
24799#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk
24800#define HRTIM_BDMUPR_MCNT_Pos (3U)
24801#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos)
24802#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk
24803#define HRTIM_BDMUPR_MPER_Pos (4U)
24804#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos)
24805#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk
24806#define HRTIM_BDMUPR_MREP_Pos (5U)
24807#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos)
24808#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk
24809#define HRTIM_BDMUPR_MCMP1_Pos (6U)
24810#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)
24811#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk
24812#define HRTIM_BDMUPR_MCMP2_Pos (7U)
24813#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)
24814#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk
24815#define HRTIM_BDMUPR_MCMP3_Pos (8U)
24816#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)
24817#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk
24818#define HRTIM_BDMUPR_MCMP4_Pos (9U)
24819#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)
24820#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk
24822/******************* Bit definition for HRTIM_BDTUPR register ***************/
24823#define HRTIM_BDTUPR_TIMCR_Pos (0U)
24824#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)
24825#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk
24826#define HRTIM_BDTUPR_TIMICR_Pos (1U)
24827#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)
24828#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk
24829#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
24830#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)
24831#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk
24832#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
24833#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)
24834#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk
24835#define HRTIM_BDTUPR_TIMPER_Pos (4U)
24836#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)
24837#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk
24838#define HRTIM_BDTUPR_TIMREP_Pos (5U)
24839#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)
24840#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk
24841#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
24842#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)
24843#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk
24844#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
24845#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)
24846#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk
24847#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
24848#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)
24849#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk
24850#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
24851#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)
24852#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk
24853#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
24854#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)
24855#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk
24856#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
24857#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)
24858#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk
24859#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
24860#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)
24861#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk
24862#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
24863#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)
24864#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk
24865#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
24866#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)
24867#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk
24868#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
24869#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)
24870#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk
24871#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
24872#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)
24873#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk
24874#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
24875#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)
24876#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk
24877#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
24878#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)
24879#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk
24880#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
24881#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)
24882#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk
24883#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
24884#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)
24885#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk
24887/******************* Bit definition for HRTIM_BDMADR register ***************/
24888#define HRTIM_BDMADR_BDMADR_Pos (0U)
24889#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)
24890#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk
24892/******************************************************************************/
24893/* */
24894/* RAM ECC monitoring */
24895/* */
24896/******************************************************************************/
24897/****************** Bit definition for RAMECC_IER register ******************/
24898#define RAMECC_IER_GECCDEBWIE_Pos (3U)
24899#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
24900#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk
24901#define RAMECC_IER_GECCDEIE_Pos (2U)
24902#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos)
24903#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk
24904#define RAMECC_IER_GECCSEIE_Pos (1U)
24905#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos)
24906#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk
24907#define RAMECC_IER_GIE_Pos (0U)
24908#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos)
24909#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk
24911/******************* Bit definition for RAMECC_CR register ******************/
24912#define RAMECC_CR_ECCELEN_Pos (5U)
24913#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos)
24914#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk
24915#define RAMECC_CR_ECCDEBWIE_Pos (4U)
24916#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
24917#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk
24918#define RAMECC_CR_ECCDEIE_Pos (3U)
24919#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos)
24920#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk
24921#define RAMECC_CR_ECCSEIE_Pos (2U)
24922#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos)
24923#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk
24925/******************* Bit definition for RAMECC_SR register ******************/
24926#define RAMECC_SR_DEBWDF_Pos (2U)
24927#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos)
24928#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk
24929#define RAMECC_SR_DEDF_Pos (1U)
24930#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos)
24931#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk
24932#define RAMECC_SR_SEDCF_Pos (0U)
24933#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos)
24934#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk
24936/****************** Bit definition for RAMECC_FAR register ******************/
24937#define RAMECC_FAR_FADD_Pos (0U)
24938#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
24939#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk
24941/****************** Bit definition for RAMECC_FDRL register *****************/
24942#define RAMECC_FAR_FDATAL_Pos (0U)
24943#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)
24944#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk
24946/****************** Bit definition for RAMECC_FDRH register *****************/
24947#define RAMECC_FAR_FDATAH_Pos (0U)
24948#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)
24949#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
24950
24951/***************** Bit definition for RAMECC_FECR register ******************/
24952#define RAMECC_FECR_FEC_Pos (0U)
24953#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
24954#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk
24956/******************************************************************************/
24957/* */
24958/* MDIOS */
24959/* */
24960/******************************************************************************/
24961/******************** Bit definition for MDIOS_CR register *******************/
24962#define MDIOS_CR_EN_Pos (0U)
24963#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
24964#define MDIOS_CR_EN MDIOS_CR_EN_Msk
24965#define MDIOS_CR_WRIE_Pos (1U)
24966#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
24967#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
24968#define MDIOS_CR_RDIE_Pos (2U)
24969#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
24970#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
24971#define MDIOS_CR_EIE_Pos (3U)
24972#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
24973#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
24974#define MDIOS_CR_DPC_Pos (7U)
24975#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
24976#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
24977#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
24978#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
24979#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
24980#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
24981#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
24982#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
24983#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
24984#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
24986/******************** Bit definition for MDIOS_SR register *******************/
24987#define MDIOS_SR_PERF_Pos (0U)
24988#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
24989#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
24990#define MDIOS_SR_SERF_Pos (1U)
24991#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
24992#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
24993#define MDIOS_SR_TERF_Pos (2U)
24994#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
24995#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
24997/******************** Bit definition for MDIOS_CLRFR register *******************/
24998#define MDIOS_SR_CPERF_Pos (0U)
24999#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos)
25000#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk
25001#define MDIOS_SR_CSERF_Pos (1U)
25002#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos)
25003#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk
25004#define MDIOS_SR_CTERF_Pos (2U)
25005#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos)
25006#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk
25008/******************************************************************************/
25009/* */
25010/* USB_OTG */
25011/* */
25012/******************************************************************************/
25013/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
25014#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
25015#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
25016#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
25017#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
25018#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
25019#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
25020#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
25021#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
25022#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
25023#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
25024#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
25025#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
25026#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
25027#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
25028#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
25029#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
25030#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
25031#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
25032#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
25033#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
25034#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
25035#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
25036#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
25037#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
25038#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
25039#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
25040#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
25041#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
25042#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
25043#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
25044#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
25045#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
25046#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
25047#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
25048#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
25049#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
25050#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
25051#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
25052#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
25053#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
25054#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
25055#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
25056#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
25057#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
25058#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
25059#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
25060#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
25061#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
25062#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
25063#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
25064#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
25065#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
25066#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
25067#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
25069/******************** Bit definition forUSB_OTG_HCFG register ********************/
25070
25071#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
25072#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
25073#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
25074#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
25075#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
25076#define USB_OTG_HCFG_FSLSS_Pos (2U)
25077#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
25078#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
25080/******************** Bit definition forUSB_OTG_DCFG register ********************/
25081
25082#define USB_OTG_DCFG_DSPD_Pos (0U)
25083#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
25084#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
25085#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
25086#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
25087#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
25088#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
25089#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
25091#define USB_OTG_DCFG_DAD_Pos (4U)
25092#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
25093#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
25094#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
25095#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
25096#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
25097#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
25098#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
25099#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
25100#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
25102#define USB_OTG_DCFG_PFIVL_Pos (11U)
25103#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
25104#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
25105#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
25106#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
25108#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
25109#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
25110#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
25111#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
25112#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
25114/******************** Bit definition forUSB_OTG_PCGCR register ********************/
25115#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
25116#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
25117#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
25118#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
25119#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
25120#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
25121#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
25122#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
25123#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
25125/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
25126#define USB_OTG_GOTGINT_SEDET_Pos (2U)
25127#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
25128#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
25129#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
25130#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
25131#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
25132#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
25133#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
25134#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
25135#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
25136#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
25137#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
25138#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
25139#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
25140#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
25141#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
25142#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
25143#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
25145/******************** Bit definition forUSB_OTG_DCTL register ********************/
25146#define USB_OTG_DCTL_RWUSIG_Pos (0U)
25147#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
25148#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
25149#define USB_OTG_DCTL_SDIS_Pos (1U)
25150#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
25151#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
25152#define USB_OTG_DCTL_GINSTS_Pos (2U)
25153#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
25154#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
25155#define USB_OTG_DCTL_GONSTS_Pos (3U)
25156#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
25157#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
25159#define USB_OTG_DCTL_TCTL_Pos (4U)
25160#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
25161#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
25162#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
25163#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
25164#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
25165#define USB_OTG_DCTL_SGINAK_Pos (7U)
25166#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
25167#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
25168#define USB_OTG_DCTL_CGINAK_Pos (8U)
25169#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
25170#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
25171#define USB_OTG_DCTL_SGONAK_Pos (9U)
25172#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
25173#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
25174#define USB_OTG_DCTL_CGONAK_Pos (10U)
25175#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
25176#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
25177#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
25178#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
25179#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
25181/******************** Bit definition forUSB_OTG_HFIR register ********************/
25182#define USB_OTG_HFIR_FRIVL_Pos (0U)
25183#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
25184#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
25186/******************** Bit definition forUSB_OTG_HFNUM register ********************/
25187#define USB_OTG_HFNUM_FRNUM_Pos (0U)
25188#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
25189#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
25190#define USB_OTG_HFNUM_FTREM_Pos (16U)
25191#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
25192#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
25194/******************** Bit definition forUSB_OTG_DSTS register ********************/
25195#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
25196#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
25197#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
25199#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
25200#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
25201#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
25202#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
25203#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
25204#define USB_OTG_DSTS_EERR_Pos (3U)
25205#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
25206#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
25207#define USB_OTG_DSTS_FNSOF_Pos (8U)
25208#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
25209#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
25211/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
25212#define USB_OTG_GAHBCFG_GINT_Pos (0U)
25213#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
25214#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
25216#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
25217#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
25218#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
25219#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
25220#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
25221#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
25222#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
25223#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
25224#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
25225#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
25226#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
25227#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
25228#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
25229#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
25230#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
25231#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
25232#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
25234/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
25235
25236#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
25237#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
25238#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
25239#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
25240#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
25241#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
25242#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
25243#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
25244#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
25245#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
25246#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
25247#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
25248#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
25249#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
25250#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
25252#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
25253#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
25254#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
25255#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
25256#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
25257#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
25258#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
25259#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
25260#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
25261#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
25262#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
25263#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
25264#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
25265#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
25266#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
25267#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
25268#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
25269#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
25270#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
25271#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
25272#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
25273#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
25274#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
25275#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
25276#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
25277#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
25278#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
25279#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
25280#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
25281#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
25282#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
25283#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
25284#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
25285#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
25286#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
25287#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
25288#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
25289#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
25290#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
25291#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
25292#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
25293#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
25294#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
25295#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
25296#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
25297#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
25299/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
25300#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
25301#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
25302#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
25303#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
25304#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
25305#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
25306#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
25307#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
25308#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
25309#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
25310#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
25311#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
25312#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
25313#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
25314#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
25316#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
25317#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
25318#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
25319#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
25320#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
25321#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
25322#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
25323#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
25324#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
25325#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
25326#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
25327#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
25328#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
25329#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
25331/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
25332#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
25333#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
25334#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
25335#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
25336#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
25337#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
25338#define USB_OTG_DIEPMSK_TOM_Pos (3U)
25339#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
25340#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
25341#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
25342#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
25343#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
25344#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
25345#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
25346#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
25347#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
25348#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
25349#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
25350#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
25351#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
25352#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
25353#define USB_OTG_DIEPMSK_BIM_Pos (9U)
25354#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
25355#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
25357/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
25358#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
25359#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
25360#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
25362#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
25363#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25364#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
25365#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25366#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25367#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25368#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25369#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25370#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25371#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25372#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
25374#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
25375#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25376#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
25377#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25378#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25379#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25380#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25381#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25382#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25383#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25384#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
25386/******************** Bit definition forUSB_OTG_HAINT register ********************/
25387#define USB_OTG_HAINT_HAINT_Pos (0U)
25388#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
25389#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
25391/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
25392#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
25393#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
25394#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
25395#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
25396#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
25397#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
25398#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
25399#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
25400#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
25401#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
25402#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
25403#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
25404#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
25405#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
25406#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
25407#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
25408#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
25409#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
25410#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
25411#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
25412#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
25413#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
25414#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
25415#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
25416#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
25417#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
25418#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
25419#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
25420#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
25421#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
25422#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
25423#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
25424#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
25425#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
25426#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
25427#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
25429/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
25430#define USB_OTG_GINTSTS_CMOD_Pos (0U)
25431#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
25432#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
25433#define USB_OTG_GINTSTS_MMIS_Pos (1U)
25434#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
25435#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
25436#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
25437#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
25438#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
25439#define USB_OTG_GINTSTS_SOF_Pos (3U)
25440#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
25441#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
25442#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
25443#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
25444#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
25445#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
25446#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
25447#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
25448#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
25449#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
25450#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
25451#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
25452#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
25453#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
25454#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
25455#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
25456#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
25457#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
25458#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
25459#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
25460#define USB_OTG_GINTSTS_USBRST_Pos (12U)
25461#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
25462#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
25463#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
25464#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
25465#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
25466#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
25467#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
25468#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
25469#define USB_OTG_GINTSTS_EOPF_Pos (15U)
25470#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
25471#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
25472#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
25473#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
25474#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
25475#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
25476#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
25477#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
25478#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
25479#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
25480#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
25481#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
25482#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
25483#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
25484#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
25485#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
25486#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
25487#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
25488#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
25489#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
25490#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
25491#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
25492#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
25493#define USB_OTG_GINTSTS_HCINT_Pos (25U)
25494#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
25495#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
25496#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
25497#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
25498#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
25499#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
25500#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
25501#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
25502#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
25503#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
25504#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
25505#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
25506#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
25507#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
25508#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
25509#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
25510#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
25511#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
25512#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
25513#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
25515/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
25516#define USB_OTG_GINTMSK_MMISM_Pos (1U)
25517#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
25518#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
25519#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
25520#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
25521#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
25522#define USB_OTG_GINTMSK_SOFM_Pos (3U)
25523#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
25524#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
25525#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
25526#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
25527#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
25528#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
25529#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
25530#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
25531#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
25532#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
25533#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
25534#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
25535#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
25536#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
25537#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
25538#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
25539#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
25540#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
25541#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
25542#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
25543#define USB_OTG_GINTMSK_USBRST_Pos (12U)
25544#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
25545#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
25546#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
25547#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
25548#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
25549#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
25550#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
25551#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
25552#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
25553#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
25554#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
25555#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
25556#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
25557#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
25558#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
25559#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
25560#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
25561#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
25562#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
25563#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
25564#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
25565#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
25566#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
25567#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
25568#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
25569#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
25570#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
25571#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
25572#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
25573#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
25574#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
25575#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
25576#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
25577#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
25578#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
25579#define USB_OTG_GINTMSK_HCIM_Pos (25U)
25580#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
25581#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
25582#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
25583#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
25584#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
25585#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
25586#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
25587#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
25588#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
25589#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
25590#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
25591#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
25592#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
25593#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
25594#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
25595#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
25596#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
25597#define USB_OTG_GINTMSK_WUIM_Pos (31U)
25598#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
25599#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
25601/******************** Bit definition forUSB_OTG_DAINT register ********************/
25602#define USB_OTG_DAINT_IEPINT_Pos (0U)
25603#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
25604#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
25605#define USB_OTG_DAINT_OEPINT_Pos (16U)
25606#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
25607#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
25609/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
25610#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
25611#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
25612#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
25614/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
25615#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
25616#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
25617#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
25618#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
25619#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
25620#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
25621#define USB_OTG_GRXSTSP_DPID_Pos (15U)
25622#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
25623#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
25624#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
25625#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
25626#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
25628/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
25629#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
25630#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
25631#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
25632#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
25633#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
25634#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
25636/******************** Bit definition for OTG register ********************/
25637
25638#define USB_OTG_CHNUM_Pos (0U)
25639#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
25640#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
25641#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
25642#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
25643#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
25644#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
25645#define USB_OTG_BCNT_Pos (4U)
25646#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
25647#define USB_OTG_BCNT USB_OTG_BCNT_Msk
25649#define USB_OTG_DPID_Pos (15U)
25650#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
25651#define USB_OTG_DPID USB_OTG_DPID_Msk
25652#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
25653#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
25655#define USB_OTG_PKTSTS_Pos (17U)
25656#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
25657#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
25658#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
25659#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
25660#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
25661#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
25663#define USB_OTG_EPNUM_Pos (0U)
25664#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
25665#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
25666#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
25667#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
25668#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
25669#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
25671#define USB_OTG_FRMNUM_Pos (21U)
25672#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
25673#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
25674#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
25675#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
25676#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
25677#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
25679/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
25680#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
25681#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
25682#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
25684/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
25685#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
25686#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
25687#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
25689/******************** Bit definition for OTG register ********************/
25690#define USB_OTG_NPTXFSA_Pos (0U)
25691#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
25692#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
25693#define USB_OTG_NPTXFD_Pos (16U)
25694#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
25695#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
25696#define USB_OTG_TX0FSA_Pos (0U)
25697#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
25698#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
25699#define USB_OTG_TX0FD_Pos (16U)
25700#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
25701#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
25703/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
25704#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
25705#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
25706#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
25708/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
25709#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
25710#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
25711#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
25713#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
25714#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25715#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
25716#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25717#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25718#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25719#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25720#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25721#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25722#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25723#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
25725#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
25726#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25727#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
25728#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25729#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25730#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25731#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25732#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25733#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25734#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
25736/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
25737#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
25738#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
25739#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
25740#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
25741#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
25742#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
25744#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
25745#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25746#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
25747#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25748#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25749#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25750#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25751#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25752#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25753#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25754#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25755#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
25756#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
25757#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
25758#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
25760#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
25761#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25762#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
25763#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25764#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25765#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25766#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25767#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25768#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25769#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25770#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25771#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
25772#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
25773#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
25774#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
25776/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
25777#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
25778#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
25779#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
25781/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
25782#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
25783#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
25784#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
25785#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
25786#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
25787#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
25789/******************** Bit definition forUSB_OTG_GCCFG register ********************/
25790#define USB_OTG_GCCFG_DCDET_Pos (0U)
25791#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
25792#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
25793#define USB_OTG_GCCFG_PDET_Pos (1U)
25794#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
25795#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
25796#define USB_OTG_GCCFG_SDET_Pos (2U)
25797#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
25798#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
25799#define USB_OTG_GCCFG_PS2DET_Pos (3U)
25800#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
25801#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
25802#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
25803#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
25804#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
25805#define USB_OTG_GCCFG_BCDEN_Pos (17U)
25806#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
25807#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
25808#define USB_OTG_GCCFG_DCDEN_Pos (18U)
25809#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
25810#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
25811#define USB_OTG_GCCFG_PDEN_Pos (19U)
25812#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
25813#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
25814#define USB_OTG_GCCFG_SDEN_Pos (20U)
25815#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
25816#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
25817#define USB_OTG_GCCFG_VBDEN_Pos (21U)
25818#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
25819#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
25821/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
25822#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
25823#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
25824#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk
25825#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
25826#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
25827#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk
25829/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
25830#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
25831#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
25832#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
25833#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
25834#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
25835#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
25837/******************** Bit definition forUSB_OTG_CID register ********************/
25838#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
25839#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
25840#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
25842/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
25843#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
25844#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
25845#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
25846#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
25847#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
25848#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
25849#define USB_OTG_GLPMCFG_BESL_Pos (2U)
25850#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
25851#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
25852#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
25853#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
25854#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
25855#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
25856#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
25857#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
25858#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
25859#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
25860#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
25861#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
25862#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
25863#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
25864#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
25865#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
25866#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
25867#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
25868#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
25869#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
25870#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
25871#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
25872#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
25873#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
25874#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
25875#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
25876#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
25877#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
25878#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
25879#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
25880#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
25881#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
25882#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
25883#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
25884#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
25885#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
25886#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
25887#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
25889/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
25890#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
25891#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
25892#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
25893#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
25894#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
25895#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
25896#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
25897#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
25898#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
25899#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
25900#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
25901#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
25902#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
25903#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
25904#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
25905#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
25906#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
25907#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
25908#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
25909#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
25910#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
25911#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
25912#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
25913#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
25914#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
25915#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
25916#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
25918/******************** Bit definition forUSB_OTG_HPRT register ********************/
25919#define USB_OTG_HPRT_PCSTS_Pos (0U)
25920#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
25921#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
25922#define USB_OTG_HPRT_PCDET_Pos (1U)
25923#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
25924#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
25925#define USB_OTG_HPRT_PENA_Pos (2U)
25926#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
25927#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
25928#define USB_OTG_HPRT_PENCHNG_Pos (3U)
25929#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
25930#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
25931#define USB_OTG_HPRT_POCA_Pos (4U)
25932#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
25933#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
25934#define USB_OTG_HPRT_POCCHNG_Pos (5U)
25935#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
25936#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
25937#define USB_OTG_HPRT_PRES_Pos (6U)
25938#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
25939#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
25940#define USB_OTG_HPRT_PSUSP_Pos (7U)
25941#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
25942#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
25943#define USB_OTG_HPRT_PRST_Pos (8U)
25944#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
25945#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
25947#define USB_OTG_HPRT_PLSTS_Pos (10U)
25948#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
25949#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
25950#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
25951#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
25952#define USB_OTG_HPRT_PPWR_Pos (12U)
25953#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
25954#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
25956#define USB_OTG_HPRT_PTCTL_Pos (13U)
25957#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
25958#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
25959#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
25960#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
25961#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
25962#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
25964#define USB_OTG_HPRT_PSPD_Pos (17U)
25965#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
25966#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
25967#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
25968#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
25970/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
25971#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
25972#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
25973#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
25974#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
25975#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
25976#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
25977#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
25978#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
25979#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
25980#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
25981#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
25982#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
25983#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
25984#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
25985#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
25986#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
25987#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
25988#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
25989#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
25990#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
25991#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
25992#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
25993#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
25994#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
25995#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
25996#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
25997#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
25998#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
25999#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
26000#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
26001#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
26002#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
26003#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
26005/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
26006#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
26007#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
26008#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
26009#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
26010#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
26011#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
26013/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
26014#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
26015#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
26016#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
26017#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
26018#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
26019#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
26020#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
26021#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
26022#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
26023#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
26024#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
26025#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
26027#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
26028#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
26029#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
26030#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
26031#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
26032#define USB_OTG_DIEPCTL_STALL_Pos (21U)
26033#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
26034#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
26036#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
26037#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
26038#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
26039#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
26040#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
26041#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
26042#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
26043#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
26044#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
26045#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
26046#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
26047#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
26048#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
26049#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
26050#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
26051#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
26052#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
26053#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
26054#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
26055#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
26056#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
26057#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
26058#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
26059#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
26060#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
26062/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
26063#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
26064#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
26065#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
26067#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
26068#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
26069#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
26070#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
26071#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
26072#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
26073#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
26074#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
26075#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
26076#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
26077#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
26078#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
26079#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
26081#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
26082#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
26083#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
26084#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
26085#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
26087#define USB_OTG_HCCHAR_MC_Pos (20U)
26088#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
26089#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
26090#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
26091#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
26093#define USB_OTG_HCCHAR_DAD_Pos (22U)
26094#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
26095#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
26096#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
26097#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
26098#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
26099#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
26100#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
26101#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
26102#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
26103#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
26104#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
26105#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
26106#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
26107#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
26108#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
26109#define USB_OTG_HCCHAR_CHENA_Pos (31U)
26110#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
26111#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
26113/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
26114
26115#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
26116#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
26117#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
26118#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26119#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26120#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26121#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26122#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26123#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26124#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
26126#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
26127#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
26128#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
26129#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26130#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26131#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26132#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26133#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26134#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26135#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
26137#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
26138#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
26139#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
26140#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
26141#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
26142#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
26143#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
26144#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
26145#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
26146#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
26147#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
26149/******************** Bit definition forUSB_OTG_HCINT register ********************/
26150#define USB_OTG_HCINT_XFRC_Pos (0U)
26151#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
26152#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
26153#define USB_OTG_HCINT_CHH_Pos (1U)
26154#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
26155#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
26156#define USB_OTG_HCINT_AHBERR_Pos (2U)
26157#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
26158#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
26159#define USB_OTG_HCINT_STALL_Pos (3U)
26160#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
26161#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
26162#define USB_OTG_HCINT_NAK_Pos (4U)
26163#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
26164#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
26165#define USB_OTG_HCINT_ACK_Pos (5U)
26166#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
26167#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
26168#define USB_OTG_HCINT_NYET_Pos (6U)
26169#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
26170#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
26171#define USB_OTG_HCINT_TXERR_Pos (7U)
26172#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
26173#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
26174#define USB_OTG_HCINT_BBERR_Pos (8U)
26175#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
26176#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
26177#define USB_OTG_HCINT_FRMOR_Pos (9U)
26178#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
26179#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
26180#define USB_OTG_HCINT_DTERR_Pos (10U)
26181#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
26182#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
26184/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
26185#define USB_OTG_DIEPINT_XFRC_Pos (0U)
26186#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
26187#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
26188#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
26189#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
26190#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
26191#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
26192#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
26193#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
26194#define USB_OTG_DIEPINT_TOC_Pos (3U)
26195#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
26196#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
26197#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
26198#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
26199#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
26200#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
26201#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
26202#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
26203#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
26204#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
26205#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
26206#define USB_OTG_DIEPINT_TXFE_Pos (7U)
26207#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
26208#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
26209#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
26210#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
26211#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
26212#define USB_OTG_DIEPINT_BNA_Pos (9U)
26213#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
26214#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
26215#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
26216#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
26217#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
26218#define USB_OTG_DIEPINT_BERR_Pos (12U)
26219#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
26220#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
26221#define USB_OTG_DIEPINT_NAK_Pos (13U)
26222#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
26223#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
26225/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
26226#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
26227#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
26228#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
26229#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
26230#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
26231#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
26232#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
26233#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
26234#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
26235#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
26236#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
26237#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
26238#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
26239#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
26240#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
26241#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
26242#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
26243#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
26244#define USB_OTG_HCINTMSK_NYET_Pos (6U)
26245#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
26246#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
26247#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
26248#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
26249#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
26250#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
26251#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
26252#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
26253#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
26254#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
26255#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
26256#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
26257#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
26258#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
26260/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
26261
26262#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
26263#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
26264#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
26265#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
26266#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
26267#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
26268#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
26269#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
26270#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
26271/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
26272#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
26273#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
26274#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
26275#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
26276#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
26277#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
26278#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
26279#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
26280#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
26281#define USB_OTG_HCTSIZ_DPID_Pos (29U)
26282#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
26283#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
26284#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
26285#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
26287/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
26288#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
26289#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
26290#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
26292/******************** Bit definition forUSB_OTG_HCDMA register ********************/
26293#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
26294#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
26295#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
26297/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
26298#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
26299#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
26300#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
26302/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
26303#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
26304#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
26305#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
26306#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
26307#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
26308#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
26310/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
26311
26312#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
26313#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
26314#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
26315#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
26316#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
26317#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
26318#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
26319#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
26320#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
26321#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
26322#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
26323#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
26324#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
26325#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
26326#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
26327#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
26328#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
26329#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
26330#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
26331#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
26332#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
26333#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
26334#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
26335#define USB_OTG_DOEPCTL_STALL_Pos (21U)
26336#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
26337#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
26338#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
26339#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
26340#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
26341#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
26342#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
26343#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
26344#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
26345#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
26346#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
26347#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
26348#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
26349#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
26351/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
26352#define USB_OTG_DOEPINT_XFRC_Pos (0U)
26353#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
26354#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
26355#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
26356#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
26357#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
26358#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
26359#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
26360#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
26361#define USB_OTG_DOEPINT_STUP_Pos (3U)
26362#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
26363#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
26364#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
26365#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
26366#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
26367#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
26368#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
26369#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
26370#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
26371#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
26372#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
26373#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
26374#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
26375#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
26376#define USB_OTG_DOEPINT_BERR_Pos (12U)
26377#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
26378#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk
26379#define USB_OTG_DOEPINT_NAK_Pos (13U)
26380#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
26381#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
26382#define USB_OTG_DOEPINT_NYET_Pos (14U)
26383#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
26384#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
26385#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
26386#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
26387#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
26389/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
26390
26391#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
26392#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
26393#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
26394#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
26395#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
26396#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
26398#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
26399#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
26400#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
26401#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
26402#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
26404/******************** Bit definition for PCGCCTL register ********************/
26405#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
26406#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
26407#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
26408#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
26409#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
26410#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
26411#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
26412#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
26413#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
26427/******************************* ADC Instances ********************************/
26428#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
26429 ((INSTANCE) == ADC2) || \
26430 ((INSTANCE) == ADC3))
26431
26432#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
26433
26434#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
26435 ((INSTANCE) == ADC3_COMMON))
26436
26437/******************************** COMP Instances ******************************/
26438#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
26439 ((INSTANCE) == COMP2))
26440
26441#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
26442/******************** COMP Instances with window mode capability **************/
26443#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
26444
26445
26446/******************************* CRC Instances ********************************/
26447#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
26448
26449/******************************* DAC Instances ********************************/
26450#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
26451/******************************* DCMI Instances *******************************/
26452#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
26453
26454/******************************* DELAYBLOCK Instances *******************************/
26455#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
26456 ((INSTANCE) == DLYB_SDMMC2) || \
26457 ((INSTANCE) == DLYB_QUADSPI))
26458/****************************** DFSDM Instances *******************************/
26459#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
26460 ((INSTANCE) == DFSDM1_Filter1) || \
26461 ((INSTANCE) == DFSDM1_Filter2) || \
26462 ((INSTANCE) == DFSDM1_Filter3))
26463
26464#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
26465 ((INSTANCE) == DFSDM1_Channel1) || \
26466 ((INSTANCE) == DFSDM1_Channel2) || \
26467 ((INSTANCE) == DFSDM1_Channel3) || \
26468 ((INSTANCE) == DFSDM1_Channel4) || \
26469 ((INSTANCE) == DFSDM1_Channel5) || \
26470 ((INSTANCE) == DFSDM1_Channel6) || \
26471 ((INSTANCE) == DFSDM1_Channel7))
26472/****************************** RAMECC Instances ******************************/
26473#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
26474 ((INSTANCE) == RAMECC1_Monitor2) || \
26475 ((INSTANCE) == RAMECC1_Monitor3) || \
26476 ((INSTANCE) == RAMECC1_Monitor4) || \
26477 ((INSTANCE) == RAMECC1_Monitor5) || \
26478 ((INSTANCE) == RAMECC2_Monitor1) || \
26479 ((INSTANCE) == RAMECC2_Monitor2) || \
26480 ((INSTANCE) == RAMECC2_Monitor3) || \
26481 ((INSTANCE) == RAMECC2_Monitor4) || \
26482 ((INSTANCE) == RAMECC2_Monitor5) || \
26483 ((INSTANCE) == RAMECC3_Monitor1) || \
26484 ((INSTANCE) == RAMECC3_Monitor2))
26485
26486/******************************** DMA Instances *******************************/
26487#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
26488 ((INSTANCE) == DMA1_Stream1) || \
26489 ((INSTANCE) == DMA1_Stream2) || \
26490 ((INSTANCE) == DMA1_Stream3) || \
26491 ((INSTANCE) == DMA1_Stream4) || \
26492 ((INSTANCE) == DMA1_Stream5) || \
26493 ((INSTANCE) == DMA1_Stream6) || \
26494 ((INSTANCE) == DMA1_Stream7) || \
26495 ((INSTANCE) == DMA2_Stream0) || \
26496 ((INSTANCE) == DMA2_Stream1) || \
26497 ((INSTANCE) == DMA2_Stream2) || \
26498 ((INSTANCE) == DMA2_Stream3) || \
26499 ((INSTANCE) == DMA2_Stream4) || \
26500 ((INSTANCE) == DMA2_Stream5) || \
26501 ((INSTANCE) == DMA2_Stream6) || \
26502 ((INSTANCE) == DMA2_Stream7) || \
26503 ((INSTANCE) == BDMA_Channel0) || \
26504 ((INSTANCE) == BDMA_Channel1) || \
26505 ((INSTANCE) == BDMA_Channel2) || \
26506 ((INSTANCE) == BDMA_Channel3) || \
26507 ((INSTANCE) == BDMA_Channel4) || \
26508 ((INSTANCE) == BDMA_Channel5) || \
26509 ((INSTANCE) == BDMA_Channel6) || \
26510 ((INSTANCE) == BDMA_Channel7))
26511
26512/****************************** BDMA CHANNEL Instances ***************************/
26513#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
26514 ((INSTANCE) == BDMA_Channel1) || \
26515 ((INSTANCE) == BDMA_Channel2) || \
26516 ((INSTANCE) == BDMA_Channel3) || \
26517 ((INSTANCE) == BDMA_Channel4) || \
26518 ((INSTANCE) == BDMA_Channel5) || \
26519 ((INSTANCE) == BDMA_Channel6) || \
26520 ((INSTANCE) == BDMA_Channel7))
26521
26522/****************************** DMA DMAMUX ALL Instances ***************************/
26523#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
26524 ((INSTANCE) == DMA1_Stream1) || \
26525 ((INSTANCE) == DMA1_Stream2) || \
26526 ((INSTANCE) == DMA1_Stream3) || \
26527 ((INSTANCE) == DMA1_Stream4) || \
26528 ((INSTANCE) == DMA1_Stream5) || \
26529 ((INSTANCE) == DMA1_Stream6) || \
26530 ((INSTANCE) == DMA1_Stream7) || \
26531 ((INSTANCE) == DMA2_Stream0) || \
26532 ((INSTANCE) == DMA2_Stream1) || \
26533 ((INSTANCE) == DMA2_Stream2) || \
26534 ((INSTANCE) == DMA2_Stream3) || \
26535 ((INSTANCE) == DMA2_Stream4) || \
26536 ((INSTANCE) == DMA2_Stream5) || \
26537 ((INSTANCE) == DMA2_Stream6) || \
26538 ((INSTANCE) == DMA2_Stream7) || \
26539 ((INSTANCE) == BDMA_Channel0) || \
26540 ((INSTANCE) == BDMA_Channel1) || \
26541 ((INSTANCE) == BDMA_Channel2) || \
26542 ((INSTANCE) == BDMA_Channel3) || \
26543 ((INSTANCE) == BDMA_Channel4) || \
26544 ((INSTANCE) == BDMA_Channel5) || \
26545 ((INSTANCE) == BDMA_Channel6) || \
26546 ((INSTANCE) == BDMA_Channel7))
26547
26548/****************************** BDMA DMAMUX Instances ***************************/
26549#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
26550 ((INSTANCE) == BDMA_Channel1) || \
26551 ((INSTANCE) == BDMA_Channel2) || \
26552 ((INSTANCE) == BDMA_Channel3) || \
26553 ((INSTANCE) == BDMA_Channel4) || \
26554 ((INSTANCE) == BDMA_Channel5) || \
26555 ((INSTANCE) == BDMA_Channel6) || \
26556 ((INSTANCE) == BDMA_Channel7))
26557
26558/****************************** DMA STREAM Instances ***************************/
26559#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
26560 ((INSTANCE) == DMA1_Stream1) || \
26561 ((INSTANCE) == DMA1_Stream2) || \
26562 ((INSTANCE) == DMA1_Stream3) || \
26563 ((INSTANCE) == DMA1_Stream4) || \
26564 ((INSTANCE) == DMA1_Stream5) || \
26565 ((INSTANCE) == DMA1_Stream6) || \
26566 ((INSTANCE) == DMA1_Stream7) || \
26567 ((INSTANCE) == DMA2_Stream0) || \
26568 ((INSTANCE) == DMA2_Stream1) || \
26569 ((INSTANCE) == DMA2_Stream2) || \
26570 ((INSTANCE) == DMA2_Stream3) || \
26571 ((INSTANCE) == DMA2_Stream4) || \
26572 ((INSTANCE) == DMA2_Stream5) || \
26573 ((INSTANCE) == DMA2_Stream6) || \
26574 ((INSTANCE) == DMA2_Stream7))
26575
26576/****************************** DMA DMAMUX Instances ***************************/
26577#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
26578 ((INSTANCE) == DMA1_Stream1) || \
26579 ((INSTANCE) == DMA1_Stream2) || \
26580 ((INSTANCE) == DMA1_Stream3) || \
26581 ((INSTANCE) == DMA1_Stream4) || \
26582 ((INSTANCE) == DMA1_Stream5) || \
26583 ((INSTANCE) == DMA1_Stream6) || \
26584 ((INSTANCE) == DMA1_Stream7) || \
26585 ((INSTANCE) == DMA2_Stream0) || \
26586 ((INSTANCE) == DMA2_Stream1) || \
26587 ((INSTANCE) == DMA2_Stream2) || \
26588 ((INSTANCE) == DMA2_Stream3) || \
26589 ((INSTANCE) == DMA2_Stream4) || \
26590 ((INSTANCE) == DMA2_Stream5) || \
26591 ((INSTANCE) == DMA2_Stream6) || \
26592 ((INSTANCE) == DMA2_Stream7))
26593
26594/******************************** DMA Request Generator Instances **************/
26595#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
26596 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
26597 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
26598 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
26599 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
26600 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
26601 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
26602 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
26603 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
26604 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
26605 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
26606 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
26607 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
26608 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
26609 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
26610 ((INSTANCE) == DMAMUX2_RequestGenerator7))
26611
26612/******************************* DMA2D Instances *******************************/
26613#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
26614
26615/******************************** MDMA Request Generator Instances **************/
26616#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
26617 ((INSTANCE) == MDMA_Channel1) || \
26618 ((INSTANCE) == MDMA_Channel2) || \
26619 ((INSTANCE) == MDMA_Channel3) || \
26620 ((INSTANCE) == MDMA_Channel4) || \
26621 ((INSTANCE) == MDMA_Channel5) || \
26622 ((INSTANCE) == MDMA_Channel6) || \
26623 ((INSTANCE) == MDMA_Channel7) || \
26624 ((INSTANCE) == MDMA_Channel8) || \
26625 ((INSTANCE) == MDMA_Channel9) || \
26626 ((INSTANCE) == MDMA_Channel10) || \
26627 ((INSTANCE) == MDMA_Channel11) || \
26628 ((INSTANCE) == MDMA_Channel12) || \
26629 ((INSTANCE) == MDMA_Channel13) || \
26630 ((INSTANCE) == MDMA_Channel14) || \
26631 ((INSTANCE) == MDMA_Channel15))
26632
26633/******************************* QUADSPI Instances *******************************/
26634#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
26635
26636/******************************* FDCAN Instances ******************************/
26637#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
26638 ((__INSTANCE__) == FDCAN2))
26639
26640#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
26641
26642/******************************* GPIO Instances *******************************/
26643#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
26644 ((INSTANCE) == GPIOB) || \
26645 ((INSTANCE) == GPIOC) || \
26646 ((INSTANCE) == GPIOD) || \
26647 ((INSTANCE) == GPIOE) || \
26648 ((INSTANCE) == GPIOF) || \
26649 ((INSTANCE) == GPIOG) || \
26650 ((INSTANCE) == GPIOH) || \
26651 ((INSTANCE) == GPIOI) || \
26652 ((INSTANCE) == GPIOJ) || \
26653 ((INSTANCE) == GPIOK))
26654
26655/******************************* GPIO AF Instances ****************************/
26656#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
26657
26658/**************************** GPIO Lock Instances *****************************/
26659/* On H7, all GPIO Bank support the Lock mechanism */
26660#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
26661
26662/******************************** HSEM Instances *******************************/
26663#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
26664/******************** Bit definition for HSEM_CR register *****************/
26665#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
26666#define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */
26667#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
26668#define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
26669#if defined(CORE_CM4)
26670#define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
26671#else /* CORE_CM7 */
26672#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
26673#endif /* CORE_CM4 */
26674
26675#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
26676#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
26677
26678#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
26679#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
26680
26681#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
26682#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
26683
26684/******************************** I2C Instances *******************************/
26685#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
26686 ((INSTANCE) == I2C2) || \
26687 ((INSTANCE) == I2C3) || \
26688 ((INSTANCE) == I2C4))
26689
26690/****************************** SMBUS Instances *******************************/
26691#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
26692 ((INSTANCE) == I2C2) || \
26693 ((INSTANCE) == I2C3) || \
26694 ((INSTANCE) == I2C4))
26695
26696/************** I2C Instances : wakeup capability from stop modes *************/
26697#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
26698
26699/******************************** I2S Instances *******************************/
26700#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
26701 ((INSTANCE) == SPI2) || \
26702 ((INSTANCE) == SPI3))
26703
26704/****************************** LTDC Instances ********************************/
26705#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
26706
26707/******************************* RNG Instances ********************************/
26708#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
26709
26710/****************************** RTC Instances *********************************/
26711#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
26712
26713/****************************** SDMMC Instances *********************************/
26714#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
26715 ((_INSTANCE_) == SDMMC2))
26716
26717/******************************** SPI Instances *******************************/
26718#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
26719 ((INSTANCE) == SPI2) || \
26720 ((INSTANCE) == SPI3) || \
26721 ((INSTANCE) == SPI4) || \
26722 ((INSTANCE) == SPI5) || \
26723 ((INSTANCE) == SPI6))
26724
26725#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
26726 ((INSTANCE) == SPI2) || \
26727 ((INSTANCE) == SPI3))
26728
26729/******************************** SWPMI Instances *****************************/
26730#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
26731
26732/****************** LPTIM Instances : All supported instances *****************/
26733#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
26734 ((INSTANCE) == LPTIM2) || \
26735 ((INSTANCE) == LPTIM3) || \
26736 ((INSTANCE) == LPTIM4) || \
26737 ((INSTANCE) == LPTIM5))
26738
26739/****************** LPTIM Instances : supporting encoder interface **************/
26740#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
26741 ((INSTANCE) == LPTIM2))
26742
26743/****************** TIM Instances : All supported instances *******************/
26744#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26745 ((INSTANCE) == TIM2) || \
26746 ((INSTANCE) == TIM3) || \
26747 ((INSTANCE) == TIM4) || \
26748 ((INSTANCE) == TIM5) || \
26749 ((INSTANCE) == TIM6) || \
26750 ((INSTANCE) == TIM7) || \
26751 ((INSTANCE) == TIM8) || \
26752 ((INSTANCE) == TIM12) || \
26753 ((INSTANCE) == TIM13) || \
26754 ((INSTANCE) == TIM14) || \
26755 ((INSTANCE) == TIM15) || \
26756 ((INSTANCE) == TIM16) || \
26757 ((INSTANCE) == TIM17))
26758
26759/************* TIM Instances : at least 1 capture/compare channel *************/
26760#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26761 ((INSTANCE) == TIM2) || \
26762 ((INSTANCE) == TIM3) || \
26763 ((INSTANCE) == TIM4) || \
26764 ((INSTANCE) == TIM5) || \
26765 ((INSTANCE) == TIM8) || \
26766 ((INSTANCE) == TIM12) || \
26767 ((INSTANCE) == TIM13) || \
26768 ((INSTANCE) == TIM14) || \
26769 ((INSTANCE) == TIM15) || \
26770 ((INSTANCE) == TIM16) || \
26771 ((INSTANCE) == TIM17))
26772
26773/************ TIM Instances : at least 2 capture/compare channels *************/
26774#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26775 ((INSTANCE) == TIM2) || \
26776 ((INSTANCE) == TIM3) || \
26777 ((INSTANCE) == TIM4) || \
26778 ((INSTANCE) == TIM5) || \
26779 ((INSTANCE) == TIM8) || \
26780 ((INSTANCE) == TIM12) || \
26781 ((INSTANCE) == TIM15))
26782
26783/************ TIM Instances : at least 3 capture/compare channels *************/
26784#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26785 ((INSTANCE) == TIM2) || \
26786 ((INSTANCE) == TIM3) || \
26787 ((INSTANCE) == TIM4) || \
26788 ((INSTANCE) == TIM5) || \
26789 ((INSTANCE) == TIM8))
26790
26791/************ TIM Instances : at least 4 capture/compare channels *************/
26792#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26793 ((INSTANCE) == TIM2) || \
26794 ((INSTANCE) == TIM3) || \
26795 ((INSTANCE) == TIM4) || \
26796 ((INSTANCE) == TIM5) || \
26797 ((INSTANCE) == TIM8))
26798
26799/************ TIM Instances : at least 5 capture/compare channels *************/
26800#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26801 ((INSTANCE) == TIM8))
26802/************ TIM Instances : at least 6 capture/compare channels *************/
26803#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26804 ((INSTANCE) == TIM8))
26805
26806/******************** TIM Instances : Advanced-control timers *****************/
26807#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
26808 ((__INSTANCE__) == TIM8))
26809
26810/******************** TIM Instances : Advanced-control timers *****************/
26811
26812/******************* TIM Instances : Timer input XOR function *****************/
26813#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26814 ((INSTANCE) == TIM2) || \
26815 ((INSTANCE) == TIM3) || \
26816 ((INSTANCE) == TIM4) || \
26817 ((INSTANCE) == TIM5) || \
26818 ((INSTANCE) == TIM8) || \
26819 ((INSTANCE) == TIM15))
26820
26821/****************** TIM Instances : DMA requests generation (UDE) *************/
26822#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26823 ((INSTANCE) == TIM2) || \
26824 ((INSTANCE) == TIM3) || \
26825 ((INSTANCE) == TIM4) || \
26826 ((INSTANCE) == TIM5) || \
26827 ((INSTANCE) == TIM6) || \
26828 ((INSTANCE) == TIM7) || \
26829 ((INSTANCE) == TIM8) || \
26830 ((INSTANCE) == TIM15) || \
26831 ((INSTANCE) == TIM16) || \
26832 ((INSTANCE) == TIM17))
26833
26834/************ TIM Instances : DMA requests generation (CCxDE) *****************/
26835#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26836 ((INSTANCE) == TIM2) || \
26837 ((INSTANCE) == TIM3) || \
26838 ((INSTANCE) == TIM4) || \
26839 ((INSTANCE) == TIM5) || \
26840 ((INSTANCE) == TIM8) || \
26841 ((INSTANCE) == TIM15) || \
26842 ((INSTANCE) == TIM16) || \
26843 ((INSTANCE) == TIM17))
26844
26845/************ TIM Instances : DMA requests generation (COMDE) *****************/
26846#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26847 ((INSTANCE) == TIM2) || \
26848 ((INSTANCE) == TIM3) || \
26849 ((INSTANCE) == TIM4) || \
26850 ((INSTANCE) == TIM5) || \
26851 ((INSTANCE) == TIM8) || \
26852 ((INSTANCE) == TIM15))
26853
26854/******************** TIM Instances : DMA burst feature ***********************/
26855#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26856 ((INSTANCE) == TIM2) || \
26857 ((INSTANCE) == TIM3) || \
26858 ((INSTANCE) == TIM4) || \
26859 ((INSTANCE) == TIM5) || \
26860 ((INSTANCE) == TIM8))
26861
26862/*************** TIM Instances : external trigger reamp input available *******/
26863#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26864 ((INSTANCE) == TIM2) || \
26865 ((INSTANCE) == TIM3) || \
26866 ((INSTANCE) == TIM4) || \
26867 ((INSTANCE) == TIM5) || \
26868 ((INSTANCE) == TIM8))
26869
26870/****************** TIM Instances : remapping capability **********************/
26871#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26872 ((INSTANCE) == TIM2) || \
26873 ((INSTANCE) == TIM3) || \
26874 ((INSTANCE) == TIM5) || \
26875 ((INSTANCE) == TIM8) || \
26876 ((INSTANCE) == TIM16) || \
26877 ((INSTANCE) == TIM17))
26878
26879/*************** TIM Instances : external trigger reamp input available *******/
26880#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26881 ((INSTANCE) == TIM2) || \
26882 ((INSTANCE) == TIM3) || \
26883 ((INSTANCE) == TIM5) || \
26884 ((INSTANCE) == TIM8))
26885
26886/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
26887#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26888 ((INSTANCE) == TIM2) || \
26889 ((INSTANCE) == TIM3) || \
26890 ((INSTANCE) == TIM4) || \
26891 ((INSTANCE) == TIM5) || \
26892 ((INSTANCE) == TIM6) || \
26893 ((INSTANCE) == TIM7) || \
26894 ((INSTANCE) == TIM8) || \
26895 ((INSTANCE) == TIM12) || \
26896 ((INSTANCE) == TIM15))
26897
26898/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
26899#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26900 ((INSTANCE) == TIM2) || \
26901 ((INSTANCE) == TIM3) || \
26902 ((INSTANCE) == TIM4) || \
26903 ((INSTANCE) == TIM5) || \
26904 ((INSTANCE) == TIM8) || \
26905 ((INSTANCE) == TIM12) || \
26906 ((INSTANCE) == TIM15))
26907
26908/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
26909#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26910 ((INSTANCE) == TIM8))
26911
26912/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
26913#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26914 ((INSTANCE) == TIM2) || \
26915 ((INSTANCE) == TIM3) || \
26916 ((INSTANCE) == TIM4) || \
26917 ((INSTANCE) == TIM5) || \
26918 ((INSTANCE) == TIM8) || \
26919 ((INSTANCE) == TIM15) || \
26920 ((INSTANCE) == TIM16) || \
26921 ((INSTANCE) == TIM17))
26922
26923/****************** TIM Instances : supporting commutation event *************/
26924#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26925 ((INSTANCE) == TIM8) || \
26926 ((INSTANCE) == TIM15) || \
26927 ((INSTANCE) == TIM16) || \
26928 ((INSTANCE) == TIM17))
26929
26930/****************** TIM Instances : supporting encoder interface **************/
26931#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
26932 ((__INSTANCE__) == TIM2) || \
26933 ((__INSTANCE__) == TIM3) || \
26934 ((__INSTANCE__) == TIM4) || \
26935 ((__INSTANCE__) == TIM5) || \
26936 ((__INSTANCE__) == TIM8))
26937
26938/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
26939#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
26940 ((INSTANCE) == TIM8))
26941/******************* TIM Instances : output(s) available **********************/
26942#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
26943 ((((INSTANCE) == TIM1) && \
26944 (((CHANNEL) == TIM_CHANNEL_1) || \
26945 ((CHANNEL) == TIM_CHANNEL_2) || \
26946 ((CHANNEL) == TIM_CHANNEL_3) || \
26947 ((CHANNEL) == TIM_CHANNEL_4) || \
26948 ((CHANNEL) == TIM_CHANNEL_5) || \
26949 ((CHANNEL) == TIM_CHANNEL_6))) \
26950 || \
26951 (((INSTANCE) == TIM2) && \
26952 (((CHANNEL) == TIM_CHANNEL_1) || \
26953 ((CHANNEL) == TIM_CHANNEL_2) || \
26954 ((CHANNEL) == TIM_CHANNEL_3) || \
26955 ((CHANNEL) == TIM_CHANNEL_4))) \
26956 || \
26957 (((INSTANCE) == TIM3) && \
26958 (((CHANNEL) == TIM_CHANNEL_1)|| \
26959 ((CHANNEL) == TIM_CHANNEL_2) || \
26960 ((CHANNEL) == TIM_CHANNEL_3) || \
26961 ((CHANNEL) == TIM_CHANNEL_4))) \
26962 || \
26963 (((INSTANCE) == TIM4) && \
26964 (((CHANNEL) == TIM_CHANNEL_1) || \
26965 ((CHANNEL) == TIM_CHANNEL_2) || \
26966 ((CHANNEL) == TIM_CHANNEL_3) || \
26967 ((CHANNEL) == TIM_CHANNEL_4))) \
26968 || \
26969 (((INSTANCE) == TIM5) && \
26970 (((CHANNEL) == TIM_CHANNEL_1) || \
26971 ((CHANNEL) == TIM_CHANNEL_2) || \
26972 ((CHANNEL) == TIM_CHANNEL_3) || \
26973 ((CHANNEL) == TIM_CHANNEL_4))) \
26974 || \
26975 (((INSTANCE) == TIM8) && \
26976 (((CHANNEL) == TIM_CHANNEL_1) || \
26977 ((CHANNEL) == TIM_CHANNEL_2) || \
26978 ((CHANNEL) == TIM_CHANNEL_3) || \
26979 ((CHANNEL) == TIM_CHANNEL_4) || \
26980 ((CHANNEL) == TIM_CHANNEL_5) || \
26981 ((CHANNEL) == TIM_CHANNEL_6))) \
26982 || \
26983 (((INSTANCE) == TIM12) && \
26984 (((CHANNEL) == TIM_CHANNEL_1) || \
26985 ((CHANNEL) == TIM_CHANNEL_2))) \
26986 || \
26987 (((INSTANCE) == TIM13) && \
26988 (((CHANNEL) == TIM_CHANNEL_1))) \
26989 || \
26990 (((INSTANCE) == TIM14) && \
26991 (((CHANNEL) == TIM_CHANNEL_1))) \
26992 || \
26993 (((INSTANCE) == TIM15) && \
26994 (((CHANNEL) == TIM_CHANNEL_1) || \
26995 ((CHANNEL) == TIM_CHANNEL_2))) \
26996 || \
26997 (((INSTANCE) == TIM16) && \
26998 (((CHANNEL) == TIM_CHANNEL_1))) \
26999 || \
27000 (((INSTANCE) == TIM17) && \
27001 (((CHANNEL) == TIM_CHANNEL_1))))
27002
27003/****************** TIM Instances : supporting the break function *************/
27004#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
27005 (((INSTANCE) == TIM1) || \
27006 ((INSTANCE) == TIM8) || \
27007 ((INSTANCE) == TIM15) || \
27008 ((INSTANCE) == TIM16) || \
27009 ((INSTANCE) == TIM17))
27010
27011/************** TIM Instances : supporting Break source selection *************/
27012#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
27013 ((INSTANCE) == TIM8))
27014
27015/****************** TIM Instances : supporting complementary output(s) ********/
27016#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
27017 ((((INSTANCE) == TIM1) && \
27018 (((CHANNEL) == TIM_CHANNEL_1) || \
27019 ((CHANNEL) == TIM_CHANNEL_2) || \
27020 ((CHANNEL) == TIM_CHANNEL_3))) \
27021 || \
27022 (((INSTANCE) == TIM8) && \
27023 (((CHANNEL) == TIM_CHANNEL_1) || \
27024 ((CHANNEL) == TIM_CHANNEL_2) || \
27025 ((CHANNEL) == TIM_CHANNEL_3))) \
27026 || \
27027 (((INSTANCE) == TIM15) && \
27028 ((CHANNEL) == TIM_CHANNEL_1)) \
27029 || \
27030 (((INSTANCE) == TIM16) && \
27031 ((CHANNEL) == TIM_CHANNEL_1)) \
27032 || \
27033 (((INSTANCE) == TIM17) && \
27034 ((CHANNEL) == TIM_CHANNEL_1)))
27035
27036/****************** TIM Instances : supporting counting mode selection ********/
27037#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
27038 (((INSTANCE) == TIM1) || \
27039 ((INSTANCE) == TIM2) || \
27040 ((INSTANCE) == TIM3) || \
27041 ((INSTANCE) == TIM4) || \
27042 ((INSTANCE) == TIM5) || \
27043 ((INSTANCE) == TIM8))
27044
27045/****************** TIM Instances : supporting repetition counter *************/
27046#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
27047 (((INSTANCE) == TIM1) || \
27048 ((INSTANCE) == TIM8) || \
27049 ((INSTANCE) == TIM15) || \
27050 ((INSTANCE) == TIM16) || \
27051 ((INSTANCE) == TIM17))
27052
27053/****************** TIM Instances : supporting synchronization ****************/
27054#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
27055 (((__INSTANCE__) == TIM1) || \
27056 ((__INSTANCE__) == TIM2) || \
27057 ((__INSTANCE__) == TIM3) || \
27058 ((__INSTANCE__) == TIM4) || \
27059 ((__INSTANCE__) == TIM5) || \
27060 ((__INSTANCE__) == TIM6) || \
27061 ((__INSTANCE__) == TIM8) || \
27062 ((__INSTANCE__) == TIM12) || \
27063 ((__INSTANCE__) == TIM15))
27064
27065/****************** TIM Instances : supporting clock division *****************/
27066#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
27067 (((INSTANCE) == TIM1) || \
27068 ((INSTANCE) == TIM2) || \
27069 ((INSTANCE) == TIM3) || \
27070 ((INSTANCE) == TIM4) || \
27071 ((INSTANCE) == TIM5) || \
27072 ((INSTANCE) == TIM8) || \
27073 ((INSTANCE) == TIM15) || \
27074 ((INSTANCE) == TIM16) || \
27075 ((INSTANCE) == TIM17))
27076
27077/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
27078#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
27079 (((INSTANCE) == TIM1) || \
27080 ((INSTANCE) == TIM2) || \
27081 ((INSTANCE) == TIM3) || \
27082 ((INSTANCE) == TIM4) || \
27083 ((INSTANCE) == TIM5) || \
27084 ((INSTANCE) == TIM8))
27085
27086/****************** TIM Instances : supporting external clock mode 2 **********/
27087#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
27088 (((INSTANCE) == TIM1) || \
27089 ((INSTANCE) == TIM2) || \
27090 ((INSTANCE) == TIM3) || \
27091 ((INSTANCE) == TIM4) || \
27092 ((INSTANCE) == TIM5) || \
27093 ((INSTANCE) == TIM8))
27094
27095/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
27096#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
27097 (((INSTANCE) == TIM1) || \
27098 ((INSTANCE) == TIM2) || \
27099 ((INSTANCE) == TIM3) || \
27100 ((INSTANCE) == TIM4) || \
27101 ((INSTANCE) == TIM5) || \
27102 ((INSTANCE) == TIM8) || \
27103 ((INSTANCE) == TIM12) || \
27104 ((INSTANCE) == TIM15))
27105
27106/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
27107#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
27108 (((INSTANCE) == TIM1) || \
27109 ((INSTANCE) == TIM2) || \
27110 ((INSTANCE) == TIM3) || \
27111 ((INSTANCE) == TIM4) || \
27112 ((INSTANCE) == TIM5) || \
27113 ((INSTANCE) == TIM8) || \
27114 ((INSTANCE) == TIM12) || \
27115 ((INSTANCE) == TIM15))
27116
27117/****************** TIM Instances : supporting OCxREF clear *******************/
27118#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
27119 (((INSTANCE) == TIM1) || \
27120 ((INSTANCE) == TIM2) || \
27121 ((INSTANCE) == TIM3))
27122
27123/****************** TIM Instances : TIM_32B_COUNTER ***************************/
27124#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
27125 (((INSTANCE) == TIM2) || \
27126 ((INSTANCE) == TIM5))
27127
27128/****************** TIM Instances : TIM_BKIN2 ***************************/
27129#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
27130 (((INSTANCE) == TIM1) || \
27131 ((INSTANCE) == TIM8))
27132
27133/****************** TIM Instances : supporting Hall sensor interface **********/
27134#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
27135 ((__INSTANCE__) == TIM2) || \
27136 ((__INSTANCE__) == TIM3) || \
27137 ((__INSTANCE__) == TIM4) || \
27138 ((__INSTANCE__) == TIM5) || \
27139 ((__INSTANCE__) == TIM15) || \
27140 ((__INSTANCE__) == TIM8))
27141
27142/****************************** HRTIM Instances *******************************/
27143#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
27144
27145/******************** USART Instances : Synchronous mode **********************/
27146#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27147 ((INSTANCE) == USART2) || \
27148 ((INSTANCE) == USART3) || \
27149 ((INSTANCE) == USART6))
27150
27151/******************** USART Instances : SPI slave mode ************************/
27152#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27153 ((INSTANCE) == USART2) || \
27154 ((INSTANCE) == USART3) || \
27155 ((INSTANCE) == USART6))
27156
27157/******************** UART Instances : Asynchronous mode **********************/
27158#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27159 ((INSTANCE) == USART2) || \
27160 ((INSTANCE) == USART3) || \
27161 ((INSTANCE) == UART4) || \
27162 ((INSTANCE) == UART5) || \
27163 ((INSTANCE) == USART6) || \
27164 ((INSTANCE) == UART7) || \
27165 ((INSTANCE) == UART8))
27166
27167/******************** UART Instances : FIFO mode.******************************/
27168#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27169 ((INSTANCE) == USART2) || \
27170 ((INSTANCE) == USART3) || \
27171 ((INSTANCE) == UART4) || \
27172 ((INSTANCE) == UART5) || \
27173 ((INSTANCE) == USART6) || \
27174 ((INSTANCE) == UART7) || \
27175 ((INSTANCE) == UART8))
27176
27177/****************** UART Instances : Auto Baud Rate detection *****************/
27178#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27179 ((INSTANCE) == USART2) || \
27180 ((INSTANCE) == USART3) || \
27181 ((INSTANCE) == UART4) || \
27182 ((INSTANCE) == UART5) || \
27183 ((INSTANCE) == USART6) || \
27184 ((INSTANCE) == UART7) || \
27185 ((INSTANCE) == UART8))
27186
27187/*********************** UART Instances : Driver Enable ***********************/
27188#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27189 ((INSTANCE) == USART2) || \
27190 ((INSTANCE) == USART3) || \
27191 ((INSTANCE) == UART4) || \
27192 ((INSTANCE) == UART5) || \
27193 ((INSTANCE) == USART6) || \
27194 ((INSTANCE) == UART7) || \
27195 ((INSTANCE) == UART8) || \
27196 ((INSTANCE) == LPUART1))
27197
27198/********************* UART Instances : Half-Duplex mode **********************/
27199#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27200 ((INSTANCE) == USART2) || \
27201 ((INSTANCE) == USART3) || \
27202 ((INSTANCE) == UART4) || \
27203 ((INSTANCE) == UART5) || \
27204 ((INSTANCE) == USART6) || \
27205 ((INSTANCE) == UART7) || \
27206 ((INSTANCE) == UART8) || \
27207 ((INSTANCE) == LPUART1))
27208
27209/******************* UART Instances : Hardware Flow control *******************/
27210#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27211 ((INSTANCE) == USART2) || \
27212 ((INSTANCE) == USART3) || \
27213 ((INSTANCE) == UART4) || \
27214 ((INSTANCE) == UART5) || \
27215 ((INSTANCE) == USART6) || \
27216 ((INSTANCE) == UART7) || \
27217 ((INSTANCE) == UART8) || \
27218 ((INSTANCE) == LPUART1))
27219
27220/************************* UART Instances : LIN mode **************************/
27221#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27222 ((INSTANCE) == USART2) || \
27223 ((INSTANCE) == USART3) || \
27224 ((INSTANCE) == UART4) || \
27225 ((INSTANCE) == UART5) || \
27226 ((INSTANCE) == USART6) || \
27227 ((INSTANCE) == UART7) || \
27228 ((INSTANCE) == UART8))
27229
27230/****************** UART Instances : Wake-up from Stop mode *******************/
27231#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27232 ((INSTANCE) == USART2) || \
27233 ((INSTANCE) == USART3) || \
27234 ((INSTANCE) == UART4) || \
27235 ((INSTANCE) == UART5) || \
27236 ((INSTANCE) == USART6) || \
27237 ((INSTANCE) == UART7) || \
27238 ((INSTANCE) == UART8) || \
27239 ((INSTANCE) == LPUART1))
27240
27241/************************* UART Instances : IRDA mode *************************/
27242#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27243 ((INSTANCE) == USART2) || \
27244 ((INSTANCE) == USART3) || \
27245 ((INSTANCE) == UART4) || \
27246 ((INSTANCE) == UART5) || \
27247 ((INSTANCE) == USART6) || \
27248 ((INSTANCE) == UART7) || \
27249 ((INSTANCE) == UART8))
27250
27251/********************* USART Instances : Smard card mode **********************/
27252#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
27253 ((INSTANCE) == USART2) || \
27254 ((INSTANCE) == USART3) || \
27255 ((INSTANCE) == USART6))
27256
27257/****************************** LPUART Instance *******************************/
27258#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
27259
27260/****************************** IWDG Instances ********************************/
27261#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
27262/****************************** USB Instances ********************************/
27263#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
27264
27265/****************************** WWDG Instances ********************************/
27266#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG1) || \
27267 ((INSTANCE) == WWDG2))
27268/****************************** MDIOS Instances ********************************/
27269#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
27270
27271/****************************** CEC Instances *********************************/
27272#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
27273
27274/****************************** SAI Instances ********************************/
27275#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
27276 ((INSTANCE) == SAI1_Block_B) || \
27277 ((INSTANCE) == SAI2_Block_A) || \
27278 ((INSTANCE) == SAI2_Block_B) || \
27279 ((INSTANCE) == SAI3_Block_A) || \
27280 ((INSTANCE) == SAI3_Block_B) || \
27281 ((INSTANCE) == SAI4_Block_A) || \
27282 ((INSTANCE) == SAI4_Block_B))
27283
27284/****************************** SPDIFRX Instances ********************************/
27285#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
27286
27287/****************************** OPAMP Instances *******************************/
27288#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
27289 ((INSTANCE) == OPAMP2))
27290
27291#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
27292
27293/*********************** USB OTG PCD Instances ********************************/
27294#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
27295 ((INSTANCE) == USB_OTG_HS))
27296
27297/*********************** USB OTG HCD Instances ********************************/
27298#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
27299 ((INSTANCE) == USB_OTG_HS))
27300
27301/******************************************************************************/
27302/* For a painless codes migration between the STM32H7xx device product */
27303/* lines, or with STM32F7xx devices the aliases defined below are put */
27304/* in place to overcome the differences in the interrupt handlers and IRQn */
27305/* definitions. No need to update developed interrupt code when moving */
27306/* across product lines within the same STM32H7 Family */
27307/******************************************************************************/
27308
27309/* Aliases for __IRQn */
27310#define HASH_RNG_IRQn RNG_IRQn
27311#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
27312#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
27313#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
27314#define PVD_IRQn PVD_AVD_IRQn
27315
27316
27317
27318/* Aliases for __IRQHandler */
27319#define HASH_RNG_IRQHandler RNG_IRQHandler
27320#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
27321#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
27322#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
27323#define PVD_IRQHandler PVD_AVD_IRQHandler
27324
27325/* Aliases for COMP __IRQHandler */
27326#define COMP_IRQHandler COMP1_IRQHandler
27327
27340#ifdef __cplusplus
27341}
27342#endif /* __cplusplus */
27343
27344#endif /* STM32H745xG_H */
27345
core_cm4.h
CMSIS Cortex-M4 Core Peripheral Access Layer Header File.
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h745xg.h:49
CRS_IRQn
@ CRS_IRQn
Definition: stm32h745xg.h:200
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32h745xg.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32h745xg.h:122
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32h745xg.h:69
MDIOS_IRQn
@ MDIOS_IRQn
Definition: stm32h745xg.h:177
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32h745xg.h:74
HRTIM1_TIMB_IRQn
@ HRTIM1_TIMB_IRQn
Definition: stm32h745xg.h:162
BDMA_Channel7_IRQn
@ BDMA_Channel7_IRQn
Definition: stm32h745xg.h:192
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32h745xg.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32h745xg.h:154
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32h745xg.h:133
HRTIM1_Master_IRQn
@ HRTIM1_Master_IRQn
Definition: stm32h745xg.h:160
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32h745xg.h:116
BDMA_Channel3_IRQn
@ BDMA_Channel3_IRQn
Definition: stm32h745xg.h:188
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32h745xg.h:127
LPTIM3_IRQn
@ LPTIM3_IRQn
Definition: stm32h745xg.h:195
LPTIM4_IRQn
@ LPTIM4_IRQn
Definition: stm32h745xg.h:196
TIM15_IRQn
@ TIM15_IRQn
Definition: stm32h745xg.h:173
BDMA_Channel1_IRQn
@ BDMA_Channel1_IRQn
Definition: stm32h745xg.h:186
OTG_FS_EP1_IN_IRQn
@ OTG_FS_EP1_IN_IRQn
Definition: stm32h745xg.h:156
UART7_IRQn
@ UART7_IRQn
Definition: stm32h745xg.h:139
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32h745xg.h:93
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32h745xg.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32h745xg.h:53
TIM17_IRQn
@ TIM17_IRQn
Definition: stm32h745xg.h:175
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32h745xg.h:144
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32h745xg.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32h745xg.h:89
LTDC_ER_IRQn
@ LTDC_ER_IRQn
Definition: stm32h745xg.h:146
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32h745xg.h:128
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32h745xg.h:103
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32h745xg.h:80
USART2_IRQn
@ USART2_IRQn
Definition: stm32h745xg.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32h745xg.h:119
HOLD_CORE_IRQn
@ HOLD_CORE_IRQn
Definition: stm32h745xg.h:203
HRTIM1_FLT_IRQn
@ HRTIM1_FLT_IRQn
Definition: stm32h745xg.h:166
BDMA_Channel4_IRQn
@ BDMA_Channel4_IRQn
Definition: stm32h745xg.h:189
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32h745xg.h:56
ADC_IRQn
@ ADC_IRQn
Definition: stm32h745xg.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32h745xg.h:111
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32h745xg.h:97
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32h745xg.h:85
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32h745xg.h:115
UART8_IRQn
@ UART8_IRQn
Definition: stm32h745xg.h:140
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32h745xg.h:81
RCC_IRQn
@ RCC_IRQn
Definition: stm32h745xg.h:66
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32h745xg.h:183
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32h745xg.h:194
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32h745xg.h:114
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32h745xg.h:132
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32h745xg.h:95
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32h745xg.h:149
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32h745xg.h:167
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32h745xg.h:106
JPEG_IRQn
@ JPEG_IRQn
Definition: stm32h745xg.h:178
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32h745xg.h:55
DMAMUX2_OVR_IRQn
@ DMAMUX2_OVR_IRQn
Definition: stm32h745xg.h:184
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32h745xg.h:153
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32h745xg.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32h745xg.h:131
SAI4_IRQn
@ SAI4_IRQn
Definition: stm32h745xg.h:202
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32h745xg.h:170
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32h745xg.h:86
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32h745xg.h:130
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32h745xg.h:54
DMAMUX1_OVR_IRQn
@ DMAMUX1_OVR_IRQn
Definition: stm32h745xg.h:159
CEC_IRQn
@ CEC_IRQn
Definition: stm32h745xg.h:151
LPTIM5_IRQn
@ LPTIM5_IRQn
Definition: stm32h745xg.h:197
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32h745xg.h:142
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32h745xg.h:57
RNG_IRQn
@ RNG_IRQn
Definition: stm32h745xg.h:137
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32h745xg.h:65
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32h745xg.h:172
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32h745xg.h:126
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32h745xg.h:61
HRTIM1_TIMA_IRQn
@ HRTIM1_TIMA_IRQn
Definition: stm32h745xg.h:161
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32h745xg.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32h745xg.h:90
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32h745xg.h:117
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32h745xg.h:134
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32h745xg.h:109
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32h745xg.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32h745xg.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32h745xg.h:141
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32h745xg.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32h745xg.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32h745xg.h:150
SPI6_IRQn
@ SPI6_IRQn
Definition: stm32h745xg.h:143
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32h745xg.h:158
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32h745xg.h:157
FPU_IRQn
@ FPU_IRQn
Definition: stm32h745xg.h:138
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32h745xg.h:104
USART6_IRQn
@ USART6_IRQn
Definition: stm32h745xg.h:129
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32h745xg.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32h745xg.h:135
HSEM1_IRQn
@ HSEM1_IRQn
Definition: stm32h745xg.h:181
OTG_FS_EP1_OUT_IRQn
@ OTG_FS_EP1_OUT_IRQn
Definition: stm32h745xg.h:155
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32h745xg.h:169
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32h745xg.h:52
BDMA_Channel6_IRQn
@ BDMA_Channel6_IRQn
Definition: stm32h745xg.h:191
CM7_SEV_IRQn
@ CM7_SEV_IRQn
Definition: stm32h745xg.h:124
FMC_IRQn
@ FMC_IRQn
Definition: stm32h745xg.h:108
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32h745xg.h:67
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32h745xg.h:71
CM4_SEV_IRQn
@ CM4_SEV_IRQn
Definition: stm32h745xg.h:125
HRTIM1_TIMD_IRQn
@ HRTIM1_TIMD_IRQn
Definition: stm32h745xg.h:164
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32h745xg.h:148
HRTIM1_TIMC_IRQn
@ HRTIM1_TIMC_IRQn
Definition: stm32h745xg.h:163
FDCAN_CAL_IRQn
@ FDCAN_CAL_IRQn
Definition: stm32h745xg.h:123
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32h745xg.h:118
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32h745xg.h:63
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32h745xg.h:87
UART5_IRQn
@ UART5_IRQn
Definition: stm32h745xg.h:113
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32h745xg.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32h745xg.h:147
DCMI_IRQn
@ DCMI_IRQn
Definition: stm32h745xg.h:136
WWDG_RST_IRQn
@ WWDG_RST_IRQn
Definition: stm32h745xg.h:199
WAKEUP_PIN_IRQn
@ WAKEUP_PIN_IRQn
Definition: stm32h745xg.h:204
HSEM2_IRQn
@ HSEM2_IRQn
Definition: stm32h745xg.h:182
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32h745xg.h:152
ECC_IRQn
@ ECC_IRQn
Definition: stm32h745xg.h:201
BDMA_Channel5_IRQn
@ BDMA_Channel5_IRQn
Definition: stm32h745xg.h:190
ETH_IRQn
@ ETH_IRQn
Definition: stm32h745xg.h:121
MDIOS_WKUP_IRQn
@ MDIOS_WKUP_IRQn
Definition: stm32h745xg.h:176
USART1_IRQn
@ USART1_IRQn
Definition: stm32h745xg.h:98
PVD_AVD_IRQn
@ PVD_AVD_IRQn
Definition: stm32h745xg.h:62
COMP_IRQn
@ COMP_IRQn
Definition: stm32h745xg.h:193
MDMA_IRQn
@ MDMA_IRQn
Definition: stm32h745xg.h:179
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32h745xg.h:70
BDMA_Channel0_IRQn
@ BDMA_Channel0_IRQn
Definition: stm32h745xg.h:185
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32h745xg.h:51
UART4_IRQn
@ UART4_IRQn
Definition: stm32h745xg.h:112
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32h745xg.h:105
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32h745xg.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32h745xg.h:120
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32h745xg.h:110
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32h745xg.h:107
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32h745xg.h:76
HRTIM1_TIME_IRQn
@ HRTIM1_TIME_IRQn
Definition: stm32h745xg.h:165
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32h745xg.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32h745xg.h:88
LTDC_IRQn
@ LTDC_IRQn
Definition: stm32h745xg.h:145
SAI3_IRQn
@ SAI3_IRQn
Definition: stm32h745xg.h:171
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32h745xg.h:82
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32h745xg.h:198
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32h745xg.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32h745xg.h:180
BDMA_Channel2_IRQn
@ BDMA_Channel2_IRQn
Definition: stm32h745xg.h:187
USART3_IRQn
@ USART3_IRQn
Definition: stm32h745xg.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32h745xg.h:102
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32h745xg.h:168
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32h745xg.h:83
TIM16_IRQn
@ TIM16_IRQn
Definition: stm32h745xg.h:174
FCR
#define FCR
FIFO Control Register (write)
Definition: uart.h:89
DR
#define DR
Bits definition of the Line Status Register (LSR)
Definition: uart.h:123
IER
#define IER
Interrupt Enable Register.
Definition: uart.h:85
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
AFR
#define AFR
Alternate Function register.
Definition: uart.h:99
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
ART_TypeDef
ART.
Definition: stm32h745xg.h:327
ART_TypeDef::CTR
__IO uint32_t CTR
Definition: stm32h745xg.h:328
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32h723xx.h:418
COMPOPT_TypeDef
Comparator.
Definition: stm32h723xx.h:1576
COMP_Common_TypeDef
Definition: stm32h723xx.h:1588
COMP_TypeDef
Definition: stm32h723xx.h:1583
CRC_TypeDef
CRC calculation unit.
Definition: stm32h723xx.h:442
CRS_TypeDef
Clock Recovery System.
Definition: stm32h723xx.h:456
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DBGMCU_TypeDef
Debug MCU.
Definition: stm32h723xx.h:531
DBGMCU_TypeDef::APB3FZ2
__IO uint32_t APB3FZ2
Definition: stm32h745xg.h:558
DBGMCU_TypeDef::APB2FZ2
__IO uint32_t APB2FZ2
Definition: stm32h745xg.h:564
DBGMCU_TypeDef::APB1HFZ2
__IO uint32_t APB1HFZ2
Definition: stm32h745xg.h:562
DBGMCU_TypeDef::APB4FZ2
__IO uint32_t APB4FZ2
Definition: stm32h745xg.h:566
DBGMCU_TypeDef::APB1LFZ2
__IO uint32_t APB1LFZ2
Definition: stm32h745xg.h:560
DCMI_TypeDef
DCMI.
Definition: stm32h723xx.h:561
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32h723xx.h:518
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32h723xx.h:496
DLYB_TypeDef
Delay Block DLYB.
Definition: stm32h723xx.h:1443
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32h723xx.h:686
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition: stm32h723xx.h:645
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32h723xx.h:601
DMA_TypeDef
Definition: stm32h723xx.h:611
ETH_TypeDef
Ethernet MAC.
Definition: stm32h723xx.h:717
EXTI_Core_TypeDef
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
Definition: stm32h723xx.h:936
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32h723xx.h:891
EXTI_TypeDef::C2EMR3
__IO uint32_t C2EMR3
Definition: stm32h745xg.h:926
EXTI_TypeDef::C2IMR3
__IO uint32_t C2IMR3
Definition: stm32h745xg.h:925
EXTI_TypeDef::RESERVED8
uint32_t RESERVED8
Definition: stm32h745xg.h:924
EXTI_TypeDef::RESERVED7
uint32_t RESERVED7
Definition: stm32h745xg.h:920
EXTI_TypeDef::C2EMR1
__IO uint32_t C2EMR1
Definition: stm32h745xg.h:918
EXTI_TypeDef::C2PR1
__IO uint32_t C2PR1
Definition: stm32h745xg.h:919
EXTI_TypeDef::C2PR3
__IO uint32_t C2PR3
Definition: stm32h745xg.h:927
EXTI_TypeDef::C2EMR2
__IO uint32_t C2EMR2
Definition: stm32h745xg.h:922
EXTI_TypeDef::C2PR2
__IO uint32_t C2PR2
Definition: stm32h745xg.h:923
EXTI_TypeDef::C2IMR1
__IO uint32_t C2IMR1
Definition: stm32h745xg.h:917
EXTI_TypeDef::C2IMR2
__IO uint32_t C2IMR2
Definition: stm32h745xg.h:921
FDCAN_ClockCalibrationUnit_TypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:403
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:315
FLASH_TypeDef
FLASH Registers.
Definition: stm32h723xx.h:956
FLASH_TypeDef::BOOT7_PRG
__IO uint32_t BOOT7_PRG
Definition: stm32h745xg.h:979
FLASH_TypeDef::BOOT7_CUR
__IO uint32_t BOOT7_CUR
Definition: stm32h745xg.h:978
FLASH_TypeDef::BOOT4_PRG
__IO uint32_t BOOT4_PRG
Definition: stm32h745xg.h:981
FLASH_TypeDef::BOOT4_CUR
__IO uint32_t BOOT4_CUR
Definition: stm32h745xg.h:980
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32h723xx.h:1015
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32h723xx.h:1006
FMC_Bank2_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32h723xx.h:1024
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32h723xx.h:1038
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5 and 6.
Definition: stm32h723xx.h:1053
GPIO_TypeDef
General Purpose I/O.
Definition: stm32h723xx.h:1066
GPV_TypeDef
Global Programmer View.
Definition: stm32h723xx.h:1966
GPV_TypeDef::AXI_INI7_WRITE_QOS
__IO uint32_t AXI_INI7_WRITE_QOS
Definition: stm32h745xg.h:2132
GPV_TypeDef::AXI_INI7_READ_QOS
__IO uint32_t AXI_INI7_READ_QOS
Definition: stm32h745xg.h:2131
GPV_TypeDef::AXI_INI7_FN_MOD
__IO uint32_t AXI_INI7_FN_MOD
Definition: stm32h745xg.h:2133
HRTIM_Common_TypeDef
Definition: stm32h742xx.h:1630
HRTIM_Master_TypeDef
High resolution Timer (HRTIM)
Definition: stm32h742xx.h:1579
HRTIM_Timerx_TypeDef
Definition: stm32h742xx.h:1597
HRTIM_TypeDef
Definition: stm32h742xx.h:1663
HSEM_Common_TypeDef
Definition: stm32h723xx.h:1467
HSEM_TypeDef
HW Semaphore HSEM.
Definition: stm32h723xx.h:1453
HSEM_TypeDef::C2IER
__IO uint32_t C2IER
Definition: stm32h745xg.h:1529
HSEM_TypeDef::C2MISR
__IO uint32_t C2MISR
Definition: stm32h745xg.h:1532
HSEM_TypeDef::C2ICR
__IO uint32_t C2ICR
Definition: stm32h745xg.h:1530
HSEM_TypeDef::C2ISR
__IO uint32_t C2ISR
Definition: stm32h745xg.h:1531
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32h723xx.h:1152
JPEG_TypeDef
JPEG Codec.
Definition: stm32h743xx.h:1126
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32h723xx.h:1559
LTDC_Layer_TypeDef
LCD-TFT Display layer x Controller.
Definition: stm32h723xx.h:1191
LTDC_TypeDef
LCD-TFT Display Controller.
Definition: stm32h723xx.h:1166
MDIOS_TypeDef
MDIOS.
Definition: stm32h723xx.h:1681
MDMA_Channel_TypeDef
Definition: stm32h723xx.h:664
MDMA_TypeDef
MDMA Controller.
Definition: stm32h723xx.h:659
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32h723xx.h:1083
PWR_TypeDef
Power Control.
Definition: stm32h723xx.h:1214
PWR_TypeDef::CPU2CR
__IO uint32_t CPU2CR
Definition: stm32h745xg.h:1264
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32h742xx.h:1415
RAMECC_MonitorTypeDef
RAM_ECC_Specific_Registers.
Definition: stm32h723xx.h:1644
RAMECC_TypeDef
Definition: stm32h723xx.h:1654
RCC_Core_TypeDef
Definition: stm32h745xg.h:1347
RCC_Core_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32h745xg.h:1356
RCC_Core_TypeDef::APB1HENR
__IO uint32_t APB1HENR
Definition: stm32h745xg.h:1355
RCC_Core_TypeDef::APB1LENR
__IO uint32_t APB1LENR
Definition: stm32h745xg.h:1354
RCC_Core_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32h745xg.h:1359
RCC_Core_TypeDef::AHB4ENR
__IO uint32_t AHB4ENR
Definition: stm32h745xg.h:1352
RCC_Core_TypeDef::APB3LPENR
__IO uint32_t APB3LPENR
Definition: stm32h745xg.h:1363
RCC_Core_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32h745xg.h:1360
RCC_Core_TypeDef::APB4ENR
__IO uint32_t APB4ENR
Definition: stm32h745xg.h:1357
RCC_Core_TypeDef::RESERVED9
uint32_t RESERVED9
Definition: stm32h745xg.h:1358
RCC_Core_TypeDef::APB1LLPENR
__IO uint32_t APB1LLPENR
Definition: stm32h745xg.h:1364
RCC_Core_TypeDef::AHB4LPENR
__IO uint32_t AHB4LPENR
Definition: stm32h745xg.h:1362
RCC_Core_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32h745xg.h:1350
RCC_Core_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32h745xg.h:1351
RCC_Core_TypeDef::RSR
__IO uint32_t RSR
Definition: stm32h745xg.h:1348
RCC_Core_TypeDef::APB4LPENR
__IO uint32_t APB4LPENR
Definition: stm32h745xg.h:1367
RCC_Core_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32h745xg.h:1361
RCC_Core_TypeDef::APB1HLPENR
__IO uint32_t APB1HLPENR
Definition: stm32h745xg.h:1365
RCC_Core_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32h745xg.h:1366
RCC_Core_TypeDef::APB3ENR
__IO uint32_t APB3ENR
Definition: stm32h745xg.h:1353
RCC_Core_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32h745xg.h:1349
RCC_TypeDef
Reset and Clock Control.
Definition: stm32h723xx.h:1233
RNG_TypeDef
RNG.
Definition: stm32h723xx.h:1668
RTC_TypeDef
Real-Time Clock.
Definition: stm32h723xx.h:1307
SAI_Block_TypeDef
Definition: stm32h723xx.h:1375
SAI_TypeDef
Serial Audio Interface.
Definition: stm32h723xx.h:1367
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32h723xx.h:1408
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32h723xx.h:1391
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
SYSCFG_TypeDef
System configuration controller.
Definition: stm32h723xx.h:1094
TIM_TypeDef
TIM.
Definition: stm32h723xx.h:1525
TTCAN_TypeDef
TTFD Controller Area Network.
Definition: stm32h723xx.h:376
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32h723xx.h:1596
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32h723xx.h:1796
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32h723xx.h:1761
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32h723xx.h:1869
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32h723xx.h:1855
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32h723xx.h:1824
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32h723xx.h:1840
VREFBUF_TypeDef
VREFBUF.
Definition: stm32h723xx.h:304
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32h723xx.h:1633
_pr
Definition: hexdump.h:39
system_stm32h7xx.h
CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
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