RTEMS 6.1-rc1
samv71q20.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71Q20_
31#define _SAMV71Q20_
32
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/* CMSIS DEFINITIONS FOR SAMV71Q20 */
52/* ************************************************************************** */
55
57typedef enum IRQn
58{
59/****** Cortex-M7 Processor Exceptions Numbers ******************************/
60 NonMaskableInt_IRQn = -14,
61 HardFault_IRQn = -13,
62 MemoryManagement_IRQn = -12,
63 BusFault_IRQn = -11,
64 UsageFault_IRQn = -10,
65 SVCall_IRQn = -5,
66 DebugMonitor_IRQn = -4,
67 PendSV_IRQn = -2,
68 SysTick_IRQn = -1,
69/****** SAMV71Q20 specific Interrupt Numbers *********************************/
70
71 SUPC_IRQn = 0,
72 RSTC_IRQn = 1,
73 RTC_IRQn = 2,
74 RTT_IRQn = 3,
75 WDT_IRQn = 4,
76 PMC_IRQn = 5,
77 EFC_IRQn = 6,
78 UART0_IRQn = 7,
79 UART1_IRQn = 8,
80 PIOA_IRQn = 10,
81 PIOB_IRQn = 11,
82 PIOC_IRQn = 12,
83 USART0_IRQn = 13,
84 USART1_IRQn = 14,
85 USART2_IRQn = 15,
86 PIOD_IRQn = 16,
87 PIOE_IRQn = 17,
88 HSMCI_IRQn = 18,
89 TWIHS0_IRQn = 19,
90 TWIHS1_IRQn = 20,
91 SPI0_IRQn = 21,
92 SSC_IRQn = 22,
93 TC0_IRQn = 23,
94 TC1_IRQn = 24,
95 TC2_IRQn = 25,
96 TC3_IRQn = 26,
97 TC4_IRQn = 27,
98 TC5_IRQn = 28,
99 AFEC0_IRQn = 29,
100 DACC_IRQn = 30,
101 PWM0_IRQn = 31,
102 ICM_IRQn = 32,
103 ACC_IRQn = 33,
104 USBHS_IRQn = 34,
105 MCAN0_IRQn = 35,
106 MCAN1_IRQn = 37,
107 GMAC_IRQn = 39,
108 AFEC1_IRQn = 40,
109 TWIHS2_IRQn = 41,
110 SPI1_IRQn = 42,
111 QSPI_IRQn = 43,
112 UART2_IRQn = 44,
113 UART3_IRQn = 45,
114 UART4_IRQn = 46,
115 TC6_IRQn = 47,
116 TC7_IRQn = 48,
117 TC8_IRQn = 49,
118 TC9_IRQn = 50,
119 TC10_IRQn = 51,
120 TC11_IRQn = 52,
121 MLB_IRQn = 53,
122 AES_IRQn = 56,
123 TRNG_IRQn = 57,
124 XDMAC_IRQn = 58,
125 ISI_IRQn = 59,
126 PWM1_IRQn = 60,
127 SDRAMC_IRQn = 62,
128 RSWDT_IRQn = 63,
130 PERIPH_COUNT_IRQn = 64
131} IRQn_Type;
132
133typedef struct _DeviceVectors
134{
135 /* Stack pointer */
136 void* pvStack;
137
138 /* Cortex-M handlers */
139 void* pfnReset_Handler;
140 void* pfnNMI_Handler;
141 void* pfnHardFault_Handler;
142 void* pfnMemManage_Handler;
143 void* pfnBusFault_Handler;
144 void* pfnUsageFault_Handler;
145 void* pfnReserved1_Handler;
146 void* pfnReserved2_Handler;
147 void* pfnReserved3_Handler;
148 void* pfnReserved4_Handler;
149 void* pfnSVC_Handler;
150 void* pfnDebugMon_Handler;
151 void* pfnReserved5_Handler;
152 void* pfnPendSV_Handler;
153 void* pfnSysTick_Handler;
154
155 /* Peripheral handlers */
156 void* pfnSUPC_Handler; /* 0 Supply Controller */
157 void* pfnRSTC_Handler; /* 1 Reset Controller */
158 void* pfnRTC_Handler; /* 2 Real Time Clock */
159 void* pfnRTT_Handler; /* 3 Real Time Timer */
160 void* pfnWDT_Handler; /* 4 Watchdog Timer */
161 void* pfnPMC_Handler; /* 5 Power Management Controller */
162 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
163 void* pfnUART0_Handler; /* 7 UART 0 */
164 void* pfnUART1_Handler; /* 8 UART 1 */
165 void* pvReserved9;
166 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
167 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
168 void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */
169 void* pfnUSART0_Handler; /* 13 USART 0 */
170 void* pfnUSART1_Handler; /* 14 USART 1 */
171 void* pfnUSART2_Handler; /* 15 USART 2 */
172 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
173 void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */
174 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
175 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
176 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
177 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
178 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
179 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
180 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
181 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
182 void* pfnTC3_Handler; /* 26 Timer/Counter 3 */
183 void* pfnTC4_Handler; /* 27 Timer/Counter 4 */
184 void* pfnTC5_Handler; /* 28 Timer/Counter 5 */
185 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
186 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
187 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
188 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
189 void* pfnACC_Handler; /* 33 Analog Comparator */
190 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
191 void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */
192 void* pvReserved36;
193 void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */
194 void* pvReserved38;
195 void* pfnGMAC_Handler; /* 39 Ethernet MAC */
196 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
197 void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
198 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
199 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
200 void* pfnUART2_Handler; /* 44 UART 2 */
201 void* pfnUART3_Handler; /* 45 UART 3 */
202 void* pfnUART4_Handler; /* 46 UART 4 */
203 void* pfnTC6_Handler; /* 47 Timer/Counter 6 */
204 void* pfnTC7_Handler; /* 48 Timer/Counter 7 */
205 void* pfnTC8_Handler; /* 49 Timer/Counter 8 */
206 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
207 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
208 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
209 void* pfnMLB_Handler; /* 53 MediaLB */
210 void* pvReserved54;
211 void* pvReserved55;
212 void* pfnAES_Handler; /* 56 AES */
213 void* pfnTRNG_Handler; /* 57 True Random Generator */
214 void* pfnXDMAC_Handler; /* 58 DMA */
215 void* pfnISI_Handler; /* 59 Camera Interface */
216 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
217 void* pvReserved61;
218 void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */
219 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
220} DeviceVectors;
221
222/* Cortex-M7 core handlers */
223void Reset_Handler ( void );
224void NMI_Handler ( void );
225void HardFault_Handler ( void );
226void MemManage_Handler ( void );
227void BusFault_Handler ( void );
228void UsageFault_Handler ( void );
229void SVC_Handler ( void );
230void DebugMon_Handler ( void );
231void PendSV_Handler ( void );
232void SysTick_Handler ( void );
233
234/* Peripherals handlers */
235void ACC_Handler ( void );
236void AES_Handler ( void );
237void AFEC0_Handler ( void );
238void AFEC1_Handler ( void );
239void DACC_Handler ( void );
240void EFC_Handler ( void );
241void GMAC_Handler ( void );
242void HSMCI_Handler ( void );
243void ICM_Handler ( void );
244void ISI_Handler ( void );
245void MCAN0_Handler ( void );
246void MCAN1_Handler ( void );
247void MLB_Handler ( void );
248void PIOA_Handler ( void );
249void PIOB_Handler ( void );
250void PIOC_Handler ( void );
251void PIOD_Handler ( void );
252void PIOE_Handler ( void );
253void PMC_Handler ( void );
254void PWM0_Handler ( void );
255void PWM1_Handler ( void );
256void QSPI_Handler ( void );
257void RSTC_Handler ( void );
258void RSWDT_Handler ( void );
259void RTC_Handler ( void );
260void RTT_Handler ( void );
261void SDRAMC_Handler ( void );
262void SPI0_Handler ( void );
263void SPI1_Handler ( void );
264void SSC_Handler ( void );
265void SUPC_Handler ( void );
266void TC0_Handler ( void );
267void TC1_Handler ( void );
268void TC2_Handler ( void );
269void TC3_Handler ( void );
270void TC4_Handler ( void );
271void TC5_Handler ( void );
272void TC6_Handler ( void );
273void TC7_Handler ( void );
274void TC8_Handler ( void );
275void TC9_Handler ( void );
276void TC10_Handler ( void );
277void TC11_Handler ( void );
278void TRNG_Handler ( void );
279void TWIHS0_Handler ( void );
280void TWIHS1_Handler ( void );
281void TWIHS2_Handler ( void );
282void UART0_Handler ( void );
283void UART1_Handler ( void );
284void UART2_Handler ( void );
285void UART3_Handler ( void );
286void UART4_Handler ( void );
287void USART0_Handler ( void );
288void USART1_Handler ( void );
289void USART2_Handler ( void );
290void USBHS_Handler ( void );
291void WDT_Handler ( void );
292void XDMAC_Handler ( void );
293
298#define __CM7_REV 0x0000
299#define __MPU_PRESENT 1
300#define __NVIC_PRIO_BITS 3
301#define __FPU_PRESENT 1
302#define __FPU_DP 1
303#define __ICACHE_PRESENT 1
304#define __DCACHE_PRESENT 1
305#define __DTCM_PRESENT 1
306#define __ITCM_PRESENT 1
307#define __Vendor_SysTickConfig 0
309/*
310 * \brief CMSIS includes
311 */
312
313#include <core_cm7.h>
314#if !defined DONT_USE_CMSIS_INIT
315#include "system_samv71.h"
316#endif /* DONT_USE_CMSIS_INIT */
317
320/* ************************************************************************** */
322/* ************************************************************************** */
325
326#include "component/component_acc.h"
327#include "component/component_aes.h"
328#include "component/component_afec.h"
329#include "component/component_chipid.h"
330#include "component/component_dacc.h"
331#include "component/component_efc.h"
332#include "component/component_gmac.h"
333#include "component/component_gpbr.h"
334#include "component/component_hsmci.h"
335#include "component/component_icm.h"
336#include "component/component_isi.h"
337#include "component/component_matrix.h"
338#include "component/component_mcan.h"
339#include "component/component_mlb.h"
340#include "component/component_pio.h"
341#include "component/component_pmc.h"
342#include "component/component_pwm.h"
343#include "component/component_qspi.h"
344#include "component/component_rstc.h"
345#include "component/component_rswdt.h"
346#include "component/component_rtc.h"
347#include "component/component_rtt.h"
348#include "component/component_sdramc.h"
349#include "component/component_smc.h"
350#include "component/component_spi.h"
351#include "component/component_ssc.h"
352#include "component/component_supc.h"
353#include "component/component_tc.h"
354#include "component/component_trng.h"
355#include "component/component_twihs.h"
356#include "component/component_uart.h"
357#include "component/component_usart.h"
358#include "component/component_usbhs.h"
359#include "component/component_utmi.h"
360#include "component/component_wdt.h"
361#include "component/component_xdmac.h"
364#ifndef __rtems__
365/* ************************************************************************** */
366/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */
367/* ************************************************************************** */
370
371#include "instance/instance_hsmci.h"
372#include "instance/instance_ssc.h"
373#include "instance/instance_spi0.h"
374#include "instance/instance_tc0.h"
375#include "instance/instance_tc1.h"
376#include "instance/instance_tc2.h"
377#include "instance/instance_twihs0.h"
378#include "instance/instance_twihs1.h"
379#include "instance/instance_pwm0.h"
380#include "instance/instance_usart0.h"
381#include "instance/instance_usart1.h"
382#include "instance/instance_usart2.h"
383#include "instance/instance_mcan0.h"
384#include "instance/instance_mcan1.h"
385#include "instance/instance_usbhs.h"
386#include "instance/instance_afec0.h"
387#include "instance/instance_dacc.h"
388#include "instance/instance_acc.h"
389#include "instance/instance_icm.h"
390#include "instance/instance_isi.h"
391#include "instance/instance_gmac.h"
392#include "instance/instance_tc3.h"
393#include "instance/instance_spi1.h"
394#include "instance/instance_pwm1.h"
395#include "instance/instance_twihs2.h"
396#include "instance/instance_afec1.h"
397#include "instance/instance_mlb.h"
398#include "instance/instance_aes.h"
399#include "instance/instance_trng.h"
400#include "instance/instance_xdmac.h"
401#include "instance/instance_qspi.h"
402#include "instance/instance_smc.h"
403#include "instance/instance_sdramc.h"
404#include "instance/instance_matrix.h"
405#include "instance/instance_utmi.h"
406#include "instance/instance_pmc.h"
407#include "instance/instance_uart0.h"
408#include "instance/instance_chipid.h"
409#include "instance/instance_uart1.h"
410#include "instance/instance_efc.h"
411#include "instance/instance_pioa.h"
412#include "instance/instance_piob.h"
413#include "instance/instance_pioc.h"
414#include "instance/instance_piod.h"
415#include "instance/instance_pioe.h"
416#include "instance/instance_rstc.h"
417#include "instance/instance_supc.h"
418#include "instance/instance_rtt.h"
419#include "instance/instance_wdt.h"
420#include "instance/instance_rtc.h"
421#include "instance/instance_gpbr.h"
422#include "instance/instance_rswdt.h"
423#include "instance/instance_uart2.h"
424#include "instance/instance_uart3.h"
425#include "instance/instance_uart4.h"
427#endif /* __rtems__ */
428
429/* ************************************************************************** */
430/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */
431/* ************************************************************************** */
434
435#define ID_SUPC ( 0)
436#define ID_RSTC ( 1)
437#define ID_RTC ( 2)
438#define ID_RTT ( 3)
439#define ID_WDT ( 4)
440#define ID_PMC ( 5)
441#define ID_EFC ( 6)
442#define ID_UART0 ( 7)
443#define ID_UART1 ( 8)
444#define ID_SMC ( 9)
445#define ID_PIOA (10)
446#define ID_PIOB (11)
447#define ID_PIOC (12)
448#define ID_USART0 (13)
449#define ID_USART1 (14)
450#define ID_USART2 (15)
451#define ID_PIOD (16)
452#define ID_PIOE (17)
453#define ID_HSMCI (18)
454#define ID_TWIHS0 (19)
455#define ID_TWIHS1 (20)
456#define ID_SPI0 (21)
457#define ID_SSC (22)
458#define ID_TC0 (23)
459#define ID_TC1 (24)
460#define ID_TC2 (25)
461#define ID_TC3 (26)
462#define ID_TC4 (27)
463#define ID_TC5 (28)
464#define ID_AFEC0 (29)
465#define ID_DACC (30)
466#define ID_PWM0 (31)
467#define ID_ICM (32)
468#define ID_ACC (33)
469#define ID_USBHS (34)
470#define ID_MCAN0 (35)
471#define ID_MCAN1 (37)
472#define ID_GMAC (39)
473#define ID_AFEC1 (40)
474#define ID_TWIHS2 (41)
475#define ID_SPI1 (42)
476#define ID_QSPI (43)
477#define ID_UART2 (44)
478#define ID_UART3 (45)
479#define ID_UART4 (46)
480#define ID_TC6 (47)
481#define ID_TC7 (48)
482#define ID_TC8 (49)
483#define ID_TC9 (50)
484#define ID_TC10 (51)
485#define ID_TC11 (52)
486#define ID_MLB (53)
487#define ID_AES (56)
488#define ID_TRNG (57)
489#define ID_XDMAC (58)
490#define ID_ISI (59)
491#define ID_PWM1 (60)
492#define ID_SDRAMC (62)
493#define ID_RSWDT (63)
495#define ID_PERIPH_COUNT (64)
497
498/* ************************************************************************** */
499/* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */
500/* ************************************************************************** */
503
504#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
505#define HSMCI (0x40000000U)
506#define SSC (0x40004000U)
507#define SPI0 (0x40008000U)
508#define TC0 (0x4000C000U)
509#define TC1 (0x40010000U)
510#define TC2 (0x40014000U)
511#define TWIHS0 (0x40018000U)
512#define TWIHS1 (0x4001C000U)
513#define PWM0 (0x40020000U)
514#define USART0 (0x40024000U)
515#define USART1 (0x40028000U)
516#define USART2 (0x4002C000U)
517#define MCAN0 (0x40030000U)
518#define MCAN1 (0x40034000U)
519#define USBHS (0x40038000U)
520#define AFEC0 (0x4003C000U)
521#define DACC (0x40040000U)
522#define ACC (0x40044000U)
523#define ICM (0x40048000U)
524#define ISI (0x4004C000U)
525#define GMAC (0x40050000U)
526#define TC3 (0x40054000U)
527#define SPI1 (0x40058000U)
528#define PWM1 (0x4005C000U)
529#define TWIHS2 (0x40060000U)
530#define AFEC1 (0x40064000U)
531#define MLB (0x40068000U)
532#define AES (0x4006C000U)
533#define TRNG (0x40070000U)
534#define XDMAC (0x40078000U)
535#define QSPI (0x4007C000U)
536#define SMC (0x40080000U)
537#define SDRAMC (0x40084000U)
538#define MATRIX (0x40088000U)
539#define UTMI (0x400E0400U)
540#define PMC (0x400E0600U)
541#define UART0 (0x400E0800U)
542#define CHIPID (0x400E0940U)
543#define UART1 (0x400E0A00U)
544#define EFC (0x400E0C00U)
545#define PIOA (0x400E0E00U)
546#define PIOB (0x400E1000U)
547#define PIOC (0x400E1200U)
548#define PIOD (0x400E1400U)
549#define PIOE (0x400E1600U)
550#define RSTC (0x400E1800U)
551#define SUPC (0x400E1810U)
552#define RTT (0x400E1830U)
553#define WDT (0x400E1850U)
554#define RTC (0x400E1860U)
555#define GPBR (0x400E1890U)
556#define RSWDT (0x400E1900U)
557#define UART2 (0x400E1A00U)
558#define UART3 (0x400E1C00U)
559#define UART4 (0x400E1E00U)
560#else
561#define HSMCI ((Hsmci *)0x40000000U)
562#define SSC ((Ssc *)0x40004000U)
563#define SPI0 ((Spi *)0x40008000U)
564#define TC0 ((Tc *)0x4000C000U)
565#define TC1 ((Tc *)0x40010000U)
566#define TC2 ((Tc *)0x40014000U)
567#define TWIHS0 ((Twihs *)0x40018000U)
568#define TWIHS1 ((Twihs *)0x4001C000U)
569#define PWM0 ((Pwm *)0x40020000U)
570#define USART0 ((Usart *)0x40024000U)
571#define USART1 ((Usart *)0x40028000U)
572#define USART2 ((Usart *)0x4002C000U)
573#define MCAN0 ((Mcan *)0x40030000U)
574#define MCAN1 ((Mcan *)0x40034000U)
575#define USBHS ((Usbhs *)0x40038000U)
576#define AFEC0 ((Afec *)0x4003C000U)
577#define DACC ((Dacc *)0x40040000U)
578#define ACC ((Acc *)0x40044000U)
579#define ICM ((Icm *)0x40048000U)
580#define ISI ((Isi *)0x4004C000U)
581#define GMAC ((Gmac *)0x40050000U)
582#define TC3 ((Tc *)0x40054000U)
583#define SPI1 ((Spi *)0x40058000U)
584#define PWM1 ((Pwm *)0x4005C000U)
585#define TWIHS2 ((Twihs *)0x40060000U)
586#define AFEC1 ((Afec *)0x40064000U)
587#define MLB ((Mlb *)0x40068000U)
588#define AES ((Aes *)0x4006C000U)
589#define TRNG ((Trng *)0x40070000U)
590#define XDMAC ((Xdmac *)0x40078000U)
591#define QSPI ((Qspi *)0x4007C000U)
592#define SMC ((Smc *)0x40080000U)
593#define SDRAMC ((Sdramc *)0x40084000U)
594#define MATRIX ((Matrix *)0x40088000U)
595#define UTMI ((Utmi *)0x400E0400U)
596#define PMC ((Pmc *)0x400E0600U)
597#define UART0 ((Uart *)0x400E0800U)
598#define CHIPID ((Chipid *)0x400E0940U)
599#define UART1 ((Uart *)0x400E0A00U)
600#define EFC ((Efc *)0x400E0C00U)
601#define PIOA ((Pio *)0x400E0E00U)
602#define PIOB ((Pio *)0x400E1000U)
603#define PIOC ((Pio *)0x400E1200U)
604#define PIOD ((Pio *)0x400E1400U)
605#define PIOE ((Pio *)0x400E1600U)
606#define RSTC ((Rstc *)0x400E1800U)
607#define SUPC ((Supc *)0x400E1810U)
608#define RTT ((Rtt *)0x400E1830U)
609#define WDT ((Wdt *)0x400E1850U)
610#define RTC ((Rtc *)0x400E1860U)
611#define GPBR ((Gpbr *)0x400E1890U)
612#define RSWDT ((Rswdt *)0x400E1900U)
613#define UART2 ((Uart *)0x400E1A00U)
614#define UART3 ((Uart *)0x400E1C00U)
615#define UART4 ((Uart *)0x400E1E00U)
616#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
619/* ************************************************************************** */
620/* PIO DEFINITIONS FOR SAMV71Q20 */
621/* ************************************************************************** */
624
625#include "pio/pio_samv71q20.h"
628/* ************************************************************************** */
629/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */
630/* ************************************************************************** */
631
632#define IFLASH_SIZE (0x100000u)
633#define IFLASH_PAGE_SIZE (512u)
634#define IFLASH_LOCK_REGION_SIZE (8192u)
635#define IFLASH_NB_OF_PAGES (2048u)
636#define IFLASH_NB_OF_LOCK_BITS (64u)
637#define IRAM_SIZE (0x60000u)
638
639#define QSPIMEM_ADDR (0x80000000u)
640#define AXIMX_ADDR (0xA0000000u)
641#define ITCM_ADDR (0x00000000u)
642#define IFLASH_ADDR (0x00400000u)
643#define IROM_ADDR (0x00800000u)
644#define DTCM_ADDR (0x20000000u)
645#define IRAM_ADDR (0x20400000u)
646#define EBI_CS0_ADDR (0x60000000u)
647#define EBI_CS1_ADDR (0x61000000u)
648#define EBI_CS2_ADDR (0x62000000u)
649#define EBI_CS3_ADDR (0x63000000u)
650#define SDRAM_CS_ADDR (0x70000000u)
652/* ************************************************************************** */
653/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */
654/* ************************************************************************** */
655
656#define CHIP_JTAGID (0x05B3D03FUL)
657#define CHIP_CIDR (0xA1220C00UL)
658#define CHIP_EXID (0x00000002UL)
659
660/* ************************************************************************** */
661/* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */
662/* ************************************************************************** */
663
664/* %ATMEL_ELECTRICAL% */
665
666/* Device characteristics */
667#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
668#define CHIP_FREQ_SLCK_RC (32000UL)
669#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
670#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
671#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
672#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
673#define CHIP_FREQ_CPU_MAX (120000000UL)
674#define CHIP_FREQ_XTAL_32K (32768UL)
675#define CHIP_FREQ_XTAL_12M (12000000UL)
676
677/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
678#define CHIP_FREQ_FWS_0 (20000000UL)
679#define CHIP_FREQ_FWS_1 (40000000UL)
680#define CHIP_FREQ_FWS_2 (60000000UL)
681#define CHIP_FREQ_FWS_3 (80000000UL)
682#define CHIP_FREQ_FWS_4 (100000000UL)
683#define CHIP_FREQ_FWS_5 (123000000UL)
685#ifdef __cplusplus
686}
687#endif
688
691#endif /* _SAMV71Q20_ */
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
UsageFault_Handler
void UsageFault_Handler(void)
Default UsageFault interrupt handler.
Definition: exceptions.c:207
HardFault_Handler
void HardFault_Handler(void)
Default HardFault interrupt handler.
Definition: exceptions.c:168
MemManage_Handler
void MemManage_Handler(void)
Default MemManage interrupt handler.
Definition: exceptions.c:180
NMI_Handler
void NMI_Handler(void)
Default NMI interrupt handler.
Definition: exceptions.c:53
BusFault_Handler
void BusFault_Handler(void)
Default BusFault interrupt handler.
Definition: exceptions.c:193
TC9_IRQn
@ TC9_IRQn
Definition: samv71q20.h:118
PendSV_IRQn
@ PendSV_IRQn
Definition: samv71q20.h:67
PWM1_IRQn
@ PWM1_IRQn
Definition: samv71q20.h:126
UART3_IRQn
@ UART3_IRQn
Definition: samv71q20.h:113
XDMAC_IRQn
@ XDMAC_IRQn
Definition: samv71q20.h:124
TC6_IRQn
@ TC6_IRQn
Definition: samv71q20.h:115
TC0_IRQn
@ TC0_IRQn
Definition: samv71q20.h:93
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: samv71q20.h:62
ISI_IRQn
@ ISI_IRQn
Definition: samv71q20.h:125
TWIHS1_IRQn
@ TWIHS1_IRQn
Definition: samv71q20.h:90
MCAN1_IRQn
@ MCAN1_IRQn
Definition: samv71q20.h:106
USART2_IRQn
@ USART2_IRQn
Definition: samv71q20.h:85
USART0_IRQn
@ USART0_IRQn
Definition: samv71q20.h:83
GMAC_IRQn
@ GMAC_IRQn
Definition: samv71q20.h:107
SVCall_IRQn
@ SVCall_IRQn
Definition: samv71q20.h:65
PIOC_IRQn
@ PIOC_IRQn
Definition: samv71q20.h:82
RSWDT_IRQn
@ RSWDT_IRQn
Definition: samv71q20.h:128
AFEC0_IRQn
@ AFEC0_IRQn
Definition: samv71q20.h:99
TC4_IRQn
@ TC4_IRQn
Definition: samv71q20.h:97
SDRAMC_IRQn
@ SDRAMC_IRQn
Definition: samv71q20.h:127
TC1_IRQn
@ TC1_IRQn
Definition: samv71q20.h:94
UsageFault_IRQn
@ UsageFault_IRQn
Definition: samv71q20.h:64
SysTick_IRQn
@ SysTick_IRQn
Definition: samv71q20.h:68
PMC_IRQn
@ PMC_IRQn
Definition: samv71q20.h:76
SUPC_IRQn
@ SUPC_IRQn
Definition: samv71q20.h:71
WDT_IRQn
@ WDT_IRQn
Definition: samv71q20.h:75
SSC_IRQn
@ SSC_IRQn
Definition: samv71q20.h:92
PIOA_IRQn
@ PIOA_IRQn
Definition: samv71q20.h:80
TC5_IRQn
@ TC5_IRQn
Definition: samv71q20.h:98
PERIPH_COUNT_IRQn
@ PERIPH_COUNT_IRQn
Definition: samv71q20.h:130
PIOE_IRQn
@ PIOE_IRQn
Definition: samv71q20.h:87
AES_IRQn
@ AES_IRQn
Definition: samv71q20.h:122
BusFault_IRQn
@ BusFault_IRQn
Definition: samv71q20.h:63
TC7_IRQn
@ TC7_IRQn
Definition: samv71q20.h:116
TC11_IRQn
@ TC11_IRQn
Definition: samv71q20.h:120
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: samv71q20.h:66
TC2_IRQn
@ TC2_IRQn
Definition: samv71q20.h:95
UART1_IRQn
@ UART1_IRQn
Definition: samv71q20.h:79
TWIHS2_IRQn
@ TWIHS2_IRQn
Definition: samv71q20.h:109
TC3_IRQn
@ TC3_IRQn
Definition: samv71q20.h:96
MLB_IRQn
@ MLB_IRQn
Definition: samv71q20.h:121
TC8_IRQn
@ TC8_IRQn
Definition: samv71q20.h:117
TC10_IRQn
@ TC10_IRQn
Definition: samv71q20.h:119
RSTC_IRQn
@ RSTC_IRQn
Definition: samv71q20.h:72
PIOD_IRQn
@ PIOD_IRQn
Definition: samv71q20.h:86
SPI1_IRQn
@ SPI1_IRQn
Definition: samv71q20.h:110
UART2_IRQn
@ UART2_IRQn
Definition: samv71q20.h:112
HardFault_IRQn
@ HardFault_IRQn
Definition: samv71q20.h:61
TRNG_IRQn
@ TRNG_IRQn
Definition: samv71q20.h:123
RTT_IRQn
@ RTT_IRQn
Definition: samv71q20.h:74
AFEC1_IRQn
@ AFEC1_IRQn
Definition: samv71q20.h:108
QSPI_IRQn
@ QSPI_IRQn
Definition: samv71q20.h:111
USART1_IRQn
@ USART1_IRQn
Definition: samv71q20.h:84
RTC_IRQn
@ RTC_IRQn
Definition: samv71q20.h:73
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: samv71q20.h:60
UART4_IRQn
@ UART4_IRQn
Definition: samv71q20.h:114
TWIHS0_IRQn
@ TWIHS0_IRQn
Definition: samv71q20.h:89
PIOB_IRQn
@ PIOB_IRQn
Definition: samv71q20.h:81
USBHS_IRQn
@ USBHS_IRQn
Definition: samv71q20.h:104
PWM0_IRQn
@ PWM0_IRQn
Definition: samv71q20.h:101
HSMCI_IRQn
@ HSMCI_IRQn
Definition: samv71q20.h:88
UART0_IRQn
@ UART0_IRQn
Definition: samv71q20.h:78
ICM_IRQn
@ ICM_IRQn
Definition: samv71q20.h:102
ACC_IRQn
@ ACC_IRQn
Definition: samv71q20.h:103
MCAN0_IRQn
@ MCAN0_IRQn
Definition: samv71q20.h:105
EFC_IRQn
@ EFC_IRQn
Definition: samv71q20.h:77
SPI0_IRQn
@ SPI0_IRQn
Definition: samv71q20.h:91
DACC_IRQn
@ DACC_IRQn
Definition: samv71q20.h:100
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
_DeviceVectors
Definition: same70j19.h:122
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