RTEMS 6.1-rc1
sams70n21.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
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7/* All rights reserved. */
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28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70N21_
31#define _SAMS70N21_
32
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/* CMSIS DEFINITIONS FOR SAMS70N21 */
52/* ************************************************************************** */
55
57typedef enum IRQn
58{
59/****** Cortex-M7 Processor Exceptions Numbers ******************************/
60 NonMaskableInt_IRQn = -14,
61 HardFault_IRQn = -13,
62 MemoryManagement_IRQn = -12,
63 BusFault_IRQn = -11,
64 UsageFault_IRQn = -10,
65 SVCall_IRQn = -5,
66 DebugMonitor_IRQn = -4,
67 PendSV_IRQn = -2,
68 SysTick_IRQn = -1,
69/****** SAMS70N21 specific Interrupt Numbers *********************************/
70
71 SUPC_IRQn = 0,
72 RSTC_IRQn = 1,
73 RTC_IRQn = 2,
74 RTT_IRQn = 3,
75 WDT_IRQn = 4,
76 PMC_IRQn = 5,
77 EFC_IRQn = 6,
78 UART0_IRQn = 7,
79 UART1_IRQn = 8,
80 PIOA_IRQn = 10,
81 PIOB_IRQn = 11,
82 USART0_IRQn = 13,
83 USART1_IRQn = 14,
84 USART2_IRQn = 15,
85 PIOD_IRQn = 16,
86 HSMCI_IRQn = 18,
87 TWIHS0_IRQn = 19,
88 TWIHS1_IRQn = 20,
89 SPI0_IRQn = 21,
90 SSC_IRQn = 22,
91 TC0_IRQn = 23,
92 TC1_IRQn = 24,
93 TC2_IRQn = 25,
94 AFEC0_IRQn = 29,
95 DACC_IRQn = 30,
96 PWM0_IRQn = 31,
97 ICM_IRQn = 32,
98 ACC_IRQn = 33,
99 USBHS_IRQn = 34,
100 AFEC1_IRQn = 40,
101 TWIHS2_IRQn = 41,
102 SPI1_IRQn = 42,
103 QSPI_IRQn = 43,
104 UART2_IRQn = 44,
105 UART3_IRQn = 45,
106 UART4_IRQn = 46,
107 TC9_IRQn = 50,
108 TC10_IRQn = 51,
109 TC11_IRQn = 52,
110 AES_IRQn = 56,
111 TRNG_IRQn = 57,
112 XDMAC_IRQn = 58,
113 ISI_IRQn = 59,
114 PWM1_IRQn = 60,
115 RSWDT_IRQn = 63,
117 PERIPH_COUNT_IRQn = 64
118} IRQn_Type;
119
120typedef struct _DeviceVectors
121{
122 /* Stack pointer */
123 void* pvStack;
124
125 /* Cortex-M handlers */
126 void* pfnReset_Handler;
127 void* pfnNMI_Handler;
128 void* pfnHardFault_Handler;
129 void* pfnMemManage_Handler;
130 void* pfnBusFault_Handler;
131 void* pfnUsageFault_Handler;
132 void* pfnReserved1_Handler;
133 void* pfnReserved2_Handler;
134 void* pfnReserved3_Handler;
135 void* pfnReserved4_Handler;
136 void* pfnSVC_Handler;
137 void* pfnDebugMon_Handler;
138 void* pfnReserved5_Handler;
139 void* pfnPendSV_Handler;
140 void* pfnSysTick_Handler;
141
142 /* Peripheral handlers */
143 void* pfnSUPC_Handler; /* 0 Supply Controller */
144 void* pfnRSTC_Handler; /* 1 Reset Controller */
145 void* pfnRTC_Handler; /* 2 Real Time Clock */
146 void* pfnRTT_Handler; /* 3 Real Time Timer */
147 void* pfnWDT_Handler; /* 4 Watchdog Timer */
148 void* pfnPMC_Handler; /* 5 Power Management Controller */
149 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
150 void* pfnUART0_Handler; /* 7 UART 0 */
151 void* pfnUART1_Handler; /* 8 UART 1 */
152 void* pvReserved9;
153 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
154 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
155 void* pvReserved12;
156 void* pfnUSART0_Handler; /* 13 USART 0 */
157 void* pfnUSART1_Handler; /* 14 USART 1 */
158 void* pfnUSART2_Handler; /* 15 USART 2 */
159 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
160 void* pvReserved17;
161 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
162 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
163 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
164 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
165 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
166 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
167 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
168 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
169 void* pvReserved26;
170 void* pvReserved27;
171 void* pvReserved28;
172 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
173 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
174 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
175 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
176 void* pfnACC_Handler; /* 33 Analog Comparator */
177 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
178 void* pvReserved35;
179 void* pvReserved36;
180 void* pvReserved37;
181 void* pvReserved38;
182 void* pvReserved39;
183 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
184 void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */
185 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
186 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
187 void* pfnUART2_Handler; /* 44 UART 2 */
188 void* pfnUART3_Handler; /* 45 UART 3 */
189 void* pfnUART4_Handler; /* 46 UART 4 */
190 void* pvReserved47;
191 void* pvReserved48;
192 void* pvReserved49;
193 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
194 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
195 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
196 void* pvReserved53;
197 void* pvReserved54;
198 void* pvReserved55;
199 void* pfnAES_Handler; /* 56 AES */
200 void* pfnTRNG_Handler; /* 57 True Random Generator */
201 void* pfnXDMAC_Handler; /* 58 DMA */
202 void* pfnISI_Handler; /* 59 Camera Interface */
203 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
204 void* pvReserved61;
205 void* pvReserved62;
206 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
207} DeviceVectors;
208
209/* Cortex-M7 core handlers */
210void Reset_Handler ( void );
211void NMI_Handler ( void );
212void HardFault_Handler ( void );
213void MemManage_Handler ( void );
214void BusFault_Handler ( void );
215void UsageFault_Handler ( void );
216void SVC_Handler ( void );
217void DebugMon_Handler ( void );
218void PendSV_Handler ( void );
219void SysTick_Handler ( void );
220
221/* Peripherals handlers */
222void ACC_Handler ( void );
223void AES_Handler ( void );
224void AFEC0_Handler ( void );
225void AFEC1_Handler ( void );
226void DACC_Handler ( void );
227void EFC_Handler ( void );
228void HSMCI_Handler ( void );
229void ICM_Handler ( void );
230void ISI_Handler ( void );
231void PIOA_Handler ( void );
232void PIOB_Handler ( void );
233void PIOD_Handler ( void );
234void PMC_Handler ( void );
235void PWM0_Handler ( void );
236void PWM1_Handler ( void );
237void QSPI_Handler ( void );
238void RSTC_Handler ( void );
239void RSWDT_Handler ( void );
240void RTC_Handler ( void );
241void RTT_Handler ( void );
242void SPI0_Handler ( void );
243void SPI1_Handler ( void );
244void SSC_Handler ( void );
245void SUPC_Handler ( void );
246void TC0_Handler ( void );
247void TC1_Handler ( void );
248void TC2_Handler ( void );
249void TC9_Handler ( void );
250void TC10_Handler ( void );
251void TC11_Handler ( void );
252void TRNG_Handler ( void );
253void TWIHS0_Handler ( void );
254void TWIHS1_Handler ( void );
255void TWIHS2_Handler ( void );
256void UART0_Handler ( void );
257void UART1_Handler ( void );
258void UART2_Handler ( void );
259void UART3_Handler ( void );
260void UART4_Handler ( void );
261void USART0_Handler ( void );
262void USART1_Handler ( void );
263void USART2_Handler ( void );
264void USBHS_Handler ( void );
265void WDT_Handler ( void );
266void XDMAC_Handler ( void );
267
272#define __CM7_REV 0x0000
273#define __MPU_PRESENT 1
274#define __NVIC_PRIO_BITS 3
275#define __FPU_PRESENT 1
276#define __FPU_DP 1
277#define __ICACHE_PRESENT 1
278#define __DCACHE_PRESENT 1
279#define __DTCM_PRESENT 1
280#define __ITCM_PRESENT 1
281#define __Vendor_SysTickConfig 0
283/*
284 * \brief CMSIS includes
285 */
286
287#include <core_cm7.h>
288#if !defined DONT_USE_CMSIS_INIT
289#include "system_sams70.h"
290#endif /* DONT_USE_CMSIS_INIT */
291
294/* ************************************************************************** */
296/* ************************************************************************** */
299
300#include "component/component_acc.h"
301#include "component/component_aes.h"
302#include "component/component_afec.h"
303#include "component/component_chipid.h"
304#include "component/component_dacc.h"
305#include "component/component_efc.h"
306#include "component/component_gpbr.h"
307#include "component/component_hsmci.h"
308#include "component/component_icm.h"
309#include "component/component_isi.h"
310#include "component/component_matrix.h"
311#include "component/component_pio.h"
312#include "component/component_pmc.h"
313#include "component/component_pwm.h"
314#include "component/component_qspi.h"
315#include "component/component_rstc.h"
316#include "component/component_rswdt.h"
317#include "component/component_rtc.h"
318#include "component/component_rtt.h"
319#include "component/component_spi.h"
320#include "component/component_ssc.h"
321#include "component/component_supc.h"
322#include "component/component_tc.h"
323#include "component/component_trng.h"
324#include "component/component_twihs.h"
325#include "component/component_uart.h"
326#include "component/component_usart.h"
327#include "component/component_usbhs.h"
328#include "component/component_utmi.h"
329#include "component/component_wdt.h"
330#include "component/component_xdmac.h"
333#ifndef __rtems__
334/* ************************************************************************** */
335/* REGISTER ACCESS DEFINITIONS FOR SAMS70N21 */
336/* ************************************************************************** */
339
340#include "instance/instance_hsmci.h"
341#include "instance/instance_ssc.h"
342#include "instance/instance_spi0.h"
343#include "instance/instance_tc0.h"
344#include "instance/instance_twihs0.h"
345#include "instance/instance_twihs1.h"
346#include "instance/instance_pwm0.h"
347#include "instance/instance_usart0.h"
348#include "instance/instance_usart1.h"
349#include "instance/instance_usart2.h"
350#include "instance/instance_usbhs.h"
351#include "instance/instance_afec0.h"
352#include "instance/instance_dacc.h"
353#include "instance/instance_acc.h"
354#include "instance/instance_icm.h"
355#include "instance/instance_isi.h"
356#include "instance/instance_tc3.h"
357#include "instance/instance_spi1.h"
358#include "instance/instance_pwm1.h"
359#include "instance/instance_twihs2.h"
360#include "instance/instance_afec1.h"
361#include "instance/instance_aes.h"
362#include "instance/instance_trng.h"
363#include "instance/instance_xdmac.h"
364#include "instance/instance_qspi.h"
365#include "instance/instance_matrix.h"
366#include "instance/instance_utmi.h"
367#include "instance/instance_pmc.h"
368#include "instance/instance_uart0.h"
369#include "instance/instance_chipid.h"
370#include "instance/instance_uart1.h"
371#include "instance/instance_efc.h"
372#include "instance/instance_pioa.h"
373#include "instance/instance_piob.h"
374#include "instance/instance_piod.h"
375#include "instance/instance_rstc.h"
376#include "instance/instance_supc.h"
377#include "instance/instance_rtt.h"
378#include "instance/instance_wdt.h"
379#include "instance/instance_rtc.h"
380#include "instance/instance_gpbr.h"
381#include "instance/instance_rswdt.h"
382#include "instance/instance_uart2.h"
383#include "instance/instance_uart3.h"
384#include "instance/instance_uart4.h"
386#endif /* __rtems__ */
387
388/* ************************************************************************** */
389/* PERIPHERAL ID DEFINITIONS FOR SAMS70N21 */
390/* ************************************************************************** */
393
394#define ID_SUPC ( 0)
395#define ID_RSTC ( 1)
396#define ID_RTC ( 2)
397#define ID_RTT ( 3)
398#define ID_WDT ( 4)
399#define ID_PMC ( 5)
400#define ID_EFC ( 6)
401#define ID_UART0 ( 7)
402#define ID_UART1 ( 8)
403#define ID_PIOA (10)
404#define ID_PIOB (11)
405#define ID_USART0 (13)
406#define ID_USART1 (14)
407#define ID_USART2 (15)
408#define ID_PIOD (16)
409#define ID_HSMCI (18)
410#define ID_TWIHS0 (19)
411#define ID_TWIHS1 (20)
412#define ID_SPI0 (21)
413#define ID_SSC (22)
414#define ID_TC0 (23)
415#define ID_TC1 (24)
416#define ID_TC2 (25)
417#define ID_AFEC0 (29)
418#define ID_DACC (30)
419#define ID_PWM0 (31)
420#define ID_ICM (32)
421#define ID_ACC (33)
422#define ID_USBHS (34)
423#define ID_AFEC1 (40)
424#define ID_TWIHS2 (41)
425#define ID_SPI1 (42)
426#define ID_QSPI (43)
427#define ID_UART2 (44)
428#define ID_UART3 (45)
429#define ID_UART4 (46)
430#define ID_TC9 (50)
431#define ID_TC10 (51)
432#define ID_TC11 (52)
433#define ID_AES (56)
434#define ID_TRNG (57)
435#define ID_XDMAC (58)
436#define ID_ISI (59)
437#define ID_PWM1 (60)
438#define ID_RSWDT (63)
440#define ID_PERIPH_COUNT (64)
442
443/* ************************************************************************** */
444/* BASE ADDRESS DEFINITIONS FOR SAMS70N21 */
445/* ************************************************************************** */
448
449#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
450#define HSMCI (0x40000000U)
451#define SSC (0x40004000U)
452#define SPI0 (0x40008000U)
453#define TC0 (0x4000C000U)
454#define TWIHS0 (0x40018000U)
455#define TWIHS1 (0x4001C000U)
456#define PWM0 (0x40020000U)
457#define USART0 (0x40024000U)
458#define USART1 (0x40028000U)
459#define USART2 (0x4002C000U)
460#define USBHS (0x40038000U)
461#define AFEC0 (0x4003C000U)
462#define DACC (0x40040000U)
463#define ACC (0x40044000U)
464#define ICM (0x40048000U)
465#define ISI (0x4004C000U)
466#define TC3 (0x40054000U)
467#define SPI1 (0x40058000U)
468#define PWM1 (0x4005C000U)
469#define TWIHS2 (0x40060000U)
470#define AFEC1 (0x40064000U)
471#define AES (0x4006C000U)
472#define TRNG (0x40070000U)
473#define XDMAC (0x40078000U)
474#define QSPI (0x4007C000U)
475#define MATRIX (0x40088000U)
476#define UTMI (0x400E0400U)
477#define PMC (0x400E0600U)
478#define UART0 (0x400E0800U)
479#define CHIPID (0x400E0940U)
480#define UART1 (0x400E0A00U)
481#define EFC (0x400E0C00U)
482#define PIOA (0x400E0E00U)
483#define PIOB (0x400E1000U)
484#define PIOD (0x400E1400U)
485#define RSTC (0x400E1800U)
486#define SUPC (0x400E1810U)
487#define RTT (0x400E1830U)
488#define WDT (0x400E1850U)
489#define RTC (0x400E1860U)
490#define GPBR (0x400E1890U)
491#define RSWDT (0x400E1900U)
492#define UART2 (0x400E1A00U)
493#define UART3 (0x400E1C00U)
494#define UART4 (0x400E1E00U)
495#else
496#define HSMCI ((Hsmci *)0x40000000U)
497#define SSC ((Ssc *)0x40004000U)
498#define SPI0 ((Spi *)0x40008000U)
499#define TC0 ((Tc *)0x4000C000U)
500#define TWIHS0 ((Twihs *)0x40018000U)
501#define TWIHS1 ((Twihs *)0x4001C000U)
502#define PWM0 ((Pwm *)0x40020000U)
503#define USART0 ((Usart *)0x40024000U)
504#define USART1 ((Usart *)0x40028000U)
505#define USART2 ((Usart *)0x4002C000U)
506#define USBHS ((Usbhs *)0x40038000U)
507#define AFEC0 ((Afec *)0x4003C000U)
508#define DACC ((Dacc *)0x40040000U)
509#define ACC ((Acc *)0x40044000U)
510#define ICM ((Icm *)0x40048000U)
511#define ISI ((Isi *)0x4004C000U)
512#define TC3 ((Tc *)0x40054000U)
513#define SPI1 ((Spi *)0x40058000U)
514#define PWM1 ((Pwm *)0x4005C000U)
515#define TWIHS2 ((Twihs *)0x40060000U)
516#define AFEC1 ((Afec *)0x40064000U)
517#define AES ((Aes *)0x4006C000U)
518#define TRNG ((Trng *)0x40070000U)
519#define XDMAC ((Xdmac *)0x40078000U)
520#define QSPI ((Qspi *)0x4007C000U)
521#define MATRIX ((Matrix *)0x40088000U)
522#define UTMI ((Utmi *)0x400E0400U)
523#define PMC ((Pmc *)0x400E0600U)
524#define UART0 ((Uart *)0x400E0800U)
525#define CHIPID ((Chipid *)0x400E0940U)
526#define UART1 ((Uart *)0x400E0A00U)
527#define EFC ((Efc *)0x400E0C00U)
528#define PIOA ((Pio *)0x400E0E00U)
529#define PIOB ((Pio *)0x400E1000U)
530#define PIOD ((Pio *)0x400E1400U)
531#define RSTC ((Rstc *)0x400E1800U)
532#define SUPC ((Supc *)0x400E1810U)
533#define RTT ((Rtt *)0x400E1830U)
534#define WDT ((Wdt *)0x400E1850U)
535#define RTC ((Rtc *)0x400E1860U)
536#define GPBR ((Gpbr *)0x400E1890U)
537#define RSWDT ((Rswdt *)0x400E1900U)
538#define UART2 ((Uart *)0x400E1A00U)
539#define UART3 ((Uart *)0x400E1C00U)
540#define UART4 ((Uart *)0x400E1E00U)
541#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
544/* ************************************************************************** */
545/* PIO DEFINITIONS FOR SAMS70N21 */
546/* ************************************************************************** */
549
550#include "pio/pio_sams70n21.h"
553/* ************************************************************************** */
554/* MEMORY MAPPING DEFINITIONS FOR SAMS70N21 */
555/* ************************************************************************** */
556
557#define IFLASH_SIZE (0x200000u)
558#define IFLASH_PAGE_SIZE (512u)
559#define IFLASH_LOCK_REGION_SIZE (8192u)
560#define IFLASH_NB_OF_PAGES (4096u)
561#define IFLASH_NB_OF_LOCK_BITS (128u)
562#define IRAM_SIZE (0x60000u)
563
564#define QSPIMEM_ADDR (0x80000000u)
565#define AXIMX_ADDR (0xA0000000u)
566#define ITCM_ADDR (0x00000000u)
567#define IFLASH_ADDR (0x00400000u)
568#define IROM_ADDR (0x00800000u)
569#define DTCM_ADDR (0x20000000u)
570#define IRAM_ADDR (0x20400000u)
571#define EBI_CS0_ADDR (0x60000000u)
572#define EBI_CS1_ADDR (0x61000000u)
573#define EBI_CS2_ADDR (0x62000000u)
574#define EBI_CS3_ADDR (0x63000000u)
575#define SDRAM_CS_ADDR (0x70000000u)
577/* ************************************************************************** */
578/* MISCELLANEOUS DEFINITIONS FOR SAMS70N21 */
579/* ************************************************************************** */
580
581#define CHIP_JTAGID (0x05B3D03FUL)
582#define CHIP_CIDR (0xA1120E00UL)
583#define CHIP_EXID (0x00000001UL)
584
585/* ************************************************************************** */
586/* ELECTRICAL DEFINITIONS FOR SAMS70N21 */
587/* ************************************************************************** */
588
589/* %ATMEL_ELECTRICAL% */
590
591/* Device characteristics */
592#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
593#define CHIP_FREQ_SLCK_RC (32000UL)
594#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
595#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
596#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
597#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
598#define CHIP_FREQ_CPU_MAX (120000000UL)
599#define CHIP_FREQ_XTAL_32K (32768UL)
600#define CHIP_FREQ_XTAL_12M (12000000UL)
601
602/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
603#define CHIP_FREQ_FWS_0 (20000000UL)
604#define CHIP_FREQ_FWS_1 (40000000UL)
605#define CHIP_FREQ_FWS_2 (60000000UL)
606#define CHIP_FREQ_FWS_3 (80000000UL)
607#define CHIP_FREQ_FWS_4 (100000000UL)
608#define CHIP_FREQ_FWS_5 (123000000UL)
610#ifdef __cplusplus
611}
612#endif
613
616#endif /* _SAMS70N21_ */
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
UsageFault_Handler
void UsageFault_Handler(void)
Default UsageFault interrupt handler.
Definition: exceptions.c:207
HardFault_Handler
void HardFault_Handler(void)
Default HardFault interrupt handler.
Definition: exceptions.c:168
MemManage_Handler
void MemManage_Handler(void)
Default MemManage interrupt handler.
Definition: exceptions.c:180
NMI_Handler
void NMI_Handler(void)
Default NMI interrupt handler.
Definition: exceptions.c:53
BusFault_Handler
void BusFault_Handler(void)
Default BusFault interrupt handler.
Definition: exceptions.c:193
TC9_IRQn
@ TC9_IRQn
Definition: sams70n21.h:107
PendSV_IRQn
@ PendSV_IRQn
Definition: sams70n21.h:67
PWM1_IRQn
@ PWM1_IRQn
Definition: sams70n21.h:114
UART3_IRQn
@ UART3_IRQn
Definition: sams70n21.h:105
XDMAC_IRQn
@ XDMAC_IRQn
Definition: sams70n21.h:112
TC0_IRQn
@ TC0_IRQn
Definition: sams70n21.h:91
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: sams70n21.h:62
ISI_IRQn
@ ISI_IRQn
Definition: sams70n21.h:113
TWIHS1_IRQn
@ TWIHS1_IRQn
Definition: sams70n21.h:88
USART2_IRQn
@ USART2_IRQn
Definition: sams70n21.h:84
USART0_IRQn
@ USART0_IRQn
Definition: sams70n21.h:82
SVCall_IRQn
@ SVCall_IRQn
Definition: sams70n21.h:65
RSWDT_IRQn
@ RSWDT_IRQn
Definition: sams70n21.h:115
AFEC0_IRQn
@ AFEC0_IRQn
Definition: sams70n21.h:94
TC1_IRQn
@ TC1_IRQn
Definition: sams70n21.h:92
UsageFault_IRQn
@ UsageFault_IRQn
Definition: sams70n21.h:64
SysTick_IRQn
@ SysTick_IRQn
Definition: sams70n21.h:68
PMC_IRQn
@ PMC_IRQn
Definition: sams70n21.h:76
SUPC_IRQn
@ SUPC_IRQn
Definition: sams70n21.h:71
WDT_IRQn
@ WDT_IRQn
Definition: sams70n21.h:75
SSC_IRQn
@ SSC_IRQn
Definition: sams70n21.h:90
PIOA_IRQn
@ PIOA_IRQn
Definition: sams70n21.h:80
PERIPH_COUNT_IRQn
@ PERIPH_COUNT_IRQn
Definition: sams70n21.h:117
AES_IRQn
@ AES_IRQn
Definition: sams70n21.h:110
BusFault_IRQn
@ BusFault_IRQn
Definition: sams70n21.h:63
TC11_IRQn
@ TC11_IRQn
Definition: sams70n21.h:109
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: sams70n21.h:66
TC2_IRQn
@ TC2_IRQn
Definition: sams70n21.h:93
UART1_IRQn
@ UART1_IRQn
Definition: sams70n21.h:79
TWIHS2_IRQn
@ TWIHS2_IRQn
Definition: sams70n21.h:101
TC10_IRQn
@ TC10_IRQn
Definition: sams70n21.h:108
RSTC_IRQn
@ RSTC_IRQn
Definition: sams70n21.h:72
PIOD_IRQn
@ PIOD_IRQn
Definition: sams70n21.h:85
SPI1_IRQn
@ SPI1_IRQn
Definition: sams70n21.h:102
UART2_IRQn
@ UART2_IRQn
Definition: sams70n21.h:104
HardFault_IRQn
@ HardFault_IRQn
Definition: sams70n21.h:61
TRNG_IRQn
@ TRNG_IRQn
Definition: sams70n21.h:111
RTT_IRQn
@ RTT_IRQn
Definition: sams70n21.h:74
AFEC1_IRQn
@ AFEC1_IRQn
Definition: sams70n21.h:100
QSPI_IRQn
@ QSPI_IRQn
Definition: sams70n21.h:103
USART1_IRQn
@ USART1_IRQn
Definition: sams70n21.h:83
RTC_IRQn
@ RTC_IRQn
Definition: sams70n21.h:73
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: sams70n21.h:60
UART4_IRQn
@ UART4_IRQn
Definition: sams70n21.h:106
TWIHS0_IRQn
@ TWIHS0_IRQn
Definition: sams70n21.h:87
PIOB_IRQn
@ PIOB_IRQn
Definition: sams70n21.h:81
USBHS_IRQn
@ USBHS_IRQn
Definition: sams70n21.h:99
PWM0_IRQn
@ PWM0_IRQn
Definition: sams70n21.h:96
HSMCI_IRQn
@ HSMCI_IRQn
Definition: sams70n21.h:86
UART0_IRQn
@ UART0_IRQn
Definition: sams70n21.h:78
ICM_IRQn
@ ICM_IRQn
Definition: sams70n21.h:97
ACC_IRQn
@ ACC_IRQn
Definition: sams70n21.h:98
EFC_IRQn
@ EFC_IRQn
Definition: sams70n21.h:77
SPI0_IRQn
@ SPI0_IRQn
Definition: sams70n21.h:89
DACC_IRQn
@ DACC_IRQn
Definition: sams70n21.h:95
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
_DeviceVectors
Definition: same70j19.h:122
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