RTEMS 6.1-rc1
sams70j20.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
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11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
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16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMS70J20_
31#define _SAMS70J20_
32
41
42#ifdef __cplusplus
43 extern "C" {
44#endif
45
46#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
47#include <stdint.h>
48#endif
49
50/* ************************************************************************** */
51/* CMSIS DEFINITIONS FOR SAMS70J20 */
52/* ************************************************************************** */
55
57typedef enum IRQn
58{
59/****** Cortex-M7 Processor Exceptions Numbers ******************************/
60 NonMaskableInt_IRQn = -14,
61 HardFault_IRQn = -13,
62 MemoryManagement_IRQn = -12,
63 BusFault_IRQn = -11,
64 UsageFault_IRQn = -10,
65 SVCall_IRQn = -5,
66 DebugMonitor_IRQn = -4,
67 PendSV_IRQn = -2,
68 SysTick_IRQn = -1,
69/****** SAMS70J20 specific Interrupt Numbers *********************************/
70
71 SUPC_IRQn = 0,
72 RSTC_IRQn = 1,
73 RTC_IRQn = 2,
74 RTT_IRQn = 3,
75 WDT_IRQn = 4,
76 PMC_IRQn = 5,
77 EFC_IRQn = 6,
78 UART0_IRQn = 7,
79 UART1_IRQn = 8,
80 PIOA_IRQn = 10,
81 PIOB_IRQn = 11,
82 USART0_IRQn = 13,
83 USART1_IRQn = 14,
84 USART2_IRQn = 15,
85 PIOD_IRQn = 16,
86 HSMCI_IRQn = 18,
87 TWIHS0_IRQn = 19,
88 TWIHS1_IRQn = 20,
89 SPI0_IRQn = 21,
90 SSC_IRQn = 22,
91 TC0_IRQn = 23,
92 TC1_IRQn = 24,
93 TC2_IRQn = 25,
94 AFEC0_IRQn = 29,
95 DACC_IRQn = 30,
96 PWM0_IRQn = 31,
97 ICM_IRQn = 32,
98 ACC_IRQn = 33,
99 USBHS_IRQn = 34,
100 AFEC1_IRQn = 40,
101 SPI1_IRQn = 42,
102 QSPI_IRQn = 43,
103 UART2_IRQn = 44,
104 UART3_IRQn = 45,
105 UART4_IRQn = 46,
106 TC9_IRQn = 50,
107 TC10_IRQn = 51,
108 TC11_IRQn = 52,
109 AES_IRQn = 56,
110 TRNG_IRQn = 57,
111 XDMAC_IRQn = 58,
112 ISI_IRQn = 59,
113 PWM1_IRQn = 60,
114 RSWDT_IRQn = 63,
116 PERIPH_COUNT_IRQn = 64
117} IRQn_Type;
118
119typedef struct _DeviceVectors
120{
121 /* Stack pointer */
122 void* pvStack;
123
124 /* Cortex-M handlers */
125 void* pfnReset_Handler;
126 void* pfnNMI_Handler;
127 void* pfnHardFault_Handler;
128 void* pfnMemManage_Handler;
129 void* pfnBusFault_Handler;
130 void* pfnUsageFault_Handler;
131 void* pfnReserved1_Handler;
132 void* pfnReserved2_Handler;
133 void* pfnReserved3_Handler;
134 void* pfnReserved4_Handler;
135 void* pfnSVC_Handler;
136 void* pfnDebugMon_Handler;
137 void* pfnReserved5_Handler;
138 void* pfnPendSV_Handler;
139 void* pfnSysTick_Handler;
140
141 /* Peripheral handlers */
142 void* pfnSUPC_Handler; /* 0 Supply Controller */
143 void* pfnRSTC_Handler; /* 1 Reset Controller */
144 void* pfnRTC_Handler; /* 2 Real Time Clock */
145 void* pfnRTT_Handler; /* 3 Real Time Timer */
146 void* pfnWDT_Handler; /* 4 Watchdog Timer */
147 void* pfnPMC_Handler; /* 5 Power Management Controller */
148 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */
149 void* pfnUART0_Handler; /* 7 UART 0 */
150 void* pfnUART1_Handler; /* 8 UART 1 */
151 void* pvReserved9;
152 void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */
153 void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */
154 void* pvReserved12;
155 void* pfnUSART0_Handler; /* 13 USART 0 */
156 void* pfnUSART1_Handler; /* 14 USART 1 */
157 void* pfnUSART2_Handler; /* 15 USART 2 */
158 void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */
159 void* pvReserved17;
160 void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */
161 void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
162 void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
163 void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */
164 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */
165 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */
166 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */
167 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */
168 void* pvReserved26;
169 void* pvReserved27;
170 void* pvReserved28;
171 void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */
172 void* pfnDACC_Handler; /* 30 Digital To Analog Converter */
173 void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */
174 void* pfnICM_Handler; /* 32 Integrity Check Monitor */
175 void* pfnACC_Handler; /* 33 Analog Comparator */
176 void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */
177 void* pvReserved35;
178 void* pvReserved36;
179 void* pvReserved37;
180 void* pvReserved38;
181 void* pvReserved39;
182 void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */
183 void* pvReserved41;
184 void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */
185 void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */
186 void* pfnUART2_Handler; /* 44 UART 2 */
187 void* pfnUART3_Handler; /* 45 UART 3 */
188 void* pfnUART4_Handler; /* 46 UART 4 */
189 void* pvReserved47;
190 void* pvReserved48;
191 void* pvReserved49;
192 void* pfnTC9_Handler; /* 50 Timer/Counter 9 */
193 void* pfnTC10_Handler; /* 51 Timer/Counter 10 */
194 void* pfnTC11_Handler; /* 52 Timer/Counter 11 */
195 void* pvReserved53;
196 void* pvReserved54;
197 void* pvReserved55;
198 void* pfnAES_Handler; /* 56 AES */
199 void* pfnTRNG_Handler; /* 57 True Random Generator */
200 void* pfnXDMAC_Handler; /* 58 DMA */
201 void* pfnISI_Handler; /* 59 Camera Interface */
202 void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */
203 void* pvReserved61;
204 void* pvReserved62;
205 void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */
206} DeviceVectors;
207
208/* Cortex-M7 core handlers */
209void Reset_Handler ( void );
210void NMI_Handler ( void );
211void HardFault_Handler ( void );
212void MemManage_Handler ( void );
213void BusFault_Handler ( void );
214void UsageFault_Handler ( void );
215void SVC_Handler ( void );
216void DebugMon_Handler ( void );
217void PendSV_Handler ( void );
218void SysTick_Handler ( void );
219
220/* Peripherals handlers */
221void ACC_Handler ( void );
222void AES_Handler ( void );
223void AFEC0_Handler ( void );
224void AFEC1_Handler ( void );
225void DACC_Handler ( void );
226void EFC_Handler ( void );
227void HSMCI_Handler ( void );
228void ICM_Handler ( void );
229void ISI_Handler ( void );
230void PIOA_Handler ( void );
231void PIOB_Handler ( void );
232void PIOD_Handler ( void );
233void PMC_Handler ( void );
234void PWM0_Handler ( void );
235void PWM1_Handler ( void );
236void QSPI_Handler ( void );
237void RSTC_Handler ( void );
238void RSWDT_Handler ( void );
239void RTC_Handler ( void );
240void RTT_Handler ( void );
241void SPI0_Handler ( void );
242void SPI1_Handler ( void );
243void SSC_Handler ( void );
244void SUPC_Handler ( void );
245void TC0_Handler ( void );
246void TC1_Handler ( void );
247void TC2_Handler ( void );
248void TC9_Handler ( void );
249void TC10_Handler ( void );
250void TC11_Handler ( void );
251void TRNG_Handler ( void );
252void TWIHS0_Handler ( void );
253void TWIHS1_Handler ( void );
254void UART0_Handler ( void );
255void UART1_Handler ( void );
256void UART2_Handler ( void );
257void UART3_Handler ( void );
258void UART4_Handler ( void );
259void USART0_Handler ( void );
260void USART1_Handler ( void );
261void USART2_Handler ( void );
262void USBHS_Handler ( void );
263void WDT_Handler ( void );
264void XDMAC_Handler ( void );
265
270#define __CM7_REV 0x0000
271#define __MPU_PRESENT 1
272#define __NVIC_PRIO_BITS 3
273#define __FPU_PRESENT 1
274#define __FPU_DP 1
275#define __ICACHE_PRESENT 1
276#define __DCACHE_PRESENT 1
277#define __DTCM_PRESENT 1
278#define __ITCM_PRESENT 1
279#define __Vendor_SysTickConfig 0
281/*
282 * \brief CMSIS includes
283 */
284
285#include <core_cm7.h>
286#if !defined DONT_USE_CMSIS_INIT
287#include "system_sams70.h"
288#endif /* DONT_USE_CMSIS_INIT */
289
292/* ************************************************************************** */
294/* ************************************************************************** */
297
298#include "component/component_acc.h"
299#include "component/component_aes.h"
300#include "component/component_afec.h"
301#include "component/component_chipid.h"
302#include "component/component_dacc.h"
303#include "component/component_efc.h"
304#include "component/component_gpbr.h"
305#include "component/component_hsmci.h"
306#include "component/component_icm.h"
307#include "component/component_isi.h"
308#include "component/component_matrix.h"
309#include "component/component_pio.h"
310#include "component/component_pmc.h"
311#include "component/component_pwm.h"
312#include "component/component_qspi.h"
313#include "component/component_rstc.h"
314#include "component/component_rswdt.h"
315#include "component/component_rtc.h"
316#include "component/component_rtt.h"
317#include "component/component_spi.h"
318#include "component/component_ssc.h"
319#include "component/component_supc.h"
320#include "component/component_tc.h"
321#include "component/component_trng.h"
322#include "component/component_twihs.h"
323#include "component/component_uart.h"
324#include "component/component_usart.h"
325#include "component/component_usbhs.h"
326#include "component/component_utmi.h"
327#include "component/component_wdt.h"
328#include "component/component_xdmac.h"
331#ifndef __rtems__
332/* ************************************************************************** */
333/* REGISTER ACCESS DEFINITIONS FOR SAMS70J20 */
334/* ************************************************************************** */
337
338#include "instance/instance_hsmci.h"
339#include "instance/instance_ssc.h"
340#include "instance/instance_spi0.h"
341#include "instance/instance_tc0.h"
342#include "instance/instance_twihs0.h"
343#include "instance/instance_twihs1.h"
344#include "instance/instance_pwm0.h"
345#include "instance/instance_usart0.h"
346#include "instance/instance_usart1.h"
347#include "instance/instance_usart2.h"
348#include "instance/instance_usbhs.h"
349#include "instance/instance_afec0.h"
350#include "instance/instance_dacc.h"
351#include "instance/instance_acc.h"
352#include "instance/instance_icm.h"
353#include "instance/instance_isi.h"
354#include "instance/instance_tc3.h"
355#include "instance/instance_spi1.h"
356#include "instance/instance_pwm1.h"
357#include "instance/instance_afec1.h"
358#include "instance/instance_aes.h"
359#include "instance/instance_trng.h"
360#include "instance/instance_xdmac.h"
361#include "instance/instance_qspi.h"
362#include "instance/instance_matrix.h"
363#include "instance/instance_utmi.h"
364#include "instance/instance_pmc.h"
365#include "instance/instance_uart0.h"
366#include "instance/instance_chipid.h"
367#include "instance/instance_uart1.h"
368#include "instance/instance_efc.h"
369#include "instance/instance_pioa.h"
370#include "instance/instance_piob.h"
371#include "instance/instance_piod.h"
372#include "instance/instance_rstc.h"
373#include "instance/instance_supc.h"
374#include "instance/instance_rtt.h"
375#include "instance/instance_wdt.h"
376#include "instance/instance_rtc.h"
377#include "instance/instance_gpbr.h"
378#include "instance/instance_rswdt.h"
379#include "instance/instance_uart2.h"
380#include "instance/instance_uart3.h"
381#include "instance/instance_uart4.h"
383#endif /* __rtems__ */
384
385/* ************************************************************************** */
386/* PERIPHERAL ID DEFINITIONS FOR SAMS70J20 */
387/* ************************************************************************** */
390
391#define ID_SUPC ( 0)
392#define ID_RSTC ( 1)
393#define ID_RTC ( 2)
394#define ID_RTT ( 3)
395#define ID_WDT ( 4)
396#define ID_PMC ( 5)
397#define ID_EFC ( 6)
398#define ID_UART0 ( 7)
399#define ID_UART1 ( 8)
400#define ID_PIOA (10)
401#define ID_PIOB (11)
402#define ID_USART0 (13)
403#define ID_USART1 (14)
404#define ID_USART2 (15)
405#define ID_PIOD (16)
406#define ID_HSMCI (18)
407#define ID_TWIHS0 (19)
408#define ID_TWIHS1 (20)
409#define ID_SPI0 (21)
410#define ID_SSC (22)
411#define ID_TC0 (23)
412#define ID_TC1 (24)
413#define ID_TC2 (25)
414#define ID_AFEC0 (29)
415#define ID_DACC (30)
416#define ID_PWM0 (31)
417#define ID_ICM (32)
418#define ID_ACC (33)
419#define ID_USBHS (34)
420#define ID_AFEC1 (40)
421#define ID_SPI1 (42)
422#define ID_QSPI (43)
423#define ID_UART2 (44)
424#define ID_UART3 (45)
425#define ID_UART4 (46)
426#define ID_TC9 (50)
427#define ID_TC10 (51)
428#define ID_TC11 (52)
429#define ID_AES (56)
430#define ID_TRNG (57)
431#define ID_XDMAC (58)
432#define ID_ISI (59)
433#define ID_PWM1 (60)
434#define ID_RSWDT (63)
436#define ID_PERIPH_COUNT (64)
438
439/* ************************************************************************** */
440/* BASE ADDRESS DEFINITIONS FOR SAMS70J20 */
441/* ************************************************************************** */
444
445#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
446#define HSMCI (0x40000000U)
447#define SSC (0x40004000U)
448#define SPI0 (0x40008000U)
449#define TC0 (0x4000C000U)
450#define TWIHS0 (0x40018000U)
451#define TWIHS1 (0x4001C000U)
452#define PWM0 (0x40020000U)
453#define USART0 (0x40024000U)
454#define USART1 (0x40028000U)
455#define USART2 (0x4002C000U)
456#define USBHS (0x40038000U)
457#define AFEC0 (0x4003C000U)
458#define DACC (0x40040000U)
459#define ACC (0x40044000U)
460#define ICM (0x40048000U)
461#define ISI (0x4004C000U)
462#define TC3 (0x40054000U)
463#define SPI1 (0x40058000U)
464#define PWM1 (0x4005C000U)
465#define AFEC1 (0x40064000U)
466#define AES (0x4006C000U)
467#define TRNG (0x40070000U)
468#define XDMAC (0x40078000U)
469#define QSPI (0x4007C000U)
470#define MATRIX (0x40088000U)
471#define UTMI (0x400E0400U)
472#define PMC (0x400E0600U)
473#define UART0 (0x400E0800U)
474#define CHIPID (0x400E0940U)
475#define UART1 (0x400E0A00U)
476#define EFC (0x400E0C00U)
477#define PIOA (0x400E0E00U)
478#define PIOB (0x400E1000U)
479#define PIOD (0x400E1400U)
480#define RSTC (0x400E1800U)
481#define SUPC (0x400E1810U)
482#define RTT (0x400E1830U)
483#define WDT (0x400E1850U)
484#define RTC (0x400E1860U)
485#define GPBR (0x400E1890U)
486#define RSWDT (0x400E1900U)
487#define UART2 (0x400E1A00U)
488#define UART3 (0x400E1C00U)
489#define UART4 (0x400E1E00U)
490#else
491#define HSMCI ((Hsmci *)0x40000000U)
492#define SSC ((Ssc *)0x40004000U)
493#define SPI0 ((Spi *)0x40008000U)
494#define TC0 ((Tc *)0x4000C000U)
495#define TWIHS0 ((Twihs *)0x40018000U)
496#define TWIHS1 ((Twihs *)0x4001C000U)
497#define PWM0 ((Pwm *)0x40020000U)
498#define USART0 ((Usart *)0x40024000U)
499#define USART1 ((Usart *)0x40028000U)
500#define USART2 ((Usart *)0x4002C000U)
501#define USBHS ((Usbhs *)0x40038000U)
502#define AFEC0 ((Afec *)0x4003C000U)
503#define DACC ((Dacc *)0x40040000U)
504#define ACC ((Acc *)0x40044000U)
505#define ICM ((Icm *)0x40048000U)
506#define ISI ((Isi *)0x4004C000U)
507#define TC3 ((Tc *)0x40054000U)
508#define SPI1 ((Spi *)0x40058000U)
509#define PWM1 ((Pwm *)0x4005C000U)
510#define AFEC1 ((Afec *)0x40064000U)
511#define AES ((Aes *)0x4006C000U)
512#define TRNG ((Trng *)0x40070000U)
513#define XDMAC ((Xdmac *)0x40078000U)
514#define QSPI ((Qspi *)0x4007C000U)
515#define MATRIX ((Matrix *)0x40088000U)
516#define UTMI ((Utmi *)0x400E0400U)
517#define PMC ((Pmc *)0x400E0600U)
518#define UART0 ((Uart *)0x400E0800U)
519#define CHIPID ((Chipid *)0x400E0940U)
520#define UART1 ((Uart *)0x400E0A00U)
521#define EFC ((Efc *)0x400E0C00U)
522#define PIOA ((Pio *)0x400E0E00U)
523#define PIOB ((Pio *)0x400E1000U)
524#define PIOD ((Pio *)0x400E1400U)
525#define RSTC ((Rstc *)0x400E1800U)
526#define SUPC ((Supc *)0x400E1810U)
527#define RTT ((Rtt *)0x400E1830U)
528#define WDT ((Wdt *)0x400E1850U)
529#define RTC ((Rtc *)0x400E1860U)
530#define GPBR ((Gpbr *)0x400E1890U)
531#define RSWDT ((Rswdt *)0x400E1900U)
532#define UART2 ((Uart *)0x400E1A00U)
533#define UART3 ((Uart *)0x400E1C00U)
534#define UART4 ((Uart *)0x400E1E00U)
535#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
538/* ************************************************************************** */
539/* PIO DEFINITIONS FOR SAMS70J20 */
540/* ************************************************************************** */
543
544#include "pio/pio_sams70j20.h"
547/* ************************************************************************** */
548/* MEMORY MAPPING DEFINITIONS FOR SAMS70J20 */
549/* ************************************************************************** */
550
551#define IFLASH_SIZE (0x100000u)
552#define IFLASH_PAGE_SIZE (512u)
553#define IFLASH_LOCK_REGION_SIZE (8192u)
554#define IFLASH_NB_OF_PAGES (2048u)
555#define IFLASH_NB_OF_LOCK_BITS (64u)
556#define IRAM_SIZE (0x60000u)
557
558#define QSPIMEM_ADDR (0x80000000u)
559#define AXIMX_ADDR (0xA0000000u)
560#define ITCM_ADDR (0x00000000u)
561#define IFLASH_ADDR (0x00400000u)
562#define IROM_ADDR (0x00800000u)
563#define DTCM_ADDR (0x20000000u)
564#define IRAM_ADDR (0x20400000u)
565#define EBI_CS0_ADDR (0x60000000u)
566#define EBI_CS1_ADDR (0x61000000u)
567#define EBI_CS2_ADDR (0x62000000u)
568#define EBI_CS3_ADDR (0x63000000u)
569#define SDRAM_CS_ADDR (0x70000000u)
571/* ************************************************************************** */
572/* MISCELLANEOUS DEFINITIONS FOR SAMS70J20 */
573/* ************************************************************************** */
574
575#define CHIP_JTAGID (0x05B3D03FUL)
576#define CHIP_CIDR (0xA1120C00UL)
577#define CHIP_EXID (0x00000000UL)
578
579/* ************************************************************************** */
580/* ELECTRICAL DEFINITIONS FOR SAMS70J20 */
581/* ************************************************************************** */
582
583/* %ATMEL_ELECTRICAL% */
584
585/* Device characteristics */
586#define CHIP_FREQ_SLCK_RC_MIN (20000UL)
587#define CHIP_FREQ_SLCK_RC (32000UL)
588#define CHIP_FREQ_SLCK_RC_MAX (44000UL)
589#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL)
590#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL)
591#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL)
592#define CHIP_FREQ_CPU_MAX (120000000UL)
593#define CHIP_FREQ_XTAL_32K (32768UL)
594#define CHIP_FREQ_XTAL_12M (12000000UL)
595
596/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
597#define CHIP_FREQ_FWS_0 (20000000UL)
598#define CHIP_FREQ_FWS_1 (40000000UL)
599#define CHIP_FREQ_FWS_2 (60000000UL)
600#define CHIP_FREQ_FWS_3 (80000000UL)
601#define CHIP_FREQ_FWS_4 (100000000UL)
602#define CHIP_FREQ_FWS_5 (123000000UL)
604#ifdef __cplusplus
605}
606#endif
607
610#endif /* _SAMS70J20_ */
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
UsageFault_Handler
void UsageFault_Handler(void)
Default UsageFault interrupt handler.
Definition: exceptions.c:207
HardFault_Handler
void HardFault_Handler(void)
Default HardFault interrupt handler.
Definition: exceptions.c:168
MemManage_Handler
void MemManage_Handler(void)
Default MemManage interrupt handler.
Definition: exceptions.c:180
NMI_Handler
void NMI_Handler(void)
Default NMI interrupt handler.
Definition: exceptions.c:53
BusFault_Handler
void BusFault_Handler(void)
Default BusFault interrupt handler.
Definition: exceptions.c:193
TC9_IRQn
@ TC9_IRQn
Definition: sams70j20.h:106
PendSV_IRQn
@ PendSV_IRQn
Definition: sams70j20.h:67
PWM1_IRQn
@ PWM1_IRQn
Definition: sams70j20.h:113
UART3_IRQn
@ UART3_IRQn
Definition: sams70j20.h:104
XDMAC_IRQn
@ XDMAC_IRQn
Definition: sams70j20.h:111
TC0_IRQn
@ TC0_IRQn
Definition: sams70j20.h:91
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: sams70j20.h:62
ISI_IRQn
@ ISI_IRQn
Definition: sams70j20.h:112
TWIHS1_IRQn
@ TWIHS1_IRQn
Definition: sams70j20.h:88
USART2_IRQn
@ USART2_IRQn
Definition: sams70j20.h:84
USART0_IRQn
@ USART0_IRQn
Definition: sams70j20.h:82
SVCall_IRQn
@ SVCall_IRQn
Definition: sams70j20.h:65
RSWDT_IRQn
@ RSWDT_IRQn
Definition: sams70j20.h:114
AFEC0_IRQn
@ AFEC0_IRQn
Definition: sams70j20.h:94
TC1_IRQn
@ TC1_IRQn
Definition: sams70j20.h:92
UsageFault_IRQn
@ UsageFault_IRQn
Definition: sams70j20.h:64
SysTick_IRQn
@ SysTick_IRQn
Definition: sams70j20.h:68
PMC_IRQn
@ PMC_IRQn
Definition: sams70j20.h:76
SUPC_IRQn
@ SUPC_IRQn
Definition: sams70j20.h:71
WDT_IRQn
@ WDT_IRQn
Definition: sams70j20.h:75
SSC_IRQn
@ SSC_IRQn
Definition: sams70j20.h:90
PIOA_IRQn
@ PIOA_IRQn
Definition: sams70j20.h:80
PERIPH_COUNT_IRQn
@ PERIPH_COUNT_IRQn
Definition: sams70j20.h:116
AES_IRQn
@ AES_IRQn
Definition: sams70j20.h:109
BusFault_IRQn
@ BusFault_IRQn
Definition: sams70j20.h:63
TC11_IRQn
@ TC11_IRQn
Definition: sams70j20.h:108
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: sams70j20.h:66
TC2_IRQn
@ TC2_IRQn
Definition: sams70j20.h:93
UART1_IRQn
@ UART1_IRQn
Definition: sams70j20.h:79
TC10_IRQn
@ TC10_IRQn
Definition: sams70j20.h:107
RSTC_IRQn
@ RSTC_IRQn
Definition: sams70j20.h:72
PIOD_IRQn
@ PIOD_IRQn
Definition: sams70j20.h:85
SPI1_IRQn
@ SPI1_IRQn
Definition: sams70j20.h:101
UART2_IRQn
@ UART2_IRQn
Definition: sams70j20.h:103
HardFault_IRQn
@ HardFault_IRQn
Definition: sams70j20.h:61
TRNG_IRQn
@ TRNG_IRQn
Definition: sams70j20.h:110
RTT_IRQn
@ RTT_IRQn
Definition: sams70j20.h:74
AFEC1_IRQn
@ AFEC1_IRQn
Definition: sams70j20.h:100
QSPI_IRQn
@ QSPI_IRQn
Definition: sams70j20.h:102
USART1_IRQn
@ USART1_IRQn
Definition: sams70j20.h:83
RTC_IRQn
@ RTC_IRQn
Definition: sams70j20.h:73
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: sams70j20.h:60
UART4_IRQn
@ UART4_IRQn
Definition: sams70j20.h:105
TWIHS0_IRQn
@ TWIHS0_IRQn
Definition: sams70j20.h:87
PIOB_IRQn
@ PIOB_IRQn
Definition: sams70j20.h:81
USBHS_IRQn
@ USBHS_IRQn
Definition: sams70j20.h:99
PWM0_IRQn
@ PWM0_IRQn
Definition: sams70j20.h:96
HSMCI_IRQn
@ HSMCI_IRQn
Definition: sams70j20.h:86
UART0_IRQn
@ UART0_IRQn
Definition: sams70j20.h:78
ICM_IRQn
@ ICM_IRQn
Definition: sams70j20.h:97
ACC_IRQn
@ ACC_IRQn
Definition: sams70j20.h:98
EFC_IRQn
@ EFC_IRQn
Definition: sams70j20.h:77
SPI0_IRQn
@ SPI0_IRQn
Definition: sams70j20.h:89
DACC_IRQn
@ DACC_IRQn
Definition: sams70j20.h:95
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h723xx.h:49
_DeviceVectors
Definition: same70j19.h:122
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