RTEMS
6.1-rc1
bsps
arm
tms570
include
bsp
ti_herc
reg_sys.h
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/* The header file is generated by make_header.py from SYS.json */
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/* Current script's version can be found at: */
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/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
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/*
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* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation are those
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* of the authors and should not be interpreted as representing official policies,
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* either expressed or implied, of the FreeBSD Project.
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*/
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#ifndef LIBBSP_ARM_TMS570_SYS1
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#define LIBBSP_ARM_TMS570_SYS1
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#include <
bsp/utility.h
>
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typedef
struct
{
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uint32_t SYSPC1;
/*SYS Pin Control Register 1*/
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uint32_t SYSPC2;
/*SYS Pin Control Register 2*/
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uint32_t SYSPC3;
/*SYS Pin Control Register 3*/
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uint32_t SYSPC4;
/*SYS Pin Control Register 4*/
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uint32_t SYSPC5;
/*SYS Pin Control Register 5*/
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uint32_t SYSPC6;
/*SYS Pin Control Register 6*/
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uint32_t SYSPC7;
/*SYS Pin Control Register 7*/
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uint32_t SYSPC8;
/*SYS Pin Control Register 8*/
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uint32_t SYSPC9;
/*SYS Pin Control Register 9*/
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uint8_t reserved1 [12];
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uint32_t CSDIS;
/*Clock Source Disable Register*/
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uint32_t CSDISSET;
/*Clock Source Disable Set Register*/
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uint32_t CSDISCLR;
/*Clock Source Disable Clear Register*/
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uint32_t CDDIS;
/*Clock Domain Disable Register*/
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uint32_t CDDISSET;
/*Clock Domain Disable Set Register*/
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uint32_t CDDISCLR;
/*Clock Domain Disable Clear Register*/
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uint32_t GHVSRC;
/*GCLK, HCLK, VCLK, and VCLK2 Source Register*/
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uint32_t VCLKASRC;
/*Peripheral Asynchronous Clock Source Register*/
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uint32_t RCLKSRC;
/*RTI Clock Source Register*/
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uint32_t CSVSTAT;
/*Clock Source Valid Status Register*/
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uint32_t MSTGCR;
/*Memory Self-Test Global Control Register*/
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uint32_t MINITGCR;
/*Memory Hardware Initialization Global Control Register*/
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uint32_t MSIENA;
/*Memory Self-Test/Initialization Enable Register*/
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uint8_t reserved2 [4];
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uint32_t MSTCGSTAT;
/*MSTC Global Status Register*/
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uint32_t MINISTAT;
/*Memory Hardware Initialization Status Register*/
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uint32_t PLLCTL1;
/*PLL Control Register 1*/
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uint32_t PLLCTL2;
/*PLL Control Register 2*/
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uint32_t SYSPC10;
/*SYS Pin Control Register 10*/
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uint32_t DIEIDL;
/*Die Identification Register, Lower Word*/
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uint32_t DIEIDH;
/*Die Identification Register, Upper Word*/
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uint8_t reserved3 [4];
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uint32_t LPOMONCTL;
/*LPO/Clock Monitor Control Register*/
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uint32_t CLKTEST;
/*Clock Test Register*/
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uint32_t DFTCTRLREG1;
/*DFT Control Register*/
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uint32_t DFTCTRLREG2;
/*DFT Control Register 2*/
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uint8_t reserved4 [8];
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uint32_t GPREG1;
/*General Purpose Register*/
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uint8_t reserved5 [4];
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uint32_t IMPFASTS;
/*Imprecise Fault Status Register*/
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uint32_t IMPFTADD;
/*Imprecise Fault Write Address Register*/
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uint32_t SSIR1;
/*System Software Interrupt Request 1 Register*/
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uint32_t SSIR2;
/*System Software Interrupt Request 2 Register*/
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uint32_t SSIR3;
/*System Software Interrupt Request 3 Register*/
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uint32_t SSIR4;
/*System Software Interrupt Request 4 Register*/
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uint32_t RAMGCR;
/*RAM Control Register*/
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uint32_t BMMCR1;
/*Bus Matrix Module Control Register 1*/
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uint8_t reserved6 [4];
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uint32_t CPURSTCR;
/*CPU Reset Control Register*/
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uint32_t CLKCNTL;
/*Clock Control Register*/
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uint32_t ECPCNTL;
/*ECP Control Register*/
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uint8_t reserved7 [4];
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uint32_t DEVCR1;
/*DEV Parity Control Register 1*/
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uint32_t SYSECR;
/*System Exception Control Register*/
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uint32_t SYSESR;
/*System Exception Status Register*/
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uint32_t SYSTASR;
/*System Test Abort Status Register*/
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uint32_t GLBSTAT;
/*Global Status Register*/
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uint32_t DEVID;
/*Device Identification Register*/
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uint32_t SSIVEC;
/*Software Interrupt Vector Register*/
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uint32_t SSIF;
/*System Software Interrupt Flag Register*/
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}
tms570_sys1_t
;
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/*---------------------TMS570_SYS1_SYSPCx---------------------*/
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/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
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#define TMS570_SYS1_SYSPCx_ECPCLKFUN BSP_BIT32(0)
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/*---------------------TMS570_SYS1_CSDIS---------------------*/
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/* field: CLKSROFF - Clock source[7-0] off. 2 reserved */
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#define TMS570_SYS1_CSDIS_CLKSROFF(val) BSP_FLD32(val,0, 7)
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#define TMS570_SYS1_CSDIS_CLKSROFF_GET(reg) BSP_FLD32GET(reg,0, 7)
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#define TMS570_SYS1_CSDIS_CLKSROFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
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/* Clock Source 0 Oscillator */
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#define TMS570_SYS1_CSDIS_CLKSR_OSC_NUM 0
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#define TMS570_SYS1_CSDIS_CLKSROFF_OSC BSP_BIT32(0)
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/* Clock Source 1 PLL1 */
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#define TMS570_SYS1_CSDIS_CLKSR_PLL1_NUM 1
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#define TMS570_SYS1_CSDIS_CLKSROFF_PLL1 BSP_BIT32(1)
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/* Clock Source 3 EXTCLKIN */
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#define TMS570_SYS1_CSDIS_CLKSR_EXTCLKIN_NUM 3
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#define TMS570_SYS1_CSDIS_CLKSROFF_EXTCLKIN BSP_BIT32(3)
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/* Clock Source 4 Low Frequency LPO (Low Power Oscillator) clock */
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#define TMS570_SYS1_CSDIS_CLKSR_LPO_NUM 4
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#define TMS570_SYS1_CSDIS_CLKSROFF_LPO BSP_BIT32(4)
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/* Clock Source 5 High Frequency LPO (Low Power Oscillator) clock */
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#define TMS570_SYS1_CSDIS_CLKSR_HPO_NUM 5
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#define TMS570_SYS1_CSDIS_CLKSROFF_HPO BSP_BIT32(5)
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/* Clock Source 6 PLL2 */
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#define TMS570_SYS1_CSDIS_CLKSR_PLL2_NUM 6
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#define TMS570_SYS1_CSDIS_CLKSROFF_PLL2 BSP_BIT32(6)
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/* Clock Source 7 EXTCLKIN2 */
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#define TMS570_SYS1_CSDIS_CLKSR_EXTCLKIN2_NUM 7
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#define TMS570_SYS1_CSDIS_CLKSROFF_EXTCLKIN2 BSP_BIT32(7)
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/*--------------------TMS570_SYS1_CSDISSET--------------------*/
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/* field: SETCLKSR_OFF - Set clock source[7-0] to the disabled state. */
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#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF(val) BSP_FLD32(val,0, 7)
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#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
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#define TMS570_SYS1_CSDISSET_SETCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
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/*--------------------TMS570_SYS1_CSDISCLR--------------------*/
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/* field: CLRCLKSR_OFF - Enables clock source[7-0] */
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#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF(val) BSP_FLD32(val,0, 7)
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#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_GET(reg) BSP_FLD32GET(reg,0, 7)
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#define TMS570_SYS1_CSDISCLR_CLRCLKSR_OFF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
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/*---------------------TMS570_SYS1_CDDIS---------------------*/
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/* field: VCLKAOFF - VCLKA4 domain off. */
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#define TMS570_SYS1_CDDIS_VCLKAOFF4 BSP_BIT32(11)
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/* field: VCLKAOFF - VCLKA3 domain off. */
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#define TMS570_SYS1_CDDIS_VCLKAOFF3 BSP_BIT32(10)
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/* field: VCLK3OFF - VCLK3 domain off. */
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#define TMS570_SYS1_CDDIS_VCLK3OFF BSP_BIT32(8)
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/* field: RTICLK1OFF - RTICLK1 domain off. */
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#define TMS570_SYS1_CDDIS_RTICLK1OFF BSP_BIT32(6)
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/* field: VCLKAOFF - VCLKA2 domain off. */
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#define TMS570_SYS1_CDDIS_VCLKAOFF2 BSP_BIT32(5)
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/* field: VCLKAOFF - VCLKA1 domain off. */
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#define TMS570_SYS1_CDDIS_VCLKAOFF1 BSP_BIT32(4)
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/* field: VCLK2OFF - VCLK2 domain off. */
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#define TMS570_SYS1_CDDIS_VCLK2OFF BSP_BIT32(3)
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/* field: VCLKPOFF - VCLK_periph domain off. */
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#define TMS570_SYS1_CDDIS_VCLKPOFF BSP_BIT32(2)
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/* field: HCLKOFF - HCLK and VCLK_sys domains off. */
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#define TMS570_SYS1_CDDIS_HCLKOFF BSP_BIT32(1)
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/* field: GCLKOFF - GCLK domain off. */
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#define TMS570_SYS1_CDDIS_GCLKOFF BSP_BIT32(0)
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/*--------------------TMS570_SYS1_CDDISSET--------------------*/
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/* field: SETVCLKA_OFF - Set VCLKA[4-3] domain. */
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#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF(val) BSP_FLD32(val,10, 11)
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#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_GET(reg) BSP_FLD32GET(reg,10, 11)
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#define TMS570_SYS1_CDDISSET_SETVCLKA_OFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
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/* field: SETVCLK3OFF - Set VCLK3 domain. */
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#define TMS570_SYS1_CDDISSET_SETVCLK3OFF BSP_BIT32(8)
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/* field: SETRTI1CLKOFF - Set RTICLK1 domain. */
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#define TMS570_SYS1_CDDISSET_SETRTI1CLKOFF BSP_BIT32(6)
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/* field: SETTVCLKA2OFF - Set VCLKA2 domain. */
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#define TMS570_SYS1_CDDISSET_SETTVCLKA2OFF BSP_BIT32(5)
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/* field: SETVCLKA1OFF - Set VCLKA1 domain. */
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#define TMS570_SYS1_CDDISSET_SETVCLKA1OFF BSP_BIT32(4)
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/* field: SETVCLK2OFF - Set VCLK2 domain. */
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#define TMS570_SYS1_CDDISSET_SETVCLK2OFF BSP_BIT32(3)
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/* field: SETVCLKPOFF - Set VCLK_periph domain. */
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#define TMS570_SYS1_CDDISSET_SETVCLKPOFF BSP_BIT32(2)
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/* field: SETHCLKOFF - Set HCLK and VCLK_sys domains. */
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#define TMS570_SYS1_CDDISSET_SETHCLKOFF BSP_BIT32(1)
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/* field: SETGCLKOFF - Set GCLK domain. */
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#define TMS570_SYS1_CDDISSET_SETGCLKOFF BSP_BIT32(0)
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/*--------------------TMS570_SYS1_CDDISCLR--------------------*/
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/* field: CLRVCLKAOFF - Clear VCLKA[4-3] domain. */
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#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF(val) BSP_FLD32(val,10, 11)
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#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_GET(reg) BSP_FLD32GET(reg,10, 11)
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#define TMS570_SYS1_CDDISCLR_CLRVCLKAOFF_SET(reg,val) BSP_FLD32SET(reg, val,10, 11)
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/* field: Reserved - Reserved */
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#define TMS570_SYS1_CDDISCLR_Reserved BSP_BIT32(9)
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/* field: CLRVCLK3OFF - Clear VCLK3 domain. */
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#define TMS570_SYS1_CDDISCLR_CLRVCLK3OFF BSP_BIT32(8)
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/* field: CLRRTI1CLKOFF - Clear RTICLK1 domain. */
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#define TMS570_SYS1_CDDISCLR_CLRRTI1CLKOFF BSP_BIT32(6)
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/* field: CLRTVCLKA2OFF - Clear VCLKA2 domain. */
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#define TMS570_SYS1_CDDISCLR_CLRTVCLKA2OFF BSP_BIT32(5)
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/* field: CLRVCLKA1OFF - Clear VCLKA1 domain. */
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#define TMS570_SYS1_CDDISCLR_CLRVCLKA1OFF BSP_BIT32(4)
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/* field: CLRVCLK2OFF - Clear VCLK2 domain. */
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#define TMS570_SYS1_CDDISCLR_CLRVCLK2OFF BSP_BIT32(3)
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/* field: CLRVCLKPOFF - CLRVCLKPOFF */
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#define TMS570_SYS1_CDDISCLR_CLRVCLKPOFF BSP_BIT32(2)
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/* field: CLRHCLKOFF - Clear HCLK and VCLK_sys domains. */
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#define TMS570_SYS1_CDDISCLR_CLRHCLKOFF BSP_BIT32(1)
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/* field: CLRGCLKOFF - Clear GCLK domain. */
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#define TMS570_SYS1_CDDISCLR_CLRGCLKOFF BSP_BIT32(0)
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/*---------------------TMS570_SYS1_GHVSRC---------------------*/
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/* field: GHVWAKE - GCLK, HCLK, VCLK, VCLK2 source on wakeup. */
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#define TMS570_SYS1_GHVSRC_GHVWAKE(val) BSP_FLD32(val,24, 27)
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#define TMS570_SYS1_GHVSRC_GHVWAKE_GET(reg) BSP_FLD32GET(reg,24, 27)
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#define TMS570_SYS1_GHVSRC_GHVWAKE_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
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/* field: HVLPM - HCLK, VCLK, VCLK2 source on wakeup when GCLK is turned off. */
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#define TMS570_SYS1_GHVSRC_HVLPM(val) BSP_FLD32(val,16, 19)
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#define TMS570_SYS1_GHVSRC_HVLPM_GET(reg) BSP_FLD32GET(reg,16, 19)
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#define TMS570_SYS1_GHVSRC_HVLPM_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
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/* field: GHVSRC - GCLK, HCLK, VCLK, VCLK2 current source. */
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#define TMS570_SYS1_GHVSRC_GHVSRC(val) BSP_FLD32(val,0, 3)
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#define TMS570_SYS1_GHVSRC_GHVSRC_GET(reg) BSP_FLD32GET(reg,0, 3)
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#define TMS570_SYS1_GHVSRC_GHVSRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
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/*--------------------TMS570_SYS1_VCLKASRC--------------------*/
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/* field: VCLKA2S - Peripheral asynchronous clock2 source. */
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#define TMS570_SYS1_VCLKASRC_VCLKA2S(val) BSP_FLD32(val,8, 11)
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#define TMS570_SYS1_VCLKASRC_VCLKA2S_GET(reg) BSP_FLD32GET(reg,8, 11)
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#define TMS570_SYS1_VCLKASRC_VCLKA2S_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
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/* field: VCLKA1S - Peripheral asynchronous clock1 source. */
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#define TMS570_SYS1_VCLKASRC_VCLKA1S(val) BSP_FLD32(val,0, 3)
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#define TMS570_SYS1_VCLKASRC_VCLKA1S_GET(reg) BSP_FLD32GET(reg,0, 3)
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#define TMS570_SYS1_VCLKASRC_VCLKA1S_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
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/*--------------------TMS570_SYS1_RCLKSRC--------------------*/
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/* field: RTI1DIV - RTI clock1 Divider. */
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#define TMS570_SYS1_RCLKSRC_RTI1DIV(val) BSP_FLD32(val,8, 9)
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#define TMS570_SYS1_RCLKSRC_RTI1DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
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#define TMS570_SYS1_RCLKSRC_RTI1DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
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/* field: RTI1SRC - RTI clock1 source. */
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#define TMS570_SYS1_RCLKSRC_RTI1SRC(val) BSP_FLD32(val,0, 3)
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#define TMS570_SYS1_RCLKSRC_RTI1SRC_GET(reg) BSP_FLD32GET(reg,0, 3)
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#define TMS570_SYS1_RCLKSRC_RTI1SRC_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
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/*--------------------TMS570_SYS1_CSVSTAT--------------------*/
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/* field: CLKSRV - Clock source[7-0] valid. */
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#define TMS570_SYS1_CSVSTAT_CLKSRV(val) BSP_FLD32(val,3, 7)
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#define TMS570_SYS1_CSVSTAT_CLKSRV_GET(reg) BSP_FLD32GET(reg,3, 7)
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#define TMS570_SYS1_CSVSTAT_CLKSRV_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
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/* field: CLKSR - Clock source[1-0] valid. */
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#define TMS570_SYS1_CSVSTAT_CLKSR(val) BSP_FLD32(val,0, 1)
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#define TMS570_SYS1_CSVSTAT_CLKSR_GET(reg) BSP_FLD32GET(reg,0, 1)
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#define TMS570_SYS1_CSVSTAT_CLKSR_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
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/*---------------------TMS570_SYS1_MSTGCR---------------------*/
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/* field: ROM_DIV - Prescaler divider bits for ROM clock source. */
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#define TMS570_SYS1_MSTGCR_ROM_DIV(val) BSP_FLD32(val,8, 9)
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#define TMS570_SYS1_MSTGCR_ROM_DIV_GET(reg) BSP_FLD32GET(reg,8, 9)
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#define TMS570_SYS1_MSTGCR_ROM_DIV_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
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/* field: MSTGENA - Memory self-test controller global enable key */
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#define TMS570_SYS1_MSTGCR_MSTGENA(val) BSP_FLD32(val,0, 3)
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#define TMS570_SYS1_MSTGCR_MSTGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
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#define TMS570_SYS1_MSTGCR_MSTGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
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/*--------------------TMS570_SYS1_MINITGCR--------------------*/
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/* field: MINITGENA - Memory hardware initialization global enable key. */
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#define TMS570_SYS1_MINITGCR_MINITGENA(val) BSP_FLD32(val,0, 3)
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#define TMS570_SYS1_MINITGCR_MINITGENA_GET(reg) BSP_FLD32GET(reg,0, 3)
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#define TMS570_SYS1_MINITGCR_MINITGENA_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
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/*---------------------TMS570_SYS1_MSIENA---------------------*/
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/* field: MSIENA - PBIST controller and memory initialization enable register. */
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/* Whole 32 bits */
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/*-------------------TMS570_SYS1_MSTCGSTAT-------------------*/
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/* field: MINIDONE - Memory hardware initialization complete status. */
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#define TMS570_SYS1_MSTCGSTAT_MINIDONE BSP_BIT32(8)
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/* field: MSTDONE - Memory self-test run complete status. */
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#define TMS570_SYS1_MSTCGSTAT_MSTDONE BSP_BIT32(0)
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/*--------------------TMS570_SYS1_MINISTAT--------------------*/
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/* field: MIDONE - Memory hardware initialization status bit. */
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/* Whole 32 bits */
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/*--------------------TMS570_SYS1_PLLCTL1--------------------*/
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/* field: ROS - Reset on PLL Slip */
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#define TMS570_SYS1_PLLCTL1_ROS BSP_BIT32(31)
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/* field: MASK_SLIP - Mask detection of PLL slip */
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#define TMS570_SYS1_PLLCTL1_MASK_SLIP(val) BSP_FLD32(val,29, 30)
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#define TMS570_SYS1_PLLCTL1_MASK_SLIP_GET(reg) BSP_FLD32GET(reg,29, 30)
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#define TMS570_SYS1_PLLCTL1_MASK_SLIP_SET(reg,val) BSP_FLD32SET(reg, val,29, 30)
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/* field: PLLDIV - PLL Output Clock Divider */
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#define TMS570_SYS1_PLLCTL1_PLLDIV(val) BSP_FLD32(val,24, 28)
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#define TMS570_SYS1_PLLCTL1_PLLDIV_GET(reg) BSP_FLD32GET(reg,24, 28)
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#define TMS570_SYS1_PLLCTL1_PLLDIV_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
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/* field: ROF - Reset on Oscillator Fail */
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#define TMS570_SYS1_PLLCTL1_ROF BSP_BIT32(23)
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/* field: REFCLKDIV - Reference Clock Divider */
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#define TMS570_SYS1_PLLCTL1_REFCLKDIV(val) BSP_FLD32(val,16, 21)
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#define TMS570_SYS1_PLLCTL1_REFCLKDIV_GET(reg) BSP_FLD32GET(reg,16, 21)
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#define TMS570_SYS1_PLLCTL1_REFCLKDIV_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
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/* field: PLLMUL - PLL Multiplication Factor */
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#define TMS570_SYS1_PLLCTL1_PLLMUL(val) BSP_FLD32(val,0, 15)
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#define TMS570_SYS1_PLLCTL1_PLLMUL_GET(reg) BSP_FLD32GET(reg,0, 15)
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#define TMS570_SYS1_PLLCTL1_PLLMUL_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
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/*--------------------TMS570_SYS1_PLLCTL2--------------------*/
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/* field: FMENA - Frequency Modulation Enable. */
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#define TMS570_SYS1_PLLCTL2_FMENA BSP_BIT32(31)
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/* field: SPREADINGRATE - NS = SPREADINGRATE + 1 */
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#define TMS570_SYS1_PLLCTL2_SPREADINGRATE(val) BSP_FLD32(val,22, 30)
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#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_GET(reg) BSP_FLD32GET(reg,22, 30)
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#define TMS570_SYS1_PLLCTL2_SPREADINGRATE_SET(reg,val) BSP_FLD32SET(reg, val,22, 30)
380
381
/* field: MULMOD - Multiplier Correction when Frequency Modulation is enabled. */
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#define TMS570_SYS1_PLLCTL2_MULMOD(val) BSP_FLD32(val,12, 20)
383
#define TMS570_SYS1_PLLCTL2_MULMOD_GET(reg) BSP_FLD32GET(reg,12, 20)
384
#define TMS570_SYS1_PLLCTL2_MULMOD_SET(reg,val) BSP_FLD32SET(reg, val,12, 20)
385
386
/* field: ODPLL - Internal PLL Output Divider. */
387
#define TMS570_SYS1_PLLCTL2_ODPLL(val) BSP_FLD32(val,9, 11)
388
#define TMS570_SYS1_PLLCTL2_ODPLL_GET(reg) BSP_FLD32GET(reg,9, 11)
389
#define TMS570_SYS1_PLLCTL2_ODPLL_SET(reg,val) BSP_FLD32SET(reg, val,9, 11)
390
391
/* field: SPR_AMOUNT - Spreading Amount. */
392
#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT(val) BSP_FLD32(val,0, 8)
393
#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_GET(reg) BSP_FLD32GET(reg,0, 8)
394
#define TMS570_SYS1_PLLCTL2_SPR_AMOUNT_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
395
396
397
/*--------------------TMS570_SYS1_SYSPC10--------------------*/
398
/* field: ECPCLK_SLEW - ECPCLK slew control. This bit controls between the fast or slow slew mode. */
399
#define TMS570_SYS1_SYSPC10_ECPCLK_SLEW BSP_BIT32(0)
400
401
402
/*---------------------TMS570_SYS1_DIEIDL---------------------*/
403
/* field: LOT - These read only bits contain the lower 10 bits of the device lot number. */
404
#define TMS570_SYS1_DIEIDL_LOT(val) BSP_FLD32(val,22, 31)
405
#define TMS570_SYS1_DIEIDL_LOT_GET(reg) BSP_FLD32GET(reg,22, 31)
406
#define TMS570_SYS1_DIEIDL_LOT_SET(reg,val) BSP_FLD32SET(reg, val,22, 31)
407
408
/* field: WAFER - These read only bits contain the wafer number of the device. */
409
#define TMS570_SYS1_DIEIDL_WAFER(val) BSP_FLD32(val,16, 21)
410
#define TMS570_SYS1_DIEIDL_WAFER_GET(reg) BSP_FLD32GET(reg,16, 21)
411
#define TMS570_SYS1_DIEIDL_WAFER_SET(reg,val) BSP_FLD32SET(reg, val,16, 21)
412
413
/* field: Y_WAFER_COORDINATE - These read only bits contain the Y wafer coordinate of the device */
414
#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE(val) BSP_FLD32(val,8, 15)
415
#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,8, 15)
416
#define TMS570_SYS1_DIEIDL_Y_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
417
418
/* field: X_WAFER_COORDINATE - These read only bits contain the X wafer coordinate of the device */
419
#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE(val) BSP_FLD32(val,0, 7)
420
#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_GET(reg) BSP_FLD32GET(reg,0, 7)
421
#define TMS570_SYS1_DIEIDL_X_WAFER_COORDINATE_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
422
423
424
/*---------------------TMS570_SYS1_DIEIDH---------------------*/
425
/* field: LOT - This read-only register contains the upper 14 bits of the device lot number. */
426
#define TMS570_SYS1_DIEIDH_LOT(val) BSP_FLD32(val,0, 13)
427
#define TMS570_SYS1_DIEIDH_LOT_GET(reg) BSP_FLD32GET(reg,0, 13)
428
#define TMS570_SYS1_DIEIDH_LOT_SET(reg,val) BSP_FLD32SET(reg, val,0, 13)
429
430
431
/*-------------------TMS570_SYS1_LPOMONCTL-------------------*/
432
/* field: BIAS_ENABLE - Bias enable. */
433
#define TMS570_SYS1_LPOMONCTL_BIAS_ENABLE BSP_BIT32(24)
434
435
/* field: OSCFRQCONFIGCNT - Configures the counter based on OSC frequency. */
436
#define TMS570_SYS1_LPOMONCTL_OSCFRQCONFIGCNT BSP_BIT32(16)
437
438
/* field: HFTRIM - High frequency oscillator trim value. */
439
#define TMS570_SYS1_LPOMONCTL_HFTRIM(val) BSP_FLD32(val,8, 12)
440
#define TMS570_SYS1_LPOMONCTL_HFTRIM_GET(reg) BSP_FLD32GET(reg,8, 12)
441
#define TMS570_SYS1_LPOMONCTL_HFTRIM_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
442
443
444
/*--------------------TMS570_SYS1_CLKTEST--------------------*/
445
/* field: ALTLIMPCLOCKENABLE - This bit selects a clock driven by the GIOB[0] pin as an alternate limp clock to the clock */
446
#define TMS570_SYS1_CLKTEST_ALTLIMPCLOCKENABLE BSP_BIT32(26)
447
448
/* field: RANGEDETCTRL - Range detection control. */
449
#define TMS570_SYS1_CLKTEST_RANGEDETCTRL BSP_BIT32(25)
450
451
/* field: RANGEDETENASSEL - Selects range detection enable. This bit resets asynchronously on power on reset. */
452
#define TMS570_SYS1_CLKTEST_RANGEDETENASSEL BSP_BIT32(24)
453
454
/* field: CLK_TEST_EN - Clock test enable. This bit enables the clock going to the ECLK pin. */
455
#define TMS570_SYS1_CLKTEST_CLK_TEST_EN(val) BSP_FLD32(val,16, 19)
456
#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
457
#define TMS570_SYS1_CLKTEST_CLK_TEST_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
458
459
/* field: SEL_GIO_PIN - GIOB[0] pin clock source valid, clock source select */
460
#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN(val) BSP_FLD32(val,8, 11)
461
#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_GET(reg) BSP_FLD32GET(reg,8, 11)
462
#define TMS570_SYS1_CLKTEST_SEL_GIO_PIN_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
463
464
/* field: SEL_ECP_PIN - ECLK pin clock source select */
465
#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN(val) BSP_FLD32(val,0, 3)
466
#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_GET(reg) BSP_FLD32GET(reg,0, 3)
467
#define TMS570_SYS1_CLKTEST_SEL_ECP_PIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
468
469
470
/*------------------TMS570_SYS1_DFTCTRLREG1------------------*/
471
/* field: DFTWRITE - DFT logic access. */
472
#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE(val) BSP_FLD32(val,12, 13)
473
#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_GET(reg) BSP_FLD32GET(reg,12, 13)
474
#define TMS570_SYS1_DFTCTRLREG1_DFTWRITE_SET(reg,val) BSP_FLD32SET(reg, val,12, 13)
475
476
/* field: DFTREAD - DFT logic access. */
477
#define TMS570_SYS1_DFTCTRLREG1_DFTREAD(val) BSP_FLD32(val,8, 9)
478
#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_GET(reg) BSP_FLD32GET(reg,8, 9)
479
#define TMS570_SYS1_DFTCTRLREG1_DFTREAD_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
480
481
/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
482
#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
483
#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
484
#define TMS570_SYS1_DFTCTRLREG1_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
485
486
487
/*------------------TMS570_SYS1_DFTCTRLREG2------------------*/
488
/* field: IMPDF - DFT Implementation defined bits. */
489
#define TMS570_SYS1_DFTCTRLREG2_IMPDF(val) BSP_FLD32(val,4, 31)
490
#define TMS570_SYS1_DFTCTRLREG2_IMPDF_GET(reg) BSP_FLD32GET(reg,4, 31)
491
#define TMS570_SYS1_DFTCTRLREG2_IMPDF_SET(reg,val) BSP_FLD32SET(reg, val,4, 31)
492
493
/* field: TEST_MODE_KEY - Test mode key. This register is for internal TI use only. */
494
#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY(val) BSP_FLD32(val,0, 3)
495
#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_GET(reg) BSP_FLD32GET(reg,0, 3)
496
#define TMS570_SYS1_DFTCTRLREG2_TEST_MODE_KEY_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
497
498
499
/*---------------------TMS570_SYS1_GPREG1---------------------*/
500
/* field: EMIF_FUNC - Enable EMIF functions to be output. */
501
#define TMS570_SYS1_GPREG1_EMIF_FUNC BSP_BIT32(31)
502
503
/* field: PLL1_FBSLIP_FILTER__COUNT - FBSLIP down counter programmed value. */
504
#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT(val) BSP_FLD32(val,20, 25)
505
#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_GET(reg) BSP_FLD32GET(reg,20, 25)
506
#define TMS570_SYS1_GPREG1_PLL1_FBSLIP_FILTER__COUNT_SET(reg,val) BSP_FLD32SET(reg, val,20, 25)
507
508
/* field: PLL1_RFSLIP_FILTER__KEY - Configures the system response when a FBSLIP is indicated by the */
509
#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY(val) BSP_FLD32(val,16, 19)
510
#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_GET(reg) BSP_FLD32GET(reg,16, 19)
511
#define TMS570_SYS1_GPREG1_PLL1_RFSLIP_FILTER__KEY_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
512
513
/* field: OUTPUT_BUFFER_LOW_EMI_MODE - Control field for the low-EMI mode of output buffers for */
514
#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE(val) BSP_FLD32(val,0, 15)
515
#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_GET(reg) BSP_FLD32GET(reg,0, 15)
516
#define TMS570_SYS1_GPREG1_OUTPUT_BUFFER_LOW_EMI_MODE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
517
518
519
/*--------------------TMS570_SYS1_IMPFASTS--------------------*/
520
/* field: ECPCLKFUN - ECLK function. This bit changes the function of the ECLK pin. */
521
#define TMS570_SYS1_IMPFASTS_ECPCLKFUN BSP_BIT32(0)
522
523
524
/*--------------------TMS570_SYS1_IMPFTADD--------------------*/
525
/* field: IMPFTADD - These bits contain the fault address when an imprecise abort occurs. */
526
/* Whole 32 bits */
527
528
/*---------------------TMS570_SYS1_SSIRx---------------------*/
529
/* field: SSKEY1 - System software interrupt request key. A 075h written to these bits initiates IRQ/FIQ interrupts. */
530
#define TMS570_SYS1_SSIRx_SSKEY1(val) BSP_FLD32(val,8, 15)
531
#define TMS570_SYS1_SSIRx_SSKEY1_GET(reg) BSP_FLD32GET(reg,8, 15)
532
#define TMS570_SYS1_SSIRx_SSKEY1_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
533
534
/* field: SSDATA1 - System software interrupt data. These bits contain user read/write register bits. */
535
#define TMS570_SYS1_SSIRx_SSDATA1(val) BSP_FLD32(val,0, 7)
536
#define TMS570_SYS1_SSIRx_SSDATA1_GET(reg) BSP_FLD32GET(reg,0, 7)
537
#define TMS570_SYS1_SSIRx_SSDATA1_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
538
539
540
/*---------------------TMS570_SYS1_RAMGCR---------------------*/
541
/* field: RAM_DFT_EN - Functional mode RAM DFT (Design For Test) port enable key. */
542
#define TMS570_SYS1_RAMGCR_RAM_DFT_EN(val) BSP_FLD32(val,16, 19)
543
#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_GET(reg) BSP_FLD32GET(reg,16, 19)
544
#define TMS570_SYS1_RAMGCR_RAM_DFT_EN_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
545
546
/* field: WST_AENA0 - eSRAM data phase wait state enable bit. */
547
#define TMS570_SYS1_RAMGCR_WST_AENA0 BSP_BIT32(2)
548
549
/* field: WST_DENA0 - eSRAM data phase wait state enable bit. */
550
#define TMS570_SYS1_RAMGCR_WST_DENA0 BSP_BIT32(0)
551
552
553
/*---------------------TMS570_SYS1_BMMCR1---------------------*/
554
/* field: MEMSW - Memory swap key. */
555
#define TMS570_SYS1_BMMCR1_MEMSW(val) BSP_FLD32(val,0, 3)
556
#define TMS570_SYS1_BMMCR1_MEMSW_GET(reg) BSP_FLD32GET(reg,0, 3)
557
#define TMS570_SYS1_BMMCR1_MEMSW_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
558
559
560
/*--------------------TMS570_SYS1_CPURSTCR--------------------*/
561
/* field: CPU_RESET - CPU Reset. */
562
#define TMS570_SYS1_CPURSTCR_CPU_RESET BSP_BIT32(0)
563
564
565
/*--------------------TMS570_SYS1_CLKCNTL--------------------*/
566
/* field: VCLK2R - VBUS clock2 ratio. */
567
#define TMS570_SYS1_CLKCNTL_VCLK2R(val) BSP_FLD32(val,24, 27)
568
#define TMS570_SYS1_CLKCNTL_VCLK2R_GET(reg) BSP_FLD32GET(reg,24, 27)
569
#define TMS570_SYS1_CLKCNTL_VCLK2R_SET(reg,val) BSP_FLD32SET(reg, val,24, 27)
570
571
/* field: VCLKR - VBUS clock ratio. */
572
#define TMS570_SYS1_CLKCNTL_VCLKR(val) BSP_FLD32(val,16, 19)
573
#define TMS570_SYS1_CLKCNTL_VCLKR_GET(reg) BSP_FLD32GET(reg,16, 19)
574
#define TMS570_SYS1_CLKCNTL_VCLKR_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
575
576
/* field: PENA - Peripheral enable bit. */
577
#define TMS570_SYS1_CLKCNTL_PENA BSP_BIT32(8)
578
579
580
/*--------------------TMS570_SYS1_ECPCNTL--------------------*/
581
/* field: ECPSSEL - This bit allows the selection between VCLK and OSCIN as the clock source for ECLK. */
582
#define TMS570_SYS1_ECPCNTL_ECPSSEL BSP_BIT32(24)
583
584
/* field: ECPCOS - ECP continue on suspend. */
585
#define TMS570_SYS1_ECPCNTL_ECPCOS BSP_BIT32(23)
586
587
/* field: ECPINSEL - Select ECP input clock source. */
588
#define TMS570_SYS1_ECPCNTL_ECPINSEL(val) BSP_FLD32(val,6, 17)
589
#define TMS570_SYS1_ECPCNTL_ECPINSEL_GET(reg) BSP_FLD32GET(reg,6, 17)
590
#define TMS570_SYS1_ECPCNTL_ECPINSEL_SET(reg,val) BSP_FLD32SET(reg, val,6, 17)
591
592
/* field: ECPDIV - ECP divider value. */
593
#define TMS570_SYS1_ECPCNTL_ECPDIV(val) BSP_FLD32(val,0, 15)
594
#define TMS570_SYS1_ECPCNTL_ECPDIV_GET(reg) BSP_FLD32GET(reg,0, 15)
595
#define TMS570_SYS1_ECPCNTL_ECPDIV_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
596
597
598
/*---------------------TMS570_SYS1_DEVCR1---------------------*/
599
/* field: DEVPARSEL - Device parity select bit key. */
600
#define TMS570_SYS1_DEVCR1_DEVPARSEL(val) BSP_FLD32(val,0, 3)
601
#define TMS570_SYS1_DEVCR1_DEVPARSEL_GET(reg) BSP_FLD32GET(reg,0, 3)
602
#define TMS570_SYS1_DEVCR1_DEVPARSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
603
604
605
/*---------------------TMS570_SYS1_SYSECR---------------------*/
606
/* field: RESET - Software reset bits. Setting RESET1 or clearing RESET0 causes a system software reset. */
607
#define TMS570_SYS1_SYSECR_RESET(val) BSP_FLD32(val,14, 15)
608
#define TMS570_SYS1_SYSECR_RESET_GET(reg) BSP_FLD32GET(reg,14, 15)
609
#define TMS570_SYS1_SYSECR_RESET_SET(reg,val) BSP_FLD32SET(reg, val,14, 15)
610
611
612
/*---------------------TMS570_SYS1_SYSESR---------------------*/
613
/* field: PORST - Power-up reset. This bit is set when VCCOR (VCC Out of Range) is detected. */
614
#define TMS570_SYS1_SYSESR_PORST BSP_BIT32(15)
615
616
/* field: OSCRST - Reset caused by an oscillator failure or PLL cycle slip. */
617
#define TMS570_SYS1_SYSESR_OSCRST BSP_BIT32(14)
618
619
/* field: WDRST - Watchdog reset flag. */
620
#define TMS570_SYS1_SYSESR_WDRST BSP_BIT32(13)
621
622
/* field: CPURST - CPU reset flag. This bit is set when the CPU is reset. */
623
#define TMS570_SYS1_SYSESR_CPURST BSP_BIT32(5)
624
625
/* field: SWRST - Software reset flag. This bit is set when a software system reset has occurred. */
626
#define TMS570_SYS1_SYSESR_SWRST BSP_BIT32(4)
627
628
/* field: EXTRST - External reset flag. This bit is set when a reset is caused by the external reset pin nRST. */
629
#define TMS570_SYS1_SYSESR_EXTRST BSP_BIT32(3)
630
631
/* field: MPMODE - This indicates the current memory protection unit (MPU) mode. */
632
#define TMS570_SYS1_SYSESR_MPMODE BSP_BIT32(0)
633
634
635
/*--------------------TMS570_SYS1_SYSTASR--------------------*/
636
/* field: EFUSE_Abort - Test Abort status flag. */
637
#define TMS570_SYS1_SYSTASR_EFUSE_Abort(val) BSP_FLD32(val,0, 4)
638
#define TMS570_SYS1_SYSTASR_EFUSE_Abort_GET(reg) BSP_FLD32GET(reg,0, 4)
639
#define TMS570_SYS1_SYSTASR_EFUSE_Abort_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
640
641
642
/*--------------------TMS570_SYS1_GLBSTAT--------------------*/
643
/* field: FBSLIP - PLL over cycle slip detection. */
644
#define TMS570_SYS1_GLBSTAT_FBSLIP BSP_BIT32(9)
645
646
/* field: RFSLIP - PLL under cycle slip detection. */
647
#define TMS570_SYS1_GLBSTAT_RFSLIP BSP_BIT32(8)
648
649
/* field: OSCFAIL - Oscillator fail flag bit. */
650
#define TMS570_SYS1_GLBSTAT_OSCFAIL BSP_BIT32(0)
651
652
653
/*---------------------TMS570_SYS1_DEVID---------------------*/
654
/* field: CP15 - CP15 CPU. This bit indicates whether the CPU has a coprocessor 15 (CP15). */
655
#define TMS570_SYS1_DEVID_CP15 BSP_BIT32(31)
656
657
/* field: TECH - These bits define the process technology by which the device was manufactured. */
658
#define TMS570_SYS1_DEVID_TECH(val) BSP_FLD32(val,13, 16)
659
#define TMS570_SYS1_DEVID_TECH_GET(reg) BSP_FLD32GET(reg,13, 16)
660
#define TMS570_SYS1_DEVID_TECH_SET(reg,val) BSP_FLD32SET(reg, val,13, 16)
661
662
/* field: I_O_VOLTAGE - Input/output voltage. This bit defines the I/O voltage of the device. */
663
#define TMS570_SYS1_DEVID_I_O_VOLTAGE BSP_BIT32(12)
664
665
/* field: PERIPHERAL_PARITY - The peripheral memories have no parity. */
666
#define TMS570_SYS1_DEVID_PERIPHERAL_PARITY BSP_BIT32(11)
667
668
/* field: FLASH_ECC - These bits indicate which parity is present for the program memory. */
669
#define TMS570_SYS1_DEVID_FLASH_ECC(val) BSP_FLD32(val,9, 10)
670
#define TMS570_SYS1_DEVID_FLASH_ECC_GET(reg) BSP_FLD32GET(reg,9, 10)
671
#define TMS570_SYS1_DEVID_FLASH_ECC_SET(reg,val) BSP_FLD32SET(reg, val,9, 10)
672
673
/* field: RAM_ECC - RAM ECC. This bit indicates whether or not RAM memory ECC is present. */
674
#define TMS570_SYS1_DEVID_RAM_ECC BSP_BIT32(8)
675
676
/* field: VERSION - Version. These bits provide the revision of the device. */
677
#define TMS570_SYS1_DEVID_VERSION(val) BSP_FLD32(val,3, 7)
678
#define TMS570_SYS1_DEVID_VERSION_GET(reg) BSP_FLD32GET(reg,3, 7)
679
#define TMS570_SYS1_DEVID_VERSION_SET(reg,val) BSP_FLD32SET(reg, val,3, 7)
680
681
/* field: PLATFORM_ID - The device is part of the TMS570Px family. The TMS570Px ID is always 5h. */
682
#define TMS570_SYS1_DEVID_PLATFORM_ID(val) BSP_FLD32(val,0, 2)
683
#define TMS570_SYS1_DEVID_PLATFORM_ID_GET(reg) BSP_FLD32GET(reg,0, 2)
684
#define TMS570_SYS1_DEVID_PLATFORM_ID_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
685
686
687
/*---------------------TMS570_SYS1_SSIVEC---------------------*/
688
/* field: SSIDATA - System software interrupt data key. */
689
#define TMS570_SYS1_SSIVEC_SSIDATA(val) BSP_FLD32(val,8, 15)
690
#define TMS570_SYS1_SSIVEC_SSIDATA_GET(reg) BSP_FLD32GET(reg,8, 15)
691
#define TMS570_SYS1_SSIVEC_SSIDATA_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
692
693
/* field: SSIVECT - These bits contain the source for the system software interrupt. */
694
#define TMS570_SYS1_SSIVEC_SSIVECT(val) BSP_FLD32(val,0, 7)
695
#define TMS570_SYS1_SSIVEC_SSIVECT_GET(reg) BSP_FLD32GET(reg,0, 7)
696
#define TMS570_SYS1_SSIVEC_SSIVECT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
697
698
699
/*----------------------TMS570_SYS1_SSIF----------------------*/
700
/* field: SSI_FLAG - System software interrupt flag[4-1]. */
701
#define TMS570_SYS1_SSIF_SSI_FLAG(val) BSP_FLD32(val,0, 3)
702
#define TMS570_SYS1_SSIF_SSI_FLAG_GET(reg) BSP_FLD32GET(reg,0, 3)
703
#define TMS570_SYS1_SSIF_SSI_FLAG_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
704
705
706
707
#endif
/* LIBBSP_ARM_TMS570_SYS1 */
utility.h
This header file provides utility macros for BSPs.
tms570_sys1_t
Definition:
reg_sys.h:44
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