RTEMS 6.1-rc1
reg_spi.h
1/* The header file is generated by make_header.py from SPI.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_SPI
40#define LIBBSP_ARM_TMS570_SPI
41
42#include <bsp/utility.h>
43
44typedef struct{
45 uint32_t GCR0; /*SPI Global Control Register 0*/
46 uint32_t GCR1; /*SPI Global Control Register 1*/
47 uint32_t INT0; /*SPI Interrupt Register*/
48 uint32_t LVL; /*SPI Interrupt Level Register*/
49 uint32_t FLG; /*SPI Flag Register*/
50 uint32_t PC0; /*SPI Pin Control Register 0*/
51 uint32_t PC1; /*SPI Pin Control Register 1*/
52 uint32_t PC2; /*SPI Pin Control Register 2*/
53 uint32_t PC3; /*SPI Pin Control Register 3*/
54 uint32_t PC4; /*SPI Pin Control Register 4*/
55 uint32_t PC5; /*SPI Pin Control Register 5*/
56 uint32_t PC6; /*SPI Pin Control Register 6*/
57 uint32_t PC7; /*SPI Pin Control Register 7*/
58 uint32_t PC8; /*SPI Pin Control Register 8*/
59 uint32_t DAT0; /*SPI Transmit Data Register 0*/
60 uint32_t DAT1; /*SPI Transmit Data Register 1*/
61 uint32_t BUF; /*SPI Receive Buffer Register*/
62 uint32_t EMU; /*SPI Emulation Register*/
63 uint32_t DELAY; /*SPI Delay Register*/
64 uint32_t DEF; /*SPI Default Chip Select Register*/
65 uint32_t FMT0; /*SPI Data Format Register 0*/
66 uint32_t FMT1; /*SPI Data Format Register 1*/
67 uint32_t FMT2; /*SPI Data Format Register 2*/
68 uint32_t FMT3; /*SPI Data Format Register 3*/
69 uint32_t INTVECT0; /*Interrupt Vector 0*/
70 uint32_t INTVECT1; /*Interrupt Vector 1*/
71 uint8_t reserved1 [4];
72 uint32_t PMCTRL; /*Parallel/Modulo Mode Control Register*/
73 uint32_t MIBSPIE; /*Multi-buffer Mode Enable Register*/
74 uint32_t TGITENST; /*TG Interrupt Enable Set Register*/
75 uint32_t TGITENCR; /*TG Interrupt Enable Clear Register*/
76 uint32_t TGITLVST; /*Transfer Group Interrupt Level Set Register*/
77 uint32_t TGITLVCR; /*Transfer Group Interrupt Level Clear Register*/
78 uint32_t TGINTFLG; /*Transfer Group Interrupt Flag Register*/
79 uint8_t reserved2 [8];
80 uint32_t TICKCNT; /*Tick Count Register*/
81 uint32_t LTGPEND; /*Last TG End Pointer*/
82 uint32_t TGCTRL[16]; /*TG Control Registers*/
83 uint32_t DMACTRL[8]; /*DMA Channel Control Register*/
84 uint32_t DMACOUNT[8]; /*DMA COUNT Register*/
85 uint32_t DMACNTLEN; /*DMA Large Count*/
86 uint8_t reserved3 [4];
87 uint32_t UERRCTRL; /*Multi-buffer RAM Uncorrectable Parity Error Control Register*/
88 uint32_t UERRSTAT; /*Multi-buffer RAM Uncorrectable Parity Error Status Register*/
89 uint32_t UERRADDRRX; /*RXRAM Uncorrectable Parity Error Address Register*/
90 uint32_t UERRADDRTX; /*TXRAM Uncorrectable Parity Error Address Register*/
91 uint32_t RXOVRN_BUF_ADDR; /*RXRAM Overrun Buffer Address Register*/
92 uint32_t IOLPBKTSTCR; /*I/O Loopback Test Control Register*/
93 uint32_t EXT_PRESCALE1; /*SPI Extended Prescale Register 1*/
94 uint32_t EXT_PRESCALE2; /*SPI Extended Prescale Register 2*/
95} tms570_spi_t;
96
97
98/*----------------------TMS570_SPI_GCR0----------------------*/
99/* field: nRESET - This is the local reset control for the module. */
100#define TMS570_SPI_GCR0_nRESET BSP_BIT32(0)
101
102
103/*----------------------TMS570_SPI_GCR1----------------------*/
104/* field: SPIEN - SPI enable. This bit enables SPI transfers. */
105#define TMS570_SPI_GCR1_SPIEN BSP_BIT32(24)
106
107/* field: LOOPBACK - Internal loop-back test mode. The internal self-test option can be enabled by setting this bit. */
108#define TMS570_SPI_GCR1_LOOPBACK BSP_BIT32(16)
109
110/* field: POWERDOWN - When active, the SPI state machine enters a power-down state. */
111#define TMS570_SPI_GCR1_POWERDOWN BSP_BIT32(8)
112
113/* field: CLKMOD - Clock mode. This bit selects either an internal or external clock source. */
114#define TMS570_SPI_GCR1_CLKMOD BSP_BIT32(1)
115
116/* field: MASTER - SPISIMO/SPISOMI pin direction determination. */
117#define TMS570_SPI_GCR1_MASTER BSP_BIT32(0)
118
119
120/*----------------------TMS570_SPI_INT0----------------------*/
121/* field: ENABLEHIGHZ - SPIENA pin high-impedance enable. */
122#define TMS570_SPI_INT0_ENABLEHIGHZ BSP_BIT32(24)
123
124/* field: DMAREQEN - DMA request enable. */
125#define TMS570_SPI_INT0_DMAREQEN BSP_BIT32(16)
126
127
128/*-----------------------TMS570_SPI_LVL-----------------------*/
129/* field: TXINTLVL - Transmit interrupt level. */
130#define TMS570_SPI_LVL_TXINTLVL BSP_BIT32(9)
131
132/* field: RXINTLVL - Receive interrupt level. */
133#define TMS570_SPI_LVL_RXINTLVL BSP_BIT32(8)
134
135/* field: RXOVRNINTLVL - Receive overrun interrupt level. */
136#define TMS570_SPI_LVL_RXOVRNINTLVL BSP_BIT32(6)
137
138/* field: BITERRLVL - Bit error interrupt level. */
139#define TMS570_SPI_LVL_BITERRLVL BSP_BIT32(4)
140
141/* field: DESYNCLVL - Desynchronized slave interrupt level. (master mode only). */
142#define TMS570_SPI_LVL_DESYNCLVL BSP_BIT32(3)
143
144/* field: PARERRLVL - Parity error interrupt level. */
145#define TMS570_SPI_LVL_PARERRLVL BSP_BIT32(2)
146
147/* field: TIMEOUTLVL - SPIENA pin time-out interrupt level. */
148#define TMS570_SPI_LVL_TIMEOUTLVL BSP_BIT32(1)
149
150/* field: DLENERRLVL - Data length error interrupt level (line) select. */
151#define TMS570_SPI_LVL_DLENERRLVL BSP_BIT32(0)
152
153
154/*-----------------------TMS570_SPI_FLG-----------------------*/
155/* field: BUFINITACTIVE - Indicates the status of multi-buffer initialization process. */
156#define TMS570_SPI_FLG_BUFINITACTIVE BSP_BIT32(24)
157
158/* field: TXINTFLG - Transmitter-empty interrupt flag. */
159#define TMS570_SPI_FLG_TXINTFLG BSP_BIT32(9)
160
161/* field: RXINTFLG - Receiver-full interrupt flag. */
162#define TMS570_SPI_FLG_RXINTFLG BSP_BIT32(8)
163
164/* field: RXOVRNINTFLG - Receiver overrun flag. */
165#define TMS570_SPI_FLG_RXOVRNINTFLG BSP_BIT32(6)
166
167/* field: BITERRFLG - Mismatch of internal transmit data and transmitted data. */
168#define TMS570_SPI_FLG_BITERRFLG BSP_BIT32(4)
169
170/* field: DESYNCFLG - Desynchronization of slave device. */
171#define TMS570_SPI_FLG_DESYNCFLG BSP_BIT32(3)
172
173/* field: PARITYERRFLG - Calculated parity differs from received parity bit. */
174#define TMS570_SPI_FLG_PARITYERRFLG BSP_BIT32(2)
175
176/* field: TIMEOUTFLG - Time-out caused by nonactivation of ENA signal. */
177#define TMS570_SPI_FLG_TIMEOUTFLG BSP_BIT32(1)
178
179/* field: DLENERRFLG - Data-length error flag. */
180#define TMS570_SPI_FLG_DLENERRFLG BSP_BIT32(0)
181
182
183/*-----------------------TMS570_SPI_PC0-----------------------*/
184/* field: SOMIFUN - Slave out, master in function. */
185#define TMS570_SPI_PC0_SOMIFUN(val) BSP_FLD32(val,24, 31)
186#define TMS570_SPI_PC0_SOMIFUN_GET(reg) BSP_FLD32GET(reg,24, 31)
187#define TMS570_SPI_PC0_SOMIFUN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
188
189/* field: SIMOFUN - Slave in, master out function. */
190#define TMS570_SPI_PC0_SIMOFUN(val) BSP_FLD32(val,16, 23)
191#define TMS570_SPI_PC0_SIMOFUN_GET(reg) BSP_FLD32GET(reg,16, 23)
192#define TMS570_SPI_PC0_SIMOFUN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
193
194/* field: SOMIFUN0 - SOMIFUN0 */
195#define TMS570_SPI_PC0_SOMIFUN0 BSP_BIT32(11)
196
197/* field: SIMOFUN0 - Slave in, master out function. */
198#define TMS570_SPI_PC0_SIMOFUN0 BSP_BIT32(10)
199
200/* field: CLKFUN - CLKFUN */
201#define TMS570_SPI_PC0_CLKFUN BSP_BIT32(9)
202
203/* field: ENAFUN - SPIENA function. */
204#define TMS570_SPI_PC0_ENAFUN BSP_BIT32(8)
205
206/* field: SCSFUN - SPISCSx function. */
207#define TMS570_SPI_PC0_SCSFUN(val) BSP_FLD32(val,0, 7)
208#define TMS570_SPI_PC0_SCSFUN_GET(reg) BSP_FLD32GET(reg,0, 7)
209#define TMS570_SPI_PC0_SCSFUN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
210
211
212/*-----------------------TMS570_SPI_PC1-----------------------*/
213/* field: SOMIDIR - SPISOMIx direction. Controls the direction of SPISOMIx when used for general-purpose I/O. */
214#define TMS570_SPI_PC1_SOMIDIR(val) BSP_FLD32(val,24, 31)
215#define TMS570_SPI_PC1_SOMIDIR_GET(reg) BSP_FLD32GET(reg,24, 31)
216#define TMS570_SPI_PC1_SOMIDIR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
217
218/* field: SIMODIR - SPISIMOx direction. Controls the direction of SPISIMOx when used for general-purpose I/O. */
219#define TMS570_SPI_PC1_SIMODIR(val) BSP_FLD32(val,16, 23)
220#define TMS570_SPI_PC1_SIMODIR_GET(reg) BSP_FLD32GET(reg,16, 23)
221#define TMS570_SPI_PC1_SIMODIR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
222
223/* field: SOMIDIR0 - PISOMI0 direction. */
224#define TMS570_SPI_PC1_SOMIDIR0 BSP_BIT32(11)
225
226/* field: SIMODIR0 - SPISIMO0 direction. */
227#define TMS570_SPI_PC1_SIMODIR0 BSP_BIT32(10)
228
229/* field: CLKDIR - SPICLK direction. */
230#define TMS570_SPI_PC1_CLKDIR BSP_BIT32(9)
231
232/* field: ENADIR - SPIENA direction. */
233#define TMS570_SPI_PC1_ENADIR BSP_BIT32(8)
234
235/* field: SCSDIR - SPISCSx direction. */
236#define TMS570_SPI_PC1_SCSDIR(val) BSP_FLD32(val,0, 7)
237#define TMS570_SPI_PC1_SCSDIR_GET(reg) BSP_FLD32GET(reg,0, 7)
238#define TMS570_SPI_PC1_SCSDIR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
239
240
241/*-----------------------TMS570_SPI_PC2-----------------------*/
242/* field: SOMIDIN - SPISOMIx data in. The value of the SPISOMIx pins. */
243#define TMS570_SPI_PC2_SOMIDIN(val) BSP_FLD32(val,24, 31)
244#define TMS570_SPI_PC2_SOMIDIN_GET(reg) BSP_FLD32GET(reg,24, 31)
245#define TMS570_SPI_PC2_SOMIDIN_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
246
247/* field: SIMODIN - SPISIMOx data in. The value of the SPISIMOx pins. */
248#define TMS570_SPI_PC2_SIMODIN(val) BSP_FLD32(val,16, 23)
249#define TMS570_SPI_PC2_SIMODIN_GET(reg) BSP_FLD32GET(reg,16, 23)
250#define TMS570_SPI_PC2_SIMODIN_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
251
252/* field: SOMIDIN0 - SPISOMI0 data in. The value of the SPISOMI0 pin. */
253#define TMS570_SPI_PC2_SOMIDIN0 BSP_BIT32(11)
254
255/* field: SIMODIN0 - SPISIMO0 data in. The value of the SPISIMO0 pin. */
256#define TMS570_SPI_PC2_SIMODIN0 BSP_BIT32(10)
257
258/* field: CLKDIN - Clock data in. The value of the SPICLK pin. pin. */
259#define TMS570_SPI_PC2_CLKDIN BSP_BIT32(9)
260
261/* field: ENADIN - SPIENA data in. The the value of the SPIENA pin. */
262#define TMS570_SPI_PC2_ENADIN BSP_BIT32(8)
263
264/* field: SCSDIN - SPISCSx data in. The value of the SPISCSx pin. */
265#define TMS570_SPI_PC2_SCSDIN(val) BSP_FLD32(val,0, 7)
266#define TMS570_SPI_PC2_SCSDIN_GET(reg) BSP_FLD32GET(reg,0, 7)
267#define TMS570_SPI_PC2_SCSDIN_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
268
269
270/*-----------------------TMS570_SPI_PC3-----------------------*/
271/* field: SOMIDOUT - SPISOMIx data out write. */
272#define TMS570_SPI_PC3_SOMIDOUT(val) BSP_FLD32(val,24, 31)
273#define TMS570_SPI_PC3_SOMIDOUT_GET(reg) BSP_FLD32GET(reg,24, 31)
274#define TMS570_SPI_PC3_SOMIDOUT_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
275
276/* field: SIMODOUT - SPISIMOx data out write. */
277#define TMS570_SPI_PC3_SIMODOUT(val) BSP_FLD32(val,16, 23)
278#define TMS570_SPI_PC3_SIMODOUT_GET(reg) BSP_FLD32GET(reg,16, 23)
279#define TMS570_SPI_PC3_SIMODOUT_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
280
281/* field: SOMIDOUT0 - SPISOMI0 data out write. */
282#define TMS570_SPI_PC3_SOMIDOUT0 BSP_BIT32(11)
283
284/* field: SIMODOUT0 - SPISIMO0 data out write. */
285#define TMS570_SPI_PC3_SIMODOUT0 BSP_BIT32(10)
286
287/* field: CLKDOUT - SPICLK data out write. */
288#define TMS570_SPI_PC3_CLKDOUT BSP_BIT32(9)
289
290/* field: ENADOUT - SPIENA data out write. */
291#define TMS570_SPI_PC3_ENADOUT BSP_BIT32(8)
292
293/* field: SCSDOUT - SPISCSx data out write. */
294#define TMS570_SPI_PC3_SCSDOUT(val) BSP_FLD32(val,0, 7)
295#define TMS570_SPI_PC3_SCSDOUT_GET(reg) BSP_FLD32GET(reg,0, 7)
296#define TMS570_SPI_PC3_SCSDOUT_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
297
298
299/*-----------------------TMS570_SPI_PC4-----------------------*/
300/* field: SOMISET - SPISOMIx data out set. */
301#define TMS570_SPI_PC4_SOMISET(val) BSP_FLD32(val,24, 31)
302#define TMS570_SPI_PC4_SOMISET_GET(reg) BSP_FLD32GET(reg,24, 31)
303#define TMS570_SPI_PC4_SOMISET_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
304
305/* field: SIMOSET - SPISIMOx data out set. */
306#define TMS570_SPI_PC4_SIMOSET(val) BSP_FLD32(val,16, 23)
307#define TMS570_SPI_PC4_SIMOSET_GET(reg) BSP_FLD32GET(reg,16, 23)
308#define TMS570_SPI_PC4_SIMOSET_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
309
310/* field: SOMISET0 - SPISOMI0 data out set. */
311#define TMS570_SPI_PC4_SOMISET0 BSP_BIT32(11)
312
313/* field: SIMOSET0 - purpose */
314#define TMS570_SPI_PC4_SIMOSET0 BSP_BIT32(10)
315
316/* field: CLKSET - SPICLK data out set. */
317#define TMS570_SPI_PC4_CLKSET BSP_BIT32(9)
318
319/* field: ENASET - SPIENA data out set. */
320#define TMS570_SPI_PC4_ENASET BSP_BIT32(8)
321
322/* field: SCSSET - SPISCSx data out set. */
323#define TMS570_SPI_PC4_SCSSET(val) BSP_FLD32(val,0, 7)
324#define TMS570_SPI_PC4_SCSSET_GET(reg) BSP_FLD32GET(reg,0, 7)
325#define TMS570_SPI_PC4_SCSSET_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
326
327
328/*-----------------------TMS570_SPI_PC5-----------------------*/
329/* field: SOMICLR - SPISOMIx data out clear. */
330#define TMS570_SPI_PC5_SOMICLR(val) BSP_FLD32(val,24, 31)
331#define TMS570_SPI_PC5_SOMICLR_GET(reg) BSP_FLD32GET(reg,24, 31)
332#define TMS570_SPI_PC5_SOMICLR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
333
334/* field: SIMOCLR - SPISIMOx data out clear. */
335#define TMS570_SPI_PC5_SIMOCLR(val) BSP_FLD32(val,16, 23)
336#define TMS570_SPI_PC5_SIMOCLR_GET(reg) BSP_FLD32GET(reg,16, 23)
337#define TMS570_SPI_PC5_SIMOCLR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
338
339/* field: SOMICLR0 - SPISOMI0 data out cleart. */
340#define TMS570_SPI_PC5_SOMICLR0 BSP_BIT32(11)
341
342/* field: SIMOCLR0 - SPISIMO0 data out clear. */
343#define TMS570_SPI_PC5_SIMOCLR0 BSP_BIT32(10)
344
345/* field: CLKCLR - SPICLK data out clear. */
346#define TMS570_SPI_PC5_CLKCLR BSP_BIT32(9)
347
348/* field: ENACLR - SPIENA data out clear. */
349#define TMS570_SPI_PC5_ENACLR BSP_BIT32(8)
350
351/* field: SCSCLR - SPISCSx data out clear. */
352#define TMS570_SPI_PC5_SCSCLR(val) BSP_FLD32(val,0, 7)
353#define TMS570_SPI_PC5_SCSCLR_GET(reg) BSP_FLD32GET(reg,0, 7)
354#define TMS570_SPI_PC5_SCSCLR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
355
356
357/*-----------------------TMS570_SPI_PC6-----------------------*/
358/* field: SOMIPDR - SPISOMIx open drain enable. */
359#define TMS570_SPI_PC6_SOMIPDR(val) BSP_FLD32(val,24, 31)
360#define TMS570_SPI_PC6_SOMIPDR_GET(reg) BSP_FLD32GET(reg,24, 31)
361#define TMS570_SPI_PC6_SOMIPDR_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
362
363/* field: SIMOPDR - SPISIMOx open drain enable. */
364#define TMS570_SPI_PC6_SIMOPDR(val) BSP_FLD32(val,16, 23)
365#define TMS570_SPI_PC6_SIMOPDR_GET(reg) BSP_FLD32GET(reg,16, 23)
366#define TMS570_SPI_PC6_SIMOPDR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
367
368/* field: SOMIPDR0 - SOMI0 open-drain enable. */
369#define TMS570_SPI_PC6_SOMIPDR0 BSP_BIT32(11)
370
371/* field: SIMOPDR0 - SPISIMO0 open-drain enable. */
372#define TMS570_SPI_PC6_SIMOPDR0 BSP_BIT32(10)
373
374/* field: CLKPDR - CLK open drain enable. */
375#define TMS570_SPI_PC6_CLKPDR BSP_BIT32(9)
376
377/* field: ENAPDR - SPIENA pin open drain enable. */
378#define TMS570_SPI_PC6_ENAPDR BSP_BIT32(8)
379
380/* field: SCSPDR - SPISCSx open drain enable. */
381#define TMS570_SPI_PC6_SCSPDR(val) BSP_FLD32(val,0, 7)
382#define TMS570_SPI_PC6_SCSPDR_GET(reg) BSP_FLD32GET(reg,0, 7)
383#define TMS570_SPI_PC6_SCSPDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
384
385
386/*-----------------------TMS570_SPI_PC7-----------------------*/
387/* field: SOMIDIS - SOMIx pull control enable/disable. */
388#define TMS570_SPI_PC7_SOMIDIS(val) BSP_FLD32(val,24, 31)
389#define TMS570_SPI_PC7_SOMIDIS_GET(reg) BSP_FLD32GET(reg,24, 31)
390#define TMS570_SPI_PC7_SOMIDIS_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
391
392/* field: SIMODIS - SIMOx pull control enable/disable. */
393#define TMS570_SPI_PC7_SIMODIS(val) BSP_FLD32(val,16, 23)
394#define TMS570_SPI_PC7_SIMODIS_GET(reg) BSP_FLD32GET(reg,16, 23)
395#define TMS570_SPI_PC7_SIMODIS_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
396
397/* field: SOMIPDIS0 - SPISOMI0 pull control enable/disable. */
398#define TMS570_SPI_PC7_SOMIPDIS0 BSP_BIT32(11)
399
400/* field: SIMOPDIS0 - SPISIMO0 pull control enable/disable. */
401#define TMS570_SPI_PC7_SIMOPDIS0 BSP_BIT32(10)
402
403/* field: CLKPDIS - CLK pull control enable/disable. */
404#define TMS570_SPI_PC7_CLKPDIS BSP_BIT32(9)
405
406/* field: ENAPDIS - ENAPDIS ENABLE pull control enable/disable. */
407#define TMS570_SPI_PC7_ENAPDIS BSP_BIT32(8)
408
409/* field: SCSPDIS - SCSx pull control enable/disable. */
410#define TMS570_SPI_PC7_SCSPDIS(val) BSP_FLD32(val,0, 7)
411#define TMS570_SPI_PC7_SCSPDIS_GET(reg) BSP_FLD32GET(reg,0, 7)
412#define TMS570_SPI_PC7_SCSPDIS_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
413
414
415/*-----------------------TMS570_SPI_PC8-----------------------*/
416/* field: SOMIPSEL - SPISOMIx pull select. This bit selects the type of pull logic at the SOMIx pin. */
417#define TMS570_SPI_PC8_SOMIPSEL(val) BSP_FLD32(val,24, 31)
418#define TMS570_SPI_PC8_SOMIPSEL_GET(reg) BSP_FLD32GET(reg,24, 31)
419#define TMS570_SPI_PC8_SOMIPSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
420
421/* field: SIMOPSEL - SIMOPSEL SPISIMOx pull select. This bit selects the type of pull logic at the SPISIMOx pin. */
422#define TMS570_SPI_PC8_SIMOPSEL(val) BSP_FLD32(val,16, 23)
423#define TMS570_SPI_PC8_SIMOPSEL_GET(reg) BSP_FLD32GET(reg,16, 23)
424#define TMS570_SPI_PC8_SIMOPSEL_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
425
426/* field: SOMIPSEL0 - SOMI pull select. This bit selects the type of pull logic at the SOMI pin. */
427#define TMS570_SPI_PC8_SOMIPSEL0 BSP_BIT32(11)
428
429/* field: SIMOPSEL0 - SPISIMO pull select. This bit selects the type of pull logic at the SPISIMO pin. */
430#define TMS570_SPI_PC8_SIMOPSEL0 BSP_BIT32(10)
431
432/* field: CLKPSEL - CLK pull select. This bit selects the type of pull logic at the CLK pin. */
433#define TMS570_SPI_PC8_CLKPSEL BSP_BIT32(9)
434
435/* field: ENAPSEL - ENABLE pull select. This bit selects the type of pull logic at the ENABLE pin. */
436#define TMS570_SPI_PC8_ENAPSEL BSP_BIT32(8)
437
438/* field: SCSPSEL - SCSx pull select. This bit selects the type of pull logic at the SCSx pin. */
439#define TMS570_SPI_PC8_SCSPSEL(val) BSP_FLD32(val,0, 7)
440#define TMS570_SPI_PC8_SCSPSEL_GET(reg) BSP_FLD32GET(reg,0, 7)
441#define TMS570_SPI_PC8_SCSPSEL_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
442
443
444/*----------------------TMS570_SPI_DAT0----------------------*/
445/* field: TXDATA - SPI transmit data. When written, these bits will be copied to the shift register if it is empty. */
446#define TMS570_SPI_DAT0_TXDATA(val) BSP_FLD32(val,0, 15)
447#define TMS570_SPI_DAT0_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
448#define TMS570_SPI_DAT0_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
449
450
451/*----------------------TMS570_SPI_DAT1----------------------*/
452/* field: CSHOLD - Chip select hold mode. */
453#define TMS570_SPI_DAT1_CSHOLD BSP_BIT32(28)
454
455/* field: WDEL - Enable the delay counter at the end of the current transaction. */
456#define TMS570_SPI_DAT1_WDEL BSP_BIT32(26)
457
458/* field: DFSEL - Data word format select */
459#define TMS570_SPI_DAT1_DFSEL(val) BSP_FLD32(val,24, 25)
460#define TMS570_SPI_DAT1_DFSEL_GET(reg) BSP_FLD32GET(reg,24, 25)
461#define TMS570_SPI_DAT1_DFSEL_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
462
463/* field: CSNR - Chip select number. CSNR defines the chip-select that will be activated during the data transfer. */
464#define TMS570_SPI_DAT1_CSNR(val) BSP_FLD32(val,16, 23)
465#define TMS570_SPI_DAT1_CSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
466#define TMS570_SPI_DAT1_CSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
467
468/* field: TXDATA - ransfer data.When written, these bits are copied to the shift register if it is empty. */
469#define TMS570_SPI_DAT1_TXDATA(val) BSP_FLD32(val,0, 15)
470#define TMS570_SPI_DAT1_TXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
471#define TMS570_SPI_DAT1_TXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
472
473
474/*-----------------------TMS570_SPI_BUF-----------------------*/
475/* field: RXEMPTY - Receive data buffer empty. */
476#define TMS570_SPI_BUF_RXEMPTY BSP_BIT32(31)
477
478/* field: RXOVR - Receive data buffer overrun. */
479#define TMS570_SPI_BUF_RXOVR BSP_BIT32(30)
480
481/* field: TXFULL - Transmit data buffer full.This flag is a read-only flag. */
482#define TMS570_SPI_BUF_TXFULL BSP_BIT32(29)
483
484/* field: BITERR - Bit error.There was a mismatch of internal transmit data and transmitted data. */
485#define TMS570_SPI_BUF_BITERR BSP_BIT32(28)
486
487/* field: DESYNC - Desynchronization of slave device.This bit is valid in master mode only. */
488#define TMS570_SPI_BUF_DESYNC BSP_BIT32(27)
489
490/* field: PARITYERR - Parity error.The calculated parity differs from the received parity bit. */
491#define TMS570_SPI_BUF_PARITYERR BSP_BIT32(26)
492
493/* field: TIMEOUT - Time-out because of non-activation of ENA pin. */
494#define TMS570_SPI_BUF_TIMEOUT BSP_BIT32(25)
495
496/* field: DLENERR - Data length error flag. */
497#define TMS570_SPI_BUF_DLENERR BSP_BIT32(24)
498
499/* field: LCSNR - control field. It contains the chip select number that was activated during the last word transfer. */
500#define TMS570_SPI_BUF_LCSNR(val) BSP_FLD32(val,16, 23)
501#define TMS570_SPI_BUF_LCSNR_GET(reg) BSP_FLD32GET(reg,16, 23)
502#define TMS570_SPI_BUF_LCSNR_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
503
504/* field: RXDATA - SPI receive data. */
505#define TMS570_SPI_BUF_RXDATA(val) BSP_FLD32(val,0, 15)
506#define TMS570_SPI_BUF_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
507#define TMS570_SPI_BUF_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
508
509
510/*-----------------------TMS570_SPI_EMU-----------------------*/
511/* field: EMU_RXDATA - SPI receive data. The SPI emulation register is a mirror of the SPIBUF register. */
512#define TMS570_SPI_EMU_EMU_RXDATA(val) BSP_FLD32(val,0, 15)
513#define TMS570_SPI_EMU_EMU_RXDATA_GET(reg) BSP_FLD32GET(reg,0, 15)
514#define TMS570_SPI_EMU_EMU_RXDATA_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
515
516
517/*----------------------TMS570_SPI_DELAY----------------------*/
518/* field: C2TDELAY - Chip-select-active to transmit-start delay. See Figure 25-45 for an example. */
519#define TMS570_SPI_DELAY_C2TDELAY(val) BSP_FLD32(val,24, 31)
520#define TMS570_SPI_DELAY_C2TDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
521#define TMS570_SPI_DELAY_C2TDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
522
523/* field: T2CDELAY - T2CDELAY */
524#define TMS570_SPI_DELAY_T2CDELAY(val) BSP_FLD32(val,16, 23)
525#define TMS570_SPI_DELAY_T2CDELAY_GET(reg) BSP_FLD32GET(reg,16, 23)
526#define TMS570_SPI_DELAY_T2CDELAY_SET(reg,val) BSP_FLD32SET(reg, val,16, 23)
527
528/* field: T2EDELAY - Transmit-data-finished to ENA-pin-inactive time-out. T2EDELAY is used in master mode only. */
529#define TMS570_SPI_DELAY_T2EDELAY(val) BSP_FLD32(val,8, 15)
530#define TMS570_SPI_DELAY_T2EDELAY_GET(reg) BSP_FLD32GET(reg,8, 15)
531#define TMS570_SPI_DELAY_T2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
532
533/* field: C2EDELAY - Chip-select-active to ENA-signal-active time-out. */
534#define TMS570_SPI_DELAY_C2EDELAY(val) BSP_FLD32(val,0, 7)
535#define TMS570_SPI_DELAY_C2EDELAY_GET(reg) BSP_FLD32GET(reg,0, 7)
536#define TMS570_SPI_DELAY_C2EDELAY_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
537
538
539/*-----------------------TMS570_SPI_DEF-----------------------*/
540/* field: CDEF - Chip select default pattern. Master-mode only. */
541#define TMS570_SPI_DEF_CDEF(val) BSP_FLD32(val,0, 7)
542#define TMS570_SPI_DEF_CDEF_GET(reg) BSP_FLD32GET(reg,0, 7)
543#define TMS570_SPI_DEF_CDEF_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
544
545
546/*----------------------TMS570_SPI_FMTx----------------------*/
547/* field: WDELAY - Delay in between transmissions for data format x (x= 0,1,2,3). */
548#define TMS570_SPI_FMTx_WDELAY(val) BSP_FLD32(val,24, 31)
549#define TMS570_SPI_FMTx_WDELAY_GET(reg) BSP_FLD32GET(reg,24, 31)
550#define TMS570_SPI_FMTx_WDELAY_SET(reg,val) BSP_FLD32SET(reg, val,24, 31)
551
552/* field: PARPOL - Parity polarity: even or odd. PARPOLx can be modified in privilege mode only. */
553#define TMS570_SPI_FMTx_PARPOL BSP_BIT32(23)
554
555/* field: PARITYENA - Parity enable for data format x. */
556#define TMS570_SPI_FMTx_PARITYENA BSP_BIT32(22)
557
558/* field: WAITENA - The master waits for the ENA signal from slave for data format x. */
559#define TMS570_SPI_FMTx_WAITENA BSP_BIT32(21)
560
561/* field: SHIFTDIR - Shift direction for data format x. */
562#define TMS570_SPI_FMTx_SHIFTDIR BSP_BIT32(20)
563
564/* field: HDUPLEX_ENAx - Half Duplex transfer mode enable for Data Format x. */
565#define TMS570_SPI_FMTx_HDUPLEX_ENAx BSP_BIT32(19)
566
567/* field: DIS_CS_TIMERS - Disable chip-select timers for this format. */
568#define TMS570_SPI_FMTx_DIS_CS_TIMERS BSP_BIT32(18)
569
570/* field: POLARITY - POLARITY */
571#define TMS570_SPI_FMTx_POLARITY BSP_BIT32(17)
572
573/* field: PHASE - SPI data format x clock delay. PHASEx defines the clock delay of data format x. */
574#define TMS570_SPI_FMTx_PHASE BSP_BIT32(16)
575
576/* field: PRESCALE - SPI data format x prescaler. */
577#define TMS570_SPI_FMTx_PRESCALE(val) BSP_FLD32(val,8, 15)
578#define TMS570_SPI_FMTx_PRESCALE_GET(reg) BSP_FLD32GET(reg,8, 15)
579#define TMS570_SPI_FMTx_PRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,8, 15)
580
581/* field: CHARLEN - SPI data format x data-word length. CHARLENx defines the word length of data format x. */
582#define TMS570_SPI_FMTx_CHARLEN(val) BSP_FLD32(val,0, 4)
583#define TMS570_SPI_FMTx_CHARLEN_GET(reg) BSP_FLD32GET(reg,0, 4)
584#define TMS570_SPI_FMTx_CHARLEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 4)
585
586
587/*--------------------TMS570_SPI_INTVECT0--------------------*/
588/* field: INTVECT0 - INTVECT0. Interrupt vector for interrupt line INT0. */
589#define TMS570_SPI_INTVECT0_INTVECT0(val) BSP_FLD32(val,1, 5)
590#define TMS570_SPI_INTVECT0_INTVECT0_GET(reg) BSP_FLD32GET(reg,1, 5)
591#define TMS570_SPI_INTVECT0_INTVECT0_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
592
593/* field: SUSPEND0 - Transfer suspended / Transfer finished interrupt flag. */
594#define TMS570_SPI_INTVECT0_SUSPEND0 BSP_BIT32(0)
595
596
597/*--------------------TMS570_SPI_INTVECT1--------------------*/
598/* field: INTVECT1 - INTVECT1. Interrupt vector for interrupt line INT1. */
599#define TMS570_SPI_INTVECT1_INTVECT1(val) BSP_FLD32(val,1, 5)
600#define TMS570_SPI_INTVECT1_INTVECT1_GET(reg) BSP_FLD32GET(reg,1, 5)
601#define TMS570_SPI_INTVECT1_INTVECT1_SET(reg,val) BSP_FLD32SET(reg, val,1, 5)
602
603/* field: SUSPEND1 - Transfer suspended / Transfer finished interrupt flag. */
604#define TMS570_SPI_INTVECT1_SUSPEND1 BSP_BIT32(0)
605
606
607/*---------------------TMS570_SPI_PMCTRL---------------------*/
608/* field: MOD_CLK_POL_3 - Modulo mode SPICLK polarity. */
609#define TMS570_SPI_PMCTRL_MOD_CLK_POL_3 BSP_BIT32(29)
610
611/* field: MMODE_3 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
612#define TMS570_SPI_PMCTRL_MMODE_3(val) BSP_FLD32(val,26, 28)
613#define TMS570_SPI_PMCTRL_MMODE_3_GET(reg) BSP_FLD32GET(reg,26, 28)
614#define TMS570_SPI_PMCTRL_MMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,26, 28)
615
616/* field: PMODE_3 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
617#define TMS570_SPI_PMCTRL_PMODE_3(val) BSP_FLD32(val,24, 25)
618#define TMS570_SPI_PMCTRL_PMODE_3_GET(reg) BSP_FLD32GET(reg,24, 25)
619#define TMS570_SPI_PMCTRL_PMODE_3_SET(reg,val) BSP_FLD32SET(reg, val,24, 25)
620
621/* field: MOD_CLK_POL_2 - Modulo mode SPICLK polarity. */
622#define TMS570_SPI_PMCTRL_MOD_CLK_POL_2 BSP_BIT32(21)
623
624/* field: MMODE_2 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
625#define TMS570_SPI_PMCTRL_MMODE_2(val) BSP_FLD32(val,18, 20)
626#define TMS570_SPI_PMCTRL_MMODE_2_GET(reg) BSP_FLD32GET(reg,18, 20)
627#define TMS570_SPI_PMCTRL_MMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,18, 20)
628
629/* field: PMODE_2 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
630#define TMS570_SPI_PMCTRL_PMODE_2(val) BSP_FLD32(val,16, 17)
631#define TMS570_SPI_PMCTRL_PMODE_2_GET(reg) BSP_FLD32GET(reg,16, 17)
632#define TMS570_SPI_PMCTRL_PMODE_2_SET(reg,val) BSP_FLD32SET(reg, val,16, 17)
633
634/* field: MOD_CLK_POL_1 - Modulo mode SPICLK polarity. */
635#define TMS570_SPI_PMCTRL_MOD_CLK_POL_1 BSP_BIT32(13)
636
637/* field: MMODE_1 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
638#define TMS570_SPI_PMCTRL_MMODE_1(val) BSP_FLD32(val,10, 12)
639#define TMS570_SPI_PMCTRL_MMODE_1_GET(reg) BSP_FLD32GET(reg,10, 12)
640#define TMS570_SPI_PMCTRL_MMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,10, 12)
641
642/* field: PMODE_1 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
643#define TMS570_SPI_PMCTRL_PMODE_1(val) BSP_FLD32(val,8, 9)
644#define TMS570_SPI_PMCTRL_PMODE_1_GET(reg) BSP_FLD32GET(reg,8, 9)
645#define TMS570_SPI_PMCTRL_PMODE_1_SET(reg,val) BSP_FLD32SET(reg, val,8, 9)
646
647/* field: MOD_CLK_POL_0 - Modulo mode SPICLK polarity. */
648#define TMS570_SPI_PMCTRL_MOD_CLK_POL_0 BSP_BIT32(5)
649
650/* field: MMODE_0 - These bits determine whether the SPI/MibSPI operates with 1, 2, 4, 5, or 6 data lines (if */
651#define TMS570_SPI_PMCTRL_MMODE_0(val) BSP_FLD32(val,2, 4)
652#define TMS570_SPI_PMCTRL_MMODE_0_GET(reg) BSP_FLD32GET(reg,2, 4)
653#define TMS570_SPI_PMCTRL_MMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,2, 4)
654
655/* field: PMODE_0 - Parallel mode bits determine whether the SPI/MibSPI operates with 1, 2, 4 or 8 data lines. */
656#define TMS570_SPI_PMCTRL_PMODE_0(val) BSP_FLD32(val,0, 1)
657#define TMS570_SPI_PMCTRL_PMODE_0_GET(reg) BSP_FLD32GET(reg,0, 1)
658#define TMS570_SPI_PMCTRL_PMODE_0_SET(reg,val) BSP_FLD32SET(reg, val,0, 1)
659
660
661/*---------------------TMS570_SPI_MIBSPIE---------------------*/
662/* field: RXRAM_ACCESS - Receive-RAM access control. */
663#define TMS570_SPI_MIBSPIE_RXRAM_ACCESS BSP_BIT32(16)
664
665/* field: MSPIENA - Multi-buffer mode enable. */
666#define TMS570_SPI_MIBSPIE_MSPIENA BSP_BIT32(0)
667
668
669/*--------------------TMS570_SPI_TGITENST--------------------*/
670/* field: SET_INTENRDY - TG interrupt set (enable) when transfer finished. */
671#define TMS570_SPI_TGITENST_SET_INTENRDY(val) BSP_FLD32(val,16, 31)
672#define TMS570_SPI_TGITENST_SET_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
673#define TMS570_SPI_TGITENST_SET_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
674
675/* field: SET_INTENSUS - TG interrupt set (enabled) when transfer suspended */
676#define TMS570_SPI_TGITENST_SET_INTENSUS(val) BSP_FLD32(val,0, 15)
677#define TMS570_SPI_TGITENST_SET_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
678#define TMS570_SPI_TGITENST_SET_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
679
680
681/*--------------------TMS570_SPI_TGITENCR--------------------*/
682/* field: CLR_INTENRDY - TG interrupt clear (disabled) when transfer finished. */
683#define TMS570_SPI_TGITENCR_CLR_INTENRDY(val) BSP_FLD32(val,16, 31)
684#define TMS570_SPI_TGITENCR_CLR_INTENRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
685#define TMS570_SPI_TGITENCR_CLR_INTENRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
686
687/* field: CLR_INTENSUS - CLR INTENSUS */
688#define TMS570_SPI_TGITENCR_CLR_INTENSUS(val) BSP_FLD32(val,0, 15)
689#define TMS570_SPI_TGITENCR_CLR_INTENSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
690#define TMS570_SPI_TGITENCR_CLR_INTENSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
691
692
693/*--------------------TMS570_SPI_TGITLVST--------------------*/
694/* field: SET_INTLVLRDY - Transfer-group completed interrupt level set. */
695#define TMS570_SPI_TGITLVST_SET_INTLVLRDY(val) BSP_FLD32(val,16, 31)
696#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
697#define TMS570_SPI_TGITLVST_SET_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
698
699/* field: SET_INTLVLSUS - Transfer-group suspended interrupt level set. */
700#define TMS570_SPI_TGITLVST_SET_INTLVLSUS(val) BSP_FLD32(val,0, 15)
701#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
702#define TMS570_SPI_TGITLVST_SET_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
703
704
705/*--------------------TMS570_SPI_TGITLVCR--------------------*/
706/* field: CLR_INTLVLRDY - Transfer-group completed interrupt level clear. */
707#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY(val) BSP_FLD32(val,16, 31)
708#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
709#define TMS570_SPI_TGITLVCR_CLR_INTLVLRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
710
711/* field: CLR_INTLVLSUS - Transfer group suspended interrupt level clear. */
712#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS(val) BSP_FLD32(val,0, 15)
713#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
714#define TMS570_SPI_TGITLVCR_CLR_INTLVLSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
715
716
717/*--------------------TMS570_SPI_TGINTFLG--------------------*/
718/* field: INTFLGRDY - Transfer-group interrupt flag for a transfer-completed interrupt. */
719#define TMS570_SPI_TGINTFLG_INTFLGRDY(val) BSP_FLD32(val,16, 31)
720#define TMS570_SPI_TGINTFLG_INTFLGRDY_GET(reg) BSP_FLD32GET(reg,16, 31)
721#define TMS570_SPI_TGINTFLG_INTFLGRDY_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
722
723/* field: INTFLGSUS - ransfer-group interrupt flag for a transfer-suspend interrupt. */
724#define TMS570_SPI_TGINTFLG_INTFLGSUS(val) BSP_FLD32(val,0, 15)
725#define TMS570_SPI_TGINTFLG_INTFLGSUS_GET(reg) BSP_FLD32GET(reg,0, 15)
726#define TMS570_SPI_TGINTFLG_INTFLGSUS_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
727
728
729/*---------------------TMS570_SPI_TICKCNT---------------------*/
730/* field: TICKENA - Tick counter enable. */
731#define TMS570_SPI_TICKCNT_TICKENA BSP_BIT32(31)
732
733/* field: RELOAD - Pre-load the tick counter. */
734#define TMS570_SPI_TICKCNT_RELOAD BSP_BIT32(30)
735
736/* field: CLKCTRL - Tick counter clock source control. */
737#define TMS570_SPI_TICKCNT_CLKCTRL(val) BSP_FLD32(val,28, 29)
738#define TMS570_SPI_TICKCNT_CLKCTRL_GET(reg) BSP_FLD32GET(reg,28, 29)
739#define TMS570_SPI_TICKCNT_CLKCTRL_SET(reg,val) BSP_FLD32SET(reg, val,28, 29)
740
741/* field: TICKVALUE - counter is loaded with the contents of TICKVALUE every time an underflow condition occurs and */
742#define TMS570_SPI_TICKCNT_TICKVALUE(val) BSP_FLD32(val,0, 15)
743#define TMS570_SPI_TICKCNT_TICKVALUE_GET(reg) BSP_FLD32GET(reg,0, 15)
744#define TMS570_SPI_TICKCNT_TICKVALUE_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
745
746
747/*---------------------TMS570_SPI_LTGPEND---------------------*/
748/* field: TG_IN_SERVICE - The TG number currently being serviced by the sequencer. */
749#define TMS570_SPI_LTGPEND_TG_IN_SERVICE(val) BSP_FLD32(val,24, 28)
750#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_GET(reg) BSP_FLD32GET(reg,24, 28)
751#define TMS570_SPI_LTGPEND_TG_IN_SERVICE_SET(reg,val) BSP_FLD32SET(reg, val,24, 28)
752
753/* field: LPEND - Last TG end pointer. */
754#define TMS570_SPI_LTGPEND_LPEND(val) BSP_FLD32(val,8, 14)
755#define TMS570_SPI_LTGPEND_LPEND_GET(reg) BSP_FLD32GET(reg,8, 14)
756#define TMS570_SPI_LTGPEND_LPEND_SET(reg,val) BSP_FLD32SET(reg, val,8, 14)
757
758
759/*---------------------TMS570_SPI_TGCTRL---------------------*/
760/* field: TGENA - TGx enable. */
761#define TMS570_SPI_TGCTRL_TGENA BSP_BIT32(31)
762
763/* field: ONESHOTx - Single transfer for TGx. */
764#define TMS570_SPI_TGCTRL_ONESHOTx BSP_BIT32(30)
765
766/* field: PRSTx - TGx pointer reset mode. Configures the way to resolve trigger events during an ongoing transfer. */
767#define TMS570_SPI_TGCTRL_PRSTx BSP_BIT32(29)
768
769/* field: TGTDx - TG triggered. */
770#define TMS570_SPI_TGCTRL_TGTDx BSP_BIT32(28)
771
772
773/*---------------------TMS570_SPI_DMACTRL---------------------*/
774/* field: ONESHOT - Auto-disable of DMA channel after ICOUNT+1 transfers. */
775#define TMS570_SPI_DMACTRL_ONESHOT BSP_BIT32(31)
776
777/* field: BUFIDx - Buffer utilized for DMA transfer. */
778#define TMS570_SPI_DMACTRL_BUFIDx(val) BSP_FLD32(val,24, 30)
779#define TMS570_SPI_DMACTRL_BUFIDx_GET(reg) BSP_FLD32GET(reg,24, 30)
780#define TMS570_SPI_DMACTRL_BUFIDx_SET(reg,val) BSP_FLD32SET(reg, val,24, 30)
781
782/* field: RXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
783#define TMS570_SPI_DMACTRL_RXDMA_MAPx(val) BSP_FLD32(val,20, 23)
784#define TMS570_SPI_DMACTRL_RXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,20, 23)
785#define TMS570_SPI_DMACTRL_RXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,20, 23)
786
787/* field: TXDMA_MAPx - Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA */
788#define TMS570_SPI_DMACTRL_TXDMA_MAPx(val) BSP_FLD32(val,16, 19)
789#define TMS570_SPI_DMACTRL_TXDMA_MAPx_GET(reg) BSP_FLD32GET(reg,16, 19)
790#define TMS570_SPI_DMACTRL_TXDMA_MAPx_SET(reg,val) BSP_FLD32SET(reg, val,16, 19)
791
792/* field: RXDMAENAx - Receive data DMA channel enable. */
793#define TMS570_SPI_DMACTRL_RXDMAENAx BSP_BIT32(15)
794
795/* field: TXDAMENAx - Transmit data DMA channel enable. */
796#define TMS570_SPI_DMACTRL_TXDAMENAx BSP_BIT32(14)
797
798/* field: NOBRKx - Non-interleaved DMA block transfer. This bit is available in master mode only. */
799#define TMS570_SPI_DMACTRL_NOBRKx BSP_BIT32(13)
800
801/* field: ICOUNTx - Initial count of DMA transfers. */
802#define TMS570_SPI_DMACTRL_ICOUNTx(val) BSP_FLD32(val,8, 12)
803#define TMS570_SPI_DMACTRL_ICOUNTx_GET(reg) BSP_FLD32GET(reg,8, 12)
804#define TMS570_SPI_DMACTRL_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,8, 12)
805
806/* field: COUNT_BIT17x - The 17th bit of the COUNT field of DMAxCOUNT register. */
807#define TMS570_SPI_DMACTRL_COUNT_BIT17x BSP_BIT32(6)
808
809/* field: COUNTx - Actual number of remaining DMA transfers. */
810#define TMS570_SPI_DMACTRL_COUNTx(val) BSP_FLD32(val,0, 5)
811#define TMS570_SPI_DMACTRL_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 5)
812#define TMS570_SPI_DMACTRL_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
813
814
815/*--------------------TMS570_SPI_DMACOUNT--------------------*/
816/* field: ICOUNTx - Every time COUNTx hits zero, it is reloaded with ICOUNTx. */
817#define TMS570_SPI_DMACOUNT_ICOUNTx(val) BSP_FLD32(val,16, 31)
818#define TMS570_SPI_DMACOUNT_ICOUNTx_GET(reg) BSP_FLD32GET(reg,16, 31)
819#define TMS570_SPI_DMACOUNT_ICOUNTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 31)
820
821/* field: COUNTx - The actual number of remaining DMA transfers. */
822#define TMS570_SPI_DMACOUNT_COUNTx(val) BSP_FLD32(val,0, 15)
823#define TMS570_SPI_DMACOUNT_COUNTx_GET(reg) BSP_FLD32GET(reg,0, 15)
824#define TMS570_SPI_DMACOUNT_COUNTx_SET(reg,val) BSP_FLD32SET(reg, val,0, 15)
825
826
827/*--------------------TMS570_SPI_DMACNTLEN--------------------*/
828/* field: LARGE_COUNT - Select either the 16-bit DMAxCOUNT counters or the smaller counters in DMAxCTRL. */
829#define TMS570_SPI_DMACNTLEN_LARGE_COUNT BSP_BIT32(0)
830
831
832/*--------------------TMS570_SPI_UERRCTRL--------------------*/
833/* field: PTESTEN - Parity memory test enable. */
834#define TMS570_SPI_UERRCTRL_PTESTEN BSP_BIT32(8)
835
836/* field: EDEN - Error detection enable. These bits enable parity error detection. */
837#define TMS570_SPI_UERRCTRL_EDEN(val) BSP_FLD32(val,0, 3)
838#define TMS570_SPI_UERRCTRL_EDEN_GET(reg) BSP_FLD32GET(reg,0, 3)
839#define TMS570_SPI_UERRCTRL_EDEN_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
840
841
842/*--------------------TMS570_SPI_UERRSTAT--------------------*/
843/* field: EDFLG1 - RXRAM. */
844#define TMS570_SPI_UERRSTAT_EDFLG1 BSP_BIT32(1)
845
846/* field: EDFLG0 - Uncorrectable parity error detection flag. */
847#define TMS570_SPI_UERRSTAT_EDFLG0 BSP_BIT32(0)
848
849
850/*-------------------TMS570_SPI_UERRADDRRX-------------------*/
851/* field: OVERADDR1 - Uncorrectable parity error address for RXRAM. */
852#define TMS570_SPI_UERRADDRRX_OVERADDR1(val) BSP_FLD32(val,0, 9)
853#define TMS570_SPI_UERRADDRRX_OVERADDR1_GET(reg) BSP_FLD32GET(reg,0, 9)
854#define TMS570_SPI_UERRADDRRX_OVERADDR1_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
855
856
857/*-------------------TMS570_SPI_UERRADDRTX-------------------*/
858/* field: UERRADDR0 - a parity error is generated while reading from TXRAM. */
859#define TMS570_SPI_UERRADDRTX_UERRADDR0(val) BSP_FLD32(val,0, 8)
860#define TMS570_SPI_UERRADDRTX_UERRADDR0_GET(reg) BSP_FLD32GET(reg,0, 8)
861#define TMS570_SPI_UERRADDRTX_UERRADDR0_SET(reg,val) BSP_FLD32SET(reg, val,0, 8)
862
863
864/*-----------------TMS570_SPI_RXOVRN_BUF_ADDR-----------------*/
865/* field: RXOVRN_BUF_ADDR - Address in RXRAM at which an overwrite occurred. */
866#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR(val) BSP_FLD32(val,0, 9)
867#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_GET(reg) BSP_FLD32GET(reg,0, 9)
868#define TMS570_SPI_RXOVRN_BUF_ADDR_RXOVRN_BUF_ADDR_SET(reg,val) BSP_FLD32SET(reg, val,0, 9)
869
870
871/*-------------------TMS570_SPI_IOLPBKTSTCR-------------------*/
872/* field: SCS_FAIL_FLG - Bit indicating a failure on SPISCS pin compare during analog loopback. */
873#define TMS570_SPI_IOLPBKTSTCR_SCS_FAIL_FLG BSP_BIT32(24)
874
875/* field: CTRL_BITERR - Controls inducing of BITERR during I/O loopback test mode. */
876#define TMS570_SPI_IOLPBKTSTCR_CTRL_BITERR BSP_BIT32(20)
877
878/* field: CTRL_DESYNC - Controls inducing of the desync error during I/O loopback test mode. */
879#define TMS570_SPI_IOLPBKTSTCR_CTRL_DESYNC BSP_BIT32(19)
880
881/* field: CTRL_PARERR - Controls inducing of the parity errors during I/O loopback test mode. */
882#define TMS570_SPI_IOLPBKTSTCR_CTRL_PARERR BSP_BIT32(18)
883
884/* field: CTRL_TIMEOUT - Controls inducing of the timeout error during I/O loopback test mode. */
885#define TMS570_SPI_IOLPBKTSTCR_CTRL_TIMEOUT BSP_BIT32(17)
886
887/* field: CTRL_DLENERR - Controls inducing of the data length error during I/O loopback test mode. */
888#define TMS570_SPI_IOLPBKTSTCR_CTRL_DLENERR BSP_BIT32(16)
889
890/* field: IOLPBKSTENA - Module I/O loopback test enable key. */
891#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA(val) BSP_FLD32(val,8, 11)
892#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
893#define TMS570_SPI_IOLPBKTSTCR_IOLPBKSTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
894
895/* field: ERR_SCS_PIN - Inject error on chip-select pin number x. */
896#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN(val) BSP_FLD32(val,3, 5)
897#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_GET(reg) BSP_FLD32GET(reg,3, 5)
898#define TMS570_SPI_IOLPBKTSTCR_ERR_SCS_PIN_SET(reg,val) BSP_FLD32SET(reg, val,3, 5)
899
900/* field: CTRL_SCS_PIN - Enable/disable the injection of an error on the SPISCS[3:0] pins. */
901#define TMS570_SPI_IOLPBKTSTCR_CTRL_SCS_PIN BSP_BIT32(2)
902
903/* field: LPBK_TYPE - Module I/O loopback type (analog/digital). */
904#define TMS570_SPI_IOLPBKTSTCR_LPBK_TYPE BSP_BIT32(1)
905
906/* field: RXP_ENA - Enable analog loopback through the receive pin. */
907#define TMS570_SPI_IOLPBKTSTCR_RXP_ENA BSP_BIT32(0)
908
909
910/*------------------TMS570_SPI_EXT_PRESCALEx------------------*/
911/* field: EPRESCALE_FMTx - EPRESCALE_FMTx. Extended Prescale value for SPIFMTx. */
912#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx(val) BSP_FLD32(val,16, 26)
913#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_GET(reg) BSP_FLD32GET(reg,16, 26)
914#define TMS570_SPI_EXT_PRESCALEx_EPRESCALE_FMTx_SET(reg,val) BSP_FLD32SET(reg, val,16, 26)
915
916
917
918#endif /* LIBBSP_ARM_TMS570_SPI */
utility.h
This header file provides utility macros for BSPs.
tms570_spi_t
Definition: reg_spi.h:44
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