RTEMS 6.1-rc1
reg_emacc.h
1/* The header file is generated by make_header.py from EMACC.json */
2/* Current script's version can be found at: */
3/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
4
5/*
6 * Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
7 *
8 * Czech Technical University in Prague
9 * Zikova 1903/4
10 * 166 36 Praha 6
11 * Czech Republic
12 *
13 * All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 *
18 * 1. Redistributions of source code must retain the above copyright notice, this
19 * list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright notice,
21 * this list of conditions and the following disclaimer in the documentation
22 * and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
31 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * The views and conclusions contained in the software and documentation are those
36 * of the authors and should not be interpreted as representing official policies,
37 * either expressed or implied, of the FreeBSD Project.
38*/
39#ifndef LIBBSP_ARM_TMS570_EMACC
40#define LIBBSP_ARM_TMS570_EMACC
41
42#include <bsp/utility.h>
43
44typedef struct{
45 uint32_t REVID; /*EMAC Control Module Revision ID Register*/
46 uint32_t SOFTRESET; /*EMAC Control Module Software Reset Register*/
47 uint8_t reserved1 [4];
48 uint32_t INTCONTROL; /*EMAC Control Module Interrupt Control Register*/
49 uint32_t C0RXTHRESHEN; /*EMAC Control Module Receive Threshold Interrupt Enable Register*/
50 uint32_t C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/
51 uint32_t C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/
52 uint32_t C0MISCEN; /*EMAC Control Module Miscellaneous Interrupt Enable Register*/
53 uint8_t reserved2 [32];
54 uint32_t C0RXTHRESHSTAT; /*EMAC Control Module Receive Threshold Interrupt Status Register*/
55 uint32_t C0RXSTAT; /*EMAC Control Module Receive Interrupt Status Register*/
56 uint32_t C0TXSTAT; /*EMAC Control Module Transmit Interrupt Status Register*/
57 uint32_t C0MISCSTAT; /*EMAC Control Module Miscellaneous Interrupt Status Register*/
58 uint8_t reserved3 [32];
59 uint32_t C0RXIMAX; /*EMAC Control Module Receive Interrupts Per Millisecond Register*/
60 uint32_t C0TXIMAX; /*EMAC Control Module Transmit Interrupts Per Millisecond Register*/
61} tms570_emacc_t;
62
63
64/*---------------------TMS570_EMACC_REVID---------------------*/
65/* field: REV - Identifies the EMAC Control Module revision. */
66/* Whole 32 bits */
67
68/*-------------------TMS570_EMACC_SOFTRESET-------------------*/
69/* field: RESET - Software reset bit for the EMAC Control Module. */
70#define TMS570_EMACC_SOFTRESET_RESET BSP_BIT32(0)
71
72
73/*------------------TMS570_EMACC_INTCONTROL------------------*/
74/* field: C0TXPACEEN - Enable pacing for TX interrupt pulse generation */
75#define TMS570_EMACC_INTCONTROL_C0TXPACEEN BSP_BIT32(17)
76
77/* field: C0RXPACEEN - Enable pacing for RX interrupt pulse generation */
78#define TMS570_EMACC_INTCONTROL_C0RXPACEEN BSP_BIT32(16)
79
80/* field: INTPRESCALE - Number of internal EMAC module reference clock periods within a 4 us time window (see */
81#define TMS570_EMACC_INTCONTROL_INTPRESCALE(val) BSP_FLD32(val,0, 11)
82#define TMS570_EMACC_INTCONTROL_INTPRESCALE_GET(reg) BSP_FLD32GET(reg,0, 11)
83#define TMS570_EMACC_INTCONTROL_INTPRESCALE_SET(reg,val) BSP_FLD32SET(reg, val,0, 11)
84
85
86/*-----------------TMS570_EMACC_C0RXTHRESHEN-----------------*/
87/* field: RXCH7THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7 */
88#define TMS570_EMACC_C0RXTHRESHEN_RXCH7THRESHEN BSP_BIT32(7)
89
90/* field: RXCH6THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6 */
91#define TMS570_EMACC_C0RXTHRESHEN_RXCH6THRESHEN BSP_BIT32(6)
92
93/* field: RXCH5THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5 */
94#define TMS570_EMACC_C0RXTHRESHEN_RXCH5THRESHEN BSP_BIT32(5)
95
96/* field: RXCH4THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4 */
97#define TMS570_EMACC_C0RXTHRESHEN_RXCH4THRESHEN BSP_BIT32(4)
98
99/* field: RXCH3THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3 */
100#define TMS570_EMACC_C0RXTHRESHEN_RXCH3THRESHEN BSP_BIT32(3)
101
102/* field: RXCH2THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2 */
103#define TMS570_EMACC_C0RXTHRESHEN_RXCH2THRESHEN BSP_BIT32(2)
104
105/* field: RXCH1THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1 */
106#define TMS570_EMACC_C0RXTHRESHEN_RXCH1THRESHEN BSP_BIT32(1)
107
108/* field: RXCH0THRESHEN - Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0 */
109#define TMS570_EMACC_C0RXTHRESHEN_RXCH0THRESHEN BSP_BIT32(0)
110
111
112/*--------------------TMS570_EMACC_C0RXEN--------------------*/
113/* field: RXCH7EN - Enable C0RXPULSE interrupt generation for RX Channel 7 */
114#define TMS570_EMACC_C0RXEN_RXCH7EN BSP_BIT32(7)
115
116/* field: RXCH6EN - Enable C0RXPULSE interrupt generation for RX Channel 6 */
117#define TMS570_EMACC_C0RXEN_RXCH6EN BSP_BIT32(6)
118
119/* field: RXCH5EN - Enable C0RXPULSE interrupt generation for RX Channel 5 */
120#define TMS570_EMACC_C0RXEN_RXCH5EN BSP_BIT32(5)
121
122/* field: RXCH4EN - Enable C0RXPULSE interrupt generation for RX Channel 4 */
123#define TMS570_EMACC_C0RXEN_RXCH4EN BSP_BIT32(4)
124
125/* field: RXCH3EN - Enable C0RXPULSE interrupt generation for RX Channel 3 */
126#define TMS570_EMACC_C0RXEN_RXCH3EN BSP_BIT32(3)
127
128/* field: RXCH2EN - Enable C0RXPULSE interrupt generation for RX Channel 2 */
129#define TMS570_EMACC_C0RXEN_RXCH2EN BSP_BIT32(2)
130
131/* field: RXCH1EN - Enable C0RXPULSE interrupt generation for RX Channel 1 */
132#define TMS570_EMACC_C0RXEN_RXCH1EN BSP_BIT32(1)
133
134/* field: RXCH0EN - Enable C0RXPULSE interrupt generation for RX Channel 0 */
135#define TMS570_EMACC_C0RXEN_RXCH0EN BSP_BIT32(0)
136
137
138/*--------------------TMS570_EMACC_C0TXEN--------------------*/
139/* field: TXCH7EN - Enable C0TXPULSE interrupt generation for TX Channel 7 */
140#define TMS570_EMACC_C0TXEN_TXCH7EN BSP_BIT32(7)
141
142/* field: TXCH6EN - TXCH6EN */
143#define TMS570_EMACC_C0TXEN_TXCH6EN BSP_BIT32(6)
144
145/* field: TXCH5EN - Enable C0TXPULSE interrupt generation for TX Channel 5 */
146#define TMS570_EMACC_C0TXEN_TXCH5EN BSP_BIT32(5)
147
148/* field: TXCH4EN - Enable C0TXPULSE interrupt generation for TX Channel 4 */
149#define TMS570_EMACC_C0TXEN_TXCH4EN BSP_BIT32(4)
150
151/* field: TXCH3EN - Enable C0TXPULSE interrupt generation for TX Channel 3 */
152#define TMS570_EMACC_C0TXEN_TXCH3EN BSP_BIT32(3)
153
154/* field: TXCH2EN - Enable C0TXPULSE interrupt generation for TX Channel 2 */
155#define TMS570_EMACC_C0TXEN_TXCH2EN BSP_BIT32(2)
156
157/* field: TXCH1EN - Enable C0TXPULSE interrupt generation for TX Channel 1 */
158#define TMS570_EMACC_C0TXEN_TXCH1EN BSP_BIT32(1)
159
160/* field: TXCH0EN - Enable C0TXPULSE interrupt generation for TX Channel 0 */
161#define TMS570_EMACC_C0TXEN_TXCH0EN BSP_BIT32(0)
162
163
164/*-------------------TMS570_EMACC_C0MISCEN-------------------*/
165/* field: STATPENDEN - Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated */
166#define TMS570_EMACC_C0MISCEN_STATPENDEN BSP_BIT32(3)
167
168/* field: HOSTPENDEN - HOSTPENDEN */
169#define TMS570_EMACC_C0MISCEN_HOSTPENDEN BSP_BIT32(2)
170
171/* field: LINKINT0EN - Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts (corresponding to */
172#define TMS570_EMACC_C0MISCEN_LINKINT0EN BSP_BIT32(1)
173
174/* field: USERINT0EN - Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding */
175#define TMS570_EMACC_C0MISCEN_USERINT0EN BSP_BIT32(0)
176
177
178/*----------------TMS570_EMACC_C0RXTHRESHSTAT----------------*/
179/* field: RXCH7THRESHSTAT - Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register */
180#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH7THRESHSTAT BSP_BIT32(7)
181
182/* field: RXCH6THRESHSTAT - Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register */
183#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH6THRESHSTAT BSP_BIT32(6)
184
185/* field: RXCH5THRESHSTAT - Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register */
186#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH5THRESHSTAT BSP_BIT32(5)
187
188/* field: RXCH4THRESHSTAT - Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register */
189#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH4THRESHSTAT BSP_BIT32(4)
190
191/* field: RXCH3THRESHSTAT - Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register */
192#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH3THRESHSTAT BSP_BIT32(3)
193
194/* field: RXCH2THRESHSTAT - Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register */
195#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH2THRESHSTAT BSP_BIT32(2)
196
197/* field: RXCH1THRESHSTAT - Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register */
198#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH1THRESHSTAT BSP_BIT32(1)
199
200/* field: RXCH0THRESHSTAT - Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register */
201#define TMS570_EMACC_C0RXTHRESHSTAT_RXCH0THRESHSTAT BSP_BIT32(0)
202
203
204/*-------------------TMS570_EMACC_C0RXSTAT-------------------*/
205/* field: RXCH7STAT - RXCH7STAT */
206#define TMS570_EMACC_C0RXSTAT_RXCH7STAT BSP_BIT32(7)
207
208/* field: RXCH6STAT - Interrupt status for RX Channel 6 masked by the C0RXEN register */
209#define TMS570_EMACC_C0RXSTAT_RXCH6STAT BSP_BIT32(6)
210
211/* field: RXCH5STAT - Interrupt status for RX Channel 5 masked by the C0RXEN register */
212#define TMS570_EMACC_C0RXSTAT_RXCH5STAT BSP_BIT32(5)
213
214/* field: RXCH4STAT - Interrupt status for RX Channel 4 masked by the C0RXEN register */
215#define TMS570_EMACC_C0RXSTAT_RXCH4STAT BSP_BIT32(4)
216
217/* field: RXCH3STAT - Interrupt status for RX Channel 3 masked by the C0RXEN register */
218#define TMS570_EMACC_C0RXSTAT_RXCH3STAT BSP_BIT32(3)
219
220/* field: RXCH2STAT - H2STAT Interrupt status for RX Channel 2 masked by the C0RXEN register */
221#define TMS570_EMACC_C0RXSTAT_RXCH2STAT BSP_BIT32(2)
222
223/* field: RXCH1STAT - Interrupt status for RX Channel 1 masked by the C0RXEN register */
224#define TMS570_EMACC_C0RXSTAT_RXCH1STAT BSP_BIT32(1)
225
226/* field: RXCH0STAT - Interrupt status for RX Channel 0 masked by the C0RXEN register */
227#define TMS570_EMACC_C0RXSTAT_RXCH0STAT BSP_BIT32(0)
228
229
230/*-------------------TMS570_EMACC_C0TXSTAT-------------------*/
231/* field: TXCH7STAT - Interrupt status for TX Channel 7 masked by the C0TXEN register */
232#define TMS570_EMACC_C0TXSTAT_TXCH7STAT BSP_BIT32(7)
233
234/* field: TXCH6STAT - TXCH6STAT */
235#define TMS570_EMACC_C0TXSTAT_TXCH6STAT BSP_BIT32(6)
236
237/* field: TXCH5STAT - Interrupt status for TX Channel 5 masked by the C0TXEN register */
238#define TMS570_EMACC_C0TXSTAT_TXCH5STAT BSP_BIT32(5)
239
240/* field: TXCH4STAT - Interrupt status for TX Channel 4 masked by the C0TXEN register */
241#define TMS570_EMACC_C0TXSTAT_TXCH4STAT BSP_BIT32(4)
242
243/* field: TXCH3STAT - Interrupt status for TX Channel 3 masked by the C0TXEN register */
244#define TMS570_EMACC_C0TXSTAT_TXCH3STAT BSP_BIT32(3)
245
246/* field: TXCH2STAT - Interrupt status for TX Channel 2 masked by the C0TXEN register */
247#define TMS570_EMACC_C0TXSTAT_TXCH2STAT BSP_BIT32(2)
248
249/* field: TXCH1STAT - Interrupt status for TX Channel 1 masked by the C0TXEN register */
250#define TMS570_EMACC_C0TXSTAT_TXCH1STAT BSP_BIT32(1)
251
252/* field: TXCH0STAT - Interrupt status for TX Channel 0 masked by the C0TXEN register */
253#define TMS570_EMACC_C0TXSTAT_TXCH0STAT BSP_BIT32(0)
254
255
256/*------------------TMS570_EMACC_C0MISCSTAT------------------*/
257/* field: STATPENDSTAT - Interrupt status for EMAC STATPEND masked by the C0MISCEN register */
258#define TMS570_EMACC_C0MISCSTAT_STATPENDSTAT BSP_BIT32(3)
259
260/* field: HOSTPENDSTAT - Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register */
261#define TMS570_EMACC_C0MISCSTAT_HOSTPENDSTAT BSP_BIT32(2)
262
263/* field: LINKINT0STAT - Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register */
264#define TMS570_EMACC_C0MISCSTAT_LINKINT0STAT BSP_BIT32(1)
265
266/* field: USERINT0STAT - Interrupt status for MDIO USERINT0 masked by the C0MISCEN register */
267#define TMS570_EMACC_C0MISCSTAT_USERINT0STAT BSP_BIT32(0)
268
269
270/*-------------------TMS570_EMACC_C0RXIMAX-------------------*/
271/* field: RXIMAX - RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond when */
272#define TMS570_EMACC_C0RXIMAX_RXIMAX(val) BSP_FLD32(val,0, 5)
273#define TMS570_EMACC_C0RXIMAX_RXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5)
274#define TMS570_EMACC_C0RXIMAX_RXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
275
276
277/*-------------------TMS570_EMACC_C0TXIMAX-------------------*/
278/* field: TXIMAX - TXIMAX is the desired number of C0TXPULSE interrupts generated per millisecond when */
279#define TMS570_EMACC_C0TXIMAX_TXIMAX(val) BSP_FLD32(val,0, 5)
280#define TMS570_EMACC_C0TXIMAX_TXIMAX_GET(reg) BSP_FLD32GET(reg,0, 5)
281#define TMS570_EMACC_C0TXIMAX_TXIMAX_SET(reg,val) BSP_FLD32SET(reg, val,0, 5)
282
283
284
285#endif /* LIBBSP_ARM_TMS570_EMACC */
utility.h
This header file provides utility macros for BSPs.
tms570_emacc_t
Definition: reg_emacc.h:44
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