RTEMS 6.1-rc1
mpu.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
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28/* ---------------------------------------------------------------------------- */
29
30#ifndef _MPU_H_
31#define _MPU_H_
32#ifdef __rtems__
33#include <bsp.h>
34#endif /* __rtems__ */
35
36/*----------------------------------------------------------------------------
37 * Definitions
38 *----------------------------------------------------------------------------*/
39#define ARM_MODE_USR 0x10
40
41#define PRIVILEGE_MODE 0
42#define USER_MODE 1
43
44#define MPU_DEFAULT_ITCM_REGION (1)
45#define MPU_DEFAULT_IFLASH_REGION (2)
46#define MPU_DEFAULT_DTCM_REGION (3)
47#define MPU_DEFAULT_SRAM_REGION_1 (4)
48#define MPU_DEFAULT_SRAM_REGION_2 (5)
49#define MPU_PERIPHERALS_REGION (6)
50#define MPU_EXT_EBI_REGION (7)
51#define MPU_DEFAULT_SDRAM_REGION (8)
52#define MPU_QSPIMEM_REGION (9)
53#define MPU_USBHSRAM_REGION (10)
54#if defined MPU_HAS_NOCACHE_REGION
55 #define MPU_NOCACHE_SRAM_REGION (11)
56#endif
57#define MPU_SYSTEM_REGION (12)
58#ifdef __rtems__
59#define MPU_NULL_REGION (13)
60/* Reserve the region with highest priority for user applications */
61#define MPU_USER_DEFINED_REGION (15)
62#endif /* __rtems__ */
63
64#define MPU_REGION_VALID (0x10)
65#define MPU_REGION_ENABLE (0x01)
66#define MPU_REGION_DISABLE (0x0)
67
68#define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos)
69#define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos)
70#define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos)
71
72
73#define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos)
74#define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos)
75#define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos)
76
77#define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos)
78
79#define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos)
80#define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos)
81#define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos)
82#define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos)
83#define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos)
84#define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos)
85#define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos)
86#define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos)
87
88#define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos)
89#define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos)
90#define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos)
91#define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos)
92#define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos)
93#define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos)
94#define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos)
95#define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos)
96
97/* Default memory map
98 Address range Memory region Memory type Shareability Cache policy
99 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT
100 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA
101 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable -
102 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA
103 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT
104 0xA0000000- 0xBFFFFFFF Device Device Shareable
105 0xC0000000- 0xDFFFFFFF Device Device Non Shareable
106 0xE0000000- 0xFFFFFFFF System - -
107 */
108
109/********* IFLASH memory macros *********************/
110#ifdef __rtems__
111#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin)
112#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1)
113#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin)
114#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1)
115#else /* !__rtems__ */
116#define ITCM_START_ADDRESS 0x00000000UL
117#define ITCM_END_ADDRESS 0x003FFFFFUL
118#define IFLASH_START_ADDRESS 0x00400000UL
119#define IFLASH_END_ADDRESS 0x005FFFFFUL
120#endif /* __rtems__ */
121
122
123#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
124#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF)
125
126#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1)
127#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
128
129/**************** DTCM *******************************/
130#ifdef __rtems__
131#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin)
132#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1)
133#else /* !__rtems__ */
134#define DTCM_START_ADDRESS 0x20000000UL
135#define DTCM_END_ADDRESS 0x203FFFFFUL
136#endif /* __rtems__ */
137
138
139/******* SRAM memory macros ***************************/
140
141#ifdef __rtems__
142#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
143#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
144#else /* !__rtems__ */
145#define SRAM_START_ADDRESS 0x20400000UL
146#define SRAM_END_ADDRESS 0x2045FFFFUL
147#endif /* __rtems__ */
148
149#ifndef __rtems__
150#if defined MPU_HAS_NOCACHE_REGION
151 #define NOCACHE_SRAM_REGION_SIZE 0x1000
152#endif
153#endif /* __rtems__ */
154
155/* Regions should be a 2^(N+1) where 4 < N < 31 */
156#ifdef __rtems__
157#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin)
158#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1)
159#else /* !__rtems__ */
160#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
161#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
162#endif /* __rtems__ */
163
164#if defined MPU_HAS_NOCACHE_REGION
165#ifdef __rtems__
166 #define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
167 #define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
168 #define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS)
169#else /* !__rtems__ */
170 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
171 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
172 #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
173 #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
174#endif /* __rtems__ */
175#else
176#ifndef __rtems__
177 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
178 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
179#endif /* __rtems__ */
180#endif
181/************** Peripherals memory region macros ********/
182#define PERIPHERALS_START_ADDRESS 0x40000000UL
183#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
184#ifdef __rtems__
185#define SYSTEM_START_ADDRESS 0xE0000000UL
186#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL
187#endif /* __rtems__ */
188
189/******* Ext EBI memory macros ***************************/
190#define EXT_EBI_START_ADDRESS 0x60000000UL
191#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
192
193/******* Ext-SRAM memory macros ***************************/
194#ifdef __rtems__
195#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
196#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
197#else /* !__rtems__ */
198#define SDRAM_START_ADDRESS 0x70000000UL
199#define SDRAM_END_ADDRESS 0x7FFFFFFFUL
200#endif /* __rtems__ */
201
202/******* QSPI macros ***************************/
203#ifdef __rtems__
204#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin)
205#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1)
206#else /* !__rtems__ */
207#define QSPI_START_ADDRESS 0x80000000UL
208#define QSPI_END_ADDRESS 0x9FFFFFFFUL
209#endif /* __rtems__ */
210
211/************** USBHS_RAM region macros ******************/
212#define USBHSRAM_START_ADDRESS 0xA0100000UL
213#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL
214
215/*----------------------------------------------------------------------------
216 * Export functions
217 *----------------------------------------------------------------------------*/
218void MPU_Enable(uint32_t dwMPUEnable);
219void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr);
220void MPU_SetRegionNum(uint32_t dwRegionNum);
221void MPU_DisableRegion(void);
222uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes);
223void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
224 uint32_t dwRegionAttr);
225
226#endif /* #ifndef _MMU_ */
227
MPU_Enable
void MPU_Enable(uint32_t dwMPUEnable)
Enables the MPU module.
Definition: mpu.c:78
MPU_SetRegion
void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr)
Setup a memory region.
Definition: mpu.c:107
MPU_CalMPURegionSize
uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes)
Calculate region size for the RASR.
Definition: mpu.c:117
MPU_SetRegionNum
void MPU_SetRegionNum(uint32_t dwRegionNum)
Set active memory region.
Definition: mpu.c:88
MPU_UpdateRegions
void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr)
Update MPU regions.
Definition: mpu.c:140
MPU_DisableRegion
void MPU_DisableRegion(void)
Disable the current active region.
Definition: mpu.c:96
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