171#define M8260_RCCR_TIME (1<<31)
172#define M8260_RCCR_TIMEP(x) ((x)<<24)
173#define M8260_RCCR_DR1M (1<<23)
174#define M8260_RCCR_DR2M (1<<22)
175#define M8260_RCCR_DR1QP(x) ((x)<<20)
176#define M8260_RCCR_EIE (1<<19)
177#define M8260_RCCR_SCD (1<<18)
178#define M8260_RCCR_DR2QP(x) ((x)<<16)
179#define M8260_RCCR_ERAM(x) ((x)<<13)
180#define M8260_RCCR_EDM1 (1<<11)
181#define M8260_RCCR_EDM2 (1<<10)
182#define M8260_RCCR_EDM3 (1<<9)
183#define M8260_RCCR_EDM4 (1<<8)
184#define M8260_RCCR_DR3M (1<<7)
185#define M8260_RCCR_DR4M (1<<6)
186#define M8260_RCCR_DR3QP(x) ((x)<<4)
187#define M8260_RCCR_DEM12 (1<<3)
188#define M8260_RCCR_DEM34 (1<<2)
189#define M8260_RCCR_DR4QP(x) (x)
198#define M8260_TM_CMD_V (1<<31)
199#define M8260_TM_CMD_R (1<<30)
200#define M8260_TM_CMD_PWM (1<<29)
201#define M8260_TM_CMD_TIMER(x) ((x)<<16)
202#define M8260_TM_CMD_PERIOD(x) (x)
217 uint16_t _dpr_in_ptr;
219 uint16_t _dpr_out_ptr;
272 uint16_t character[8];
306 uint16_t character[8];
333 uint32_t _tbuf0data0;
334 uint32_t _tbuf0data1;
345 uint32_t _tbuf1data0;
346 uint32_t _tbuf1data1;
367#define M8260_SCCE_BRKE (1<<6)
368#define M8260_SCCE_BRK (1<<5)
369#define M8260_SCCE_TXE (1<<4)
370#define M8260_SCCE_RXF (1<<3)
371#define M8260_SCCE_BSY (1<<2)
372#define M8260_SCCE_TX (1<<1)
373#define M8260_SCCE_RX (1<<0)
512#define M8260_RFCR_BO(x) ((x)<<3)
513#define M8260_RFCR_MOT (2<<3)
514#define M8260_RFCR_LOCAL_BUS (2)
515#define M8260_RFCR_60X_BUS (0)
516#define M8260_TFCR_BO(x) ((x)<<3)
517#define M8260_TFCR_MOT (2<<3)
518#define M8260_TFCR_LOCAL_BUS (2)
519#define M8260_TFCR_60X_BUS (0)
561#define M8260_SMCMR_CLEN(x) ((x)<<11)
562#define M8260_SMCMR_2STOP (1<<10)
563#define M8260_SMCMR_PARITY (1<<9)
564#define M8260_SMCMR_EVEN (1<<8)
565#define M8260_SMCMR_SM_GCI (0<<4)
566#define M8260_SMCMR_SM_UART (2<<4)
567#define M8260_SMCMR_SM_TRANSPARENT (3<<4)
568#define M8260_SMCMR_DM_LOOPBACK (1<<2)
569#define M8260_SMCMR_DM_ECHO (2<<2)
570#define M8260_SMCMR_TEN (1<<1)
571#define M8260_SMCMR_REN (1<<0)
576#define M8260_SMCE_TXE (1<<4)
577#define M8260_SMCE_BSY (1<<2)
578#define M8260_SMCE_TX (1<<1)
579#define M8260_SMCE_RX (1<<0)
607#define M8260_SPMODE_LOOP (1<<14)
608#define M8260_SPMODE_CI (1<<13)
609#define M8260_SPMODE_CP (1<<12)
610#define M8260_SPMODE_DIV16 (1<<11)
611#define M8260_SPMODE_REV (1<<10)
612#define M8260_SPMODE_MASTER (1<<9)
613#define M8260_SPMODE_EN (1<<8)
614#define M8260_SPMODE_CLEN(x) ((x)<<4)
615#define M8260_SPMODE_PM(x) (x)
620#define M8260_SPCOM_STR (1<<7)
625#define M8260_SPIE_MME (1<<5)
626#define M8260_SPIE_TXE (1<<4)
627#define M8260_SPIE_BSY (1<<2)
628#define M8260_SPIE_TXB (1<<1)
629#define M8260_SPIE_RXB (1<<0)
639 volatile void *buffer;
645#define M8260_BD_EMPTY (1<<15)
646#define M8260_BD_WRAP (1<<13)
647#define M8260_BD_INTERRUPT (1<<12)
648#define M8260_BD_LAST (1<<11)
649#define M8260_BD_CONTROL_CHAR (1<<11)
650#define M8260_BD_FIRST_IN_FRAME (1<<10)
651#define M8260_BD_ADDRESS (1<<10)
652#define M8260_BD_CONTINUOUS (1<<9)
653#define M8260_BD_MISS (1<<8)
654#define M8260_BD_IDLE (1<<8)
655#define M8260_BD_ADDRSS_MATCH (1<<7)
656#define M8260_BD_LONG (1<<5)
657#define M8260_BD_BREAK (1<<5)
658#define M8260_BD_NONALIGNED (1<<4)
659#define M8260_BD_FRAMING_ERROR (1<<4)
660#define M8260_BD_SHORT (1<<3)
661#define M8260_BD_PARITY_ERROR (1<<3)
662#define M8260_BD_ABORT (1<<3)
663#define M8260_BD_CRC_ERROR (1<<2)
664#define M8260_BD_OVERRUN (1<<1)
665#define M8260_BD_COLLISION (1<<0)
666#define M8260_BD_CARRIER_LOST (1<<0)
667#define M8260_BD_MASTER_ERROR (1<<0)
669#define M8xx_BD_EMPTY (1<<15)
670#define M8xx_BD_WRAP (1<<13)
671#define M8xx_BD_INTERRUPT (1<<12)
672#define M8xx_BD_LAST (1<<11)
673#define M8xx_BD_CONTROL_CHAR (1<<11)
674#define M8xx_BD_FIRST_IN_FRAME (1<<10)
675#define M8xx_BD_ADDRESS (1<<10)
676#define M8xx_BD_CONTINUOUS (1<<9)
677#define M8xx_BD_MISS (1<<8)
678#define M8xx_BD_IDLE (1<<8)
679#define M8xx_BD_ADDRSS_MATCH (1<<7)
680#define M8xx_BD_LONG (1<<5)
681#define M8xx_BD_BREAK (1<<5)
682#define M8xx_BD_NONALIGNED (1<<4)
683#define M8xx_BD_FRAMING_ERROR (1<<4)
684#define M8xx_BD_SHORT (1<<3)
685#define M8xx_BD_PARITY_ERROR (1<<3)
686#define M8xx_BD_ABORT (1<<3)
687#define M8xx_BD_CRC_ERROR (1<<2)
688#define M8xx_BD_OVERRUN (1<<1)
689#define M8xx_BD_COLLISION (1<<0)
690#define M8xx_BD_CARRIER_LOST (1<<0)
691#define M8xx_BD_MASTER_ERROR (1<<0)
697#define M8260_BD_READY (1<<15)
698#define M8260_BD_PAD (1<<14)
699#define M8260_BD_CTS_REPORT (1<<11)
700#define M8260_BD_TX_CRC (1<<10)
701#define M8260_BD_DEFER (1<<9)
702#define M8260_BD_HEARTBEAT (1<<8)
703#define M8260_BD_PREAMBLE (1<<8)
704#define M8260_BD_LATE_COLLISION (1<<7)
705#define M8260_BD_NO_STOP_BIT (1<<7)
706#define M8260_BD_RETRY_LIMIT (1<<6)
707#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2)
708#define M8260_BD_UNDERRUN (1<<1)
709#define M8260_BD_CARRIER_LOST (1<<0)
710#define M8260_BD_CTS_LOST (1<<0)
712#define M8xx_BD_READY (1<<15)
713#define M8xx_BD_PAD (1<<14)
714#define M8xx_BD_CTS_REPORT (1<<11)
715#define M8xx_BD_TX_CRC (1<<10)
716#define M8xx_BD_DEFER (1<<9)
717#define M8xx_BD_HEARTBEAT (1<<8)
718#define M8xx_BD_PREAMBLE (1<<8)
719#define M8xx_BD_LATE_COLLISION (1<<7)
720#define M8xx_BD_NO_STOP_BIT (1<<7)
721#define M8xx_BD_RETRY_LIMIT (1<<6)
722#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2)
723#define M8xx_BD_UNDERRUN (1<<1)
724#define M8xx_BD_CARRIER_LOST (1<<0)
725#define M8xx_BD_CTS_LOST (1<<0)
746#define M8260_CR_RST (1<<31)
748#define M8260_CR_FCC1 ((4<<26)|(16<<21))
749#define M8260_CR_FCC1_ATM ((4<<26)|(14<<21))
750#define M8260_CR_FCC2 ((5<<26)|(17<<21))
751#define M8260_CR_FCC2_ATM ((5<<26)|(14<<21))
752#define M8260_CR_FCC3 ((6<<26)|(18<<21))
753#define M8260_CR_SCC1 ((0<<26)|(4<<21))
754#define M8260_CR_SCC2 ((1<<26)|(5<<21))
755#define M8260_CR_SCC3 ((2<<26)|(6<<21))
756#define M8260_CR_SCC4 ((3<<26)|(7<<21))
757#define M8260_CR_SMC1 ((7<<26)|(8<<21))
758#define M8260_CR_SMC2 ((8<<26)|(9<<21))
759#define M8260_CR_RAND ((10<<26)|(14<<21))
760#define M8260_CR_SPI ((9<<26)|(10<<21))
761#define M8260_CR_I2C ((10<<26)|(11<<21))
762#define M8260_CR_TMR ((10<<26)|(15<<21))
763#define M8260_CR_MCC1 ((7<<26)|(28<<21))
764#define M8260_CR_MCC2 ((8<<26)|(29<<21))
765#define M8260_CR_IDMA1 ((7<<26)|(20<<21))
766#define M8260_CR_IDMA2 ((8<<26)|(21<<21))
767#define M8260_CR_IDMA3 ((9<<26)|(22<<21))
768#define M8260_CR_IDMA4 ((10<<26)|(23<<21))
770#define M8260_CR_FLG (1<<16)
772#define M8260_CR_MCC_CHAN(x) ((x)<<6)
773#define M8260_CR_FCC_HDLC (0<<6)
774#define M8260_CR_FCC_ATM (10<<6)
775#define M8260_CR_FCC_ETH (12<<6)
777#define M8260_CR_OP_INIT_RX_TX (0)
778#define M8260_CR_OP_INIT_RX (1)
779#define M8260_CR_OP_INIT_TX (2)
780#define M8260_CR_OP_INIT_HUNT (3)
781#define M8260_CR_OP_STOP_TX (4)
782#define M8260_CR_OP_GR_STOP_TX (5)
783#define M8260_CR_OP_RESTART_TX (6)
784#define M8260_CR_OP_CLOSE_RX_BD (7)
785#define M8260_CR_OP_SET_GRP_ADDR (8)
786#define M8260_CR_OP_SET_TIMER (8)
787#define M8260_CR_OP_GCI_TIMEOUT (9)
788#define M8260_CR_OP_START_IDMA (9)
789#define M8260_CR_OP_STOP_RX (9)
790#define M8260_CR_OP_ATM_TX (10)
791#define M8260_CR_OP_RESET_BCS (10)
792#define M8260_CR_OP_GCI_ABORT (10)
793#define M8260_CR_OP_STOP_IDMA (11)
794#define M8260_CR_OP_RANDOM (12)
801#define M8260_SYPCR_SWTC(x) ((x)<<16)
802#define M8260_SYPCR_BMT(x) ((x)<<8)
803#define M8260_SYPCR_BME (1<<7)
804#define M8260_SYPCR_SWF (1<<3)
805#define M8260_SYPCR_SWE (1<<2)
806#define M8260_SYPCR_SWRI (1<<1)
807#define M8260_SYPCR_SWP (1<<0)
814#define M8260_UPM_AMX_8col (0<<20)
815#define M8260_UPM_AMX_9col (1<<20)
816#define M8260_UPM_AMX_10col (2<<20)
817#define M8260_UPM_AMX_11col (3<<20)
818#define M8260_UPM_AMX_12col (4<<20)
819#define M8260_UPM_AMX_13col (5<<20)
820#define M8260_MSR_PER(x) (0x100<<(7-x))
821#define M8260_MSR_WPER (1<<7)
822#define M8260_MPTPR_PTP(x) ((x)<<8)
823#define M8260_BR_BA(x) ((x)&0xffff8000)
824#define M8260_BR_AT(x) ((x)<<12)
825#define M8260_BR_PS8 (1<<10)
826#define M8260_BR_PS16 (2<<10)
827#define M8260_BR_PS32 (0<<10)
828#define M8260_BR_PARE (1<<9)
829#define M8260_BR_WP (1<<8)
830#define M8260_BR_MS_GPCM (0<<6)
831#define M8260_BR_MS_UPMA (2<<6)
832#define M8260_BR_MS_UPMB (3<<6)
833#define M8260_MEMC_BR_V (1<<0)
835#define M8260_MEMC_OR_32K 0xffff8000
836#define M8260_MEMC_OR_64K 0xffff0000
837#define M8260_MEMC_OR_128K 0xfffe0000
838#define M8260_MEMC_OR_256K 0xfffc0000
839#define M8260_MEMC_OR_512K 0xfff80000
840#define M8260_MEMC_OR_1M 0xfff00000
841#define M8260_MEMC_OR_2M 0xffe00000
842#define M8260_MEMC_OR_4M 0xffc00000
843#define M8260_MEMC_OR_8M 0xff800000
844#define M8260_MEMC_OR_16M 0xff000000
845#define M8260_MEMC_OR_32M 0xfe000000
846#define M8260_MEMC_OR_64M 0xfc000000
847#define M8260_MEMC_OR_128 0xf8000000
848#define M8260_MEMC_OR_256M 0xf0000000
849#define M8260_MEMC_OR_512M 0xe0000000
850#define M8260_MEMC_OR_1G 0xc0000000
851#define M8260_MEMC_OR_2G 0x80000000
852#define M8260_MEMC_OR_4G 0x00000000
853#define M8260_MEMC_OR_ATM(x) ((x)<<12)
854#define M8260_MEMC_OR_CSNT (1<<11)
855#define M8260_MEMC_OR_SAM (1<<11)
856#define M8260_MEMC_OR_ACS_NORM (0<<9)
857#define M8260_MEMC_OR_ACS_QRTR (2<<9)
858#define M8260_MEMC_OR_ACS_HALF (3<<9)
859#define M8260_MEMC_OR_BI (1<8)
860#define M8260_MEMC_OR_SCY(x) ((x)<<4)
861#define M8260_MEMC_OR_SETA (1<<3)
862#define M8260_MEMC_OR_TRLX (1<<2)
863#define M8260_MEMC_OR_EHTR (1<<1)
870#define M8260_MEMC_MMR_PTP(x) ((x)<<24)
871#define M8260_MEMC_MMR_PTE (1<<23)
872#define M8260_MEMC_MMR_DSP(x) ((x)<<17)
873#define M8260_MEMC_MMR_G0CL(x) ((x)<<13)
874#define M8260_MEMC_MMR_UPWAIT (1<<12)
875#define M8260_MEMC_MMR_RLF(x) ((x)<<8)
876#define M8260_MEMC_MMR_WLF(x) ((x)<<4)
877#define M8260_MEMC_MMR_TLF(x) ((x)<<0)
883#define M8260_MEMC_MCR_WRITE (0<<30)
884#define M8260_MEMC_MCR_READ (1<<30)
885#define M8260_MEMC_MCR_RUN (2<<30)
886#define M8260_MEMC_MCR_UPMA (0<<23)
887#define M8260_MEMC_MCR_UPMB (1<<23)
888#define M8260_MEMC_MCR_MB(x) ((x)<<13)
889#define M8260_MEMC_MCR_MCLF(x) ((x)<<8)
890#define M8260_MEMC_MCR_MAD(x) (x)
899#define M8260_SI_SMC2_BITS 0xFFFF0000
900#define M8260_SI_SMC2_TDM (1<<31)
901#define M8260_SI_SMC2_BRG1 (0<<28)
902#define M8260_SI_SMC2_BRG2 (1<<28)
903#define M8260_SI_SMC2_BRG3 (2<<28)
904#define M8260_SI_SMC2_BRG4 (3<<28)
905#define M8260_SI_SMC2_CLK5 (0<<28)
906#define M8260_SI_SMC2_CLK6 (1<<28)
907#define M8260_SI_SMC2_CLK7 (2<<28)
908#define M8260_SI_SMC2_CLK8 (3<<28)
909#define M8260_SI_SMC1_BITS 0x0000FFFF
910#define M8260_SI_SMC1_TDM (1<<15)
911#define M8260_SI_SMC1_BRG1 (0<<12)
912#define M8260_SI_SMC1_BRG2 (1<<12)
913#define M8260_SI_SMC1_BRG3 (2<<12)
914#define M8260_SI_SMC1_BRG4 (3<<12)
915#define M8260_SI_SMC1_CLK1 (0<<12)
916#define M8260_SI_SMC1_CLK2 (1<<12)
917#define M8260_SI_SMC1_CLK3 (2<<12)
918#define M8260_SI_SMC1_CLK4 (3<<12)
925#define M8260_SDCR_FREEZE (2<<13)
926#define M8260_SDCR_RAID_5 (1<<0)
933#define M8260_SDSR_SBER (1<<7)
934#define M8260_SDSR_DSP2 (1<<1)
935#define M8260_SDSR_DSP1 (1<<0)
942#define M8260_BRG_RST (1<<17)
943#define M8260_BRG_EN (1<<16)
944#define M8260_BRG_EXTC_BRGCLK (0<<14)
945#define M8260_BRG_EXTC_CLK2 (1<<14)
946#define M8260_BRG_EXTC_CLK6 (2<<14)
947#define M8260_BRG_ATB (1<<13)
948#define M8260_BRG_115200 (21<<1)
949#define M8260_BRG_57600 (32<<1)
950#define M8260_BRG_38400 (64<<1)
951#define M8260_BRG_19200 (129<<1)
952#define M8260_BRG_9600 (259<<1)
953#define M8260_BRG_4800 (520<<1)
954#define M8260_BRG_2400 (1040<<1)
955#define M8260_BRG_1200 (2082<<1)
956#define M8260_BRG_600 ((259<<1) | 1)
957#define M8260_BRG_300 ((520<<1) | 1)
958#define M8260_BRG_150 ((1040<<1) | 1)
959#define M8260_BRG_75 ((2080<<1) | 1)
961#define M8xx_BRG_RST (1<<17)
962#define M8xx_BRG_EN (1<<16)
963#define M8xx_BRG_EXTC_BRGCLK (0<<14)
965#define M8260_BRG1 (1<<7)
966#define M8260_BRG2 (1<<6)
967#define M8260_BRG3 (1<<5)
968#define M8260_BRG4 (1<<4)
969#define M8260_BRG5 (1<<3)
970#define M8260_BRG6 (1<<2)
971#define M8260_BRG7 (1<<1)
972#define M8260_BRG8 (1<<0)
976#define M8260_TGCR_CAS4 (1<<15)
977#define M8260_TGCR_CAS2 (1<<7)
978#define M8260_TGCR_FRZ1 (1<<2)
979#define M8260_TGCR_FRZ2 (1<<6)
980#define M8260_TGCR_FRZ3 (1<<10)
981#define M8260_TGCR_FRZ4 (1<<14)
982#define M8260_TGCR_STP1 (1<<1)
983#define M8260_TGCR_STP2 (1<<5)
984#define M8260_TGCR_STP3 (1<<9)
985#define M8260_TGCR_STP4 (1<<13)
986#define M8260_TGCR_RST1 (1<<0)
987#define M8260_TGCR_RST2 (1<<4)
988#define M8260_TGCR_RST3 (1<<8)
989#define M8260_TGCR_RST4 (1<<12)
990#define M8260_TGCR_GM1 (1<<3)
991#define M8260_TGCR_GM2 (1<<11)
993#define M8260_TMR_PS(x) ((x)<<8)
994#define M8260_TMR_CE_RISE (1<<6)
995#define M8260_TMR_CE_FALL (2<<6)
996#define M8260_TMR_CE_ANY (3<<6)
997#define M8260_TMR_OM_TOGGLE (1<<5)
998#define M8260_TMR_ORI (1<<4)
999#define M8260_TMR_RESTART (1<<3)
1000#define M8260_TMR_ICLK_INT (1<<1)
1001#define M8260_TMR_ICLK_INT16 (2<<1)
1002#define M8260_TMR_ICLK_TIN (3<<1)
1003#define M8260_TMR_TGATE (1<<0)
1006#define M8260_PISCR_PS (1<<6)
1008#define M8260_PISCR_PS (1<<7)
1010#define M8260_PISCR_PIE (1<<2)
1011#define M8260_PISCR_PTF (1<<1)
1012#define M8260_PISCR_PTE (1<<0)
1015#define M8260_TBSCR_TBIRQ(x) (1<<(15-x))
1016#define M8260_TBSCR_REFA (1<<7)
1017#define M8260_TBSCR_REFB (1<<6)
1018#define M8260_TBSCR_REFAE (1<<3)
1019#define M8260_TBSCR_REFBE (1<<2)
1020#define M8260_TBSCR_TBF (1<<1)
1021#define M8260_TBSCR_TBE (1<<0)
1024#define M8260_TMCNTSC_SEC (1<<7)
1025#define M8260_TMCNTSC_ALR (1<<6)
1026#define M8260_TMCNTSC_SIE (1<<3)
1027#define M8260_TMCNTSC_ALE (1<<2)
1028#define M8260_TMCNTSC_TCF (1<<1)
1029#define M8260_TMCNTSC_TCE (1<<0)
1031#define M8260_SIMASK_PC0 (1<<31)
1032#define M8260_SIMASK_PC1 (1<<30)
1033#define M8260_SIMASK_PC2 (1<<29)
1034#define M8260_SIMASK_PC3 (1<<28)
1035#define M8260_SIMASK_PC4 (1<<27)
1036#define M8260_SIMASK_PC5 (1<<26)
1037#define M8260_SIMASK_PC6 (1<<25)
1038#define M8260_SIMASK_PC7 (1<<24)
1039#define M8260_SIMASK_PC8 (1<<23)
1040#define M8260_SIMASK_PC9 (1<<22)
1041#define M8260_SIMASK_PC10 (1<<21)
1042#define M8260_SIMASK_PC11 (1<<20)
1043#define M8260_SIMASK_PC12 (1<<19)
1044#define M8260_SIMASK_PC13 (1<<18)
1045#define M8260_SIMASK_PC14 (1<<17)
1046#define M8260_SIMASK_PC15 (1<<16)
1047#define M8260_SIMASK_IRQ1 (1<<14)
1048#define M8260_SIMASK_IRQ2 (1<<13)
1049#define M8260_SIMASK_IRQ3 (1<<12)
1050#define M8260_SIMASK_IRQ4 (1<<11)
1051#define M8260_SIMASK_IRQ5 (1<<10)
1052#define M8260_SIMASK_IRQ6 (1<<9)
1053#define M8260_SIMASK_IRQ7 (1<<8)
1054#define M8260_SIMASK_TMCNT (1<<2)
1055#define M8260_SIMASK_PIT (1<<1)
1057#define M8260_SIMASK_FCC1 (1<<31)
1058#define M8260_SIMASK_FCC2 (1<<30)
1059#define M8260_SIMASK_FCC3 (1<<29)
1060#define M8260_SIMASK_MCC1 (1<<27)
1061#define M8260_SIMASK_MCC2 (1<<26)
1062#define M8260_SIMASK_SCC1 (1<<23)
1063#define M8260_SIMASK_SCC2 (1<<22)
1064#define M8260_SIMASK_SCC3 (1<<21)
1065#define M8260_SIMASK_SCC4 (1<<20)
1066#define M8260_SIMASK_I2C (1<<15)
1067#define M8260_SIMASK_SPI (1<<14)
1068#define M8260_SIMASK_RTT (1<<13)
1069#define M8260_SIMASK_SMC1 (1<<12)
1070#define M8260_SIMASK_SMC2 (1<<11)
1071#define M8260_SIMASK_IDMA1 (1<<10)
1072#define M8260_SIMASK_IDMA2 (1<<9)
1073#define M8260_SIMASK_IDMA3 (1<<8)
1074#define M8260_SIMASK_IDMA4 (1<<7)
1075#define M8260_SIMASK_SDMA (1<<6)
1076#define M8260_SIMASK_TIMER1 (1<<4)
1077#define M8260_SIMASK_TIMER2 (1<<3)
1078#define M8260_SIMASK_TIMER3 (1<<2)
1079#define M8260_SIMASK_TIMER4 (1<<1)
1081#define M8260_SIUMCR_EARB (1<<31)
1082#define M8260_SIUMCR_EARP0 (0<<28)
1083#define M8260_SIUMCR_EARP1 (1<<28)
1084#define M8260_SIUMCR_EARP2 (2<<28)
1085#define M8260_SIUMCR_EARP3 (3<<28)
1086#define M8260_SIUMCR_EARP4 (4<<28)
1087#define M8260_SIUMCR_EARP5 (5<<28)
1088#define M8260_SIUMCR_EARP6 (6<<28)
1089#define M8260_SIUMCR_EARP7 (7<<28)
1090#define M8260_SIUMCR_DSHW (1<<23)
1091#define M8260_SIUMCR_DBGC0 (0<<21)
1092#define M8260_SIUMCR_DBGC1 (1<<21)
1093#define M8260_SIUMCR_DBGC2 (2<<21)
1094#define M8260_SIUMCR_DBGC3 (3<<21)
1095#define M8260_SIUMCR_DBPC0 (0<<19)
1096#define M8260_SIUMCR_DBPC1 (1<<19)
1097#define M8260_SIUMCR_DBPC2 (2<<19)
1098#define M8260_SIUMCR_DBPC3 (3<<19)
1099#define M8260_SIUMCR_FRC (1<<17)
1100#define M8260_SIUMCR_DLK (1<<16)
1101#define M8260_SIUMCR_PNCS (1<<15)
1102#define M8260_SIUMCR_OPAR (1<<14)
1103#define M8260_SIUMCR_DPC (1<<13)
1104#define M8260_SIUMCR_MPRE (1<<12)
1105#define M8260_SIUMCR_MLRC0 (0<<10)
1106#define M8260_SIUMCR_MLRC1 (1<<10)
1107#define M8260_SIUMCR_MLRC2 (2<<10)
1108#define M8260_SIUMCR_MLRC3 (3<<10)
1109#define M8260_SIUMCR_AEME (1<<9)
1110#define M8260_SIUMCR_SEME (1<<8)
1111#define M8260_SIUMCR_BSC (1<<7)
1112#define M8260_SIUMCR_GB5E (1<<6)
1113#define M8260_SIUMCR_B2DD (1<<5)
1114#define M8260_SIUMCR_B3DD (1<<4)
1126 uint8_t dpram1[16384];
1127 uint8_t cpm_pad0[16384];
1146 uint8_t pad_mcc1[124];
1148 uint16_t idma1_base;
1150 uint8_t pad_mcc2[124];
1152 uint16_t idma2_base;
1153 uint8_t pad_spi[252];
1155 uint16_t idma3_base;
1156 uint8_t pad_risc[224];
1157 uint8_t risc_timers[16];
1163 uint16_t idma4_base;
1164 uint8_t cpm_pad9[1282];
1166 uint8_t cpm_pad1[8192];
1172 uint8_t cpm_pad2[16384];
1180 uint8_t siu_pad0[6];
1182 uint8_t siu_pad1[20];
1185 uint8_t siu_pad4[3];
1189 uint8_t siu_pad5[3];
1198 uint8_t siu_pad2[3];
1201 uint8_t siu_pad3[163];
1208 uint8_t mem_pad0[8];
1210 uint8_t mem_pad1[4];
1215 uint8_t mem_pad2[4];
1217 uint8_t mem_pad5[2];
1219 uint8_t mem_pad3[4];
1223 uint8_t mem_pad6[3];
1225 uint8_t mem_pad7[3];
1227 uint8_t mem_pad8[3];
1229 uint8_t mem_pad9[3];
1231 uint8_t mem_pad4[84];
1237 uint8_t sit_pad0[32];
1239 uint8_t sit_pad6[2];
1243 uint8_t sit_pad2[16];
1245 uint8_t sit_pad5[2];
1248 uint8_t sit_pad3[94];
1249 uint8_t sit_pad4[2390];
1256 uint8_t ict_pad1[2];
1266 uint8_t ict_pad0[88];
1273 uint8_t clr_pad1[4];
1275 uint8_t clr_pad2[4];
1278 uint8_t clr_pad0[104];
1289 uint8_t iop_pad0[12];
1295 uint8_t iop_pad1[12];
1301 uint8_t iop_pad2[12];
1307 uint8_t iop_pad3[12];
1314 uint8_t cpt_pad0[3];
1316 uint8_t cpt_pad1[11];
1337 uint8_t cpt_pad2[608];
1344 uint8_t dma_pad0[3];
1346 uint8_t dma_pad1[3];
1349 uint8_t dma_pad2[3];
1351 uint8_t dma_pad3[3];
1353 uint8_t dma_pad4[3];
1355 uint8_t dma_pad5[3];
1357 uint8_t dma_pad6[3];
1359 uint8_t dma_pad7[3];
1361 uint8_t dma_pad8[3];
1363 uint8_t dma_pad9[707];
1373 uint8_t fcc_pad0[656];
1382 uint8_t brg_pad0[608];
1389 uint8_t i2m_pad0[3];
1391 uint8_t i2m_pad1[3];
1393 uint8_t i2m_pad2[3];
1395 uint8_t i2m_pad3[3];
1397 uint8_t i2m_pad4[3];
1399 uint8_t i2m_pad5[331];
1407 uint8_t cpm_pad3[14];
1412 uint8_t cpm_pad4[2];
1414 uint8_t cpm_pad5[12];
1446 uint8_t spi_pad0[4];
1448 uint8_t spi_pad1[3];
1450 uint8_t spi_pad2[2];
1452 uint8_t spi_pad3[82];
1459 uint8_t cmx_pad0[1];
1461 uint8_t cmx_pad1[1];
1465 uint8_t cmx_pad2[1];
1467 uint8_t cmx_pad3[16];
1478 uint8_t mcc_pad0[1152];
1483 uint8_t si1txram[512];
1484 uint8_t ram_pad0[512];
1485 uint8_t si1rxram[512];
1486 uint8_t ram_pad1[512];
1492 uint8_t si2txram[512];
1493 uint8_t ram_pad2[512];
1494 uint8_t si2rxram[512];
1495 uint8_t ram_pad3[512];
Definition: mpc8260.h:636
Definition: mpc8260.h:383
Definition: mpc8260.h:732
Definition: mpc8260.h:210
Definition: mpc8260.h:141
Definition: mpc8260.h:239
Definition: mpc8260.h:123
Definition: mpc8260.h:109
Definition: mpc8260.h:526
Definition: mpc8260.h:586
Definition: mpc8260.h:1121