RTEMS
6.1-rc1
bsps
shared
dev
serial
mc68681_p.h
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MC68681_P_H_
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#define _MC68681_P_H_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/*
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* Define MC68681_STATIC to nothing while debugging so the entry points
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* will show up in the symbol table.
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*/
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#define MC68681_STATIC
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/* #define MC68681_STATIC static */
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/*
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* mc68681 register offsets Read/Write Addresses
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*/
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#define MC68681_MODE_REG_1A 0
/* MR1A-MR Prior to Read */
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#define MC68681_MODE_REG_2A 0
/* MR2A-MR After Read */
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#define MC68681_COUNT_MODE_CURRENT_MSB 6
/* CTU */
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#define MC68681_COUNTER_TIMER_UPPER_REG 6
/* CTU */
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#define MC68681_COUNT_MODE_CURRENT_LSB 7
/* CTL */
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#define MC68681_COUNTER_TIMER_LOWER_REG 7
/* CTL */
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#define MC68681_INTERRUPT_VECTOR_REG 12
/* IVR */
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#define MC68681_MODE_REG_1B 8
/* MR1B-MR Prior to Read */
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#define MC68681_MODE_REG_2B 8
/* MR2BA-MR After Read */
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/*
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* mc68681 register offsets Read Only Addresses
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*/
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#define MC68681_STATUS_REG_A 1
/* SRA */
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#define MC68681_MASK_ISR_REG 2
/* MISR */
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#define MC68681_RECEIVE_BUFFER_A 3
/* RHRA */
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#define MC68681_INPUT_PORT_CHANGE_REG 4
/* IPCR */
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#define MC68681_INTERRUPT_STATUS_REG 5
/* ISR */
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#define MC68681_STATUS_REG_B 9
/* SRB */
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#define MC68681_RECEIVE_BUFFER_B 11
/* RHRB */
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#define MC68681_INPUT_PORT 13
/* IP */
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#define MC68681_START_COUNT_CMD 14
/* SCC */
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#define MC68681_STOP_COUNT_CMD 15
/* STC */
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/*
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* mc68681 register offsets Write Only Addresses
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*/
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#define MC68681_CLOCK_SELECT_REG_A 1
/* CSRA */
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#define MC68681_COMMAND_REG_A 2
/* CRA */
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#define MC68681_TRANSMIT_BUFFER_A 3
/* THRA */
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#define MC68681_AUX_CTRL_REG 4
/* ACR */
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#define MC68681_INTERRUPT_MASK_REG 5
/* IMR */
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#define MC68681_CLOCK_SELECT_REG_B 9
/* CSRB */
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#define MC68681_COMMAND_REG_B 10
/* CRB */
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#define MC68681_TRANSMIT_BUFFER_B 11
/* THRB */
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#define MC68681_OUTPUT_PORT_CONFIG_REG 13
/* OPCR */
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#define MC68681_OUTPUT_PORT_SET_REG 14
/* SOPBC */
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#define MC68681_OUTPUT_PORT_RESET_BITS 15
/* COPBC */
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/*
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* DUART Command Register Definitions:
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*
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* MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B
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*/
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#define MC68681_MODE_REG_ENABLE_RX 0x01
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#define MC68681_MODE_REG_DISABLE_RX 0x02
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#define MC68681_MODE_REG_ENABLE_TX 0x04
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#define MC68681_MODE_REG_DISABLE_TX 0x08
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#define MC68681_MODE_REG_RESET_MR_PTR 0x10
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#define MC68681_MODE_REG_RESET_RX 0x20
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#define MC68681_MODE_REG_RESET_TX 0x30
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#define MC68681_MODE_REG_RESET_ERROR 0x40
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#define MC68681_MODE_REG_RESET_BREAK 0x50
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#define MC68681_MODE_REG_START_BREAK 0x60
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#define MC68681_MODE_REG_STOP_BREAK 0x70
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#define MC68681_MODE_REG_SET_RX_BRG 0x80
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#define MC68681_MODE_REG_CLEAR_RX_BRG 0x90
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#define MC68681_MODE_REG_SET_TX_BRG 0xa0
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#define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0
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#define MC68681_MODE_REG_SET_STANDBY 0xc0
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#define MC68681_MODE_REG_SET_ACTIVE 0xd0
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/*
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* Mode Register Definitions
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*
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* MC68681_MODE_REG_1A
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* MC68681_MODE_REG_1B
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*/
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#define MC68681_5BIT_CHARS 0x00
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#define MC68681_6BIT_CHARS 0x01
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#define MC68681_7BIT_CHARS 0x02
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#define MC68681_8BIT_CHARS 0x03
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#define MC68681_ODD_PARITY 0x00
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#define MC68681_EVEN_PARITY 0x04
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#define MC68681_WITH_PARITY 0x00
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#define MC68681_FORCE_PARITY 0x08
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#define MC68681_NO_PARITY 0x10
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#define MC68681_MULTI_DROP 0x18
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#define MC68681_ERR_MODE_CHAR 0x00
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#define MC68681_ERR_MODE_BLOCK 0x20
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#define MC68681_RX_INTR_RX_READY 0x00
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#define MC68681_RX_INTR_FFULL 0x40
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#define MC68681_NO_RX_RTS_CTL 0x00
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#define MC68681_RX_RTS_CTRL 0x80
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/*
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* Mode Register Definitions
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*
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* MC68681_MODE_REG_2A
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* MC68681_MODE_REG_2B
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*/
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#define MC68681_STOP_BIT_LENGTH__563 0x00
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#define MC68681_STOP_BIT_LENGTH__625 0x01
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#define MC68681_STOP_BIT_LENGTH__688 0x02
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#define MC68681_STOP_BIT_LENGTH__75 0x03
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#define MC68681_STOP_BIT_LENGTH__813 0x04
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#define MC68681_STOP_BIT_LENGTH__875 0x05
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#define MC68681_STOP_BIT_LENGTH__938 0x06
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#define MC68681_STOP_BIT_LENGTH_1 0x07
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#define MC68681_STOP_BIT_LENGTH_1_563 0x08
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#define MC68681_STOP_BIT_LENGTH_1_625 0x09
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#define MC68681_STOP_BIT_LENGTH_1_688 0x0a
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#define MC68681_STOP_BIT_LENGTH_1_75 0x0b
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#define MC68681_STOP_BIT_LENGTH_1_813 0x0c
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#define MC68681_STOP_BIT_LENGTH_1_875 0x0d
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#define MC68681_STOP_BIT_LENGTH_1_938 0x0e
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#define MC68681_STOP_BIT_LENGTH_2 0x0f
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#define MC68681_CTS_ENABLE_TX 0x10
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#define MC68681_TX_RTS_CTRL 0x20
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#define MC68681_CHANNEL_MODE_NORMAL 0x00
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#define MC68681_CHANNEL_MODE_ECHO 0x40
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#define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80
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#define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0
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/*
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* Status Register Definitions
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*
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* MC68681_STATUS_REG_A, MC68681_STATUS_REG_B
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*/
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#define MC68681_RX_READY 0x01
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#define MC68681_FFULL 0x02
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#define MC68681_TX_READY 0x04
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#define MC68681_TX_EMPTY 0x08
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#define MC68681_OVERRUN_ERROR 0x10
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#define MC68681_PARITY_ERROR 0x20
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#define MC68681_FRAMING_ERROR 0x40
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#define MC68681_RECEIVED_BREAK 0x80
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#define MC68681_RX_ERRORS \
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(MC68681_OVERRUN_ERROR|MC68681_PARITY_ERROR| \
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MC68681_FRAMING_ERROR|MC68681_RECEIVED_BREAK)
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/*
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* Interupt Status Register Definitions.
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*
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* MC68681_INTERRUPT_STATUS_REG
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*/
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/*
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* Interupt Mask Register Definitions
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*
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* MC68681_INTERRUPT_MASK_REG
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*/
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/* These are passed to mc68681_build_imr */
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#define MC68681_IR_TX_READY 0x01
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#define MC68681_IR_RX_READY 0x02
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#define MC68681_IR_BREAK 0x04
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#define MC68681_IMR_ENABLE_ALL 0x07
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#define MC68681_IMR_DISABLE_ALL 0x00
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#define MC68681_IMR_ENABLE_ALL_EXCEPT_TX 0x06
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#define MC68681_IR_TX_READY_A 0x01
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#define MC68681_IR_RX_READY_A 0x02
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#define MC68681_IR_BREAK_A 0x04
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#define MC68681_IR_COUNTER_READY 0x08
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#define MC68681_IR_TX_READY_B 0x10
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#define MC68681_IR_RX_READY_B 0x20
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#define MC68681_IR_BREAK_B 0x40
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#define MC68681_IR_INPUT_PORT_CHANGE 0x80
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/*
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* Status Register Definitions.
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*
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* MC68681_STATUS_REG_A,MC68681_STATUS_REG_B
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*/
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#define MC68681_STATUS_RXRDY 0x01
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#define MC68681_STATUS_FFULL 0x02
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#define MC68681_STATUS_TXRDY 0x04
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#define MC68681_STATUS_TXEMT 0x08
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#define MC68681_STATUS_OVERRUN_ERROR 0x10
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#define MC68681_STATUS_PARITY_ERROR 0x20
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#define MC68681_STATUS_FRAMING_ERROR 0x40
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#define MC68681_STATUS_RECEIVED_BREAK 0x80
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/*
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* Definitions for the Interrupt Vector Register:
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*
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* MC68681_INTERRUPT_VECTOR_REG
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*/
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#define MC68681_INTERRUPT_VECTOR_INIT 0x0f
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/*
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* Definitions for the Auxiliary Control Register
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*
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* MC68681_AUX_CTRL_REG
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*/
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#define MC68681_AUX_BRG_SET1 0x00
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#define MC68681_AUX_BRG_SET2 0x80
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/*
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* Per chip context control
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*/
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typedef
struct
_mc68681_context
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{
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int
mate;
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unsigned
char
imr;
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}
mc68681_context
;
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/*
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* Driver functions
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*/
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MC68681_STATIC
void
mc68681_initialize_context(
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int
minor,
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mc68681_context
*pmc68681Context
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);
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MC68681_STATIC
bool
mc68681_probe(
int
minor);
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MC68681_STATIC
int
mc68681_set_attributes(
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int
minor,
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const
struct
termios *t
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);
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MC68681_STATIC
void
mc68681_init(
int
minor);
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MC68681_STATIC
int
mc68681_open(
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int
major,
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int
minor,
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void
* arg
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);
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MC68681_STATIC
int
mc68681_close(
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int
major,
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int
minor,
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void
* arg
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);
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MC68681_STATIC
void
mc68681_write_polled(
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int
minor,
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char
cChar
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);
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MC68681_STATIC
void
mc68681_initialize_interrupts(
int
minor);
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MC68681_STATIC ssize_t mc68681_write_support_int(
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int
minor,
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const
char
*buf,
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size_t
len
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);
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MC68681_STATIC ssize_t mc68681_write_support_polled(
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int
minor,
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const
char
*buf,
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size_t
len
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);
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MC68681_STATIC
int
mc68681_inbyte_nonblocking_polled(
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int
minor
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);
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MC68681_STATIC
unsigned
int
mc68681_build_imr(
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int
minor,
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int
enable_flag
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);
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MC68681_STATIC
void
mc68681_process(
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int
minor
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);
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MC68681_STATIC
void
mc68681_enable_interrupts(
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int
minor,
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int
imr_mask
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);
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MC68681_STATIC
rtems_isr
mc68681_isr(
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rtems_vector_number
vector
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);
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#ifdef __cplusplus
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}
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#endif
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#endif
/* _MC68681_P_H_ */
rtems_isr
ISR_Handler rtems_isr
This type defines the return type of interrupt service routines.
Definition:
intr.h:123
rtems_vector_number
ISR_Vector_number rtems_vector_number
This integer type represents interrupt vector numbers.
Definition:
intr.h:102
_mc68681_context
Definition:
mc68681_p.h:263
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