RTEMS 6.1-rc1
leon.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
25/*
26 * COPYRIGHT (c) 1989-1998.
27 * On-Line Applications Research Corporation (OAR).
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 * 1. Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
42 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
43 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
44 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
45 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
46 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
47 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
48 * POSSIBILITY OF SUCH DAMAGE.
49 *
50 * Ported to LEON implementation of the SPARC by On-Line Applications
51 * Research Corporation (OAR) under contract to the European Space
52 * Agency (ESA).
53 *
54 * LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
55 * European Space Agency.
56 */
57
58#ifndef _INCLUDE_LEON_h
59#define _INCLUDE_LEON_h
60
61#include <rtems/score/sparc.h>
62
63#ifdef __cplusplus
64extern "C" {
65#endif
66
67/*
68 * Interrupt Sources
69 *
70 * The interrupt source numbers directly map to the trap type and to
71 * the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
72 * and the Interrupt Pending Registers.
73 */
74
75#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1
76#define LEON_INTERRUPT_UART_2_RX_TX 2
77#define LEON_INTERRUPT_UART_1_RX_TX 3
78#define LEON_INTERRUPT_EXTERNAL_0 4
79#define LEON_INTERRUPT_EXTERNAL_1 5
80#define LEON_INTERRUPT_EXTERNAL_2 6
81#define LEON_INTERRUPT_EXTERNAL_3 7
82#define LEON_INTERRUPT_TIMER1 8
83#define LEON_INTERRUPT_TIMER2 9
84#define LEON_INTERRUPT_EMPTY1 10
85#define LEON_INTERRUPT_EMPTY2 11
86#define LEON_INTERRUPT_EMPTY3 12
87#define LEON_INTERRUPT_EMPTY4 13
88#define LEON_INTERRUPT_EMPTY5 14
89#define LEON_INTERRUPT_EMPTY6 15
90
91#ifndef ASM
92
93/*
94 * Trap Types for on-chip peripherals
95 *
96 * Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
97 *
98 * NOTE: The priority level for each source corresponds to the least
99 * significant nibble of the trap type.
100 */
101
102#define LEON_TRAP_TYPE( _source ) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source )
103
104#define LEON_TRAP_SOURCE( _trap ) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap )
105
106#define LEON_INT_TRAP( _trap ) SPARC_IS_INTERRUPT_TRAP( _trap )
107
108/*
109 * Structure for LEON memory mapped registers.
110 *
111 * Source: Section 6.1 - On-chip registers
112 *
113 * NOTE: There is only one of these structures per CPU, its base address
114 * is 0x80000000, and the variable LEON_REG is placed there by the
115 * linkcmds file.
116 */
117
118typedef struct {
119 volatile unsigned int Memory_Config_1;
120 volatile unsigned int Memory_Config_2;
121 volatile unsigned int Edac_Control;
122 volatile unsigned int Failed_Address;
123 volatile unsigned int Memory_Status;
124 volatile unsigned int Cache_Control;
125 volatile unsigned int Power_Down;
126 volatile unsigned int Write_Protection_1;
127 volatile unsigned int Write_Protection_2;
128 volatile unsigned int Leon_Configuration;
129 volatile unsigned int dummy2;
130 volatile unsigned int dummy3;
131 volatile unsigned int dummy4;
132 volatile unsigned int dummy5;
133 volatile unsigned int dummy6;
134 volatile unsigned int dummy7;
135 volatile unsigned int Timer_Counter_1;
136 volatile unsigned int Timer_Reload_1;
137 volatile unsigned int Timer_Control_1;
138 volatile unsigned int Watchdog;
139 volatile unsigned int Timer_Counter_2;
140 volatile unsigned int Timer_Reload_2;
141 volatile unsigned int Timer_Control_2;
142 volatile unsigned int dummy8;
143 volatile unsigned int Scaler_Counter;
144 volatile unsigned int Scaler_Reload;
145 volatile unsigned int dummy9;
146 volatile unsigned int dummy10;
147 volatile unsigned int UART_Channel_1;
148 volatile unsigned int UART_Status_1;
149 volatile unsigned int UART_Control_1;
150 volatile unsigned int UART_Scaler_1;
151 volatile unsigned int UART_Channel_2;
152 volatile unsigned int UART_Status_2;
153 volatile unsigned int UART_Control_2;
154 volatile unsigned int UART_Scaler_2;
155 volatile unsigned int Interrupt_Mask;
156 volatile unsigned int Interrupt_Pending;
157 volatile unsigned int Interrupt_Force;
158 volatile unsigned int Interrupt_Clear;
159 volatile unsigned int PIO_Data;
160 volatile unsigned int PIO_Direction;
161 volatile unsigned int PIO_Interrupt;
162} LEON_Register_Map;
163
164#endif
165
166/*
167 * The following constants are intended to be used ONLY in assembly
168 * language files.
169 *
170 * NOTE: The intended style of usage is to load the address of LEON REGS
171 * into a register and then use these as displacements from
172 * that register.
173 */
174
175#ifdef ASM
176
177#define LEON_REG_MEMCFG1_OFFSET 0x00
178#define LEON_REG_MEMCFG2_OFFSET 0x04
179#define LEON_REG_EDACCTRL_OFFSET 0x08
180#define LEON_REG_FAILADDR_OFFSET 0x0C
181#define LEON_REG_MEMSTATUS_OFFSET 0x10
182#define LEON_REG_CACHECTRL_OFFSET 0x14
183#define LEON_REG_POWERDOWN_OFFSET 0x18
184#define LEON_REG_WRITEPROT1_OFFSET 0x1C
185#define LEON_REG_WRITEPROT2_OFFSET 0x20
186#define LEON_REG_LEONCONF_OFFSET 0x24
187#define LEON_REG_UNIMPLEMENTED_2_OFFSET 0x28
188#define LEON_REG_UNIMPLEMENTED_3_OFFSET 0x2C
189#define LEON_REG_UNIMPLEMENTED_4_OFFSET 0x30
190#define LEON_REG_UNIMPLEMENTED_5_OFFSET 0x34
191#define LEON_REG_UNIMPLEMENTED_6_OFFSET 0x38
192#define LEON_REG_UNIMPLEMENTED_7_OFFSET 0x3C
193#define LEON_REG_TIMERCNT1_OFFSET 0x40
194#define LEON_REG_TIMERLOAD1_OFFSET 0x44
195#define LEON_REG_TIMERCTRL1_OFFSET 0x48
196#define LEON_REG_WDOG_OFFSET 0x4C
197#define LEON_REG_TIMERCNT2_OFFSET 0x50
198#define LEON_REG_TIMERLOAD2_OFFSET 0x54
199#define LEON_REG_TIMERCTRL2_OFFSET 0x58
200#define LEON_REG_UNIMPLEMENTED_8_OFFSET 0x5C
201#define LEON_REG_SCALERCNT_OFFSET 0x60
202#define LEON_REG_SCALER_LOAD_OFFSET 0x64
203#define LEON_REG_UNIMPLEMENTED_9_OFFSET 0x68
204#define LEON_REG_UNIMPLEMENTED_10_OFFSET 0x6C
205#define LEON_REG_UARTDATA1_OFFSET 0x70
206#define LEON_REG_UARTSTATUS1_OFFSET 0x74
207#define LEON_REG_UARTCTRL1_OFFSET 0x78
208#define LEON_REG_UARTSCALER1_OFFSET 0x7C
209#define LEON_REG_UARTDATA2_OFFSET 0x80
210#define LEON_REG_UARTSTATUS2_OFFSET 0x84
211#define LEON_REG_UARTCTRL2_OFFSET 0x88
212#define LEON_REG_UARTSCALER2_OFFSET 0x8C
213#define LEON_REG_IRQMASK_OFFSET 0x90
214#define LEON_REG_IRQPEND_OFFSET 0x94
215#define LEON_REG_IRQFORCE_OFFSET 0x98
216#define LEON_REG_IRQCLEAR_OFFSET 0x9C
217#define LEON_REG_PIODATA_OFFSET 0xA0
218#define LEON_REG_PIODIR_OFFSET 0xA4
219#define LEON_REG_PIOIRQ_OFFSET 0xA8
220#define LEON_REG_SIM_RAM_SIZE_OFFSET 0xF4
221#define LEON_REG_SIM_ROM_SIZE_OFFSET 0xF8
222
223#endif
224
225/*
226 * The following defines the bits in Memory Configuration Register 1.
227 */
228
229#define LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000
230
231/*
232 * The following defines the bits in Memory Configuration Register 1.
233 */
234
235#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00
236
237
238/*
239 * The following defines the bits in the Timer Control Register.
240 */
241
242#define LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */
243 /* 0 = hold scalar and counter */
244#define LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */
245 /* 0 = stop at 0 */
246#define LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */
247 /* 0 = no function */
248
249/*
250 * The following defines the bits in the UART Control Registers.
251 *
252 */
253
254#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
255
256/*
257 * The following defines the bits in the LEON UART Status Registers.
258 */
259
260#define LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */
261#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
262#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
263#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
264#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
265#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
266#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
267#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
268#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
269
270
271/*
272 * The following defines the bits in the LEON UART Status Registers.
273 */
274
275#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
276#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
277#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
278#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
279#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
280#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
281#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
282#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
283
284#ifndef ASM
285
286/*
287 * This is used to manipulate the on-chip registers.
288 *
289 * The following symbol must be defined in the linkcmds file and point
290 * to the correct location.
291 */
292
293extern LEON_Register_Map LEON_REG;
294
295/*
296 * Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
297 * and the Interrupt Pending Registers.
298 *
299 * NOTE: For operations which are not atomic, this code disables interrupts
300 * to guarantee there are no intervening accesses to the same register.
301 * The operations which read the register, modify the value and then
302 * store the result back are vulnerable.
303 */
304
305#define LEON_Clear_interrupt( _source ) \
306 do { \
307 LEON_REG.Interrupt_Clear = (1 << (_source)); \
308 } while (0)
309
310#define LEON_Force_interrupt( _source ) \
311 do { \
312 uint32_t _level; \
313 \
314 _level = sparc_disable_interrupts(); \
315 LEON_REG.Interrupt_Force |= (1 << (_source)); \
316 sparc_enable_interrupts( _level ); \
317 } while (0)
318
319#define LEON_Is_interrupt_pending( _source ) \
320 (LEON_REG.Interrupt_Pending & (1 << (_source)))
321
322#define LEON_Is_interrupt_masked( _source ) \
323 (!(LEON_REG.Interrupt_Mask & (1 << (_source))))
324
325#define LEON_Mask_interrupt( _source ) \
326 do { \
327 uint32_t _level; \
328 \
329 _level = sparc_disable_interrupts(); \
330 LEON_REG.Interrupt_Mask &= ~(1 << (_source)); \
331 sparc_enable_interrupts( _level ); \
332 } while (0)
333
334#define LEON_Unmask_interrupt( _source ) \
335 do { \
336 uint32_t _level; \
337 \
338 _level = sparc_disable_interrupts(); \
339 LEON_REG.Interrupt_Mask |= (1 << (_source)); \
340 sparc_enable_interrupts( _level ); \
341 } while (0)
342
343#define LEON_Disable_interrupt( _source, _previous ) \
344 do { \
345 uint32_t _level; \
346 uint32_t _mask = 1 << (_source); \
347 \
348 _level = sparc_disable_interrupts(); \
349 (_previous) = LEON_REG.Interrupt_Mask; \
350 LEON_REG.Interrupt_Mask = _previous & ~_mask; \
351 sparc_enable_interrupts( _level ); \
352 (_previous) &= _mask; \
353 } while (0)
354
355#define LEON_Restore_interrupt( _source, _previous ) \
356 do { \
357 uint32_t _level; \
358 uint32_t _mask = 1 << (_source); \
359 \
360 _level = sparc_disable_interrupts(); \
361 LEON_REG.Interrupt_Mask = \
362 (LEON_REG.Interrupt_Mask & ~_mask) | (_previous); \
363 sparc_enable_interrupts( _level ); \
364 } while (0)
365
366/* Make all SPARC BSPs have common macros for interrupt handling */
367#define BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source)
368#define BSP_Force_interrupt(_source) LEON_Force_interrupt(_source)
369#define BSP_Clear_forced_interrupt( _source ) \
370 do { \
371 uint32_t _level; \
372 \
373 _level = sparc_disable_interrupts(); \
374 LEON_REG.Interrupt_Force &= ~(1 << (_source)); \
375 sparc_enable_interrupts( _level ); \
376 } while (0)
377#define BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source)
378#define BSP_Is_interrupt_forced(_source) \
379 (LEON_REG.Interrupt_Force & (1 << (_source)))
380#define BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source)
381#define BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source)
382#define BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source)
383#define BSP_Disable_interrupt(_source, _previous) \
384 LEON_Disable_interrupt(_source, _prev)
385#define BSP_Restore_interrupt(_source, _previous) \
386 LEON_Restore_interrupt(_source, _previous)
387
388/* Make all SPARC BSPs have common macros for interrupt handling on any CPU */
389#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
390 BSP_Is_interrupt_masked(_source)
391#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
392 BSP_Unmask_interrupt(_source)
393#define BSP_Cpu_Mask_interrupt(_source, _cpu) \
394 BSP_Mask_interrupt(_source)
395#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
396 BSP_Disable_interrupt(_source, _prev)
397#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
398 BSP_Cpu_Restore_interrupt(_source, _previous)
399
400/*
401 * Each timer control register is organized as follows:
402 *
403 * D0 - Enable
404 * 1 = enable counting
405 * 0 = hold scaler and counter
406 *
407 * D1 - Counter Reload
408 * 1 = reload counter at zero and restart
409 * 0 = stop counter at zero
410 *
411 * D2 - Counter Load
412 * 1 = load counter with preset value
413 * 0 = no function
414 *
415 */
416
417#define LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002
418#define LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
419
420#define LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004
421
422#define LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001
423#define LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
424
425#define LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002
426#define LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001
427
428#define LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003
429#define LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003
430
431/* Load 32-bit word by forcing a cache-miss */
432static inline unsigned int leon_r32_no_cache(uintptr_t addr)
433{
434 unsigned int tmp;
435 __asm__ volatile (" lda [%1] 1, %0\n" : "=r"(tmp) : "r"(addr));
436 return tmp;
437}
438
439#endif /* !ASM */
440
441#ifdef __cplusplus
442}
443#endif
444
445#endif /* !_INCLUDE_LEON_h */
446
__asm__
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
sparc.h
This header file provides information required to build RTEMS for a particular member of the SPARC fa...
LEON_Register_Map
Definition: leon.h:118
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