RTEMS 6.1-rc1
l2c.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * GRLIB L2CACHE Driver
5 *
6 * COPYRIGHT (c) 2017
7 * Cobham Gaisler AB
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 * OVERVIEW
31 * ========
32 * This driver controls the L2CACHE device located
33 * at an on-chip AMBA.
34 */
35
36#ifndef __L2CACHE_H__
37#define __L2CACHE_H__
38
39#include <stdint.h>
40#include <stdio.h>
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46extern void l2cache_register_drv(void);
47
48#define L2CACHE_ERR_OK 0
49#define L2CACHE_ERR_NOINIT -1
50#define L2CACHE_ERR_EINVAL -2
51#define L2CACHE_ERR_TOOMANY -3
52#define L2CACHE_ERR_ERROR -4
53
54/* L2C Flush options */
55#define L2CACHE_OPTIONS_FLUSH_WAIT (0x1 << 2)
56#define L2CACHE_OPTIONS_FLUSH_INVALIDATE (0x3 << 0)
57#define L2CACHE_OPTIONS_FLUSH_WRITEBACK (0x2 << 0)
58#define L2CACHE_OPTIONS_FLUSH_INV_WBACK (0x1 << 0)
59#define L2CACHE_OPTIONS_FLUSH_NONE (0 << 0)
60
61/* L2C Status */
62#define L2CACHE_STATUS_ENABLED 1
63#define L2CACHE_STATUS_SPLIT_ENABLED (0x1 << 1)
64#define L2CACHE_STATUS_EDAC_ENABLED (0x1 << 2)
65#define L2CACHE_STATUS_REPL (0x3 << L2CACHE_STATUS_REPL_BIT)
66#define L2CACHE_STATUS_REPL_BIT 3
67#define L2CACHE_STATUS_WRITETHROUGH (0x1 << 5)
68#define L2CACHE_STATUS_LOCK (0xf << L2CACHE_STATUS_LOCK_BIT)
69#define L2CACHE_STATUS_LOCK_BIT 6
70#define L2CACHE_STATUS_SCRUB_ENABLED (0x1 << 10)
71#define L2CACHE_STATUS_INT (0xf << L2CACHE_STATUS_INT_BIT)
72#define L2CACHE_STATUS_INT_BIT 11
73#define L2CACHE_STATUS_INT_BCKEND (0x1 << 11)
74#define L2CACHE_STATUS_INT_WPHIT (0x1 << 12)
75#define L2CACHE_STATUS_INT_UEE (0x1 << 13)
76#define L2CACHE_STATUS_INT_CEE (0x1 << 14)
77#define L2CACHE_STATUS_SCRUB_DELAY (0xffff << L2CACHE_STATUS_SCRUB_DELAY_BIT)
78#define L2CACHE_STATUS_SCRUB_DELAY_BIT 15
79#define L2CACHE_STATUS_SIGN_BIT 31
80
81/* status helper macros */
82#define L2CACHE_ENABLED(status) (status & L2CACHE_STATUS_ENABLED)
83#define L2CACHE_DISABLED(status) (!(status & L2CACHE_STATUS_ENABLED))
84#define L2CACHE_SPLIT_ENABLED(status) (status & L2CACHE_STATUS_SPLIT_ENABLED)
85#define L2CACHE_SPLIT_DISABLED(status) \
86 (!(status & L2CACHE_STATUS_SPLIT_ENABLED))
87#define L2CACHE_EDAC_ENABLED(status) (status & L2CACHE_STATUS_EDAC_ENABLED)
88#define L2CACHE_EDAC_DISABLED(status) (!(status & L2CACHE_STATUS_EDAC_ENABLED))
89#define L2CACHE_REPL(status) \
90 ((status & L2CACHE_STATUS_REPL) >> L2CACHE_STATUS_REPL_BIT)
91#define L2CACHE_WRITETHROUGH(status) (status & L2CACHE_STATUS_WRITETHROUGH)
92#define L2CACHE_WRITEBACK(status) (!(status & L2CACHE_STATUS_WRITETHROUGH))
93#define L2CACHE_LOCKED_WAYS(status) \
94 ((status & L2CACHE_STATUS_LOCK) >> L2CACHE_STATUS_LOCK_BIT)
95#define L2CACHE_SCRUB_ENABLED(status) (status & L2CACHE_STATUS_SCRUB_ENABLED)
96#define L2CACHE_SCRUB_DISABLED(status) \
97 (!(status & L2CACHE_STATUS_SCRUB_ENABLED))
98#define L2CACHE_SCRUB_DELAY(status) \
99 ((status & L2CACHE_STATUS_SCRUB_DELAY) >> L2CACHE_STATUS_SCRUB_DELAY_BIT)
100#define L2CACHE_INT_ENABLED(status) (status & L2CACHE_STATUS_INT)
101#define L2CACHE_INT_DISABLED(status) (!(status & L2CACHE_STATUS_INT))
102extern int l2cache_status(void);
103
104/* L2C Setup */
105extern int l2cache_enable(int flush);
106extern int l2cache_disable(int flush);
107
108extern int l2cache_split_enable(void);
109extern int l2cache_split_disable(void);
110
111extern int l2cache_edac_enable(int flush);
112extern int l2cache_edac_disable(int flush);
113
114extern int l2cache_scrub_enable(int delay);
115extern int l2cache_scrub_disable(void);
116extern int l2cache_scrub_line(int way, int index);
117
118extern int l2cache_writethrough(int flush);
119extern int l2cache_writeback(int flush);
120
121#define L2CACHE_OPTIONS_REPL_INDEX_WAY_BIT (2)
122#define L2CACHE_OPTIONS_REPL_MASTERIDX_MOD (3 << 0)
123#define L2CACHE_OPTIONS_REPL_MASTERIDX_IDX (2 << 0)
124#define L2CACHE_OPTIONS_REPL_RANDOM (1 << 0)
125#define L2CACHE_OPTIONS_REPL_LRU (0 << 0)
126extern int l2cache_replacement(int options, int flush);
127
128/* L2C Flush */
129extern int l2cache_flush(int flush);
130extern int l2cache_flush_address(uint32_t addr, int size, int flush);
131extern int l2cache_flush_line(int way, int index, int flush);
132extern int l2cache_flush_way(int way, int flush);
133
134/* L2C Lock way */
135#define L2CACHE_OPTIONS_DIRTY (0x1 << 2)
136#define L2CACHE_OPTIONS_VALID (0x1 << 1)
137#define L2CACHE_OPTIONS_FETCH (0x1 << 0)
138#define L2CACHE_OPTIONS_DISABLE 2
139#define L2CACHE_OPTIONS_ENABLE 1
140#define L2CACHE_OPTIONS_NONE 0
141extern int l2cache_lock_way(uint32_t tag, int options, int flush, int enable);
142extern int l2cache_unlock(void);
143
144/* L2C Fill a way */
145extern int l2cache_fill_way(int way, uint32_t tag, int options, int flush);
146
147/* L2C MTRR */
148#define L2CACHE_OPTIONS_MTRR_ACCESS_WRITETHROUGH (0x1 << 2)
149#define L2CACHE_OPTIONS_MTRR_ACCESS_UNCACHED (0x0 << 2)
150#define L2CACHE_OPTIONS_MTRR_WRITEPROT_ENABLE (0x1 << 1)
151#define L2CACHE_OPTIONS_MTRR_WRITEPROT_DISABLE (0x0 << 1)
152extern int l2cache_mtrr_enable(int id, uint32_t addr, uint32_t mask,
153 int options, int flush);
154extern int l2cache_mtrr_disable(int id);
155
156/* L2C Debug print */
157extern int l2cache_print(void);
158
159/* L2C Interrupts */
160/* Function Interrupt-Code ISR callback prototype.
161 * arg - Custom arg provided by user
162 * addr - Cacheline addr that generated the error
163 * status - Error status register of the L2CACHE core
164 */
165typedef void (*l2cache_isr_t)(void *arg, uint32_t addr, uint32_t status);
166#define L2CACHE_INTERRUPT_ALL (0xf << 0)
167#define L2CACHE_INTERRUPT_BACKENDERROR (0x1 << 3)
168#define L2CACHE_INTERRUPT_WPROTHIT (0x1 << 2)
169#define L2CACHE_INTERRUPT_UNCORRERROR (0x1 << 1)
170#define L2CACHE_INTERRUPT_CORRERROR (0x1 << 0)
171extern int l2cache_isr_register( l2cache_isr_t isr, void * arg, int options);
172extern int l2cache_isr_unregister(void);
173extern int l2cache_interrupt_mask(int options);
174extern int l2cache_interrupt_unmask(int options);
175
176/* L2C error interface */
177#define L2CACHE_STATUS_MULTIPLEERRORS 2
178#define L2CACHE_STATUS_NEWERROR 1
179#define L2CACHE_STATUS_NOERROR 0
180extern int l2cache_error_status(uint32_t * addr, uint32_t * status);
181
182/*#define TEST_L2CACHE*/
183#ifdef TEST_L2CACHE
184/* Used for internal testing */
185/*
186 * L2CACHE Tag private data struture
187 */
188struct l2cache_tag {
189 uint32_t tag;
190 int valid;
191 int dirty;
192 int lru;
193};
194
195/*
196 * L2CACHE Line private data struture
197 */
198struct l2cache_dataline {
199 uint32_t data[16];
200 int words;
201};
202extern int l2cache_get_index( uint32_t addr);
203extern uint32_t l2cache_get_tag( uint32_t addr);
204
205extern int l2cache_diag_tag( int way, int index, struct l2cache_tag * tag);
206extern int l2cache_diag_line( int way, int index,
207 struct l2cache_dataline * dataline);
208
209#define L2CACHE_HIT 1
210#define L2CACHE_MISS 0
211extern int l2cache_lookup(uint32_t addr, int * way);
212
213extern int l2cache_error_inject_address( uint32_t addr, uint32_t mask);
214#endif /* TEST_L2CACHE */
215
216#ifdef __cplusplus
217}
218#endif
219
220#endif /* __L2CACHE_H__ */
size
unsigned size
Definition: tte.h:1
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