RTEMS 6.1-rc1
irqamp-regs.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2021 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36/*
37 * This file is part of the RTEMS quality process and was automatically
38 * generated. If you find something that needs to be fixed or
39 * worded better please post a report or patch to an RTEMS mailing list
40 * or raise a bug report:
41 *
42 * https://www.rtems.org/bugs.html
43 *
44 * For information on updating and regenerating please refer to the How-To
45 * section in the Software Requirements Engineering chapter of the
46 * RTEMS Software Engineering manual. The manual is provided as a part of
47 * a release. For development sources please refer to the online
48 * documentation at:
49 *
50 * https://docs.rtems.org
51 */
52
53/* Generated from spec:/dev/grlib/if/irqamp-header */
54
55#ifndef _GRLIB_IRQAMP_REGS_H
56#define _GRLIB_IRQAMP_REGS_H
57
58#include <stdint.h>
59
60#ifdef __cplusplus
61extern "C" {
62#endif
63
64/* Generated from spec:/dev/grlib/if/irqamp-timestamp */
65
85#define IRQAMP_ITCNT_TCNT_SHIFT 0
86#define IRQAMP_ITCNT_TCNT_MASK 0xffffffffU
87#define IRQAMP_ITCNT_TCNT_GET( _reg ) \
88 ( ( ( _reg ) & IRQAMP_ITCNT_TCNT_MASK ) >> \
89 IRQAMP_ITCNT_TCNT_SHIFT )
90#define IRQAMP_ITCNT_TCNT_SET( _reg, _val ) \
91 ( ( ( _reg ) & ~IRQAMP_ITCNT_TCNT_MASK ) | \
92 ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \
93 IRQAMP_ITCNT_TCNT_MASK ) )
94#define IRQAMP_ITCNT_TCNT( _val ) \
95 ( ( ( _val ) << IRQAMP_ITCNT_TCNT_SHIFT ) & \
96 IRQAMP_ITCNT_TCNT_MASK )
97
109#define IRQAMP_ITSTMPC_TSTAMP_SHIFT 27
110#define IRQAMP_ITSTMPC_TSTAMP_MASK 0xf8000000U
111#define IRQAMP_ITSTMPC_TSTAMP_GET( _reg ) \
112 ( ( ( _reg ) & IRQAMP_ITSTMPC_TSTAMP_MASK ) >> \
113 IRQAMP_ITSTMPC_TSTAMP_SHIFT )
114#define IRQAMP_ITSTMPC_TSTAMP_SET( _reg, _val ) \
115 ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSTAMP_MASK ) | \
116 ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \
117 IRQAMP_ITSTMPC_TSTAMP_MASK ) )
118#define IRQAMP_ITSTMPC_TSTAMP( _val ) \
119 ( ( ( _val ) << IRQAMP_ITSTMPC_TSTAMP_SHIFT ) & \
120 IRQAMP_ITSTMPC_TSTAMP_MASK )
121
122#define IRQAMP_ITSTMPC_S1 0x4000000U
123
124#define IRQAMP_ITSTMPC_S2 0x2000000U
125
126#define IRQAMP_ITSTMPC_KS 0x20U
127
128#define IRQAMP_ITSTMPC_TSISEL_SHIFT 0
129#define IRQAMP_ITSTMPC_TSISEL_MASK 0x1fU
130#define IRQAMP_ITSTMPC_TSISEL_GET( _reg ) \
131 ( ( ( _reg ) & IRQAMP_ITSTMPC_TSISEL_MASK ) >> \
132 IRQAMP_ITSTMPC_TSISEL_SHIFT )
133#define IRQAMP_ITSTMPC_TSISEL_SET( _reg, _val ) \
134 ( ( ( _reg ) & ~IRQAMP_ITSTMPC_TSISEL_MASK ) | \
135 ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \
136 IRQAMP_ITSTMPC_TSISEL_MASK ) )
137#define IRQAMP_ITSTMPC_TSISEL( _val ) \
138 ( ( ( _val ) << IRQAMP_ITSTMPC_TSISEL_SHIFT ) & \
139 IRQAMP_ITSTMPC_TSISEL_MASK )
140
152#define IRQAMP_ITSTMPAS_TASSERTION_SHIFT 0
153#define IRQAMP_ITSTMPAS_TASSERTION_MASK 0xffffffffU
154#define IRQAMP_ITSTMPAS_TASSERTION_GET( _reg ) \
155 ( ( ( _reg ) & IRQAMP_ITSTMPAS_TASSERTION_MASK ) >> \
156 IRQAMP_ITSTMPAS_TASSERTION_SHIFT )
157#define IRQAMP_ITSTMPAS_TASSERTION_SET( _reg, _val ) \
158 ( ( ( _reg ) & ~IRQAMP_ITSTMPAS_TASSERTION_MASK ) | \
159 ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \
160 IRQAMP_ITSTMPAS_TASSERTION_MASK ) )
161#define IRQAMP_ITSTMPAS_TASSERTION( _val ) \
162 ( ( ( _val ) << IRQAMP_ITSTMPAS_TASSERTION_SHIFT ) & \
163 IRQAMP_ITSTMPAS_TASSERTION_MASK )
164
176#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT 0
177#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK 0xffffffffU
178#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_GET( _reg ) \
179 ( ( ( _reg ) & IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) >> \
180 IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT )
181#define IRQAMP_ITSTMPAC_TACKNOWLEDGE_SET( _reg, _val ) \
182 ( ( ( _reg ) & ~IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) | \
183 ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \
184 IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK ) )
185#define IRQAMP_ITSTMPAC_TACKNOWLEDGE( _val ) \
186 ( ( ( _val ) << IRQAMP_ITSTMPAC_TACKNOWLEDGE_SHIFT ) & \
187 IRQAMP_ITSTMPAC_TACKNOWLEDGE_MASK )
188
195typedef struct irqamp_timestamp {
199 uint32_t itcnt;
200
204 uint32_t itstmpc;
205
209 uint32_t itstmpas;
210
214 uint32_t itstmpac;
215} irqamp_timestamp;
216
219/* Generated from spec:/dev/grlib/if/irqamp */
220
239#define IRQAMP_ILEVEL_IL_15_1_SHIFT 1
240#define IRQAMP_ILEVEL_IL_15_1_MASK 0xfffeU
241#define IRQAMP_ILEVEL_IL_15_1_GET( _reg ) \
242 ( ( ( _reg ) & IRQAMP_ILEVEL_IL_15_1_MASK ) >> \
243 IRQAMP_ILEVEL_IL_15_1_SHIFT )
244#define IRQAMP_ILEVEL_IL_15_1_SET( _reg, _val ) \
245 ( ( ( _reg ) & ~IRQAMP_ILEVEL_IL_15_1_MASK ) | \
246 ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \
247 IRQAMP_ILEVEL_IL_15_1_MASK ) )
248#define IRQAMP_ILEVEL_IL_15_1( _val ) \
249 ( ( ( _val ) << IRQAMP_ILEVEL_IL_15_1_SHIFT ) & \
250 IRQAMP_ILEVEL_IL_15_1_MASK )
251
262#define IRQAMP_IPEND_EIP_31_16_SHIFT 16
263#define IRQAMP_IPEND_EIP_31_16_MASK 0xffff0000U
264#define IRQAMP_IPEND_EIP_31_16_GET( _reg ) \
265 ( ( ( _reg ) & IRQAMP_IPEND_EIP_31_16_MASK ) >> \
266 IRQAMP_IPEND_EIP_31_16_SHIFT )
267#define IRQAMP_IPEND_EIP_31_16_SET( _reg, _val ) \
268 ( ( ( _reg ) & ~IRQAMP_IPEND_EIP_31_16_MASK ) | \
269 ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \
270 IRQAMP_IPEND_EIP_31_16_MASK ) )
271#define IRQAMP_IPEND_EIP_31_16( _val ) \
272 ( ( ( _val ) << IRQAMP_IPEND_EIP_31_16_SHIFT ) & \
273 IRQAMP_IPEND_EIP_31_16_MASK )
274
275#define IRQAMP_IPEND_IP_15_1_SHIFT 1
276#define IRQAMP_IPEND_IP_15_1_MASK 0xfffeU
277#define IRQAMP_IPEND_IP_15_1_GET( _reg ) \
278 ( ( ( _reg ) & IRQAMP_IPEND_IP_15_1_MASK ) >> \
279 IRQAMP_IPEND_IP_15_1_SHIFT )
280#define IRQAMP_IPEND_IP_15_1_SET( _reg, _val ) \
281 ( ( ( _reg ) & ~IRQAMP_IPEND_IP_15_1_MASK ) | \
282 ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \
283 IRQAMP_IPEND_IP_15_1_MASK ) )
284#define IRQAMP_IPEND_IP_15_1( _val ) \
285 ( ( ( _val ) << IRQAMP_IPEND_IP_15_1_SHIFT ) & \
286 IRQAMP_IPEND_IP_15_1_MASK )
287
299#define IRQAMP_IFORCE0_IF_15_1_SHIFT 1
300#define IRQAMP_IFORCE0_IF_15_1_MASK 0xfffeU
301#define IRQAMP_IFORCE0_IF_15_1_GET( _reg ) \
302 ( ( ( _reg ) & IRQAMP_IFORCE0_IF_15_1_MASK ) >> \
303 IRQAMP_IFORCE0_IF_15_1_SHIFT )
304#define IRQAMP_IFORCE0_IF_15_1_SET( _reg, _val ) \
305 ( ( ( _reg ) & ~IRQAMP_IFORCE0_IF_15_1_MASK ) | \
306 ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \
307 IRQAMP_IFORCE0_IF_15_1_MASK ) )
308#define IRQAMP_IFORCE0_IF_15_1( _val ) \
309 ( ( ( _val ) << IRQAMP_IFORCE0_IF_15_1_SHIFT ) & \
310 IRQAMP_IFORCE0_IF_15_1_MASK )
311
322#define IRQAMP_ICLEAR_EIC_31_16_SHIFT 16
323#define IRQAMP_ICLEAR_EIC_31_16_MASK 0xffff0000U
324#define IRQAMP_ICLEAR_EIC_31_16_GET( _reg ) \
325 ( ( ( _reg ) & IRQAMP_ICLEAR_EIC_31_16_MASK ) >> \
326 IRQAMP_ICLEAR_EIC_31_16_SHIFT )
327#define IRQAMP_ICLEAR_EIC_31_16_SET( _reg, _val ) \
328 ( ( ( _reg ) & ~IRQAMP_ICLEAR_EIC_31_16_MASK ) | \
329 ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \
330 IRQAMP_ICLEAR_EIC_31_16_MASK ) )
331#define IRQAMP_ICLEAR_EIC_31_16( _val ) \
332 ( ( ( _val ) << IRQAMP_ICLEAR_EIC_31_16_SHIFT ) & \
333 IRQAMP_ICLEAR_EIC_31_16_MASK )
334
335#define IRQAMP_ICLEAR_IC_15_1_SHIFT 1
336#define IRQAMP_ICLEAR_IC_15_1_MASK 0xfffeU
337#define IRQAMP_ICLEAR_IC_15_1_GET( _reg ) \
338 ( ( ( _reg ) & IRQAMP_ICLEAR_IC_15_1_MASK ) >> \
339 IRQAMP_ICLEAR_IC_15_1_SHIFT )
340#define IRQAMP_ICLEAR_IC_15_1_SET( _reg, _val ) \
341 ( ( ( _reg ) & ~IRQAMP_ICLEAR_IC_15_1_MASK ) | \
342 ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \
343 IRQAMP_ICLEAR_IC_15_1_MASK ) )
344#define IRQAMP_ICLEAR_IC_15_1( _val ) \
345 ( ( ( _val ) << IRQAMP_ICLEAR_IC_15_1_SHIFT ) & \
346 IRQAMP_ICLEAR_IC_15_1_MASK )
347
359#define IRQAMP_MPSTAT_NCPU_SHIFT 28
360#define IRQAMP_MPSTAT_NCPU_MASK 0xf0000000U
361#define IRQAMP_MPSTAT_NCPU_GET( _reg ) \
362 ( ( ( _reg ) & IRQAMP_MPSTAT_NCPU_MASK ) >> \
363 IRQAMP_MPSTAT_NCPU_SHIFT )
364#define IRQAMP_MPSTAT_NCPU_SET( _reg, _val ) \
365 ( ( ( _reg ) & ~IRQAMP_MPSTAT_NCPU_MASK ) | \
366 ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \
367 IRQAMP_MPSTAT_NCPU_MASK ) )
368#define IRQAMP_MPSTAT_NCPU( _val ) \
369 ( ( ( _val ) << IRQAMP_MPSTAT_NCPU_SHIFT ) & \
370 IRQAMP_MPSTAT_NCPU_MASK )
371
372#define IRQAMP_MPSTAT_BA 0x8000000U
373
374#define IRQAMP_MPSTAT_ER 0x4000000U
375
376#define IRQAMP_MPSTAT_EIRQ_SHIFT 16
377#define IRQAMP_MPSTAT_EIRQ_MASK 0xf0000U
378#define IRQAMP_MPSTAT_EIRQ_GET( _reg ) \
379 ( ( ( _reg ) & IRQAMP_MPSTAT_EIRQ_MASK ) >> \
380 IRQAMP_MPSTAT_EIRQ_SHIFT )
381#define IRQAMP_MPSTAT_EIRQ_SET( _reg, _val ) \
382 ( ( ( _reg ) & ~IRQAMP_MPSTAT_EIRQ_MASK ) | \
383 ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \
384 IRQAMP_MPSTAT_EIRQ_MASK ) )
385#define IRQAMP_MPSTAT_EIRQ( _val ) \
386 ( ( ( _val ) << IRQAMP_MPSTAT_EIRQ_SHIFT ) & \
387 IRQAMP_MPSTAT_EIRQ_MASK )
388
389#define IRQAMP_MPSTAT_STATUS_SHIFT 0
390#define IRQAMP_MPSTAT_STATUS_MASK 0xfU
391#define IRQAMP_MPSTAT_STATUS_GET( _reg ) \
392 ( ( ( _reg ) & IRQAMP_MPSTAT_STATUS_MASK ) >> \
393 IRQAMP_MPSTAT_STATUS_SHIFT )
394#define IRQAMP_MPSTAT_STATUS_SET( _reg, _val ) \
395 ( ( ( _reg ) & ~IRQAMP_MPSTAT_STATUS_MASK ) | \
396 ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \
397 IRQAMP_MPSTAT_STATUS_MASK ) )
398#define IRQAMP_MPSTAT_STATUS( _val ) \
399 ( ( ( _val ) << IRQAMP_MPSTAT_STATUS_SHIFT ) & \
400 IRQAMP_MPSTAT_STATUS_MASK )
401
412#define IRQAMP_BRDCST_BM15_1_SHIFT 1
413#define IRQAMP_BRDCST_BM15_1_MASK 0xfffeU
414#define IRQAMP_BRDCST_BM15_1_GET( _reg ) \
415 ( ( ( _reg ) & IRQAMP_BRDCST_BM15_1_MASK ) >> \
416 IRQAMP_BRDCST_BM15_1_SHIFT )
417#define IRQAMP_BRDCST_BM15_1_SET( _reg, _val ) \
418 ( ( ( _reg ) & ~IRQAMP_BRDCST_BM15_1_MASK ) | \
419 ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \
420 IRQAMP_BRDCST_BM15_1_MASK ) )
421#define IRQAMP_BRDCST_BM15_1( _val ) \
422 ( ( ( _val ) << IRQAMP_BRDCST_BM15_1_SHIFT ) & \
423 IRQAMP_BRDCST_BM15_1_MASK )
424
435#define IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT 0
436#define IRQAMP_ERRSTAT_ERRMODE_3_0_MASK 0xfU
437#define IRQAMP_ERRSTAT_ERRMODE_3_0_GET( _reg ) \
438 ( ( ( _reg ) & IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) >> \
439 IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT )
440#define IRQAMP_ERRSTAT_ERRMODE_3_0_SET( _reg, _val ) \
441 ( ( ( _reg ) & ~IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) | \
442 ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \
443 IRQAMP_ERRSTAT_ERRMODE_3_0_MASK ) )
444#define IRQAMP_ERRSTAT_ERRMODE_3_0( _val ) \
445 ( ( ( _val ) << IRQAMP_ERRSTAT_ERRMODE_3_0_SHIFT ) & \
446 IRQAMP_ERRSTAT_ERRMODE_3_0_MASK )
447
459#define IRQAMP_WDOGCTRL_NWDOG_SHIFT 27
460#define IRQAMP_WDOGCTRL_NWDOG_MASK 0xf8000000U
461#define IRQAMP_WDOGCTRL_NWDOG_GET( _reg ) \
462 ( ( ( _reg ) & IRQAMP_WDOGCTRL_NWDOG_MASK ) >> \
463 IRQAMP_WDOGCTRL_NWDOG_SHIFT )
464#define IRQAMP_WDOGCTRL_NWDOG_SET( _reg, _val ) \
465 ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_NWDOG_MASK ) | \
466 ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \
467 IRQAMP_WDOGCTRL_NWDOG_MASK ) )
468#define IRQAMP_WDOGCTRL_NWDOG( _val ) \
469 ( ( ( _val ) << IRQAMP_WDOGCTRL_NWDOG_SHIFT ) & \
470 IRQAMP_WDOGCTRL_NWDOG_MASK )
471
472#define IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT 16
473#define IRQAMP_WDOGCTRL_WDOGIRQ_MASK 0xf0000U
474#define IRQAMP_WDOGCTRL_WDOGIRQ_GET( _reg ) \
475 ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) >> \
476 IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT )
477#define IRQAMP_WDOGCTRL_WDOGIRQ_SET( _reg, _val ) \
478 ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) | \
479 ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \
480 IRQAMP_WDOGCTRL_WDOGIRQ_MASK ) )
481#define IRQAMP_WDOGCTRL_WDOGIRQ( _val ) \
482 ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGIRQ_SHIFT ) & \
483 IRQAMP_WDOGCTRL_WDOGIRQ_MASK )
484
485#define IRQAMP_WDOGCTRL_WDOGMSK_SHIFT 0
486#define IRQAMP_WDOGCTRL_WDOGMSK_MASK 0xfU
487#define IRQAMP_WDOGCTRL_WDOGMSK_GET( _reg ) \
488 ( ( ( _reg ) & IRQAMP_WDOGCTRL_WDOGMSK_MASK ) >> \
489 IRQAMP_WDOGCTRL_WDOGMSK_SHIFT )
490#define IRQAMP_WDOGCTRL_WDOGMSK_SET( _reg, _val ) \
491 ( ( ( _reg ) & ~IRQAMP_WDOGCTRL_WDOGMSK_MASK ) | \
492 ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \
493 IRQAMP_WDOGCTRL_WDOGMSK_MASK ) )
494#define IRQAMP_WDOGCTRL_WDOGMSK( _val ) \
495 ( ( ( _val ) << IRQAMP_WDOGCTRL_WDOGMSK_SHIFT ) & \
496 IRQAMP_WDOGCTRL_WDOGMSK_MASK )
497
509#define IRQAMP_ASMPCTRL_NCTRL_SHIFT 28
510#define IRQAMP_ASMPCTRL_NCTRL_MASK 0xf0000000U
511#define IRQAMP_ASMPCTRL_NCTRL_GET( _reg ) \
512 ( ( ( _reg ) & IRQAMP_ASMPCTRL_NCTRL_MASK ) >> \
513 IRQAMP_ASMPCTRL_NCTRL_SHIFT )
514#define IRQAMP_ASMPCTRL_NCTRL_SET( _reg, _val ) \
515 ( ( ( _reg ) & ~IRQAMP_ASMPCTRL_NCTRL_MASK ) | \
516 ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \
517 IRQAMP_ASMPCTRL_NCTRL_MASK ) )
518#define IRQAMP_ASMPCTRL_NCTRL( _val ) \
519 ( ( ( _val ) << IRQAMP_ASMPCTRL_NCTRL_SHIFT ) & \
520 IRQAMP_ASMPCTRL_NCTRL_MASK )
521
522#define IRQAMP_ASMPCTRL_ICF 0x2U
523
524#define IRQAMP_ASMPCTRL_L 0x1U
525
537#define IRQAMP_ICSELR_ICSEL0_SHIFT 28
538#define IRQAMP_ICSELR_ICSEL0_MASK 0xf0000000U
539#define IRQAMP_ICSELR_ICSEL0_GET( _reg ) \
540 ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL0_MASK ) >> \
541 IRQAMP_ICSELR_ICSEL0_SHIFT )
542#define IRQAMP_ICSELR_ICSEL0_SET( _reg, _val ) \
543 ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL0_MASK ) | \
544 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \
545 IRQAMP_ICSELR_ICSEL0_MASK ) )
546#define IRQAMP_ICSELR_ICSEL0( _val ) \
547 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL0_SHIFT ) & \
548 IRQAMP_ICSELR_ICSEL0_MASK )
549
550#define IRQAMP_ICSELR_ICSEL1_SHIFT 24
551#define IRQAMP_ICSELR_ICSEL1_MASK 0xf000000U
552#define IRQAMP_ICSELR_ICSEL1_GET( _reg ) \
553 ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL1_MASK ) >> \
554 IRQAMP_ICSELR_ICSEL1_SHIFT )
555#define IRQAMP_ICSELR_ICSEL1_SET( _reg, _val ) \
556 ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL1_MASK ) | \
557 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \
558 IRQAMP_ICSELR_ICSEL1_MASK ) )
559#define IRQAMP_ICSELR_ICSEL1( _val ) \
560 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL1_SHIFT ) & \
561 IRQAMP_ICSELR_ICSEL1_MASK )
562
563#define IRQAMP_ICSELR_ICSEL2_SHIFT 20
564#define IRQAMP_ICSELR_ICSEL2_MASK 0xf00000U
565#define IRQAMP_ICSELR_ICSEL2_GET( _reg ) \
566 ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL2_MASK ) >> \
567 IRQAMP_ICSELR_ICSEL2_SHIFT )
568#define IRQAMP_ICSELR_ICSEL2_SET( _reg, _val ) \
569 ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL2_MASK ) | \
570 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \
571 IRQAMP_ICSELR_ICSEL2_MASK ) )
572#define IRQAMP_ICSELR_ICSEL2( _val ) \
573 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL2_SHIFT ) & \
574 IRQAMP_ICSELR_ICSEL2_MASK )
575
576#define IRQAMP_ICSELR_ICSEL3_SHIFT 16
577#define IRQAMP_ICSELR_ICSEL3_MASK 0xf0000U
578#define IRQAMP_ICSELR_ICSEL3_GET( _reg ) \
579 ( ( ( _reg ) & IRQAMP_ICSELR_ICSEL3_MASK ) >> \
580 IRQAMP_ICSELR_ICSEL3_SHIFT )
581#define IRQAMP_ICSELR_ICSEL3_SET( _reg, _val ) \
582 ( ( ( _reg ) & ~IRQAMP_ICSELR_ICSEL3_MASK ) | \
583 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \
584 IRQAMP_ICSELR_ICSEL3_MASK ) )
585#define IRQAMP_ICSELR_ICSEL3( _val ) \
586 ( ( ( _val ) << IRQAMP_ICSELR_ICSEL3_SHIFT ) & \
587 IRQAMP_ICSELR_ICSEL3_MASK )
588
600#define IRQAMP_PIMASK_EIM_31_16_SHIFT 16
601#define IRQAMP_PIMASK_EIM_31_16_MASK 0xffff0000U
602#define IRQAMP_PIMASK_EIM_31_16_GET( _reg ) \
603 ( ( ( _reg ) & IRQAMP_PIMASK_EIM_31_16_MASK ) >> \
604 IRQAMP_PIMASK_EIM_31_16_SHIFT )
605#define IRQAMP_PIMASK_EIM_31_16_SET( _reg, _val ) \
606 ( ( ( _reg ) & ~IRQAMP_PIMASK_EIM_31_16_MASK ) | \
607 ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \
608 IRQAMP_PIMASK_EIM_31_16_MASK ) )
609#define IRQAMP_PIMASK_EIM_31_16( _val ) \
610 ( ( ( _val ) << IRQAMP_PIMASK_EIM_31_16_SHIFT ) & \
611 IRQAMP_PIMASK_EIM_31_16_MASK )
612
613#define IRQAMP_PIMASK_IM15_1_SHIFT 1
614#define IRQAMP_PIMASK_IM15_1_MASK 0xfffeU
615#define IRQAMP_PIMASK_IM15_1_GET( _reg ) \
616 ( ( ( _reg ) & IRQAMP_PIMASK_IM15_1_MASK ) >> \
617 IRQAMP_PIMASK_IM15_1_SHIFT )
618#define IRQAMP_PIMASK_IM15_1_SET( _reg, _val ) \
619 ( ( ( _reg ) & ~IRQAMP_PIMASK_IM15_1_MASK ) | \
620 ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \
621 IRQAMP_PIMASK_IM15_1_MASK ) )
622#define IRQAMP_PIMASK_IM15_1( _val ) \
623 ( ( ( _val ) << IRQAMP_PIMASK_IM15_1_SHIFT ) & \
624 IRQAMP_PIMASK_IM15_1_MASK )
625
637#define IRQAMP_PIFORCE_FC_15_1_SHIFT 17
638#define IRQAMP_PIFORCE_FC_15_1_MASK 0xfffe0000U
639#define IRQAMP_PIFORCE_FC_15_1_GET( _reg ) \
640 ( ( ( _reg ) & IRQAMP_PIFORCE_FC_15_1_MASK ) >> \
641 IRQAMP_PIFORCE_FC_15_1_SHIFT )
642#define IRQAMP_PIFORCE_FC_15_1_SET( _reg, _val ) \
643 ( ( ( _reg ) & ~IRQAMP_PIFORCE_FC_15_1_MASK ) | \
644 ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \
645 IRQAMP_PIFORCE_FC_15_1_MASK ) )
646#define IRQAMP_PIFORCE_FC_15_1( _val ) \
647 ( ( ( _val ) << IRQAMP_PIFORCE_FC_15_1_SHIFT ) & \
648 IRQAMP_PIFORCE_FC_15_1_MASK )
649
650#define IRQAMP_PIFORCE_IF15_1_SHIFT 1
651#define IRQAMP_PIFORCE_IF15_1_MASK 0xfffeU
652#define IRQAMP_PIFORCE_IF15_1_GET( _reg ) \
653 ( ( ( _reg ) & IRQAMP_PIFORCE_IF15_1_MASK ) >> \
654 IRQAMP_PIFORCE_IF15_1_SHIFT )
655#define IRQAMP_PIFORCE_IF15_1_SET( _reg, _val ) \
656 ( ( ( _reg ) & ~IRQAMP_PIFORCE_IF15_1_MASK ) | \
657 ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \
658 IRQAMP_PIFORCE_IF15_1_MASK ) )
659#define IRQAMP_PIFORCE_IF15_1( _val ) \
660 ( ( ( _val ) << IRQAMP_PIFORCE_IF15_1_SHIFT ) & \
661 IRQAMP_PIFORCE_IF15_1_MASK )
662
674#define IRQAMP_PEXTACK_EID_4_0_SHIFT 0
675#define IRQAMP_PEXTACK_EID_4_0_MASK 0x1fU
676#define IRQAMP_PEXTACK_EID_4_0_GET( _reg ) \
677 ( ( ( _reg ) & IRQAMP_PEXTACK_EID_4_0_MASK ) >> \
678 IRQAMP_PEXTACK_EID_4_0_SHIFT )
679#define IRQAMP_PEXTACK_EID_4_0_SET( _reg, _val ) \
680 ( ( ( _reg ) & ~IRQAMP_PEXTACK_EID_4_0_MASK ) | \
681 ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \
682 IRQAMP_PEXTACK_EID_4_0_MASK ) )
683#define IRQAMP_PEXTACK_EID_4_0( _val ) \
684 ( ( ( _val ) << IRQAMP_PEXTACK_EID_4_0_SHIFT ) & \
685 IRQAMP_PEXTACK_EID_4_0_MASK )
686
698#define IRQAMP_BADDR_BOOTADDR_31_3_SHIFT 3
699#define IRQAMP_BADDR_BOOTADDR_31_3_MASK 0xfffffff8U
700#define IRQAMP_BADDR_BOOTADDR_31_3_GET( _reg ) \
701 ( ( ( _reg ) & IRQAMP_BADDR_BOOTADDR_31_3_MASK ) >> \
702 IRQAMP_BADDR_BOOTADDR_31_3_SHIFT )
703#define IRQAMP_BADDR_BOOTADDR_31_3_SET( _reg, _val ) \
704 ( ( ( _reg ) & ~IRQAMP_BADDR_BOOTADDR_31_3_MASK ) | \
705 ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \
706 IRQAMP_BADDR_BOOTADDR_31_3_MASK ) )
707#define IRQAMP_BADDR_BOOTADDR_31_3( _val ) \
708 ( ( ( _val ) << IRQAMP_BADDR_BOOTADDR_31_3_SHIFT ) & \
709 IRQAMP_BADDR_BOOTADDR_31_3_MASK )
710
711#define IRQAMP_BADDR_AS 0x1U
712
723#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT 24
724#define IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK 0xff000000U
725#define IRQAMP_IRQMAP_IRQMAP_4_N_0_GET( _reg ) \
726 ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) >> \
727 IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT )
728#define IRQAMP_IRQMAP_IRQMAP_4_N_0_SET( _reg, _val ) \
729 ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) | \
730 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \
731 IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK ) )
732#define IRQAMP_IRQMAP_IRQMAP_4_N_0( _val ) \
733 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_0_SHIFT ) & \
734 IRQAMP_IRQMAP_IRQMAP_4_N_0_MASK )
735
736#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT 16
737#define IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK 0xff0000U
738#define IRQAMP_IRQMAP_IRQMAP_4_N_1_GET( _reg ) \
739 ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) >> \
740 IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT )
741#define IRQAMP_IRQMAP_IRQMAP_4_N_1_SET( _reg, _val ) \
742 ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) | \
743 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \
744 IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK ) )
745#define IRQAMP_IRQMAP_IRQMAP_4_N_1( _val ) \
746 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_1_SHIFT ) & \
747 IRQAMP_IRQMAP_IRQMAP_4_N_1_MASK )
748
749#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT 8
750#define IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK 0xff00U
751#define IRQAMP_IRQMAP_IRQMAP_4_N_2_GET( _reg ) \
752 ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) >> \
753 IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT )
754#define IRQAMP_IRQMAP_IRQMAP_4_N_2_SET( _reg, _val ) \
755 ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) | \
756 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \
757 IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK ) )
758#define IRQAMP_IRQMAP_IRQMAP_4_N_2( _val ) \
759 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_2_SHIFT ) & \
760 IRQAMP_IRQMAP_IRQMAP_4_N_2_MASK )
761
762#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT 0
763#define IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK 0xffU
764#define IRQAMP_IRQMAP_IRQMAP_4_N_3_GET( _reg ) \
765 ( ( ( _reg ) & IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) >> \
766 IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT )
767#define IRQAMP_IRQMAP_IRQMAP_4_N_3_SET( _reg, _val ) \
768 ( ( ( _reg ) & ~IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) | \
769 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \
770 IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK ) )
771#define IRQAMP_IRQMAP_IRQMAP_4_N_3( _val ) \
772 ( ( ( _val ) << IRQAMP_IRQMAP_IRQMAP_4_N_3_SHIFT ) & \
773 IRQAMP_IRQMAP_IRQMAP_4_N_3_MASK )
774
780typedef struct irqamp {
784 uint32_t ilevel;
785
789 uint32_t ipend;
790
794 uint32_t iforce0;
795
799 uint32_t iclear;
800
804 uint32_t mpstat;
805
809 uint32_t brdcst;
810
814 uint32_t errstat;
815
819 uint32_t wdogctrl;
820
824 uint32_t asmpctrl;
825
829 uint32_t icselr[ 2 ];
830
831 uint32_t reserved_2c_40[ 5 ];
832
836 uint32_t pimask[ 16 ];
837
841 uint32_t piforce[ 16 ];
842
846 uint32_t pextack[ 16 ];
847
851 irqamp_timestamp itstmp[ 16 ];
852
856 uint32_t baddr[ 16 ];
857
858 uint32_t reserved_240_300[ 48 ];
859
863 uint32_t irqmap[ 16 ];
864
865 uint32_t reserved_340_400[ 48 ];
866} irqamp;
867
870#ifdef __cplusplus
871}
872#endif
873
874#endif /* _GRLIB_IRQAMP_REGS_H */
irqamp_timestamp
struct irqamp_timestamp irqamp_timestamp
This structure defines the IRQ(A)MP Timestamp register block memory map.
irqamp
struct irqamp irqamp
This structure defines the IRQ(A)MP register block memory map.
irqamp_timestamp
This structure defines the IRQ(A)MP Timestamp register block memory map.
Definition: irqamp-regs.h:195
irqamp_timestamp::itcnt
uint32_t itcnt
See Interrupt timestamp counter n register (ITCNT).
Definition: irqamp-regs.h:199
irqamp_timestamp::itstmpac
uint32_t itstmpac
See Interrupt Acknowledge Timestamp n register (ITSTMPAC).
Definition: irqamp-regs.h:214
irqamp_timestamp::itstmpas
uint32_t itstmpas
See Interrupt Assertion Timestamp n register (ITSTMPAS).
Definition: irqamp-regs.h:209
irqamp_timestamp::itstmpc
uint32_t itstmpc
See Interrupt timestamp n control register (ITSTMPC).
Definition: irqamp-regs.h:204
irqamp
This structure defines the IRQ(A)MP register block memory map.
Definition: irqamp-regs.h:780
irqamp::ilevel
uint32_t ilevel
See Interrupt level register (ILEVEL).
Definition: irqamp-regs.h:784
irqamp::pimask
uint32_t pimask[16]
See Processor n interrupt mask register (PIMASK).
Definition: irqamp-regs.h:836
irqamp::iforce0
uint32_t iforce0
See Interrupt force register for processor 0 (IFORCE0).
Definition: irqamp-regs.h:794
irqamp::errstat
uint32_t errstat
See Error Mode Status Register (ERRSTAT).
Definition: irqamp-regs.h:814
irqamp::baddr
uint32_t baddr[16]
See Processor n Boot Address register (BADDR).
Definition: irqamp-regs.h:856
irqamp::irqmap
uint32_t irqmap[16]
See Interrupt map register n (IRQMAP).
Definition: irqamp-regs.h:863
irqamp::pextack
uint32_t pextack[16]
See Processor n extended interrupt acknowledge register (PEXTACK).
Definition: irqamp-regs.h:846
irqamp::wdogctrl
uint32_t wdogctrl
See Watchdog control register (WDOGCTRL).
Definition: irqamp-regs.h:819
irqamp::asmpctrl
uint32_t asmpctrl
See Asymmetric multiprocessing control register (ASMPCTRL).
Definition: irqamp-regs.h:824
irqamp::itstmp
irqamp_timestamp itstmp[16]
See IRQ(A)MP Timestamp.
Definition: irqamp-regs.h:851
irqamp::mpstat
uint32_t mpstat
See Multiprocessor status register (MPSTAT).
Definition: irqamp-regs.h:804
irqamp::brdcst
uint32_t brdcst
See Broadcast register (BRDCST).
Definition: irqamp-regs.h:809
irqamp::piforce
uint32_t piforce[16]
See Processor n interrupt force register (PIFORCE).
Definition: irqamp-regs.h:841
irqamp::iclear
uint32_t iclear
See Interrupt clear register (ICLEAR).
Definition: irqamp-regs.h:799
irqamp::ipend
uint32_t ipend
See Interrupt pending register (IPEND).
Definition: irqamp-regs.h:789
irqamp::icselr
uint32_t icselr[2]
See Interrupt controller select register (ICSELR).
Definition: irqamp-regs.h:829
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