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#define | EDMA_CR_EDBG (1 << 1) |
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#define | EDMA_CR_ERCA (1 << 2) |
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#define | EDMA_CR_ERGA (1 << 3) |
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#define | EDMA_CR_GRPxPRI_SHIFT(x) (8 + (x) * 2) |
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#define | EDMA_CR_GRPxPRI_MASK(x) (0x3 << EDMA_CR_GRPxPRI_SHIFT(x)) |
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#define | EDMA_CR_GRPxPRI(x, val) (((val) << EDMA_CR_GRPxPRI_SHIFT(x)) & EDMA_CR_GRPxPRI_MASK(x)) |
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#define | EDMA_CR_GRPxPRI_GET(x, reg) (((reg) & EDMA_CR_GRPxPRI_MASK(x)) >> EDMA_CR_GRPxPRI_SHIFT(x)) |
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#define | EDMA_ESR_DBE (1 << 0) |
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#define | EDMA_ESR_SBE (1 << 1) |
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#define | EDMA_ESR_SGE (1 << 2) |
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#define | EDMA_ESR_NCE (1 << 3) |
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#define | EDMA_ESR_DOE (1 << 4) |
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#define | EDMA_ESR_DAE (1 << 5) |
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#define | EDMA_ESR_SOE (1 << 6) |
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#define | EDMA_ESR_SAE (1 << 7) |
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#define | EDMA_ESR_ERRCHN_SHIFT (8) |
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#define | EDMA_ESR_ERRCHN_MASK (0x3F << EDMA_ESR_ERRCHN_SHIFT) |
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#define | EDMA_ESR_ERRCHN(val) (((val) << EDMA_ESR_ERRCHN_SHIFT) & EDMA_ESR_ERRCHN_MASK) |
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#define | EDMA_ESR_ERRCHN_GET(reg) (((reg) & EDMA_ESR_ERRCHN_MASK) >> EDMA_ESR_ERRCHN_SHIFT) |
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#define | EDMA_ESR_CPE (1 << 14) |
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#define | EDMA_ESR_GPE (1 << 15) |
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#define | EDMA_ESR_VLD (1 << 31) |
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#define | EDMA_ERRQH_ERRQ(x) (1 << ((x) - 32)) |
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#define | EDMA_ERRQL_ERRQ(x) (1 << (x)) |
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#define | EDMA_EEIH_EEI(x) (1 << ((x) - 32)) |
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#define | EDMA_EEIL_EEI(x) (1 << (x)) |
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#define | EDMA_SERQR_NOP (1 << 7) |
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#define | EDMA_SERQR_SAER (1 << 6) |
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#define | EDMA_SERQR_SERQ_SHIFT (0) |
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#define | EDMA_SERQR_SERQ_MASK (0x1F << EDMA_CIRQR_SERQ_SHIFT) |
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#define | EDMA_SERQR_SERQ(val) (((val) << EDMA_CIRQR_SERQ_SHIFT) & EDMA_CIRQR_SERQ_MASK) |
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#define | EDMA_SERQR_SERQ_GET(reg) (((reg) & EDMA_CIRQR_SERQ_MASK) >> EDMA_CIRQR_SERQ_SHIFT) |
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#define | EDMA_CERQR_NOP (1 << 7) |
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#define | EDMA_CERQR_CAER (1 << 6) |
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#define | EDMA_CERQR_CERQ_SHIFT (0) |
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#define | EDMA_CERQR_CERQ_MASK (0x1F << EDMA_CIRQR_CERQ_SHIFT) |
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#define | EDMA_CERQR_CERQ(val) (((val) << EDMA_CIRQR_CERQ_SHIFT) & EDMA_CIRQR_CERQ_MASK) |
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#define | EDMA_CERQR_CERQ_GET(reg) (((reg) & EDMA_CIRQR_CERQ_MASK) >> EDMA_CIRQR_CERQ_SHIFT) |
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#define | EDMA_SEEIR_NOP (1 << 7) |
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#define | EDMA_SEEIR_SAEE (1 << 6) |
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#define | EDMA_SEEIR_SEEI_SHIFT (0) |
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#define | EDMA_SEEIR_SEEI_MASK (0x1F << EDMA_CIRQR_SEEI_SHIFT) |
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#define | EDMA_SEEIR_SEEI(val) (((val) << EDMA_CIRQR_SEEI_SHIFT) & EDMA_CIRQR_SEEI_MASK) |
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#define | EDMA_SEEIR_SEEI_GET(reg) (((reg) & EDMA_CIRQR_SEEI_MASK) >> EDMA_CIRQR_SEEI_SHIFT) |
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#define | EDMA_CEEIR_NOP (1 << 7) |
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#define | EDMA_CEEIR_CAEE (1 << 6) |
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#define | EDMA_CEEIR_CEEI_SHIFT (0) |
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#define | EDMA_CEEIR_CEEI_MASK (0x1F << EDMA_CIRQR_CEEI_SHIFT) |
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#define | EDMA_CEEIR_CEEI(val) (((val) << EDMA_CIRQR_CEEI_SHIFT) & EDMA_CIRQR_CEEI_MASK) |
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#define | EDMA_CEEIR_CEEI_GET(reg) (((reg) & EDMA_CIRQR_CEEI_MASK) >> EDMA_CIRQR_CEEI_SHIFT) |
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#define | EDMA_CIRQR_NOP (1 << 7) |
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#define | EDMA_CIRQR_CAIR (1 << 6) |
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#define | EDMA_CIRQR_CINT_SHIFT (0) |
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#define | EDMA_CIRQR_CINT_MASK (0x1F << EDMA_CIRQR_CINT_SHIFT) |
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#define | EDMA_CIRQR_CINT(val) (((val) << EDMA_CIRQR_CINT_SHIFT) & EDMA_CIRQR_CINT_MASK) |
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#define | EDMA_CIRQR_CINT_GET(reg) (((reg) & EDMA_CIRQR_CINT_MASK) >> EDMA_CIRQR_CINT_SHIFT) |
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#define | EDMA_CER_NOP (1 << 7) |
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#define | EDMA_CER_CAEI (1 << 6) |
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#define | EDMA_CER_CERR_SHIFT (0) |
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#define | EDMA_CER_CERR_MASK (0x1F << EDMA_CIRQR_CERR_SHIFT) |
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#define | EDMA_CER_CERR(val) (((val) << EDMA_CIRQR_CERR_SHIFT) & EDMA_CIRQR_CERR_MASK) |
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#define | EDMA_CER_CERR_GET(reg) (((reg) & EDMA_CIRQR_CERR_MASK) >> EDMA_CIRQR_CERR_SHIFT) |
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#define | EDMA_SSBR_NOP (1 << 7) |
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#define | EDMA_SSBR_SAST (1 << 6) |
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#define | EDMA_SSBR_SSB_SHIFT (0) |
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#define | EDMA_SSBR_SSB_MASK (0x1F << EDMA_CIRQR_SSB_SHIFT) |
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#define | EDMA_SSBR_SSB(val) (((val) << EDMA_CIRQR_SSB_SHIFT) & EDMA_CIRQR_SSB_MASK) |
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#define | EDMA_SSBR_SSB_GET(reg) (((reg) & EDMA_CIRQR_SSB_MASK) >> EDMA_CIRQR_SSB_SHIFT) |
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#define | EDMA_CDSBR_NOP (1 << 7) |
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#define | EDMA_CDSBR_CADN (1 << 6) |
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#define | EDMA_CDSBR_CDSB_SHIFT (0) |
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#define | EDMA_CDSBR_CDSB_MASK (0x1F << EDMA_CIRQR_CDSB_SHIFT) |
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#define | EDMA_CDSBR_CDSB(val) (((val) << EDMA_CIRQR_CDSB_SHIFT) & EDMA_CIRQR_CDSB_MASK) |
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#define | EDMA_CDSBR_CDSB_GET(reg) (((reg) & EDMA_CIRQR_CDSB_MASK) >> EDMA_CIRQR_CDSB_SHIFT) |
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#define | EDMA_IRQH_INT(x) (1 << ((x) - 32)) |
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#define | EDMA_IRQL_INT(x) (1 << ((x))) |
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#define | EDMA_ERH_ERR(x) (1 << ((x) - 32)) |
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#define | EDMA_ERL_ERR(x) (1 << ((x))) |
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#define | EDMA_CPR_CHPRI_SHIFT (0) |
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#define | EDMA_CPR_CHPRI_MASK (0xF << EDMA_CPR_CHPRI_SHIFT) |
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#define | EDMA_CPR_CHPRI(val) (((val) << EDMA_CPR_CHPRI_SHIFT) & EDMA_CPR_CHPRI_MASK) |
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#define | EDMA_CPR_CHPRI_GET(reg) (((reg) & EDMA_CPR_CHPRI_MASK) >> EDMA_CPR_CHPRI_SHIFT) |
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#define | EDMA_CPR_GRPPRI_SHIFT (0) |
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#define | EDMA_CPR_GRPPRI_MASK (0xF << EDMA_CPR_GRPPRI_SHIFT) |
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#define | EDMA_CPR_GRPPRI(val) (((val) << EDMA_CPR_GRPPRI_SHIFT) & EDMA_CPR_GRPPRI_MASK) |
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#define | EDMA_CPR_GRPPRI_GET(reg) (((reg) & EDMA_CPR_GRPPRI_MASK) >> EDMA_CPR_GRPPRI_SHIFT) |
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#define | EDMA_CPR_ECP (1 << 7) |
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#define | EDMA_TCD_SDF_SMOD_SHIFT (27) |
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#define | EDMA_TCD_SDF_SMOD_MASK (0x1F << EDMA_TCD_SDF_SMOD_SHIFT) |
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#define | EDMA_TCD_SDF_SMOD(val) (((val) << EDMA_TCD_SDF_SMOD_SHIFT) & EDMA_TCD_SDF_SMOD_MASK) |
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#define | EDMA_TCD_SDF_SMOD_GET(reg) (((reg) & EDMA_TCD_SDF_SMOD_MASK) >> EDMA_TCD_SDF_SMOD_SHIFT) |
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#define | EDMA_TCD_SDF_SSIZE_SHIFT (24) |
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#define | EDMA_TCD_SDF_SSIZE_MASK (0x7 << EDMA_TCD_SDF_SSIZE_SHIFT) |
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#define | EDMA_TCD_SDF_SSIZE(val) (((val) << EDMA_TCD_SDF_SSIZE_SHIFT) & EDMA_TCD_SDF_SSIZE_MASK) |
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#define | EDMA_TCD_SDF_SSIZE_GET(reg) (((reg) & EDMA_TCD_SDF_SSIZE_MASK) >> EDMA_TCD_SDF_SSIZE_SHIFT) |
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#define | EDMA_TCD_SDF_SSIZE_8BIT EDMA_TCD_SDF_SSIZE(0) |
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#define | EDMA_TCD_SDF_SSIZE_16BIT EDMA_TCD_SDF_SSIZE(1) |
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#define | EDMA_TCD_SDF_SSIZE_32BIT EDMA_TCD_SDF_SSIZE(2) |
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#define | EDMA_TCD_SDF_SSIZE_64BIT EDMA_TCD_SDF_SSIZE(3) |
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#define | EDMA_TCD_SDF_SSIZE_32BYTE EDMA_TCD_SDF_SSIZE(5) |
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#define | EDMA_TCD_SDF_DMOD_SHIFT (19) |
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#define | EDMA_TCD_SDF_DMOD_MASK (0x1F << EDMA_TCD_SDF_DMOD_SHIFT) |
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#define | EDMA_TCD_SDF_DMOD(val) (((val) << EDMA_TCD_SDF_DMOD_SHIFT) & EDMA_TCD_SDF_DMOD_MASK) |
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#define | EDMA_TCD_SDF_DMOD_GET(reg) (((reg) & EDMA_TCD_SDF_DMOD_MASK) >> EDMA_TCD_SDF_DMOD_SHIFT) |
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#define | EDMA_TCD_SDF_DSIZE_SHIFT (16) |
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#define | EDMA_TCD_SDF_DSIZE_MASK (0x7 << EDMA_TCD_SDF_DSIZE_SHIFT) |
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#define | EDMA_TCD_SDF_DSIZE(val) (((val) << EDMA_TCD_SDF_DSIZE_SHIFT) & EDMA_TCD_SDF_DSIZE_MASK) |
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#define | EDMA_TCD_SDF_DSIZE_GET(reg) (((reg) & EDMA_TCD_SDF_DSIZE_MASK) >> EDMA_TCD_SDF_DSIZE_SHIFT) |
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#define | EDMA_TCD_SDF_DSIZE_8BIT EDMA_TCD_SDF_DSIZE(0) |
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#define | EDMA_TCD_SDF_DSIZE_16BIT EDMA_TCD_SDF_DSIZE(1) |
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#define | EDMA_TCD_SDF_DSIZE_32BIT EDMA_TCD_SDF_DSIZE(2) |
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#define | EDMA_TCD_SDF_DSIZE_64BIT EDMA_TCD_SDF_DSIZE(3) |
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#define | EDMA_TCD_SDF_DSIZE_32BYTE EDMA_TCD_SDF_DSIZE(5) |
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#define | EDMA_TCD_SDF_SOFF_SHIFT (0) |
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#define | EDMA_TCD_SDF_SOFF_MASK (0xFFFF << EDMA_TCD_SDF_SOFF_SHIFT) |
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#define | EDMA_TCD_SDF_SOFF(val) (((val) << EDMA_TCD_SDF_SOFF_SHIFT) & EDMA_TCD_SDF_SOFF_MASK) |
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#define | EDMA_TCD_SDF_SOFF_GET(reg) (((reg) & EDMA_TCD_SDF_SOFF_MASK) >> EDMA_TCD_SDF_SOFF_SHIFT) |
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#define | EDMA_TCD_NBYTES_ALT_NBYTES_SHIFT (0) |
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#define | EDMA_TCD_NBYTES_ALT_NBYTES_MASK (0x3FF << EDMA_TCD_NBYTES_ALT_NBYTES_SHIFT) |
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#define | EDMA_TCD_NBYTES_ALT_NBYTES(val) (((val) << EDMA_TCD_NBYTES_ALT_NBYTES_SHIFT) & EDMA_TCD_NBYTES_ALT_NBYTES_MASK) |
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#define | EDMA_TCD_NBYTES_ALT_MLOFF_SHIFT (10) |
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#define | EDMA_TCD_NBYTES_ALT_MLOFF_MASK (0xFFFFF << EDMA_TCD_NBYTES_ALT_MLOFF_SHIFT) |
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#define | EDMA_TCD_NBYTES_ALT_MLOFF(val) (((val) << EDMA_TCD_NBYTES_ALT_MLOFF_SHIFT) & EDMA_TCD_NBYTES_ALT_MLOFF_MASK) |
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#define | EDMA_TCD_NBYTES_ALT_DMLOE (1 << 30) |
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#define | EDMA_TCD_NBYTES_ALT_SMLOE (1 << 31) |
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#define | EDMA_TCD_CDF_CITERE_LINK (1 << 31) |
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#define | EDMA_TCD_CDF_CITER_SHIFT (16) |
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#define | EDMA_TCD_CDF_CITER_MASK (0x7FFF << EDMA_TCD_CDF_CITER_SHIFT) |
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#define | EDMA_TCD_CDF_CITER(val) (((val) << EDMA_TCD_CDF_CITER_SHIFT) & EDMA_TCD_CDF_CITER_MASK) |
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#define | EDMA_TCD_CDF_CITER_GET(reg) (((reg) & EDMA_TCD_CDF_CITER_MASK) >> EDMA_TCD_CDF_CITER_SHIFT) |
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#define | EDMA_TCD_CDF_DOFF_SHIFT (0) |
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#define | EDMA_TCD_CDF_DOFF_MASK (0xFFFF << EDMA_TCD_CDF_DOFF_SHIFT) |
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#define | EDMA_TCD_CDF_DOFF(val) (((val) << EDMA_TCD_CDF_DOFF_SHIFT) & EDMA_TCD_CDF_DOFF_MASK) |
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#define | EDMA_TCD_CDF_DOFF_GET(reg) (((reg) & EDMA_TCD_CDF_DOFF_MASK) >> EDMA_TCD_CDF_DOFF_SHIFT) |
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#define | EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT (25) |
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#define | EDMA_TCD_CDF_ALT_CITERLINKCH_MASK (0x3F << EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT) |
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#define | EDMA_TCD_CDF_ALT_CITERLINKCH(val) (((val) << EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT) & EDMA_TCD_CDF_ALT_CITERLINKCH_MASK) |
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#define | EDMA_TCD_CDF_ALT_CITERLINKCH_GET(reg) (((reg) & EDMA_TCD_CDF_ALT_CITERLINKCH_MASK) >> EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT) |
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#define | EDMA_TCD_CDF_ALT_CITER_SHIFT (16) |
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#define | EDMA_TCD_CDF_ALT_CITER_MASK (0x1FF << EDMA_TCD_CDF_ALT_CITER_SHIFT) |
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#define | EDMA_TCD_CDF_ALT_CITER(val) (((val) << EDMA_TCD_CDF_ALT_CITER_SHIFT) & EDMA_TCD_CDF_ALT_CITER_MASK) |
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#define | EDMA_TCD_CDF_ALT_CITER_GET(reg) (((reg) & EDMA_TCD_CDF_ALT_CITER_MASK) >> EDMA_TCD_CDF_ALT_CITER_SHIFT) |
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#define | EDMA_TCD_CDF_NOLINK_CITER_SHIFT (16) |
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#define | EDMA_TCD_CDF_NOLINK_CITER_MASK (0xFFFF << EDMA_TCD_CDF_NOLINK_CITER_SHIFT) |
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#define | EDMA_TCD_CDF_NOLINK_CITER(val) (((val) << EDMA_TCD_CDF_NOLINK_CITER_SHIFT) & EDMA_TCD_CDF_NOLINK_CITER_MASK) |
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#define | EDMA_TCD_CDF_NOLINK_CITER_GET(reg) (((reg) & EDMA_TCD_CDF_NOLINK_CITER_MASK) >> EDMA_TCD_CDF_NOLINK_CITER_SHIFT) |
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#define | EDMA_TCD_BMF_BITERE_LINK (1 << 31) |
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#define | EDMA_TCD_BMF_BITER_SHIFT (16) |
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#define | EDMA_TCD_BMF_BITER_MASK (0x7FFF << EDMA_TCD_BMF_BITER_SHIFT) |
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#define | EDMA_TCD_BMF_BITER(val) (((val) << EDMA_TCD_BMF_BITER_SHIFT) & EDMA_TCD_BMF_BITER_MASK) |
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#define | EDMA_TCD_BMF_BITER_GET(reg) (((reg) & EDMA_TCD_BMF_BITER_MASK) >> EDMA_TCD_BMF_BITER_SHIFT) |
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#define | EDMA_TCD_BMF_BWC_SHIFT (14) |
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#define | EDMA_TCD_BMF_BWC_MASK (0x3 << EDMA_TCD_BMF_BWC_SHIFT) |
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#define | EDMA_TCD_BMF_BWC(val) (((val) << EDMA_TCD_BMF_BWC_SHIFT) & EDMA_TCD_BMF_BWC_MASK) |
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#define | EDMA_TCD_BMF_BWC_GET(reg) (((reg) & EDMA_TCD_BMF_BWC_MASK) >> EDMA_TCD_BMF_BWC_SHIFT) |
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#define | EDMA_TCD_BMF_MAJORLINKCH_SHIFT (8) |
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#define | EDMA_TCD_BMF_MAJORLINKCH_MASK (0x3F << EDMA_TCD_BMF_MAJORLINKCH_SHIFT) |
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#define | EDMA_TCD_BMF_MAJORLINKCH(val) (((val) << EDMA_TCD_BMF_MAJORLINKCH_SHIFT) & EDMA_TCD_BMF_MAJORLINKCH_MASK) |
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#define | EDMA_TCD_BMF_MAJORLINKCH_GET(reg) (((reg) & EDMA_TCD_BMF_MAJORLINKCH_MASK) >> EDMA_TCD_BMF_MAJORLINKCH_SHIFT) |
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#define | EDMA_TCD_BMF_DONE (1 << 7) |
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#define | EDMA_TCD_BMF_ACTIVE (1 << 6) |
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#define | EDMA_TCD_BMF_MAJORE_LINK (1 << 5) |
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#define | EDMA_TCD_BMF_E_SG (1 << 4) |
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#define | EDMA_TCD_BMF_D_REQ (1 << 3) |
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#define | EDMA_TCD_BMF_INT_HALF (1 << 2) |
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#define | EDMA_TCD_BMF_INT_MAJ (1 << 1) |
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#define | EDMA_TCD_BMF_START (1 << 0) |
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#define | EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT (25) |
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#define | EDMA_TCD_BMF_ALT_BITERLINKCH_MASK (0x3F << EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT) |
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#define | EDMA_TCD_BMF_ALT_BITERLINKCH(val) (((val) << EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT) & EDMA_TCD_BMF_ALT_BITERLINKCH_MASK) |
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#define | EDMA_TCD_BMF_ALT_BITERLINKCH_GET(reg) (((reg) & EDMA_TCD_BMF_ALT_BITERLINKCH_MASK) >> EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT) |
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#define | EDMA_TCD_BMF_ALT_BITER_SHIFT (16) |
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#define | EDMA_TCD_BMF_ALT_BITER_MASK (0x1FF << EDMA_TCD_BMF_ALT_BITER_SHIFT) |
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#define | EDMA_TCD_BMF_ALT_BITER(val) (((val) << EDMA_TCD_BMF_ALT_BITER_SHIFT) & EDMA_TCD_BMF_ALT_BITER_MASK) |
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#define | EDMA_TCD_BMF_ALT_BITER_GET(reg) (((reg) & EDMA_TCD_BMF_ALT_BITER_MASK) >> EDMA_TCD_BMF_ALT_BITER_SHIFT) |
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#define | EDMA_TCD_BMF_NOLINK_BITER_SHIFT (16) |
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#define | EDMA_TCD_BMF_NOLINK_BITER_MASK (0xFFFF << EDMA_TCD_BMF_NOLINK_BITER_SHIFT) |
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#define | EDMA_TCD_BMF_NOLINK_BITER(val) (((val) << EDMA_TCD_BMF_NOLINK_BITER_SHIFT) & EDMA_TCD_BMF_NOLINK_BITER_MASK) |
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#define | EDMA_TCD_BMF_NOLINK_BITER_GET(reg) (((reg) & EDMA_TCD_BMF_NOLINK_BITER_MASK) >> EDMA_TCD_BMF_NOLINK_BITER_SHIFT) |
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#define | EDMA_TCD_BITER_MASK 0x7fff |
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#define | EDMA_TCD_BITER_SIZE (EDMA_TCD_BITER_MASK + 1) |
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#define | EDMA_TCD_BITER_LINKED_MASK 0x1ff |
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#define | EDMA_TCD_BITER_LINKED_SIZE (EDMA_TCD_BITER_LINKED_MASK + 1) |
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#define | EDMA_TCD_LINK_AND_BITER(link, biter) (((link) << 9) + ((biter) & EDMA_TCD_BITER_LINKED_MASK)) |
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