HAL ETH Aliased Defines maintained for legacy purpose

Macros
#define	VLAN_TAG   ETH_VLAN_TAG
#define	MIN_ETH_PAYLOAD   ETH_MIN_ETH_PAYLOAD
#define	MAX_ETH_PAYLOAD   ETH_MAX_ETH_PAYLOAD
#define	JUMBO_FRAME_PAYLOAD   ETH_JUMBO_FRAME_PAYLOAD
#define	MACMIIAR_CR_MASK   ETH_MACMIIAR_CR_MASK
#define	MACCR_CLEAR_MASK   ETH_MACCR_CLEAR_MASK
#define	MACFCR_CLEAR_MASK   ETH_MACFCR_CLEAR_MASK
#define	DMAOMR_CLEAR_MASK   ETH_DMAOMR_CLEAR_MASK
#define	ETH_MMCCR   0x00000100U
#define	ETH_MMCRIR   0x00000104U
#define	ETH_MMCTIR   0x00000108U
#define	ETH_MMCRIMR   0x0000010CU
#define	ETH_MMCTIMR   0x00000110U
#define	ETH_MMCTGFSCCR   0x0000014CU
#define	ETH_MMCTGFMSCCR   0x00000150U
#define	ETH_MMCTGFCR   0x00000168U
#define	ETH_MMCRFCECR   0x00000194U
#define	ETH_MMCRFAECR   0x00000198U
#define	ETH_MMCRGUFCR   0x000001C4U
#define	ETH_MAC_TXFIFO_FULL   0x02000000U /* Tx FIFO full */
#define	ETH_MAC_TXFIFONOT_EMPTY   0x01000000U /* Tx FIFO not empty */
#define	ETH_MAC_TXFIFO_WRITE_ACTIVE   0x00400000U /* Tx FIFO write active */
#define	ETH_MAC_TXFIFO_IDLE   0x00000000U /* Tx FIFO read status: Idle */
#define	ETH_MAC_TXFIFO_READ   0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define	ETH_MAC_TXFIFO_WAITING   0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define	ETH_MAC_TXFIFO_WRITING   0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define	ETH_MAC_TRANSMISSION_PAUSE   0x00080000U /* MAC transmitter in pause */
#define	ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE   0x00000000U /* MAC transmit frame controller: Idle */
#define	ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING   0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define	ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define	ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING   0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define	ETH_MAC_MII_TRANSMIT_ACTIVE   0x00010000U /* MAC MII transmit engine active */
#define	ETH_MAC_RXFIFO_EMPTY   0x00000000U /* Rx FIFO fill level: empty */
#define	ETH_MAC_RXFIFO_BELOW_THRESHOLD   0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define	ETH_MAC_RXFIFO_ABOVE_THRESHOLD   0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define	ETH_MAC_RXFIFO_FULL   0x00000300U /* Rx FIFO fill level: full */
#define	ETH_MAC_READCONTROLLER_IDLE   0x00000000U /* Rx FIFO read controller IDLE state */
#define	ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U /* Rx FIFO read controller Reading frame data */
#define	ETH_MAC_READCONTROLLER_READING_STATUS   0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#define	ETH_MAC_READCONTROLLER_FLUSHING   0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define	ETH_MAC_RXFIFO_WRITE_ACTIVE   0x00000010U /* Rx FIFO write controller active */
#define	ETH_MAC_SMALL_FIFO_NOTACTIVE   0x00000000U /* MAC small FIFO read / write controllers not active */
#define	ETH_MAC_SMALL_FIFO_READ_ACTIVE   0x00000002U /* MAC small FIFO read controller active */
#define	ETH_MAC_SMALL_FIFO_WRITE_ACTIVE   0x00000004U /* MAC small FIFO write controller active */
#define	ETH_MAC_SMALL_FIFO_RW_ACTIVE   0x00000006U /* MAC small FIFO read / write controllers active */
#define	ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U /* MAC MII receive protocol engine active */

Detailed Description