RTEMS
6.1-rc1
bsps
include
grlib
grlib.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* COPYRIGHT (c) 2012
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* Aeroflex Gaisler
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GRLIB_H__
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#define __GRLIB_H__
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#include <stdbool.h>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* ESA MEMORY CONTROLLER */
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struct
mctrl_regs
{
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unsigned
int
mcfg1;
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unsigned
int
mcfg2;
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unsigned
int
mcfg3;
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};
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/* APB UART */
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struct
apbuart_regs
{
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volatile
unsigned
int
data;
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volatile
unsigned
int
status;
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volatile
unsigned
int
ctrl;
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volatile
unsigned
int
scaler;
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};
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/* IRQMP and IRQAMP interrupt controller timestamps */
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struct
irqmp_timestamp_regs
{
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volatile
unsigned
int
counter;
/* 0x00 */
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volatile
unsigned
int
control
;
/* 0x04 */
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volatile
unsigned
int
assertion;
/* 0x08 */
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volatile
unsigned
int
ack;
/* 0x0c */
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};
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static
inline
bool
irqmp_has_timestamp(
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volatile
struct
irqmp_timestamp_regs
*irqmp_ts
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)
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{
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return
(irqmp_ts->control >> 27) > 0;
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}
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/* IRQMP and IRQAMP interrupt controllers */
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struct
irqmp_regs
{
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volatile
unsigned
int
ilevel;
/* 0x00 */
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volatile
unsigned
int
ipend;
/* 0x04 */
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volatile
unsigned
int
iforce;
/* 0x08 */
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volatile
unsigned
int
iclear;
/* 0x0c */
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volatile
unsigned
int
mpstat;
/* 0x10 */
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volatile
unsigned
int
bcast;
/* 0x14 */
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volatile
unsigned
int
notused02;
/* 0x18 */
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volatile
unsigned
int
wdgctrl;
/* 0x1c */
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volatile
unsigned
int
ampctrl;
/* 0x20 */
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volatile
unsigned
int
icsel[2];
/* 0x24,0x28 */
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volatile
unsigned
int
notused13;
/* 0x2c */
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volatile
unsigned
int
notused20;
/* 0x30 */
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volatile
unsigned
int
notused21;
/* 0x34 */
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volatile
unsigned
int
notused22;
/* 0x38 */
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volatile
unsigned
int
notused23;
/* 0x3c */
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volatile
unsigned
int
mask[16];
/* 0x40 */
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volatile
unsigned
int
force[16];
/* 0x80 */
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/* Extended IRQ registers */
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volatile
unsigned
int
intid[16];
/* 0xc0 */
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volatile
struct
irqmp_timestamp_regs
timestamp[16];
/* 0x100 */
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volatile
unsigned
int
resetaddr[4];
/* 0x200 */
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volatile
unsigned
int
resv0[12];
/* 0x210 - 0x23C */
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volatile
unsigned
int
pboot;
/* 0x240 */
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volatile
unsigned
int
resv1[47];
/* 0x244 - 0x2FC */
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volatile
unsigned
int
irqmap[8];
/* 0x300 - 0x31C */
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volatile
unsigned
int
resv2[824];
/* 0x320 - 0x1000 */
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};
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/* GPTIMER Timer instance */
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struct
gptimer_timer_regs
{
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volatile
unsigned
int
value;
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volatile
unsigned
int
reload;
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volatile
unsigned
int
ctrl;
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volatile
unsigned
int
notused;
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};
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#define GPTIMER_TIMER_CTRL_EN 0x00000001U
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#define GPTIMER_TIMER_CTRL_RS 0x00000002U
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#define GPTIMER_TIMER_CTRL_LD 0x00000004U
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#define GPTIMER_TIMER_CTRL_IE 0x00000008U
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#define GPTIMER_TIMER_CTRL_IP 0x00000010U
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#define GPTIMER_TIMER_CTRL_CH 0x00000020U
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#define GPTIMER_TIMER_CTRL_DH 0x00000040U
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/* GPTIMER common registers */
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struct
gptimer_regs
{
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volatile
unsigned
int
scaler_value;
/* common timer registers */
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volatile
unsigned
int
scaler_reload;
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volatile
unsigned
int
cfg;
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volatile
unsigned
int
notused;
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struct
gptimer_timer_regs
timer[7];
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};
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/* GRGPIO GPIO */
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struct
grgpio_regs
{
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volatile
unsigned
int
data;
/* 0x00 I/O port data register */
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volatile
unsigned
int
output;
/* 0x04 I/O port output register */
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volatile
unsigned
int
dir;
/* 0x08 I/O port direction register */
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volatile
unsigned
int
imask;
/* 0x0C Interrupt mask register */
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volatile
unsigned
int
ipol;
/* 0x10 Interrupt polarity register */
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volatile
unsigned
int
iedge;
/* 0x14 Interrupt edge register */
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volatile
unsigned
int
bypass;
/* 0x18 Bypass register */
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volatile
unsigned
int
cap;
/* 0x1C Capability register */
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volatile
unsigned
int
irqmap[4];
/* 0x20 - 0x2C Interrupt map registers */
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volatile
unsigned
int
res_30;
/* 0x30 Reserved */
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volatile
unsigned
int
res_34;
/* 0x34 Reserved */
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volatile
unsigned
int
res_38;
/* 0x38 Reserved */
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volatile
unsigned
int
res_3C;
/* 0x3C Reserved */
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volatile
unsigned
int
iavail;
/* 0x40 Interrupt available register */
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volatile
unsigned
int
iflag;
/* 0x44 Interrupt flag register */
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volatile
unsigned
int
res_48;
/* 0x48 Reserved */
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volatile
unsigned
int
pulse;
/* 0x4C Pulse register */
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volatile
unsigned
int
res_50;
/* 0x50 Reserved */
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volatile
unsigned
int
output_or;
/* 0x54 I/O port output register, logical-OR */
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volatile
unsigned
int
dir_or;
/* 0x58 I/O port direction register, logical-OR */
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volatile
unsigned
int
imask_or;
/* 0x5C Interrupt mask register, logical-OR */
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volatile
unsigned
int
res_60;
/* 0x60 Reserved */
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volatile
unsigned
int
output_and;
/* 0x64 I/O port output register, logical-AND */
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volatile
unsigned
int
dir_and;
/* 0x68 I/O port direction register, logical-AND */
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volatile
unsigned
int
imask_and;
/* 0x6C Interrupt mask register, logical-AND */
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volatile
unsigned
int
res_70;
/* 0x70 Reserved */
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volatile
unsigned
int
output_xor;
/* 0x74 I/O port output register, logical-XOR */
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volatile
unsigned
int
dir_xor;
/* 0x78 I/O port direction register, logical-XOR */
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volatile
unsigned
int
imask_xor;
/* 0x7C Interrupt mask register, logical-XOR */
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};
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/* L2C - Level 2 Cache Controller registers */
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struct
l2c_regs
{
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volatile
unsigned
int
control
;
/* 0x00 Control register */
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volatile
unsigned
int
status;
/* 0x04 Status register */
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volatile
unsigned
int
flush_mem_addr;
/* 0x08 Flush (Memory address) */
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volatile
unsigned
int
flush_set_index;
/* 0x0c Flush (set, index) */
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volatile
unsigned
int
access_counter;
/* 0x10 */
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volatile
unsigned
int
hit_counter;
/* 0x14 */
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volatile
unsigned
int
bus_cycle_counter;
/* 0x18 */
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volatile
unsigned
int
bus_usage_counter;
/* 0x1c */
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volatile
unsigned
int
error_status_control;
/* 0x20 Error status/control */
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volatile
unsigned
int
error_addr;
/* 0x24 Error address */
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volatile
unsigned
int
tag_check_bit;
/* 0x28 TAG-check-bit */
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volatile
unsigned
int
data_check_bit;
/* 0x2c Data-check-bit */
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volatile
unsigned
int
scrub_control_status;
/* 0x30 Scrub Control/Status */
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volatile
unsigned
int
scrub_delay;
/* 0x34 Scrub Delay */
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volatile
unsigned
int
error_injection;
/* 0x38 Error injection */
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volatile
unsigned
int
access_control;
/* 0x3c Access control */
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volatile
unsigned
int
reserved_40[16];
/* 0x40 Reserved */
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volatile
unsigned
int
mtrr[32];
/* 0x80 - 0xFC MTRR registers */
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volatile
unsigned
int
reserved_100[131008];
/* 0x100 Reserved */
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volatile
unsigned
int
diag_iface_tag[16384];
/* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
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volatile
unsigned
int
reserved_90000[376832];
/* 0x90000 Reserved */
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volatile
unsigned
int
diag_iface_data[524288];
/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif
apbuart_regs
Definition:
grlib.h:60
control
Definition:
intercom.c:87
gptimer_regs
Definition:
grlib.h:129
gptimer_timer_regs
Definition:
grlib.h:113
grgpio_regs
Definition:
grlib.h:138
irqmp_regs
Definition:
grlib.h:83
irqmp_timestamp_regs
Definition:
grlib.h:68
l2c_regs
Definition:
grlib.h:171
mctrl_regs
Definition:
grlib.h:53
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