RTEMS 6.1-rc1
griommu.h
1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/*
4 * GRIOMMU Driver Interface
5 *
6 * COPYRIGHT (c) 2017
7 * Cobham Gaisler AB
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 * OVERVIEW
31 * ========
32 * This driver controls the GRIOMMU device located
33 * at an on-chip AMBA.
34 */
35
36#ifndef __GRIOMMU_H__
37#define __GRIOMMU_H__
38
39#include <stdint.h>
40#include <stdio.h>
41
42#ifdef __cplusplus
43extern "C" {
44#endif
45
46extern void griommu_register_drv(void);
47
48#define GRIOMMU_ERR_OK 0
49#define GRIOMMU_ERR_NOINIT -1
50#define GRIOMMU_ERR_EINVAL -2
51#define GRIOMMU_ERR_IMPLEMENTED -3
52#define GRIOMMU_ERR_NOTFOUND -4
53
54/* Size of APV (has to be divided by page size in bytes) */
55#define GRIOMMU_APV_SIZE 0x20000000
56
57/* Alignment of APV */
58#define GRIOMMU_APV_ALIGN 0x10
59
60/* IOMMU APV allocation helper functions */
61extern void * griommu_apv_new(void);
62extern void griommu_apv_delete(void * apv);
63
64/* IOMMU Master Setup */
65
66/* IOMMU Master find */
67/*
68 * GRIOMMU MASTER register fields
69 */
70#define MASTER_VENDOR (0xff << MASTER_VENDOR_BIT)
71#define MASTER_DEVICE (0xfff << MASTER_DEVICE_BIT)
72#define MASTER_BS (0x1 << MASTER_BS_BIT)
73#define MASTER_GROUP (0xf << MASTER_GROUP_BIT)
74
75#define MASTER_VENDOR_BIT 24
76#define MASTER_DEVICE_BIT 12
77#define MASTER_BS_BIT 4
78#define MASTER_GROUP_BIT 0
79
80#define GRIOMMU_OPTIONS_BUS0 0
81#define GRIOMMU_OPTIONS_BUS1 1
82extern int griommu_master_setup(int master, int group, int options);
83extern int griommu_master_find(int vendor, int device, int instance);
84extern int griommu_master_info(int master, uint32_t * info);
85#define griommu_get_master_vendor(info) \
86 ((info & MASTER_VENDOR) >> MASTER_VENDOR_BIT)
87#define griommu_get_master_device(info) \
88 ((info & MASTER_DEVICE) >> MASTER_DEVICE_BIT)
89#define griommu_get_master_routing(info) \
90 ((info & MASTER_BS) >> MASTER_BS_BIT)
91#define griommu_get_master_group(info) \
92 ((info & MASTER_GROUP) >> MASTER_GROUP_BIT)
93
94/* IOMMU Group Setup */
95#define GRIOMMU_OPTIONS_GROUP_PASSTHROUGH 2
96#define GRIOMMU_OPTIONS_GROUP_ENABLE 1
97#define GRIOMMU_OPTIONS_GROUP_DISABLE 0
98extern int griommu_group_setup(int group, void * apv, int options);
99extern int griommu_group_info(int group, uint32_t * info);
100#define GRIOMMU_OPTIONS_APV_ALLOW 0x1
101#define GRIOMMU_OPTIONS_APV_DONTALLOW 0x0
102extern int griommu_group_apv_init(int group, int options);
103extern int griommu_group_apv_address_set(int group, uint32_t addr, int size,
104 int options);
105extern int griommu_group_apv_page_set(int group, int index, int size,
106 int options);
107extern int griommu_group_apv_flush(int group);
108
109/* IOMMU Setup */
110/*
111 * GRIOMMU CTRL register fields
112 */
113#define CTRL_PGSZ (0x7 << CTRL_PGSZ_BIT)
114#define CTRL_LB (0x1 << CTRL_LB_BIT)
115#define CTRL_SP (0x1 << CTRL_SP_BIT)
116#define CTRL_ITR (0xf << CTRL_ITR_BIT)
117#define CTRL_DP (0x1 << CTRL_DP_BIT)
118#define CTRL_SIV (0x1 << CTRL_SIV_BIT)
119#define CTRL_HPROT (0x3 << CTRL_HPROT_BIT)
120#define CTRL_AU (0x1 << CTRL_AU_BIT)
121#define CTRL_WP (0x1 << CTRL_WP_BIT)
122#define CTRL_DM (0x1 << CTRL_DM_BIT)
123#define CTRL_GS (0x1 << CTRL_GS_BIT)
124#define CTRL_CE (0x1 << CTRL_CE_BIT)
125#define CTRL_PM (0x3 << CTRL_PM_BIT)
126#define CTRL_PM_APV (0x0 << CTRL_PM_BIT)
127#define CTRL_PM_IOMMU (0x1 << CTRL_PM_BIT)
128#define CTRL_EN (0x1 << CTRL_EN_BIT)
129
130#define CTRL_PGSZ_BIT 18
131#define CTRL_LB_BIT 17
132#define CTRL_SP_BIT 16
133#define CTRL_ITR_BIT 12
134#define CTRL_DP_BIT 11
135#define CTRL_SIV_BIT 10
136#define CTRL_HPROT_BIT 8
137#define CTRL_AU_BIT 7
138#define CTRL_WP_BIT 6
139#define CTRL_DM_BIT 5
140#define CTRL_GS_BIT 4
141#define CTRL_CE_BIT 3
142#define CTRL_PM_BIT 1
143#define CTRL_EN_BIT 0
144
145#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS0 0
146#define GRIOMMU_OPTIONS_LOOKUPBUS_BUS1 CTRL_LB
147#define GRIOMMU_OPTIONS_CACHE_DISABLE 0
148#define GRIOMMU_OPTIONS_CACHE_ENABLE CTRL_CE
149#define GRIOMMU_OPTIONS_GROUPADDRESSING_DISABLE 0
150#define GRIOMMU_OPTIONS_GROUPADDRESSING_ENABLE CTRL_GS
151#define GRIOMMU_OPTIONS_WPROTONLY_DISABLE 0
152#define GRIOMMU_OPTIONS_WPROTONLY_ENABLE CTRL_WP
153#define GRIOMMU_OPTIONS_AHBUPDATE_DISABLE 0
154#define GRIOMMU_OPTIONS_AHBUPDATE_ENABLE CTRL_AU
155#define GRIOMMU_OPTIONS_PREFETCH_DISABLE CTRL_DP
156#define GRIOMMU_OPTIONS_PREFETCH_ENABLE 0
157#define GRIOMMU_OPTIONS_PAGESIZE_4KIB 0
158#define GRIOMMU_OPTIONS_PAGESIZE_8KIB (0x1 << CTRL_PGSZ_BIT)
159#define GRIOMMU_OPTIONS_PAGESIZE_16KIB (0x2 << CTRL_PGSZ_BIT)
160#define GRIOMMU_OPTIONS_PAGESIZE_32KIB (0x3 << CTRL_PGSZ_BIT)
161#define GRIOMMU_OPTIONS_PAGESIZE_64KIB (0x4 << CTRL_PGSZ_BIT)
162#define GRIOMMU_OPTIONS_PAGESIZE_128KIB (0x5 << CTRL_PGSZ_BIT)
163#define GRIOMMU_OPTIONS_PAGESIZE_256KIB (0x6 << CTRL_PGSZ_BIT)
164#define GRIOMMU_OPTIONS_PAGESIZE_512KIB (0x7 << CTRL_PGSZ_BIT)
165extern int griommu_setup(int options);
166extern int griommu_status(void);
167
168#define GRIOMMU_MODE_IOMMU 1
169#define GRIOMMU_MODE_GROUPAPV 0
170extern int griommu_enable(int mode);
171extern int griommu_disable(void);
172
173/* IOMMU APV setup */
174extern int griommu_apv_flush(void);
175extern int griommu_apv_init(void * apv, int options);
176extern int griommu_apv_address_set(void * apv, uint32_t addr, int size,
177 int options);
178extern int griommu_apv_page_set(void * apv, int index, int size, int options);
179
180/* GRIOMMU Interrupts */
181/* Function Interrupt-Code ISR callback prototype.
182 * arg - Custom arg provided by user
183 * access - AHB Access that failed
184 * status - Error status register of the GRIOMMU core
185 */
186typedef void (*griommu_isr_t)(void *arg, uint32_t access, uint32_t status);
187#define GRIOMMU_INTERRUPT_ALL (0x2f << 0)
188#define GRIOMMU_INTERRUPT_PARITY_ERROR (0x1 << 5)
189#define GRIOMMU_INTERRUPT_FLUSH_COMPLETED (0x1 << 3)
190#define GRIOMMU_INTERRUPT_FLUSH_START (0x1 << 2)
191#define GRIOMMU_INTERRUPT_ACCESS_DENIED (0x1 << 1)
192#define GRIOMMU_INTERRUPT_TRANSLATION_ERROR (0x1 << 0)
193extern int griommu_isr_register(griommu_isr_t isr, void * arg, int options);
194extern int griommu_isr_unregister(void);
195extern int griommu_interrupt_unmask(int options);
196extern int griommu_interrupt_mask(int options);
197
198extern int griommu_error_status(uint32_t * access);
199
200extern int griommu_print(void);
201
202#ifdef __cplusplus
203}
204#endif
205
206#endif /* __GRIOMMU_H__ */
size
unsigned size
Definition: tte.h:1
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