RTEMS 6.1-rc1
fsl_mecc.h
1/*
2 * Copyright 2019-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_MECC_H_
10#define _FSL_MECC_H_
11
12#include "fsl_common.h"
13
19/******************************************************************************
20 * Definitions.
21 *****************************************************************************/
22
26#define FSL_MECC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
29enum
30{
32};
33
39enum
40{
42 MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK,
44 MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK,
46 MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK,
48 MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK,
51 MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK,
53 MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK,
55 MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK,
57 MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK,
60 MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK,
62 MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK,
64 MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK,
66 MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK,
69 MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK,
71 MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK,
73 MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK,
75 MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK,
78};
79
85enum
86{
88 MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK,
90 MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK,
92 MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK,
94 MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK,
97 MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK,
99 MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK,
101 MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK,
103 MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK,
106 MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK,
108 MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK,
110 MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK,
112 MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK,
115 MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK,
117 MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK,
119 MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK,
121 MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK,
124};
125
131enum
132{
134 MECC_ERR_STATUS_SINGLE_ERR0_MASK,
136 MECC_ERR_STATUS_SINGLE_ERR1_MASK,
138 MECC_ERR_STATUS_SINGLE_ERR2_MASK,
140 MECC_ERR_STATUS_SINGLE_ERR3_MASK,
143 MECC_ERR_STATUS_MULTI_ERR0_MASK,
145 MECC_ERR_STATUS_MULTI_ERR1_MASK,
147 MECC_ERR_STATUS_MULTI_ERR2_MASK,
149 MECC_ERR_STATUS_MULTI_ERR3_MASK,
152 MECC_ERR_STATUS_STRB_ERR0_MASK,
154 MECC_ERR_STATUS_STRB_ERR1_MASK,
156 MECC_ERR_STATUS_STRB_ERR2_MASK,
158 MECC_ERR_STATUS_STRB_ERR3_MASK,
160 kMECC_AccessError0InterruptFlag = MECC_ERR_STATUS_ADDR_ERR0_MASK,
161 kMECC_AccessError1InterruptFlag = MECC_ERR_STATUS_ADDR_ERR1_MASK,
162 kMECC_AccessError2InterruptFlag = MECC_ERR_STATUS_ADDR_ERR2_MASK,
163 kMECC_AccessError3InterruptFlag = MECC_ERR_STATUS_ADDR_ERR3_MASK,
166};
167
169enum
170{
175};
176
178enum
179{
182};
183
185typedef struct _mecc_config
186{
193
197{
205
208{
214
215/*******************************************************************************
216 * APIs
217 ******************************************************************************/
218
219#if defined(__cplusplus)
220extern "C" {
221#endif
222
235
241void MECC_Deinit(MECC_Type *base);
242
249
250/* @} */
251
262static inline uint32_t MECC_GetStatusFlags(MECC_Type *base)
263{
264 return base->ERR_STATUS & (uint32_t)kMECC_AllInterruptsFlag;
265}
266
273static inline void MECC_ClearStatusFlags(MECC_Type *base, uint32_t mask)
274{
275 base->ERR_STATUS = mask;
276}
277
284static inline void MECC_EnableInterruptStatus(MECC_Type *base, uint32_t mask)
285{
286 base->ERR_STAT_EN |= mask;
287}
288
295static inline void MECC_DisableInterruptStatus(MECC_Type *base, uint32_t mask)
296{
297 base->ERR_STAT_EN &= ~mask;
298}
299
300/* @} */
301
313static inline void MECC_EnableInterrupts(MECC_Type *base, uint32_t mask)
314{
315 base->ERR_SIG_EN |= mask;
316}
317
324static inline void MECC_DisableInterrupts(MECC_Type *base, uint32_t mask)
325{
326 base->ERR_SIG_EN &= ~mask;
327}
328/* @} */
329
352 MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber);
353
370
386status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber);
387
390#if defined(__cplusplus)
391}
392#endif
393
396#endif
int32_t status_t
Type used for all status and error return values.
Definition: fsl_common.h:225
#define MAKE_STATUS(group, code)
Construct a status code value from a group and code number.
Definition: fsl_common.h:47
@ kStatusGroup_MECC
Definition: fsl_common.h:190
status_t MECC_GetMultiErrorInfo(MECC_Type *base, mecc_multi_error_info_t *info, uint8_t banknumber)
MECC module get multiple error information.
Definition: fsl_mecc.c:287
status_t MECC_GetSingleErrorInfo(MECC_Type *base, mecc_single_error_info_t *info, uint8_t banknumber)
MECC module get single error information.
Definition: fsl_mecc.c:190
struct _mecc_single_error_info mecc_single_error_info_t
MECC ocram single error information, including single error address, ECC code, error data and error b...
void MECC_Init(MECC_Type *base, mecc_config_t *config)
MECC module initialization function.
Definition: fsl_mecc.c:62
void MECC_Deinit(MECC_Type *base)
Deinitializes the MECC.
Definition: fsl_mecc.c:111
struct _mecc_multi_error_info mecc_multi_error_info_t
MECC ocram multiple error information, including multiple error address, ECC code,...
void MECC_GetDefaultConfig(mecc_config_t *config)
Sets the MECC configuration structure to default values.
Definition: fsl_mecc.c:117
struct _mecc_config mecc_config_t
MECC user configuration.
status_t MECC_ErrorInjection(MECC_Type *base, uint32_t lowerrordata, uint32_t higherrordata, uint8_t eccdata, uint8_t banknumber)
MECC module error injection.
Definition: fsl_mecc.c:139
@ kMECC_OcramBank0
Definition: fsl_mecc.h:171
@ kMECC_OcramBank2
Definition: fsl_mecc.h:173
@ kMECC_OcramBank3
Definition: fsl_mecc.h:174
@ kMECC_OcramBank1
Definition: fsl_mecc.h:172
@ kMECC_Instance1
Definition: fsl_mecc.h:181
@ kMECC_Instance0
Definition: fsl_mecc.h:180
@ kMECC_MultiError0InterruptStatusEnable
Definition: fsl_mecc.h:96
@ kMECC_SingleError2InterruptStatusEnable
Definition: fsl_mecc.h:91
@ kMECC_StrobeError2InterruptStatusEnable
Definition: fsl_mecc.h:109
@ kMECC_SingleError1InterruptStatusEnable
Definition: fsl_mecc.h:89
@ kMECC_AccessError1InterruptStatusEnable
Definition: fsl_mecc.h:116
@ kMECC_StrobeError0InterruptStatusEnable
Definition: fsl_mecc.h:105
@ kMECC_StrobeError1InterruptStatusEnable
Definition: fsl_mecc.h:107
@ kMECC_AccessError0InterruptStatusEnable
Definition: fsl_mecc.h:114
@ kMECC_SingleError3InterruptStatusEnable
Definition: fsl_mecc.h:93
@ kMECC_MultiError2InterruptStatusEnable
Definition: fsl_mecc.h:100
@ kMECC_StrobeError3InterruptStatusEnable
Definition: fsl_mecc.h:111
@ kMECC_AccessError3InterruptStatusEnable
Definition: fsl_mecc.h:120
@ kMECC_SingleError0InterruptStatusEnable
Definition: fsl_mecc.h:87
@ kMECC_AccessError2InterruptStatusEnable
Definition: fsl_mecc.h:118
@ kMECC_MultiError3InterruptStatusEnable
Definition: fsl_mecc.h:102
@ kMECC_AllInterruptsStatusEnable
Definition: fsl_mecc.h:123
@ kMECC_MultiError1InterruptStatusEnable
Definition: fsl_mecc.h:98
@ kMECC_StrobeError0InterruptEnable
Definition: fsl_mecc.h:59
@ kMECC_MultiError2InterruptEnable
Definition: fsl_mecc.h:54
@ kMECC_SingleError3InterruptEnable
Definition: fsl_mecc.h:47
@ kMECC_AccessError1InterruptEnable
Definition: fsl_mecc.h:70
@ kMECC_MultiError0InterruptEnable
Definition: fsl_mecc.h:50
@ kMECC_AccessError3InterruptEnable
Definition: fsl_mecc.h:74
@ kMECC_StrobeError2InterruptEnable
Definition: fsl_mecc.h:63
@ kMECC_MultiError1InterruptEnable
Definition: fsl_mecc.h:52
@ kMECC_SingleError0InterruptEnable
Definition: fsl_mecc.h:41
@ kMECC_SingleError2InterruptEnable
Definition: fsl_mecc.h:45
@ kMECC_StrobeError1InterruptEnable
Definition: fsl_mecc.h:61
@ kMECC_MultiError3InterruptEnable
Definition: fsl_mecc.h:56
@ kMECC_AccessError0InterruptEnable
Definition: fsl_mecc.h:68
@ kMECC_AllInterruptsEnable
Definition: fsl_mecc.h:77
@ kMECC_StrobeError3InterruptEnable
Definition: fsl_mecc.h:65
@ kMECC_AccessError2InterruptEnable
Definition: fsl_mecc.h:72
@ kMECC_SingleError1InterruptEnable
Definition: fsl_mecc.h:43
@ kMECC_AllInterruptsFlag
Definition: fsl_mecc.h:165
@ kMECC_SingleError3InterruptFlag
Definition: fsl_mecc.h:139
@ kMECC_AccessError0InterruptFlag
Definition: fsl_mecc.h:160
@ kMECC_AccessError2InterruptFlag
Definition: fsl_mecc.h:162
@ kMECC_AccessError3InterruptFlag
Definition: fsl_mecc.h:163
@ kMECC_StrobeError2InterruptFlag
Definition: fsl_mecc.h:155
@ kMECC_MultiError2InterruptFlag
Definition: fsl_mecc.h:146
@ kMECC_MultiError3InterruptFlag
Definition: fsl_mecc.h:148
@ kMECC_SingleError0InterruptFlag
Definition: fsl_mecc.h:133
@ kMECC_StrobeError0InterruptFlag
Definition: fsl_mecc.h:151
@ kMECC_AccessError1InterruptFlag
Definition: fsl_mecc.h:161
@ kMECC_StrobeError1InterruptFlag
Definition: fsl_mecc.h:153
@ kMECC_MultiError0InterruptFlag
Definition: fsl_mecc.h:142
@ kMECC_StrobeError3InterruptFlag
Definition: fsl_mecc.h:157
@ kMECC_MultiError1InterruptFlag
Definition: fsl_mecc.h:144
@ kMECC_SingleError2InterruptFlag
Definition: fsl_mecc.h:137
@ kMECC_SingleError1InterruptFlag
Definition: fsl_mecc.h:135
@ kStatus_MECC_BankMiss
Definition: fsl_mecc.h:31
Definition: MIMXRT1166_cm4.h:62480
MECC user configuration.
Definition: fsl_mecc.h:186
uint32_t Ocram2EndAddress
Definition: fsl_mecc.h:191
uint32_t Ocram2StartAddress
Definition: fsl_mecc.h:190
bool enableMecc
Definition: fsl_mecc.h:187
uint32_t Ocram1StartAddress
Definition: fsl_mecc.h:188
uint32_t Ocram1EndAddress
Definition: fsl_mecc.h:189
MECC ocram multiple error information, including multiple error address, ECC code,...
Definition: fsl_mecc.h:208
uint32_t multiErrorDataLow
Definition: fsl_mecc.h:210
uint8_t multiErrorEccCode
Definition: fsl_mecc.h:212
uint32_t multiErrorAddress
Definition: fsl_mecc.h:209
uint32_t multiErrorDataHigh
Definition: fsl_mecc.h:211
MECC ocram single error information, including single error address, ECC code, error data and error b...
Definition: fsl_mecc.h:197
uint32_t singleErrorPosLow
Definition: fsl_mecc.h:201
uint32_t singleErrorPosHigh
Definition: fsl_mecc.h:202
uint32_t singleErrorDataHigh
Definition: fsl_mecc.h:200
uint32_t singleErrorDataLow
Definition: fsl_mecc.h:199
uint32_t singleErrorAddress
Definition: fsl_mecc.h:198
uint8_t singleErrorEccCode
Definition: fsl_mecc.h:203
Definition: deflate.c:114