fsl_lpadc.h

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/*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _FSL_LPADC_H_
#define _FSL_LPADC_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 6, 1))
#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT)
 
#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT)
 
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
enum _lpadc_status_flags
{
    kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, 
    kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK,    
    kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, 
    kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK,    
};
 
enum _lpadc_interrupt_enable
{
    kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, 
    kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK,      
    kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, 
    kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK,      
#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
    kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, 
    kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL),   
    kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL),   
    kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL),   
    kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL),   
    kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL),   
    kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL),   
    kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL),   
    kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL),   
    kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL),   
    kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL),   
    kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), 
    kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), 
    kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), 
    kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), 
    kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), 
    kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), 
#endif                                                                        /* FSL_FEATURE_LPADC_HAS_TSTAT */
};
#else
enum _lpadc_status_flags
{
    kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, 
    kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, 
};
 
enum _lpadc_interrupt_enable
{
    kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, 
    kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK,      
};
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
 
#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
enum _lpadc_trigger_status_flags
{
    kLPADC_Trigger0InterruptedFlag  = 1UL << 0UL,  
    kLPADC_Trigger1InterruptedFlag  = 1UL << 1UL,  
    kLPADC_Trigger2InterruptedFlag  = 1UL << 2UL,  
    kLPADC_Trigger3InterruptedFlag  = 1UL << 3UL,  
    kLPADC_Trigger4InterruptedFlag  = 1UL << 4UL,  
    kLPADC_Trigger5InterruptedFlag  = 1UL << 5UL,  
    kLPADC_Trigger6InterruptedFlag  = 1UL << 6UL,  
    kLPADC_Trigger7InterruptedFlag  = 1UL << 7UL,  
    kLPADC_Trigger8InterruptedFlag  = 1UL << 8UL,  
    kLPADC_Trigger9InterruptedFlag  = 1UL << 9UL,  
    kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, 
    kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, 
    kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, 
    kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, 
    kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, 
    kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, 
    kLPADC_Trigger0CompletedFlag = 1UL << 16UL,  
    kLPADC_Trigger1CompletedFlag = 1UL << 17UL,  
    kLPADC_Trigger2CompletedFlag = 1UL << 18UL,  
    kLPADC_Trigger3CompletedFlag = 1UL << 19UL,  
    kLPADC_Trigger4CompletedFlag = 1UL << 20UL,  
    kLPADC_Trigger5CompletedFlag = 1UL << 21UL,  
    kLPADC_Trigger6CompletedFlag = 1UL << 22UL,  
    kLPADC_Trigger7CompletedFlag = 1UL << 23UL,  
    kLPADC_Trigger8CompletedFlag = 1UL << 24UL,  
    kLPADC_Trigger9CompletedFlag = 1UL << 25UL,  
    kLPADC_Trigger10CompletedFlag = 1UL << 26UL, 
    kLPADC_Trigger11CompletedFlag = 1UL << 27UL, 
    kLPADC_Trigger12CompletedFlag = 1UL << 28UL, 
    kLPADC_Trigger13CompletedFlag = 1UL << 29UL, 
    kLPADC_Trigger14CompletedFlag = 1UL << 30UL, 
    kLPADC_Trigger15CompletedFlag = 1UL << 31UL, 
};
#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */
 
typedef enum _lpadc_sample_scale_mode
{
    kLPADC_SamplePartScale =
        0U, 
    kLPADC_SampleFullScale = 1U, 
} lpadc_sample_scale_mode_t;
 
typedef enum _lpadc_sample_channel_mode
{
    kLPADC_SampleChannelSingleEndSideA = 0U, 
    kLPADC_SampleChannelSingleEndSideB = 1U, 
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
    kLPADC_SampleChannelDiffBothSideAB = 2U, 
    kLPADC_SampleChannelDiffBothSideBA = 3U, 
#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
    kLPADC_SampleChannelDiffBothSide = 2U, 
    kLPADC_SampleChannelDualSingleEndBothSide =
        3U, 
#endif
} lpadc_sample_channel_mode_t;
 
typedef enum _lpadc_hardware_average_mode
{
    kLPADC_HardwareAverageCount1   = 0U, 
    kLPADC_HardwareAverageCount2   = 1U, 
    kLPADC_HardwareAverageCount4   = 2U, 
    kLPADC_HardwareAverageCount8   = 3U, 
    kLPADC_HardwareAverageCount16  = 4U, 
    kLPADC_HardwareAverageCount32  = 5U, 
    kLPADC_HardwareAverageCount64  = 6U, 
    kLPADC_HardwareAverageCount128 = 7U, 
#if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \
     (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4))
    kLPADC_HardwareAverageCount256  = 8U,  
    kLPADC_HardwareAverageCount512  = 9U,  
    kLPADC_HardwareAverageCount1024 = 10U, 
#endif                                     /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */
} lpadc_hardware_average_mode_t;
 
typedef enum _lpadc_sample_time_mode
{
    kLPADC_SampleTimeADCK3   = 0U, 
    kLPADC_SampleTimeADCK5   = 1U, 
    kLPADC_SampleTimeADCK7   = 2U, 
    kLPADC_SampleTimeADCK11  = 3U, 
    kLPADC_SampleTimeADCK19  = 4U, 
    kLPADC_SampleTimeADCK35  = 5U, 
    kLPADC_SampleTimeADCK67  = 6U, 
    kLPADC_SampleTimeADCK131 = 7U, 
} lpadc_sample_time_mode_t;
 
typedef enum _lpadc_hardware_compare_mode
{
    kLPADC_HardwareCompareDisabled        = 0U, 
    kLPADC_HardwareCompareStoreOnTrue     = 2U, 
    kLPADC_HardwareCompareRepeatUntilTrue = 3U, 
} lpadc_hardware_compare_mode_t;
 
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
typedef enum _lpadc_conversion_resolution_mode
{
    kLPADC_ConversionResolutionStandard = 0U, 
    kLPADC_ConversionResolutionHigh = 1U,     
} lpadc_conversion_resolution_mode_t;
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
 
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
typedef enum _lpadc_conversion_average_mode
{
    kLPADC_ConversionAverage1   = 0U, 
    kLPADC_ConversionAverage2   = 1U, 
    kLPADC_ConversionAverage4   = 2U, 
    kLPADC_ConversionAverage8   = 3U, 
    kLPADC_ConversionAverage16  = 4U, 
    kLPADC_ConversionAverage32  = 5U, 
    kLPADC_ConversionAverage64  = 6U, 
    kLPADC_ConversionAverage128 = 7U, 
#if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \
     (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4))
    kLPADC_ConversionAverage256  = 8U,  
    kLPADC_ConversionAverage512  = 9U,  
    kLPADC_ConversionAverage1024 = 10U, 
#endif                                  /* FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH */
} lpadc_conversion_average_mode_t;
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
 
typedef enum _lpadc_reference_voltage_mode
{
    kLPADC_ReferenceVoltageAlt1 = 0U, 
    kLPADC_ReferenceVoltageAlt2 = 1U, 
    kLPADC_ReferenceVoltageAlt3 = 2U, 
} lpadc_reference_voltage_source_t;
 
typedef enum _lpadc_power_level_mode
{
    kLPADC_PowerLevelAlt1 = 0U, 
    kLPADC_PowerLevelAlt2 = 1U, 
    kLPADC_PowerLevelAlt3 = 2U, 
    kLPADC_PowerLevelAlt4 = 3U, 
} lpadc_power_level_mode_t;
 
#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE)
typedef enum _lpadc_offset_calibration_mode
{
    kLPADC_OffsetCalibration12bitMode = 0U, 
    kLPADC_OffsetCalibration16bitMode = 1U, 
} lpadc_offset_calibration_mode_t;
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
 
typedef enum _lpadc_trigger_priority_policy
{
    kLPADC_TriggerPriorityPreemptImmediately = 0U, 
    kLPADC_TriggerPriorityPreemptSoftly = 1U, 
#if defined(FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY) && FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY
    kLPADC_TriggerPriorityPreemptSubsequently = 2U, 
#endif                                              /* FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY */
} lpadc_trigger_priority_policy_t;
 
typedef struct
{
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
    bool enableInternalClock; 
#endif                        /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
    bool enableVref1LowVoltage; 
#endif                          /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
    bool enableInDozeMode; 
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
    lpadc_conversion_average_mode_t conversionAverageMode; 
#endif                                                     /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
    bool enableAnalogPreliminary; 
    uint32_t powerUpDelay; 
    lpadc_reference_voltage_source_t referenceVoltageSource; 
#if !(defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 0))
    lpadc_power_level_mode_t powerLevelMode;               
#endif                                                     /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */
    lpadc_trigger_priority_policy_t triggerPriorityPolicy; 
    bool enableConvPause; 
    uint32_t convPauseDelay; 
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
    /* for FIFO0. */
    uint32_t FIFO0Watermark; 
    /* for FIFO1. */
    uint32_t FIFO1Watermark; 
#else
    /* for FIFO. */
    uint32_t FIFOWatermark; 
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
} lpadc_config_t;
 
typedef struct
{
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
    lpadc_sample_scale_mode_t sampleScaleMode; 
#endif                                         /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE
    lpadc_sample_scale_mode_t channelBScaleMode;   
#endif                                             /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */
    lpadc_sample_channel_mode_t sampleChannelMode; 
    uint32_t channelNumber;                        
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH
    uint32_t channelBNumber; 
#endif
    uint32_t chainedNextCommandNumber; 
    bool enableAutoChannelIncrement;   
    uint32_t loopCount; 
    lpadc_hardware_average_mode_t hardwareAverageMode; 
    lpadc_sample_time_mode_t sampleTimeMode;           
    lpadc_hardware_compare_mode_t hardwareCompareMode; 
    uint32_t hardwareCompareValueHigh; 
    uint32_t hardwareCompareValueLow;  
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
    lpadc_conversion_resolution_mode_t conversionResolutionMode; 
#endif                                                           /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
    bool enableWaitTrigger; 
#endif                      /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN
    bool enableChannelB; 
#endif                   /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */
} lpadc_conv_command_config_t;
 
typedef struct
{
    uint32_t targetCommandId; 
    uint32_t delayPower;      
    uint32_t priority; 
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
    uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */
    uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */
#endif                          /* FSL_FEATURE_LPADC_FIFO_COUNT */
    bool enableHardwareTrigger; 
} lpadc_conv_trigger_config_t;
 
typedef struct
{
    uint32_t commandIdSource; 
    uint32_t loopCountIndex;  
    uint32_t triggerIdSource; 
    uint16_t convValue;       
} lpadc_conv_result_t;
 
#if defined(__cplusplus)
extern "C" {
#endif
 
/*******************************************************************************
 * API
 ******************************************************************************/
void LPADC_Init(ADC_Type *base, const lpadc_config_t *config);
 
void LPADC_GetDefaultConfig(lpadc_config_t *config);
 
void LPADC_Deinit(ADC_Type *base);
 
static inline void LPADC_Enable(ADC_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL |= ADC_CTRL_ADCEN_MASK;
    }
    else
    {
        base->CTRL &= ~ADC_CTRL_ADCEN_MASK;
    }
}
 
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
static inline void LPADC_DoResetFIFO0(ADC_Type *base)
{
    base->CTRL |= ADC_CTRL_RSTFIFO0_MASK;
}
 
static inline void LPADC_DoResetFIFO1(ADC_Type *base)
{
    base->CTRL |= ADC_CTRL_RSTFIFO1_MASK;
}
#else
static inline void LPADC_DoResetFIFO(ADC_Type *base)
{
    base->CTRL |= ADC_CTRL_RSTFIFO_MASK;
}
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
 
static inline void LPADC_DoResetConfig(ADC_Type *base)
{
    base->CTRL |= ADC_CTRL_RST_MASK;
    base->CTRL &= ~ADC_CTRL_RST_MASK;
}
 
/* @} */
 
static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)
{
    return base->STAT;
}
 
static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
{
    base->STAT = mask;
}
 
#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT)
static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base)
{
    return base->TSTAT;
}
 
static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)
{
    base->TSTAT = mask;
}
#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */
 
/* @} */
 
static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
{
    base->IE |= mask;
}
 
static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
{
    base->IE &= ~mask;
}
 
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable)
{
    if (enable)
    {
        base->DE |= ADC_DE_FWMDE0_MASK;
    }
    else
    {
        base->DE &= ~ADC_DE_FWMDE0_MASK;
    }
}
 
static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable)
{
    if (enable)
    {
        base->DE |= ADC_DE_FWMDE1_MASK;
    }
    else
    {
        base->DE &= ~ADC_DE_FWMDE1_MASK;
    }
}
#else
static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
{
    if (enable)
    {
        base->DE |= ADC_DE_FWMDE_MASK;
    }
    else
    {
        base->DE &= ~ADC_DE_FWMDE_MASK;
    }
}
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
       /* @} */
 
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index)
{
    return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT;
}
 
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
#else
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
{
    return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT;
}
 
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
 
void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config);
 
void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config);
 
static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)
{
    /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */
    base->SWTRIG = triggerIdMask;
}
 
#if defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL
static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable)
{
    if (enable)
    {
        base->TCTRL[triggerId] |= ADC_TCTRL_CMD_SEL_MASK;
    }
    else
    {
        base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK;
    }
}
#endif /* FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/
 
void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config);
 
void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config);
 
#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
void LPADC_EnableCalibration(ADC_Type *base, bool enable);
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)
{
    base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT;
}
 
void LPADC_DoAutoCalibration(ADC_Type *base);
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
 
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
{
    base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB);
}
#else
static inline void LPADC_SetOffset12BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
{
    base->OFSTRIM12 = ADC_OFSTRIM12_OFSTRIM_A(valueA) | ADC_OFSTRIM12_OFSTRIM_A(valueB);
}
 
static inline void LPADC_SetOffset16BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
{
    base->OFSTRIM16 = ADC_OFSTRIM16_OFSTRIM_A(valueA) | ADC_OFSTRIM16_OFSTRIM_B(valueB);
}
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
 
static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL |= ADC_CTRL_CALOFS_MASK;
    }
    else
    {
        base->CTRL &= ~ADC_CTRL_CALOFS_MASK;
    }
}
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode)
{
    base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode);
}
 
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
 
void LPADC_DoOffsetCalibration(ADC_Type *base);
 
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
void LPADC_DoAutoCalibration(ADC_Type *base);
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
 
/* @} */
 
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_LPADC_H_ */