RTEMS 6.1-rc1
fsl_gpio.h
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_GPIO_H_
10#define _FSL_GPIO_H_
11
12#include "fsl_common.h"
13
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
26#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
31{
35
38{
46
48typedef struct _gpio_pin_config
49{
51 uint8_t outputLogic;
55
56/*******************************************************************************
57 * API
58 ******************************************************************************/
59
60#if defined(__cplusplus)
61extern "C" {
62#endif
63
78void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
95void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
96
101static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
102{
103 GPIO_PinWrite(base, pin, output);
104}
105
112static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
113{
114#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1))
115 base->DR_SET = mask;
116#else
117 base->DR |= mask;
118#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */
119}
120
125static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
126{
127 GPIO_PortSet(base, mask);
128}
129
136static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
137{
138#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1))
139 base->DR_CLEAR = mask;
140#else
141 base->DR &= ~mask;
142#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */
143}
144
149static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
150{
151 GPIO_PortClear(base, mask);
152}
153
160static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
161{
162#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1))
163 base->DR_TOGGLE = mask;
164#else
165 base->DR ^= mask;
166#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */
167}
168
176static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
177{
178 assert(pin < 32U);
179
180 return (((base->DR) >> pin) & 0x1U);
181}
182
187static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
188{
189 return GPIO_PinRead(base, pin);
190}
205static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)
206{
207 assert(pin < 32U);
208
209 return (uint8_t)(((base->PSR) >> pin) & 0x1U);
210}
211
216static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)
217{
218 return GPIO_PinReadPadStatus(base, pin);
219}
220
236void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode);
237
242static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
243{
244 GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode);
245}
246
253static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask)
254{
255 base->IMR |= mask;
256}
257
264static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask)
265{
266 GPIO_PortEnableInterrupts(base, mask);
267}
268
275static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask)
276{
277 base->IMR &= ~mask;
278}
279
284static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask)
285{
286 GPIO_PortDisableInterrupts(base, mask);
287}
288
295static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
296{
297 return base->ISR;
298}
299
306static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
307{
308 return GPIO_PortGetInterruptFlags(base);
309}
310
318static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
319{
320 base->ISR = mask;
321}
322
330static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
331{
332 GPIO_PortClearInterruptFlags(base, mask);
333}
336#if defined(__cplusplus)
337}
338#endif
339
344#endif /* _FSL_GPIO_H_*/
_gpio_pin_direction
GPIO direction definition.
Definition: fsl_gpio.h:31
void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
Sets the output level of the individual GPIO pin to logic 1 or 0.
Definition: fsl_gpio.c:115
uint8_t outputLogic
Definition: fsl_gpio.h:51
struct _gpio_pin_config gpio_pin_config_t
GPIO Init structure definition.
void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
Initializes the GPIO peripheral according to the specified parameters in the initConfig.
Definition: fsl_gpio.c:75
enum _gpio_interrupt_mode gpio_interrupt_mode_t
GPIO interrupt mode definition.
void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
Sets the current pin interrupt mode.
Definition: fsl_gpio.c:144
gpio_interrupt_mode_t interruptMode
Definition: fsl_gpio.h:53
gpio_pin_direction_t direction
Definition: fsl_gpio.h:50
enum _gpio_pin_direction gpio_pin_direction_t
GPIO direction definition.
_gpio_interrupt_mode
GPIO interrupt mode definition.
Definition: fsl_gpio.h:38
@ kGPIO_DigitalOutput
Definition: fsl_gpio.h:33
@ kGPIO_DigitalInput
Definition: fsl_gpio.h:32
@ kGPIO_IntFallingEdge
Definition: fsl_gpio.h:43
@ kGPIO_NoIntmode
Definition: fsl_gpio.h:39
@ kGPIO_IntHighLevel
Definition: fsl_gpio.h:41
@ kGPIO_IntRisingEdge
Definition: fsl_gpio.h:42
@ kGPIO_IntRisingOrFallingEdge
Definition: fsl_gpio.h:44
@ kGPIO_IntLowLevel
Definition: fsl_gpio.h:40
Definition: MIMXRT1052.h:22478
GPIO Init structure definition.
Definition: fsl_gpio.h:49