fsl_flexspi.h

/*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef __FSL_FLEXSPI_H_
#define __FSL_FLEXSPI_H_
 
#include <stddef.h>
#include "fsl_device_registers.h"
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
 
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)                                                              \
    (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
     FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
 
enum
{
    kStatus_FLEXSPI_Busy                     = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), 
    kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), 
    kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2),   
    kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3),    
};
 
enum
{
    kFLEXSPI_Command_STOP           = 0x00U, 
    kFLEXSPI_Command_SDR            = 0x01U, 
    kFLEXSPI_Command_RADDR_SDR      = 0x02U, 
    kFLEXSPI_Command_CADDR_SDR      = 0x03U, 
    kFLEXSPI_Command_MODE1_SDR      = 0x04U, 
    kFLEXSPI_Command_MODE2_SDR      = 0x05U, 
    kFLEXSPI_Command_MODE4_SDR      = 0x06U, 
    kFLEXSPI_Command_MODE8_SDR      = 0x07U, 
    kFLEXSPI_Command_WRITE_SDR      = 0x08U, 
    kFLEXSPI_Command_READ_SDR       = 0x09U, 
    kFLEXSPI_Command_LEARN_SDR      = 0x0AU, 
    kFLEXSPI_Command_DATSZ_SDR      = 0x0BU, 
    kFLEXSPI_Command_DUMMY_SDR      = 0x0CU, 
    kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, 
    kFLEXSPI_Command_DDR            = 0x21U, 
    kFLEXSPI_Command_RADDR_DDR      = 0x22U, 
    kFLEXSPI_Command_CADDR_DDR      = 0x23U, 
    kFLEXSPI_Command_MODE1_DDR      = 0x24U, 
    kFLEXSPI_Command_MODE2_DDR      = 0x25U, 
    kFLEXSPI_Command_MODE4_DDR      = 0x26U, 
    kFLEXSPI_Command_MODE8_DDR      = 0x27U, 
    kFLEXSPI_Command_WRITE_DDR      = 0x28U, 
    kFLEXSPI_Command_READ_DDR       = 0x29U, 
    kFLEXSPI_Command_LEARN_DDR      = 0x2AU, 
    kFLEXSPI_Command_DATSZ_DDR      = 0x2BU, 
    kFLEXSPI_Command_DUMMY_DDR      = 0x2CU, 
    kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, 
    kFLEXSPI_Command_JUMP_ON_CS = 0x1FU,     
};
 
typedef enum _flexspi_pad
{
    kFLEXSPI_1PAD = 0x00U, 
    kFLEXSPI_2PAD = 0x01U, 
    kFLEXSPI_4PAD = 0x02U, 
    kFLEXSPI_8PAD = 0x03U, 
} flexspi_pad_t;
 
typedef enum _flexspi_flags
{
    kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, 
#if defined(FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN) && FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN
    kFLEXSPI_AhbBusErrorFlag = FLEXSPI_INTEN_AHBBUSERROREN_MASK, 
#else
    kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, 
#endif
    kFLEXSPI_SckStoppedBecauseTxEmptyFlag =
        FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, 
    kFLEXSPI_SckStoppedBecauseRxFullFlag =
        FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, 
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
    kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, 
#endif
    kFLEXSPI_IpTxFifoWatermarkEmptyFlag     = FLEXSPI_INTEN_IPTXWEEN_MASK, 
    kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, 
    kFLEXSPI_AhbCommandSequenceErrorFlag =
        FLEXSPI_INTEN_AHBCMDERREN_MASK,                                  
    kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, 
    kFLEXSPI_AhbCommandGrantTimeoutFlag =
        FLEXSPI_INTEN_AHBCMDGEEN_MASK, 
    kFLEXSPI_IpCommandGrantTimeoutFlag =
        FLEXSPI_INTEN_IPCMDGEEN_MASK, 
    kFLEXSPI_IpCommandExecutionDoneFlag =
        FLEXSPI_INTEN_IPCMDDONEEN_MASK,  
    kFLEXSPI_AllInterruptFlags = 0xFFFU, 
} flexspi_flags_t;
 
typedef enum _flexspi_read_sample_clock
{
    kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U,      
    kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U,      
    kFLEXSPI_ReadSampleClkLoopbackFromSckPad      = 0x2U, 
    kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, 
} flexspi_read_sample_clock_t;
 
typedef enum _flexspi_cs_interval_cycle_unit
{
    kFLEXSPI_CsIntervalUnit1SckCycle   = 0x0U, 
    kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, 
} flexspi_cs_interval_cycle_unit_t;
 
typedef enum _flexspi_ahb_write_wait_unit
{
    kFLEXSPI_AhbWriteWaitUnit2AhbCycle     = 0x0U, 
    kFLEXSPI_AhbWriteWaitUnit8AhbCycle     = 0x1U, 
    kFLEXSPI_AhbWriteWaitUnit32AhbCycle    = 0x2U, 
    kFLEXSPI_AhbWriteWaitUnit128AhbCycle   = 0x3U, 
    kFLEXSPI_AhbWriteWaitUnit512AhbCycle   = 0x4U, 
    kFLEXSPI_AhbWriteWaitUnit2048AhbCycle  = 0x5U, 
    kFLEXSPI_AhbWriteWaitUnit8192AhbCycle  = 0x6U, 
    kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, 
} flexspi_ahb_write_wait_unit_t;
 
typedef enum _flexspi_ip_error_code
{
    kFLEXSPI_IpCmdErrorNoError               = 0x0U,    
    kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd       = 0x2U,    
    kFLEXSPI_IpCmdErrorUnknownOpCode         = 0x3U,    
    kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U,    
    kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U,    
    kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U,           
    kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, 
    kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss     = 0xFU, 
} flexspi_ip_error_code_t;
 
typedef enum _flexspi_ahb_error_code
{
    kFLEXSPI_AhbCmdErrorNoError            = 0x0U,    
    kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U,    
    kFLEXSPI_AhbCmdErrorUnknownOpCode         = 0x3U, 
    kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, 
    kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, 
    kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U,   
} flexspi_ahb_error_code_t;
 
typedef enum _flexspi_port
{
    kFLEXSPI_PortA1 = 0x0U, 
    kFLEXSPI_PortA2,        
#if !((defined(FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB)) && (FSL_FEATURE_FLEXSPI_NO_SUPPORT_PORTB))
    kFLEXSPI_PortB1, 
    kFLEXSPI_PortB2, 
#endif
    kFLEXSPI_PortCount
} flexspi_port_t;
 
typedef enum _flexspi_arb_command_source
{
    kFLEXSPI_AhbReadCommand   = 0x0U,
    kFLEXSPI_AhbWriteCommand  = 0x1U,
    kFLEXSPI_IpCommand        = 0x2U,
    kFLEXSPI_SuspendedCommand = 0x3U,
} flexspi_arb_command_source_t;
 
typedef enum _flexspi_command_type
{
    kFLEXSPI_Command, 
    kFLEXSPI_Config,  
    kFLEXSPI_Read,    /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */
    kFLEXSPI_Write,   /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */
} flexspi_command_type_t;
 
typedef struct _flexspi_ahbBuffer_config
{
    uint8_t priority;    
    uint8_t masterIndex; 
    uint16_t bufferSize; 
    bool enablePrefetch; 
} flexspi_ahbBuffer_config_t;
 
typedef struct _flexspi_config
{
    flexspi_read_sample_clock_t rxSampleClock; 
    bool enableSckFreeRunning;                 
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
    bool enableCombination; 
#endif
    bool enableDoze;            
    bool enableHalfSpeedAccess; 
#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB) && FSL_FEATURE_FLEXSPI_SUPPORT_SEPERATE_RXCLKSRC_PORTB
    flexspi_read_sample_clock_t rxSampleClockPortB; 
#endif
#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF
    bool rxSampleClockDiff; 
#endif
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
    bool enableSckBDiffOpt; 
#endif
    bool enableSameConfigForAll; 
    uint16_t seqTimeoutCycle;    
    uint8_t ipGrantTimeoutCycle; 
    uint8_t txWatermark;         
    uint8_t rxWatermark;         
    struct
    {
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN)
        bool enableAHBWriteIpTxFifo; 
#endif
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ARDFEN)
        bool enableAHBWriteIpRxFifo; 
#endif
        uint8_t ahbGrantTimeoutCycle; 
        uint16_t ahbBusTimeoutCycle;  
        uint8_t resumeWaitCycle;      
        flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; 
        bool enableClearAHBBufferOpt; 
        bool enableReadAddressOpt;    
        bool enableAHBPrefetch;       
        bool enableAHBBufferable;     
        bool enableAHBCachable;       
    } ahbConfig;
} flexspi_config_t;
 
typedef struct _flexspi_device_config
{
    uint32_t flexspiRootClk; 
    bool isSck2Enabled;      
    uint32_t flashSize;      
#if defined(FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT) && (FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT)
    bool addressShift;                               
#endif                                               /* FSL_FEATURE_FLEXSPI_SUPPORT_ADDRESS_SHIFT */
    flexspi_cs_interval_cycle_unit_t CSIntervalUnit; 
    uint16_t CSInterval;                             
    uint8_t CSHoldTime;                              
    uint8_t CSSetupTime;                             
    uint8_t dataValidTime;                           
    uint8_t columnspace;                             
    bool enableWordAddress;                          
    uint8_t AWRSeqIndex;                             
    uint8_t AWRSeqNumber;                            
    uint8_t ARDSeqIndex;                             
    uint8_t ARDSeqNumber;                            
    flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit;  
    uint16_t AHBWriteWaitInterval;                   
    bool enableWriteMask;                            
#if defined(FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426) && (FSL_FEATURE_FLEXSPI_HAS_ERRATA_051426)
    bool isFroClockSource; 
#endif
} flexspi_device_config_t;
 
typedef struct _flexspi_transfer
{
    uint32_t deviceAddress;         
    flexspi_port_t port;            
    flexspi_command_type_t cmdType; 
    uint8_t seqIndex;               
    uint8_t SeqNumber;              
    uint32_t *data;                 
    size_t dataSize;                
} flexspi_transfer_t;
 
/* Forward declaration of the handle typedef. */
typedef struct _flexspi_handle flexspi_handle_t;
 
typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base,
                                            flexspi_handle_t *handle,
                                            status_t status,
                                            void *userData);
 
struct _flexspi_handle
{
    uint32_t state;                                 
    uint8_t *data;                                  
    size_t dataSize;                                
    size_t transferTotalSize;                       
    flexspi_transfer_callback_t completionCallback; 
    void *userData;                                 
};
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif /*_cplusplus. */
 
uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
 
status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
 
void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
 
void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
 
void FLEXSPI_Deinit(FLEXSPI_Type *base);
 
void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
 
void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
 
static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
{
    base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
    while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
    {
    }
}
 
static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
{
    if (enable)
    {
        base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
    }
    else
    {
        base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
    }
}
 
/* @} */
 
static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask)
{
    base->INTEN |= mask;
}
 
static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
{
    base->INTEN &= ~mask;
}
 
/* @} */
 
 
static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable)
{
    if (enable)
    {
        base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK;
    }
    else
    {
        base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK;
    }
}
 
static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable)
{
    if (enable)
    {
        base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK;
    }
    else
    {
        base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK;
    }
}
 
static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base)
{
    return (uint32_t)&base->TFDR[0];
}
 
static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
{
    return (uint32_t)&base->RFDR[0];
}
 
 
static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo)
{
    if (txFifo)
    {
        base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
    }
    if (rxFifo)
    {
        base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
    }
}
 
static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount)
{
    if (NULL != txCount)
    {
        *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U;
    }
    if (NULL != rxCount)
    {
        *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U;
    }
}
 
static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
{
    return base->INTR;
}
 
static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
{
    base->INTR |= mask;
}
 
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase)
{
    if (portAPhase != NULL)
    {
        *portAPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT);
    }
 
#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB)) && (FSL_FEATURE_FLEXSPI_HAS_NO_STS0_DATALEARNPHASEB))
    if (portBPhase != NULL)
    {
        *portBPhase = (uint8_t)((base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT);
    }
#endif
}
#endif
 
static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base)
{
    return (flexspi_arb_command_source_t)(
        (uint32_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT));
}
 
static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
{
    *index = (uint8_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT);
    return (flexspi_ip_error_code_t)(
        (uint32_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT));
}
 
static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index)
{
    *index = (uint8_t)(base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT;
    return (flexspi_ahb_error_code_t)(
        (uint32_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> FLEXSPI_STS1_AHBCMDERRCODE_SHIFT));
}
 
static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
{
    return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
}
void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource);
 
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_IP_PARALLEL_MODE)
static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable)
{
    if (enable)
    {
        base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK;
    }
    else
    {
        base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK;
    }
}
#endif
 
#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE) && FSL_FEATURE_FLEXSPI_HAS_NO_AHB_PARALLEL_MODE)
static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable)
{
    if (enable)
    {
        base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK;
    }
    else
    {
        base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK;
    }
}
#endif
 
void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
 
static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex)
{
    base->TFDR[fifoIndex] = data;
}
 
static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
{
    return base->RFDR[fifoIndex];
}
 
status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size);
 
status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size);
 
status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
                                  flexspi_handle_t *handle,
                                  flexspi_transfer_callback_t callback,
                                  void *userData);
 
status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer);
 
status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count);
 
void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle);
 
void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
#if defined(__cplusplus)
}
#endif /*_cplusplus. */
#endif /* __FSL_FLEXSPI_H_ */