RTEMS 6.1-rc1
emc.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2010, 2011 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef LIBBSP_ARM_LPC32XX_EMC_H
37#define LIBBSP_ARM_LPC32XX_EMC_H
38
39#include <rtems.h>
40
41#include <bsp/lpc-emc.h>
42
43#ifdef __cplusplus
44extern "C" {
45#endif /* __cplusplus */
46
61#define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0)
62#define SDRAMCLK_DDR_MODE BSP_BIT32(1)
63#define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6)
64#define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7)
65#define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8)
66#define SDRAMCLK_CAL_DELAY BSP_BIT32(9)
67#define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12)
68#define SDRAMCLK_DCA_STATUS BSP_BIT32(13)
69#define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18)
70#define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19)
71#define SDRAMCLK_PIN_1_FAST BSP_BIT32(20)
72#define SDRAMCLK_PIN_2_FAST BSP_BIT32(21)
73#define SDRAMCLK_PIN_3_FAST BSP_BIT32(22)
74
83#define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0)
84
93#define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9)
94
103#define SDRAM_ADDR_ROW_16MB(val) ((uint32_t) (val) << 10)
104#define SDRAM_ADDR_ROW_32MB(val) ((uint32_t) (val) << 11)
105#define SDRAM_ADDR_ROW_64MB(val) ((uint32_t) (val) << 11)
106
107#define SDRAM_ADDR_BANK_16MB(ba1, ba0) \
108 (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 22))
109#define SDRAM_ADDR_BANK_32MB(ba1, ba0) \
110 (((uint32_t) (ba1) << 23) | ((uint32_t) (ba0) << 24))
111#define SDRAM_ADDR_BANK_64MB(ba1, ba0) \
112 (((uint32_t) (ba1) << 25) | ((uint32_t) (ba0) << 24))
113
114#define SDRAM_MODE_16MB(mode) \
115 (SDRAM_ADDR_BANK_16MB(0, 0) | SDRAM_ADDR_ROW_16MB(mode))
116#define SDRAM_MODE_32MB(mode) \
117 (SDRAM_ADDR_BANK_32MB(0, 0) | SDRAM_ADDR_ROW_32MB(mode))
118#define SDRAM_MODE_64MB(mode) \
119 (SDRAM_ADDR_BANK_64MB(0, 0) | SDRAM_ADDR_ROW_64MB(mode))
120
121#define SDRAM_EXTMODE_16MB(mode) \
122 (SDRAM_ADDR_BANK_16MB(1, 0) | SDRAM_ADDR_ROW_16MB(mode))
123#define SDRAM_EXTMODE_32MB(mode) \
124 (SDRAM_ADDR_BANK_32MB(1, 0) | SDRAM_ADDR_ROW_32MB(mode))
125#define SDRAM_EXTMODE_64MB(mode) \
126 (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode))
127
128#define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2)
129#define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3)
130#define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6)
131#define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8)
132#define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9)
133
134#define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2)
135#define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6)
136
139typedef struct {
140 uint32_t size;
141 uint32_t config;
142 uint32_t rascas;
143 uint32_t mode;
144 uint32_t extmode;
146
147typedef struct {
148 uint32_t sdramclk_ctrl;
149 uint32_t nop_time_in_us;
150 uint32_t control;
151 uint32_t refresh;
152 uint32_t readconfig;
153 uint32_t trp;
154 uint32_t tras;
155 uint32_t tsrex;
156 uint32_t twr;
157 uint32_t trc;
158 uint32_t trfc;
159 uint32_t txsr;
160 uint32_t trrd;
161 uint32_t tmrd;
162 uint32_t tcdlr;
163 lpc32xx_emc_dynamic_chip_config chip [EMC_DYN_CHIP_COUNT];
165
166void lpc32xx_emc_init(const lpc32xx_emc_dynamic_config *dyn_cfg);
167
170#ifdef __cplusplus
171}
172#endif /* __cplusplus */
173
174#endif /* LIBBSP_ARM_LPC32XX_EMC_H */
EMC support API.
This header file defines the RTEMS Classic API.
Definition: deflate.c:114
Definition: intercom.c:87
Definition: emc.h:139
Definition: emc.h:147
unsigned size
Definition: tte.h:1