RTEMS 6.1-rc1
component_mlb.h
1/* ---------------------------------------------------------------------------- */
2/* Atmel Microcontroller Software Support */
3/* SAM Software Package License */
4/* ---------------------------------------------------------------------------- */
5/* Copyright (c) 2015, Atmel Corporation */
6/* */
7/* All rights reserved. */
8/* */
9/* Redistribution and use in source and binary forms, with or without */
10/* modification, are permitted provided that the following condition is met: */
11/* */
12/* - Redistributions of source code must retain the above copyright notice, */
13/* this list of conditions and the disclaimer below. */
14/* */
15/* Atmel's name may not be used to endorse or promote products derived from */
16/* this software without specific prior written permission. */
17/* */
18/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
19/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
20/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
21/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
22/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
23/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
24/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
25/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
26/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
27/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
28/* ---------------------------------------------------------------------------- */
29
30#ifndef _SAMV71_MLB_COMPONENT_
31#define _SAMV71_MLB_COMPONENT_
32
33/* ============================================================================= */
35/* ============================================================================= */
38
39#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
41typedef struct {
42 __IO uint32_t MLB_MLBC0;
43 __I uint32_t Reserved1[2];
44 __IO uint32_t MLB_MS0;
45 __I uint32_t Reserved2[1];
46 __IO uint32_t MLB_MS1;
47 __I uint32_t Reserved3[2];
48 __IO uint32_t MLB_MSS;
49 __I uint32_t MLB_MSD;
50 __I uint32_t Reserved4[1];
51 __IO uint32_t MLB_MIEN;
52 __I uint32_t Reserved5[3];
53 __IO uint32_t MLB_MLBC1;
54 __I uint32_t Reserved6[1];
55 __I uint32_t Reserved7[15];
56 __IO uint32_t MLB_HCTL;
57 __I uint32_t Reserved8[1];
58 __IO uint32_t MLB_HCMR[2];
59 __I uint32_t MLB_HCER[2];
60 __I uint32_t MLB_HCBR[2];
61 __I uint32_t Reserved9[8];
62 __IO uint32_t MLB_MDAT[4];
63 __IO uint32_t MLB_MDWE[4];
64 __IO uint32_t MLB_MCTL;
65 __IO uint32_t MLB_MADR;
66 __I uint32_t Reserved10[182];
67 __IO uint32_t MLB_ACTL;
68 __I uint32_t Reserved11[3];
69 __IO uint32_t MLB_ACSR[2];
70 __IO uint32_t MLB_ACMR[2];
71} Mlb;
72#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
73/* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */
74#define MLB_MLBC0_MLBEN (0x1u << 0)
75#define MLB_MLBC0_MLBCLK_Pos 2
76#define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos)
77#define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos)))
78#define MLB_MLBC0_MLBCLK_256_FS (0x0u << 2)
79#define MLB_MLBC0_MLBCLK_512_FS (0x1u << 2)
80#define MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2)
81#define MLB_MLBC0_ZERO (0x1u << 5)
82#define MLB_MLBC0_MLBLK (0x1u << 7)
83#define MLB_MLBC0_ASYRETRY (0x1u << 12)
84#define MLB_MLBC0_CTLRETRY (0x1u << 14)
85#define MLB_MLBC0_FCNT_Pos 15
86#define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos)
87#define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos)))
88#define MLB_MLBC0_FCNT_1_FRAME (0x0u << 15)
89#define MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15)
90#define MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15)
91#define MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15)
92#define MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15)
93#define MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15)
94#define MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15)
95/* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */
96#define MLB_MS0_MCS_Pos 0
97#define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos)
98#define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos)))
99/* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */
100#define MLB_MS1_MCS_Pos 0
101#define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos)
102#define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos)))
103/* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */
104#define MLB_MSS_RSTSYSCMD (0x1u << 0)
105#define MLB_MSS_LKSYSCMD (0x1u << 1)
106#define MLB_MSS_ULKSYSCMD (0x1u << 2)
107#define MLB_MSS_CSSYSCMD (0x1u << 3)
108#define MLB_MSS_SWSYSCMD (0x1u << 4)
109#define MLB_MSS_SERVREQ (0x1u << 5)
110/* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */
111#define MLB_MSD_SD0_Pos 0
112#define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos)
113#define MLB_MSD_SD1_Pos 8
114#define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos)
115#define MLB_MSD_SD2_Pos 16
116#define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos)
117#define MLB_MSD_SD3_Pos 24
118#define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos)
119/* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */
120#define MLB_MIEN_ISOC_PE (0x1u << 0)
121#define MLB_MIEN_ISOC_BUFO (0x1u << 1)
122#define MLB_MIEN_SYNC_PE (0x1u << 16)
123#define MLB_MIEN_ARX_DONE (0x1u << 17)
124#define MLB_MIEN_ARX_PE (0x1u << 18)
125#define MLB_MIEN_ARX_BREAK (0x1u << 19)
126#define MLB_MIEN_ATX_DONE (0x1u << 20)
127#define MLB_MIEN_ATX_PE (0x1u << 21)
128#define MLB_MIEN_ATX_BREAK (0x1u << 22)
129#define MLB_MIEN_CRX_DONE (0x1u << 24)
130#define MLB_MIEN_CRX_PE (0x1u << 25)
131#define MLB_MIEN_CRX_BREAK (0x1u << 26)
132#define MLB_MIEN_CTX_DONE (0x1u << 27)
133#define MLB_MIEN_CTX_PE (0x1u << 28)
134#define MLB_MIEN_CTX_BREAK (0x1u << 29)
135/* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */
136#define MLB_MLBC1_LOCK (0x1u << 6)
137#define MLB_MLBC1_CLKM (0x1u << 7)
138#define MLB_MLBC1_NDA_Pos 8
139#define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos)
140#define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos)))
141/* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */
142#define MLB_HCTL_RST0 (0x1u << 0)
143#define MLB_HCTL_RST1 (0x1u << 1)
144#define MLB_HCTL_EN (0x1u << 15)
145/* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */
146#define MLB_HCMR_CHM_Pos 0
147#define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos)
148#define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos)))
149/* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */
150#define MLB_HCER_CERR_Pos 0
151#define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos)
152/* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */
153#define MLB_HCBR_CHB_Pos 0
154#define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos)
155/* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */
156#define MLB_MDAT_DATA_Pos 0
157#define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos)
158#define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos)))
159/* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */
160#define MLB_MDWE_MASK_Pos 0
161#define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos)
162#define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos)))
163/* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */
164#define MLB_MCTL_XCMP (0x1u << 0)
165/* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */
166#define MLB_MADR_ADDR_Pos 0
167#define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos)
168#define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos)))
169#define MLB_MADR_TB (0x1u << 30)
170#define MLB_MADR_TB_CTR (0x0u << 30)
171#define MLB_MADR_TB_DBR (0x1u << 30)
172#define MLB_MADR_WNR (0x1u << 31)
173/* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */
174#define MLB_ACTL_SCE (0x1u << 0)
175#define MLB_ACTL_SMX (0x1u << 1)
176#define MLB_ACTL_DMA_MODE (0x1u << 2)
177#define MLB_ACTL_MPB (0x1u << 4)
178#define MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4)
179#define MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4)
180/* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */
181#define MLB_ACSR_CHS_Pos 0
182#define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos)
183#define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos)))
184/* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */
185#define MLB_ACMR_CHM_Pos 0
186#define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos)
187#define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos)))
188
192#endif /* _SAMV71_MLB_COMPONENT_ */
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
Mlb
Mlb hardware registers.
Definition: component_mlb.h:41
Mlb::MLB_MIEN
__IO uint32_t MLB_MIEN
(Mlb Offset: 0x02C) MediaLB Interrupt Enable Register
Definition: component_mlb.h:51
Mlb::MLB_MADR
__IO uint32_t MLB_MADR
(Mlb Offset: 0x0E4) MIF Address Register
Definition: component_mlb.h:65
Mlb::MLB_MS0
__IO uint32_t MLB_MS0
(Mlb Offset: 0x00C) MediaLB Channel Status 0 Register
Definition: component_mlb.h:44
Mlb::MLB_MSD
__I uint32_t MLB_MSD
(Mlb Offset: 0x024) MediaLB System Data Register
Definition: component_mlb.h:49
Mlb::MLB_MS1
__IO uint32_t MLB_MS1
(Mlb Offset: 0x014) MediaLB Channel Status1 Register
Definition: component_mlb.h:46
Mlb::MLB_MCTL
__IO uint32_t MLB_MCTL
(Mlb Offset: 0x0E0) MIF Control Register
Definition: component_mlb.h:64
Mlb::MLB_MSS
__IO uint32_t MLB_MSS
(Mlb Offset: 0x020) MediaLB System Status Register
Definition: component_mlb.h:48
Mlb::MLB_ACTL
__IO uint32_t MLB_ACTL
(Mlb Offset: 0x3C0) AHB Control Register
Definition: component_mlb.h:67
Mlb::MLB_MLBC0
__IO uint32_t MLB_MLBC0
(Mlb Offset: 0x000) MediaLB Control 0 Register
Definition: component_mlb.h:42
Mlb::MLB_HCTL
__IO uint32_t MLB_HCTL
(Mlb Offset: 0x080) HBI Control Register
Definition: component_mlb.h:56
Mlb::MLB_MLBC1
__IO uint32_t MLB_MLBC1
(Mlb Offset: 0x03C) MediaLB Control 1 Register
Definition: component_mlb.h:53
Generated by doxygen 1.9.4