113#include <sys/param.h>
115#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
120#if CPU_DATA_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES
121#error "CPU_DATA_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES"
124#if CPU_INSTRUCTION_CACHE_ALIGNMENT > CPU_CACHE_LINE_BYTES
125#error "CPU_INSTRUCTION_CACHE_ALIGNMENT is greater than CPU_CACHE_LINE_BYTES"
148#if defined(CPU_DATA_CACHE_ALIGNMENT)
149#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
150 _CPU_cache_flush_data_range( d_addr, n_bytes );
152 const void * final_address;
164 final_address = (
void *)((
size_t)d_addr + n_bytes - 1);
165 d_addr = (
void *)((
size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
166 while( d_addr <= final_address ) {
167 _CPU_cache_flush_1_data_line( d_addr );
168 d_addr = (
void *)((
size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
182#if defined(CPU_DATA_CACHE_ALIGNMENT)
183#if defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
184 _CPU_cache_invalidate_data_range( d_addr, n_bytes );
186 const void * final_address;
198 final_address = (
void *)((
size_t)d_addr + n_bytes - 1);
199 d_addr = (
void *)((
size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1));
200 while( final_address >= d_addr ) {
201 _CPU_cache_invalidate_1_data_line( d_addr );
202 d_addr = (
void *)((
size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT);
215#if defined(CPU_DATA_CACHE_ALIGNMENT)
219 _CPU_cache_flush_entire_data();
230#if defined(CPU_DATA_CACHE_ALIGNMENT)
235 _CPU_cache_invalidate_entire_data();
245#if defined(CPU_DATA_CACHE_ALIGNMENT)
246 return CPU_DATA_CACHE_ALIGNMENT;
255#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
256 return _CPU_cache_get_data_cache_size( level );
269#if defined(CPU_DATA_CACHE_ALIGNMENT)
270 _CPU_cache_freeze_data();
276#if defined(CPU_DATA_CACHE_ALIGNMENT)
277 _CPU_cache_unfreeze_data();
284#if defined(CPU_DATA_CACHE_ALIGNMENT)
285 _CPU_cache_enable_data();
289#if !defined(CPU_CACHE_SUPPORT_PROVIDES_DISABLE_DATA)
293#if defined(CPU_DATA_CACHE_ALIGNMENT)
294 _CPU_cache_disable_data();
303#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \
304 && defined(RTEMS_SMP) \
305 && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
312static void smp_cache_inst_inv(
void *arg)
314 smp_cache_area *area = arg;
316 _CPU_cache_invalidate_instruction_range(area->addr, area->size);
319static void smp_cache_inst_inv_all(
void *arg)
322 _CPU_cache_invalidate_entire_instruction();
325static void smp_cache_broadcast( SMP_Action_handler handler,
void *arg )
332 if ( isr_level == 0 ) {
333 cpu_self = _Thread_Dispatch_disable();
335 cpu_self = _Per_CPU_Get();
339 _SMP_Othercast_action( handler, arg );
341 if ( isr_level == 0 ) {
353#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) \
354 && !defined(CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS)
356_CPU_cache_invalidate_instruction_range(
361 const void * final_address;
373 final_address = (
void *)((
size_t)i_addr + n_bytes - 1);
374 i_addr = (
void *)((
size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1));
375 while( final_address >= i_addr ) {
376 _CPU_cache_invalidate_1_instruction_line( i_addr );
377 i_addr = (
void *)((
size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT);
388#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
389#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
390 smp_cache_area area = { i_addr, n_bytes };
392 smp_cache_broadcast( smp_cache_inst_inv, &area );
394 _CPU_cache_invalidate_instruction_range( i_addr, n_bytes );
406#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
407#if defined(RTEMS_SMP) && defined(CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING)
408 smp_cache_broadcast( smp_cache_inst_inv_all,
NULL );
410 _CPU_cache_invalidate_entire_instruction();
421#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
422 return CPU_INSTRUCTION_CACHE_ALIGNMENT;
431#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
432 return _CPU_cache_get_instruction_cache_size( level );
445#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
446 _CPU_cache_freeze_instruction();
452#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
453 _CPU_cache_unfreeze_instruction();
460#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
461 _CPU_cache_enable_instruction();
468#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
469 _CPU_cache_disable_instruction();
476#if defined(CPU_MAXIMAL_CACHE_ALIGNMENT)
477 return CPU_MAXIMAL_CACHE_ALIGNMENT;
479 size_t data_line_size =
480#if defined(CPU_DATA_CACHE_ALIGNMENT)
481 CPU_DATA_CACHE_ALIGNMENT;
485 size_t instruction_line_size =
486#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
487 CPU_INSTRUCTION_CACHE_ALIGNMENT;
491 return MAX( data_line_size, instruction_line_size );
502 const void *code_addr,
506#if defined(CPU_CACHE_SUPPORT_PROVIDES_INSTRUCTION_SYNC_FUNCTION)
507 _CPU_cache_instruction_sync_after_code_change( code_addr, n_bytes );
void rtems_cache_unfreeze_instruction(void)
Unfreezes the instruction cache.
Definition: cacheimpl.h:450
void rtems_cache_unfreeze_data(void)
Unfreezes the data cache.
Definition: cacheimpl.h:274
void rtems_cache_freeze_instruction(void)
Freezes the instruction caches.
Definition: cacheimpl.h:443
void rtems_cache_freeze_data(void)
Freezes the data caches.
Definition: cacheimpl.h:267
void rtems_cache_instruction_sync_after_code_change(const void *code_addr, size_t n_bytes)
Ensures necessary synchronization required after code changes.
Definition: cacheimpl.h:501
size_t rtems_cache_get_maximal_line_size(void)
Gets the maximal cache line size in bytes of all caches (data, instruction, or unified).
Definition: cacheimpl.h:474
void rtems_cache_invalidate_entire_instruction(void)
Invalidates the entire instruction cache.
Definition: cacheimpl.h:404
void rtems_cache_invalidate_entire_data(void)
Invalidates the entire data cache.
Definition: cacheimpl.h:228
void rtems_cache_invalidate_multiple_instruction_lines(const void *i_addr, size_t n_bytes)
Invalidates the instruction cache lines covering the memory area.
Definition: cacheimpl.h:383
size_t rtems_cache_get_data_cache_size(uint32_t level)
Gets the data cache size in bytes for the cache level.
Definition: cacheimpl.h:253
void rtems_cache_enable_data(void)
Enables the data cache.
Definition: cacheimpl.h:282
void rtems_cache_disable_instruction(void)
Disables the instruction cache.
Definition: cacheimpl.h:466
void rtems_cache_disable_data(void)
Disables the data cache.
Definition: cacheimpl.h:291
size_t rtems_cache_get_instruction_cache_size(uint32_t level)
Gets the instruction cache size in bytes for the cache level.
Definition: cacheimpl.h:429
void rtems_cache_invalidate_multiple_data_lines(const void *d_addr, size_t n_bytes)
Invalidates the data cache lines covering the memory area.
Definition: cacheimpl.h:180
void rtems_cache_flush_entire_data(void)
Flushes the entire data cache.
Definition: cacheimpl.h:213
void rtems_cache_flush_multiple_data_lines(const void *d_addr, size_t n_bytes)
Flushes the data cache lines covering the memory area.
Definition: cacheimpl.h:146
size_t rtems_cache_get_instruction_line_size(void)
Gets the instruction cache line size in bytes.
Definition: cacheimpl.h:419
size_t rtems_cache_get_data_line_size(void)
Gets the data cache line size in bytes.
Definition: cacheimpl.h:243
void rtems_cache_enable_instruction(void)
Enables the instruction cache.
Definition: cacheimpl.h:458
#define _ISR_Get_level()
Return current interrupt level.
Definition: isrlevel.h:147
void _Thread_Dispatch_enable(Per_CPU_Control *cpu_self)
Enables thread dispatching.
#define NULL
Requests a GPIO pin group configuration.
Definition: xil_types.h:54
This header file defines the RTEMS Classic API.
This header file provides interfaces of the SMP Support which are only used by the implementation.
Per CPU Core Structure.
Definition: percpu.h:384
unsigned size
Definition: tte.h:1
This header file provides the interfaces of the Thread Handler related to thread dispatching.