23#include <bsp/residual.h>
24#include <bsp/consoleIo.h>
27#define abs __builtin_abs
30#define PTE_CHNG (0x80|PTE_REFD)
33#define PTE_COHER 0x010
38#define PTE_RAM (PTE_CHNG|PTE_COHER|PTE_RW)
39#define PTE_ROM (PTE_REFD|PTE_RO)
40#define PTE_IO (PTE_CHNG|PTE_CINH|PTE_GUAR|PTE_RW)
64 void *r6, *r7, *r8, *r9, *r10;
69 u_long o_msr, o_hid0, o_r31;
81pcibios_read_config_byte(u_char bus, u_char dev_fn,
82 u_char where, uint8_t *val) {
83 return bd->pci_functions->read_config_byte(bus, dev_fn, where, val);
87pcibios_read_config_word(u_char bus, u_char dev_fn,
88 u_char where, uint16_t *val) {
89 return bd->pci_functions->read_config_word(bus, dev_fn, where, val);
93pcibios_read_config_dword(u_char bus, u_char dev_fn,
94 u_char where, uint32_t *val) {
95 return bd->pci_functions->read_config_dword(bus, dev_fn, where, val);
99pcibios_write_config_byte(u_char bus, u_char dev_fn,
100 u_char where, uint8_t val) {
101 return bd->pci_functions->write_config_byte(bus, dev_fn, where, val);
105pcibios_write_config_word(u_char bus, u_char dev_fn,
106 u_char where, uint16_t val) {
107 return bd->pci_functions->write_config_word(bus, dev_fn, where, val);
111pcibios_write_config_dword(u_char bus, u_char dev_fn,
112 u_char where, uint32_t val) {
113 return bd->pci_functions->write_config_dword(bus, dev_fn, where, val);
117pci_bootloader_read_config_byte(
struct pci_dev *dev, u_char where, uint8_t *val) {
118 return bd->pci_functions->read_config_byte(dev->bus->number,
124pci_bootloader_read_config_word(
struct pci_dev *dev, u_char where, uint16_t *val) {
125 return bd->pci_functions->read_config_word(dev->bus->number,
131pci_bootloader_read_config_dword(
struct pci_dev *dev, u_char where, uint32_t *val) {
132 return bd->pci_functions->read_config_dword(dev->bus->number,
138pci_bootloader_write_config_byte(
struct pci_dev *dev, u_char where, uint8_t val) {
139 return bd->pci_functions->write_config_byte(dev->bus->number,
145pci_bootloader_write_config_word(
struct pci_dev *dev, u_char where, uint16_t val) {
146 return bd->pci_functions->write_config_word(dev->bus->number,
152pci_bootloader_write_config_dword(
struct pci_dev *dev, u_char where, uint32_t val) {
153 return bd->pci_functions->write_config_dword(dev->bus->number,
165extern void * codemove(
void *,
const void *,
size_t,
unsigned long);
173#define palloc(size) __palloc(size,0)
175#define isa_io_base (bd->io_base)
177void * __palloc(u_long,
int);
182#define PA_SUBALLOC 0x400
183#define PA_ALIGN_MASK 0x1f
185void * valloc(u_long
size);
188int vmap(
void *, u_long, u_long);
191void * salloc(u_long
size);
196void * memset(
void *
p,
int c,
size_t n);
198void gunzip(
void *,
int,
unsigned char *,
int *);
200void print_all_maps(
const char *);
201void print_hash_table(
void);
207void cleanup_v86_mess(
void);
208void em86_main(
struct pci_dev *);
209int find_max_mem(
struct pci_dev *);
216int em86_trap(
x86 *
p);
217void decompress_kernel(
int kernel_size,
void * zimage_start,
int len,
218 void * initrd_start,
int initrd_len );
219void boot_udelay(uint32_t _microseconds);
222int early_setup(u_long image_size);
223void mm_init(u_long image_size);
231#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
232#define GOT(NAME) .L_ ## NAME (r30)
235 .section ".got2","aw"; \
2440: .long .LCTOC1-1f; \
251#define cache_lsize 32
260#define save_ctr 12(r1)
261#define save_cr 16(r1)
262#define save_xer 20(r1)
263#define save_nip 24(r1)
264#define save_msr 28(r1)
265#define save_r(n) 32+4*n(r1)
unsigned short int uint16 __attribute__((__may_alias__))
Perform a 32-bit endian conversion.
Definition: mcf5282.h:37
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
Definition: residual.h:294
Definition: mongoose.c:443
unsigned size
Definition: tte.h:1
unsigned p
Definition: tte.h:17