RTEMS 6.1-rc1
armv7m.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (c) 2011-2014 Sebastian Huber. All rights reserved.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef RTEMS_SCORE_ARMV7M_H
38#define RTEMS_SCORE_ARMV7M_H
39
40#include <rtems/score/cpu.h>
41#ifndef ASM
42#include <rtems/score/assert.h>
43#endif
44
45#ifdef __cplusplus
46extern "C" {
47#endif /* __cplusplus */
48
49#ifdef ARM_MULTILIB_ARCH_V7M
50
51/* Coprocessor Access Control Register, CPACR */
52#define ARMV7M_CPACR 0xe000ed88
53
54#ifndef ASM
55
56typedef struct {
57 uint32_t reserved_0;
58 uint32_t ictr;
59 uint32_t actlr;
60 uint32_t reserved_1;
61} ARMV7M_ICTAC;
62
63typedef void (*ARMV7M_Exception_handler)(void);
64
65typedef struct {
66 uint32_t register_r0;
67 uint32_t register_r1;
68 uint32_t register_r2;
69 uint32_t register_r3;
70 uint32_t register_r12;
71 void *register_lr;
72 void *register_pc;
73 uint32_t register_xpsr;
74#ifdef ARM_MULTILIB_VFP
75 uint32_t register_s0;
76 uint32_t register_s1;
77 uint32_t register_s2;
78 uint32_t register_s3;
79 uint32_t register_s4;
80 uint32_t register_s5;
81 uint32_t register_s6;
82 uint32_t register_s7;
83 uint32_t register_s8;
84 uint32_t register_s9;
85 uint32_t register_s10;
86 uint32_t register_s11;
87 uint32_t register_s12;
88 uint32_t register_s13;
89 uint32_t register_s14;
90 uint32_t register_s15;
91 uint32_t register_fpscr;
92 uint32_t reserved;
93#endif
94} ARMV7M_Exception_frame;
95
96typedef struct {
97 uint32_t comp;
98 uint32_t mask;
99 uint32_t function;
100 uint32_t reserved;
101} ARMV7M_DWT_comparator;
102
103typedef struct {
104#define ARMV7M_DWT_CTRL_NOCYCCNT (1U << 25)
105#define ARMV7M_DWT_CTRL_CYCCNTENA (1U << 0)
106 uint32_t ctrl;
107 uint32_t cyccnt;
108 uint32_t cpicnt;
109 uint32_t exccnt;
110 uint32_t sleepcnt;
111 uint32_t lsucnt;
112 uint32_t foldcnt;
113 uint32_t pcsr;
114 ARMV7M_DWT_comparator comparator[249];
115#define ARMV7M_DWT_LAR_UNLOCK_MAGIC 0xc5acce55U
116 uint32_t lar;
117 uint32_t lsr;
118} ARMV7M_DWT;
119
120typedef struct {
121 uint32_t cpuid;
122
123#define ARMV7M_SCB_ICSR_NMIPENDSET (1U << 31)
124#define ARMV7M_SCB_ICSR_PENDSVSET (1U << 28)
125#define ARMV7M_SCB_ICSR_PENDSVCLR (1U << 27)
126#define ARMV7M_SCB_ICSR_PENDSTSET (1U << 26)
127#define ARMV7M_SCB_ICSR_PENDSTCLR (1U << 25)
128#define ARMV7M_SCB_ICSR_ISRPREEMPT (1U << 23)
129#define ARMV7M_SCB_ICSR_ISRPENDING (1U << 22)
130#define ARMV7M_SCB_ICSR_VECTPENDING_GET(reg) (((reg) >> 12) & 0x1ffU)
131#define ARMV7M_SCB_ICSR_RETTOBASE (1U << 11)
132#define ARMV7M_SCB_ICSR_VECTACTIVE_GET(reg) ((reg) & 0x1ffU)
133 uint32_t icsr;
134
135 ARMV7M_Exception_handler *vtor;
136
137#define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
138#define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15)
139#define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8
140#define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \
141 ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
142#define ARMV7M_SCB_AIRCR_PRIGROUP(val) \
143 (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK)
144#define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \
145 (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
146#define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \
147 (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val))
148#define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2)
149#define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1)
150#define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0)
151 uint32_t aircr;
152
153 uint32_t scr;
154 uint32_t ccr;
155 uint8_t shpr [12];
156
157#define ARMV7M_SCB_SHCSR_USGFAULTENA (1U << 18)
158#define ARMV7M_SCB_SHCSR_BUSFAULTENA (1U << 17)
159#define ARMV7M_SCB_SHCSR_MEMFAULTENA (1U << 16)
160 uint32_t shcsr;
161
162#define ARMV7M_SCB_CFSR_MMFSR_MASK 0xff
163#define ARMV7M_SCB_CFSR_MMFSR_GET(n) (n & ARMV7M_SCB_CFSR_MMFSR_MASK)
164#define ARMV7M_SCB_CFSR_BFSR_MASK 0xff00
165#define ARMV7M_SCB_CFSR_BFSR_GET(n) (n & ARMV7M_SCB_CFSR_BFSR_MASK)
166#define ARMV7M_SCB_CFSR_UFSR_MASK 0xffff0000
167#define ARMV7M_SCB_CFSR_UFSR_GET(n) (n & ARMV7M_SCB_CFSR_UFSR_MASK)
168 uint32_t cfsr;
169
170#define ARMV7M_SCB_HFSR_VECTTBL_MASK 0x2
171#define ARMV7M_SCB_HFSR_FORCED_MASK (1U << 30)
172#define ARMV7M_SCB_HFSR_DEBUGEVT_MASK (1U << 31)
173 uint32_t hfsr;
174
175 uint32_t dfsr;
176 uint32_t mmfar;
177 uint32_t bfar;
178 uint32_t afsr;
179 uint32_t reserved_e000ed40[18];
180 uint32_t cpacr;
181 uint32_t reserved_e000ed8c[106];
182 uint32_t fpccr;
183 uint32_t fpcar;
184 uint32_t fpdscr;
185 uint32_t mvfr0;
186 uint32_t mvfr1;
187} ARMV7M_SCB;
188
189typedef struct {
190#define ARMV7M_SYSTICK_CSR_COUNTFLAG (1U << 16)
191#define ARMV7M_SYSTICK_CSR_CLKSOURCE (1U << 2)
192#define ARMV7M_SYSTICK_CSR_TICKINT (1U << 1)
193#define ARMV7M_SYSTICK_CSR_ENABLE (1U << 0)
194 uint32_t csr;
195
196 uint32_t rvr;
197 uint32_t cvr;
198
199#define ARMV7M_SYSTICK_CALIB_NOREF (1U << 31)
200#define ARMV7M_SYSTICK_CALIB_SKEW (1U << 30)
201#define ARMV7M_SYSTICK_CALIB_TENMS_GET(reg) ((reg) & 0xffffffU)
202 uint32_t calib;
203} ARMV7M_Systick;
204
205typedef struct {
206 uint32_t iser [8];
207 uint32_t reserved_0 [24];
208 uint32_t icer [8];
209 uint32_t reserved_1 [24];
210 uint32_t ispr [8];
211 uint32_t reserved_2 [24];
212 uint32_t icpr [8];
213 uint32_t reserved_3 [24];
214 uint32_t iabr [8];
215 uint32_t reserved_4 [56];
216 uint8_t ipr [240];
217 uint32_t reserved_5 [644];
218 uint32_t stir;
219} ARMV7M_NVIC;
220
221typedef struct {
222#define ARMV7M_MPU_TYPE_IREGION_GET(reg) (((reg) >> 16) & 0xffU)
223#define ARMV7M_MPU_TYPE_DREGION_GET(reg) (((reg) >> 8) & 0xffU)
224#define ARMV7M_MPU_TYPE_SEPARATE (1U << 0)
225 uint32_t type;
226
227#define ARMV7M_MPU_CTRL_PRIVDEFENA (1U << 2)
228#define ARMV7M_MPU_CTRL_HFNMIENA (1U << 1)
229#define ARMV7M_MPU_CTRL_ENABLE (1U << 0)
230 uint32_t ctrl;
231
232 uint32_t rnr;
233
234#define ARMV7M_MPU_RBAR_ADDR_SHIFT 5
235#define ARMV7M_MPU_RBAR_ADDR_MASK \
236 ((0x7ffffffU) << ARMV7M_MPU_RBAR_ADDR_SHIFT)
237#define ARMV7M_MPU_RBAR_ADDR(val) \
238 (((val) << ARMV7M_MPU_RBAR_ADDR_SHIFT) & ARMV7M_MPU_RBAR_ADDR_MASK)
239#define ARMV7M_MPU_RBAR_ADDR_GET(reg) \
240 (((val) & ARMV7M_MPU_RBAR_ADDR_MASK) >> ARMV7M_MPU_RBAR_ADDR_SHIFT)
241#define ARMV7M_MPU_RBAR_ADDR_SET(reg, val) \
242 (((reg) & ~ARMV7M_MPU_RBAR_ADDR_MASK) | ARMV7M_MPU_RBAR_ADDR(val))
243#define ARMV7M_MPU_RBAR_VALID (1U << 4)
244#define ARMV7M_MPU_RBAR_REGION_SHIFT 0
245#define ARMV7M_MPU_RBAR_REGION_MASK \
246 ((0xfU) << ARMV7M_MPU_RBAR_REGION_SHIFT)
247#define ARMV7M_MPU_RBAR_REGION(val) \
248 (((val) << ARMV7M_MPU_RBAR_REGION_SHIFT) & ARMV7M_MPU_RBAR_REGION_MASK)
249#define ARMV7M_MPU_RBAR_REGION_GET(reg) \
250 (((val) & ARMV7M_MPU_RBAR_REGION_MASK) >> ARMV7M_MPU_RBAR_REGION_SHIFT)
251#define ARMV7M_MPU_RBAR_REGION_SET(reg, val) \
252 (((reg) & ~ARMV7M_MPU_RBAR_REGION_MASK) | ARMV7M_MPU_RBAR_REGION(val))
253 uint32_t rbar;
254
255#define ARMV7M_MPU_RASR_XN (1U << 28)
256#define ARMV7M_MPU_RASR_AP_SHIFT 24
257#define ARMV7M_MPU_RASR_AP_MASK \
258 ((0x7U) << ARMV7M_MPU_RASR_AP_SHIFT)
259#define ARMV7M_MPU_RASR_AP(val) \
260 (((val) << ARMV7M_MPU_RASR_AP_SHIFT) & ARMV7M_MPU_RASR_AP_MASK)
261#define ARMV7M_MPU_RASR_AP_GET(reg) \
262 (((val) & ARMV7M_MPU_RASR_AP_MASK) >> ARMV7M_MPU_RASR_AP_SHIFT)
263#define ARMV7M_MPU_RASR_AP_SET(reg, val) \
264 (((reg) & ~ARMV7M_MPU_RASR_AP_MASK) | ARMV7M_MPU_RASR_AP(val))
265#define ARMV7M_MPU_RASR_TEX_SHIFT 19
266#define ARMV7M_MPU_RASR_TEX_MASK \
267 ((0x7U) << ARMV7M_MPU_RASR_TEX_SHIFT)
268#define ARMV7M_MPU_RASR_TEX(val) \
269 (((val) << ARMV7M_MPU_RASR_TEX_SHIFT) & ARMV7M_MPU_RASR_TEX_MASK)
270#define ARMV7M_MPU_RASR_TEX_GET(reg) \
271 (((val) & ARMV7M_MPU_RASR_TEX_MASK) >> ARMV7M_MPU_RASR_TEX_SHIFT)
272#define ARMV7M_MPU_RASR_TEX_SET(reg, val) \
273 (((reg) & ~ARMV7M_MPU_RASR_TEX_MASK) | ARMV7M_MPU_RASR_TEX(val))
274#define ARMV7M_MPU_RASR_S (1U << 18)
275#define ARMV7M_MPU_RASR_C (1U << 17)
276#define ARMV7M_MPU_RASR_B (1U << 16)
277#define ARMV7M_MPU_RASR_SRD_SHIFT 8
278#define ARMV7M_MPU_RASR_SRD_MASK \
279 ((0xffU) << ARMV7M_MPU_RASR_SRD_SHIFT)
280#define ARMV7M_MPU_RASR_SRD(val) \
281 (((val) << ARMV7M_MPU_RASR_SRD_SHIFT) & ARMV7M_MPU_RASR_SRD_MASK)
282#define ARMV7M_MPU_RASR_SRD_GET(reg) \
283 (((val) & ARMV7M_MPU_RASR_SRD_MASK) >> ARMV7M_MPU_RASR_SRD_SHIFT)
284#define ARMV7M_MPU_RASR_SRD_SET(reg, val) \
285 (((reg) & ~ARMV7M_MPU_RASR_SRD_MASK) | ARMV7M_MPU_RASR_SRD(val))
286#define ARMV7M_MPU_RASR_SIZE_SHIFT 1
287#define ARMV7M_MPU_RASR_SIZE_MASK \
288 ((0x1fU) << ARMV7M_MPU_RASR_SIZE_SHIFT)
289#define ARMV7M_MPU_RASR_SIZE(val) \
290 (((val) << ARMV7M_MPU_RASR_SIZE_SHIFT) & ARMV7M_MPU_RASR_SIZE_MASK)
291#define ARMV7M_MPU_RASR_SIZE_GET(reg) \
292 (((val) & ARMV7M_MPU_RASR_SIZE_MASK) >> ARMV7M_MPU_RASR_SIZE_SHIFT)
293#define ARMV7M_MPU_RASR_SIZE_SET(reg, val) \
294 (((reg) & ~ARMV7M_MPU_RASR_SIZE_MASK) | ARMV7M_MPU_RASR_SIZE(val))
295#define ARMV7M_MPU_RASR_ENABLE (1U << 0)
296 uint32_t rasr;
297
298 uint32_t rbar_a1;
299 uint32_t rasr_a1;
300 uint32_t rbar_a2;
301 uint32_t rasr_a2;
302 uint32_t rbar_a3;
303 uint32_t rasr_a3;
304} ARMV7M_MPU;
305
306typedef enum {
307 ARMV7M_MPU_AP_PRIV_NO_USER_NO,
308 ARMV7M_MPU_AP_PRIV_RW_USER_NO,
309 ARMV7M_MPU_AP_PRIV_RW_USER_RO,
310 ARMV7M_MPU_AP_PRIV_RW_USER_RW,
311 ARMV7M_MPU_AP_PRIV_RO_USER_NO = 0x5,
312 ARMV7M_MPU_AP_PRIV_RO_USER_RO,
313} ARMV7M_MPU_Access_permissions;
314
315typedef enum {
316 ARMV7M_MPU_ATTR_R = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
317 | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN,
318 ARMV7M_MPU_ATTR_RW = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
319 | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_XN | ARMV7M_MPU_RASR_B,
320 ARMV7M_MPU_ATTR_RWX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
321 | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B,
322 ARMV7M_MPU_ATTR_X = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_NO_USER_NO)
323 | ARMV7M_MPU_RASR_C,
324 ARMV7M_MPU_ATTR_RX = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RO_USER_NO)
325 | ARMV7M_MPU_RASR_C,
326 ARMV7M_MPU_ATTR_IO = ARMV7M_MPU_RASR_AP(ARMV7M_MPU_AP_PRIV_RW_USER_NO)
327 | ARMV7M_MPU_RASR_XN,
328} ARMV7M_MPU_Attributes;
329
330typedef enum {
331 ARMV7M_MPU_SIZE_32_B = 0x4,
332 ARMV7M_MPU_SIZE_64_B,
333 ARMV7M_MPU_SIZE_128_B,
334 ARMV7M_MPU_SIZE_256_B,
335 ARMV7M_MPU_SIZE_512_B,
336 ARMV7M_MPU_SIZE_1_KB,
337 ARMV7M_MPU_SIZE_2_KB,
338 ARMV7M_MPU_SIZE_4_KB,
339 ARMV7M_MPU_SIZE_8_KB,
340 ARMV7M_MPU_SIZE_16_KB,
341 ARMV7M_MPU_SIZE_32_KB,
342 ARMV7M_MPU_SIZE_64_KB,
343 ARMV7M_MPU_SIZE_128_KB,
344 ARMV7M_MPU_SIZE_256_KB,
345 ARMV7M_MPU_SIZE_512_KB,
346 ARMV7M_MPU_SIZE_1_MB,
347 ARMV7M_MPU_SIZE_2_MB,
348 ARMV7M_MPU_SIZE_4_MB,
349 ARMV7M_MPU_SIZE_8_MB,
350 ARMV7M_MPU_SIZE_16_MB,
351 ARMV7M_MPU_SIZE_32_MB,
352 ARMV7M_MPU_SIZE_64_MB,
353 ARMV7M_MPU_SIZE_128_MB,
354 ARMV7M_MPU_SIZE_256_MB,
355 ARMV7M_MPU_SIZE_512_MB,
356 ARMV7M_MPU_SIZE_1_GB,
357 ARMV7M_MPU_SIZE_2_GB,
358 ARMV7M_MPU_SIZE_4_GB
359} ARMV7M_MPU_Size;
360
361typedef struct {
362 uint32_t rbar;
363 uint32_t rasr;
364} ARMV7M_MPU_Region;
365
366#define ARMV7M_MPU_REGION_INITIALIZER(idx, addr, size, attr) \
367 { \
368 ((addr) & ARMV7M_MPU_RBAR_ADDR_MASK) \
369 | ARMV7M_MPU_RBAR_VALID \
370 | ARMV7M_MPU_RBAR_REGION(idx), \
371 ARMV7M_MPU_RASR_SIZE(size) | (attr) | ARMV7M_MPU_RASR_ENABLE \
372 }
373
374#define ARMV7M_MPU_REGION_DISABLED_INITIALIZER(idx) \
375 { \
376 ARMV7M_MPU_RBAR_VALID | ARMV7M_MPU_RBAR_REGION(idx), \
377 0 \
378 }
379
392typedef struct {
393 const void *begin;
394 const void *end;
395 uint32_t rasr;
396} ARMV7M_MPU_Region_config;
397
398typedef struct {
399 uint32_t dhcsr;
400 uint32_t dcrsr;
401 uint32_t dcrdr;
402#define ARMV7M_DEBUG_DEMCR_VC_CORERESET (1U << 0)
403#define ARMV7M_DEBUG_DEMCR_VC_MMERR (1U << 4)
404#define ARMV7M_DEBUG_DEMCR_VC_NOCPERR (1U << 5)
405#define ARMV7M_DEBUG_DEMCR_VC_CHKERR (1U << 6)
406#define ARMV7M_DEBUG_DEMCR_VC_STATERR (1U << 7)
407#define ARMV7M_DEBUG_DEMCR_VC_BUSERR (1U << 8)
408#define ARMV7M_DEBUG_DEMCR_VC_INTERR (1U << 9)
409#define ARMV7M_DEBUG_DEMCR_VC_HARDERR (1U << 10)
410#define ARMV7M_DEBUG_DEMCR_MON_EN (1U << 16)
411#define ARMV7M_DEBUG_DEMCR_MON_PEND (1U << 17)
412#define ARMV7M_DEBUG_DEMCR_MON_STEP (1U << 18)
413#define ARMV7M_DEBUG_DEMCR_MON_REQ (1U << 19)
414#define ARMV7M_DEBUG_DEMCR_TRCENA (1U << 24)
415 uint32_t demcr;
416} ARMV7M_DEBUG;
417
418#define ARMV7M_DWT_BASE 0xe0001000
419#define ARMV7M_SCS_BASE 0xe000e000
420#define ARMV7M_ICTAC_BASE (ARMV7M_SCS_BASE + 0x0)
421#define ARMV7M_SYSTICK_BASE (ARMV7M_SCS_BASE + 0x10)
422#define ARMV7M_NVIC_BASE (ARMV7M_SCS_BASE + 0x100)
423#define ARMV7M_SCB_BASE (ARMV7M_SCS_BASE + 0xd00)
424#define ARMV7M_MPU_BASE (ARMV7M_SCS_BASE + 0xd90)
425#define ARMV7M_DEBUG_BASE (ARMV7M_SCS_BASE + 0xdf0)
426
427#define _ARMV7M_DWT \
428 ((volatile ARMV7M_DWT *) ARMV7M_DWT_BASE)
429#define _ARMV7M_ICTAC \
430 ((volatile ARMV7M_ICTAC *) ARMV7M_ICTAC_BASE)
431#define _ARMV7M_SCB \
432 ((volatile ARMV7M_SCB *) ARMV7M_SCB_BASE)
433#define _ARMV7M_Systick \
434 ((volatile ARMV7M_Systick *) ARMV7M_SYSTICK_BASE)
435#define _ARMV7M_NVIC \
436 ((volatile ARMV7M_NVIC *) ARMV7M_NVIC_BASE)
437#define _ARMV7M_MPU \
438 ((volatile ARMV7M_MPU *) ARMV7M_MPU_BASE)
439#define _ARMV7M_DEBUG \
440 ((volatile ARMV7M_DEBUG *) ARMV7M_DEBUG_BASE)
441
442#define ARMV7M_VECTOR_MSP 0
443#define ARMV7M_VECTOR_RESET 1
444#define ARMV7M_VECTOR_NMI 2
445#define ARMV7M_VECTOR_HARD_FAULT 3
446#define ARMV7M_VECTOR_MEM_MANAGE 4
447#define ARMV7M_VECTOR_BUS_FAULT 5
448#define ARMV7M_VECTOR_USAGE_FAULT 6
449#define ARMV7M_VECTOR_SVC 11
450#define ARMV7M_VECTOR_DEBUG_MONITOR 12
451#define ARMV7M_VECTOR_PENDSV 14
452#define ARMV7M_VECTOR_SYSTICK 15
453#define ARMV7M_VECTOR_IRQ(n) ((n) + 16)
454#define ARMV7M_IRQ_OF_VECTOR(n) ((n) - 16)
455
456#define ARMV7M_EXCEPTION_PRIORITY_LOWEST 255
457
458static inline bool _ARMV7M_Is_vector_an_irq( int vector )
459{
460 /* External (i.e. non-system) IRQs start after the SysTick vector. */
461 return vector > ARMV7M_VECTOR_SYSTICK;
462}
463
464static inline uint32_t _ARMV7M_Get_basepri(void)
465{
466 uint32_t val;
467 __asm__ volatile ("mrs %[val], basepri\n" : [val] "=&r" (val));
468 return val;
469}
470
471static inline void _ARMV7M_Set_basepri(uint32_t val)
472{
473 __asm__ volatile ("msr basepri, %[val]\n" : : [val] "r" (val));
474}
475
476static inline uint32_t _ARMV7M_Get_primask(void)
477{
478 uint32_t val;
479 __asm__ volatile ("mrs %[val], primask\n" : [val] "=&r" (val));
480 return val;
481}
482
483static inline void _ARMV7M_Set_primask(uint32_t val)
484{
485 __asm__ volatile ("msr primask, %[val]\n" : : [val] "r" (val));
486}
487
488static inline uint32_t _ARMV7M_Get_faultmask(void)
489{
490 uint32_t val;
491 __asm__ volatile ("mrs %[val], faultmask\n" : [val] "=&r" (val));
492 return val;
493}
494
495static inline void _ARMV7M_Set_faultmask(uint32_t val)
496{
497 __asm__ volatile ("msr faultmask, %[val]\n" : : [val] "r" (val));
498}
499
500static inline uint32_t _ARMV7M_Get_control(void)
501{
502 uint32_t val;
503 __asm__ volatile ("mrs %[val], control\n" : [val] "=&r" (val));
504 return val;
505}
506
507static inline void _ARMV7M_Set_control(uint32_t val)
508{
509 __asm__ volatile ("msr control, %[val]\n" : : [val] "r" (val));
510}
511
512static inline uint32_t _ARMV7M_Get_MSP(void)
513{
514 uint32_t val;
515 __asm__ volatile ("mrs %[val], msp\n" : [val] "=&r" (val));
516 return val;
517}
518
519static inline void _ARMV7M_Set_MSP(uint32_t val)
520{
521 __asm__ volatile ("msr msp, %[val]\n" : : [val] "r" (val));
522}
523
524static inline uint32_t _ARMV7M_Get_PSP(void)
525{
526 uint32_t val;
527 __asm__ volatile ("mrs %[val], psp\n" : [val] "=&r" (val));
528 return val;
529}
530
531static inline void _ARMV7M_Set_PSP(uint32_t val)
532{
533 __asm__ volatile ("msr psp, %[val]\n" : : [val] "r" (val));
534}
535
536static inline uint32_t _ARMV7M_Get_XPSR(void)
537{
538 uint32_t val;
539 __asm__ volatile ("mrs %[val], xpsr\n" : [val] "=&r" (val));
540 return val;
541}
542
543static inline bool _ARMV7M_NVIC_Is_enabled( int irq )
544{
545 int index = irq >> 5;
546 uint32_t bit = 1U << (irq & 0x1f);
547
548 return (_ARMV7M_NVIC->iser [index] & bit) != 0;
549}
550
551static inline void _ARMV7M_NVIC_Set_enable( int irq )
552{
553 int index = irq >> 5;
554 uint32_t bit = 1U << (irq & 0x1f);
555
556 _ARMV7M_NVIC->iser [index] = bit;
557}
558
559static inline void _ARMV7M_NVIC_Clear_enable( int irq )
560{
561 int index = irq >> 5;
562 uint32_t bit = 1U << (irq & 0x1f);
563
564 _ARMV7M_NVIC->icer [index] = bit;
565}
566
567static inline bool _ARMV7M_NVIC_Is_pending( int irq )
568{
569 int index = irq >> 5;
570 uint32_t bit = 1U << (irq & 0x1f);
571
572 return (_ARMV7M_NVIC->ispr [index] & bit) != 0;
573}
574
575static inline void _ARMV7M_NVIC_Set_pending( int irq )
576{
577 int index = irq >> 5;
578 uint32_t bit = 1U << (irq & 0x1f);
579
580 _ARMV7M_NVIC->ispr [index] = bit;
581}
582
583static inline void _ARMV7M_NVIC_Clear_pending( int irq )
584{
585 int index = irq >> 5;
586 uint32_t bit = 1U << (irq & 0x1f);
587
588 _ARMV7M_NVIC->icpr [index] = bit;
589}
590
591static inline bool _ARMV7M_NVIC_Is_active( int irq )
592{
593 int index = irq >> 5;
594 uint32_t bit = 1U << (irq & 0x1f);
595
596 return (_ARMV7M_NVIC->iabr [index] & bit) != 0;
597}
598
599static inline void _ARMV7M_NVIC_Set_priority( int irq, int priority )
600{
601 _ARMV7M_NVIC->ipr [irq] = (uint8_t) priority;
602}
603
604static inline int _ARMV7M_NVIC_Get_priority( int irq )
605{
606 return _ARMV7M_NVIC->ipr [irq];
607}
608
609static inline bool _ARMV7M_DWT_Enable_CYCCNT( void )
610{
611 uint32_t demcr;
612 uint32_t dwt_ctrl;
613
614 demcr = _ARMV7M_DEBUG->demcr;
615 _ARMV7M_DEBUG->demcr = demcr | ARMV7M_DEBUG_DEMCR_TRCENA;
616 _ARM_Data_synchronization_barrier();
617
618 dwt_ctrl = _ARMV7M_DWT->ctrl;
619 if ((dwt_ctrl & ARMV7M_DWT_CTRL_NOCYCCNT) == 0) {
620 _ARMV7M_DWT->lar = ARMV7M_DWT_LAR_UNLOCK_MAGIC;
621 _ARM_Data_synchronization_barrier();
622 _ARMV7M_DWT->ctrl = dwt_ctrl | ARMV7M_DWT_CTRL_CYCCNTENA;
623 return true;
624 } else {
625 _ARMV7M_DEBUG->demcr = demcr;
626 return false;
627 }
628}
629
630int _ARMV7M_Get_exception_priority( int vector );
631
632void _ARMV7M_Set_exception_priority( int vector, int priority );
633
634ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index );
635
636void _ARMV7M_Set_exception_handler(
637 int index,
638 ARMV7M_Exception_handler handler
639);
640
644void _ARMV7M_Set_exception_priority_and_handler(
645 int index,
646 int priority,
647 ARMV7M_Exception_handler handler
648);
649
650void _ARMV7M_Exception_default( void );
651
652void _ARMV7M_Interrupt_service_enter( void );
653
654void _ARMV7M_Interrupt_service_leave( void );
655
656void _ARMV7M_Pendable_service_call( void );
657
658void _ARMV7M_Supervisor_call( void );
659
660void _ARMV7M_Clock_handler( void );
661
662static inline uint32_t _ARMV7M_MPU_Get_region_size(uintptr_t size)
663{
664 if ((size & (size - 1)) == 0) {
665 return ARMV7M_MPU_RASR_SIZE(30 - __builtin_clz(size));
666 } else {
667 return ARMV7M_MPU_RASR_SIZE(31 - __builtin_clz(size));
668 }
669}
670
671static inline void _ARMV7M_MPU_Set_region(
672 volatile ARMV7M_MPU *mpu,
673 uint32_t region,
674 uint32_t rasr,
675 const void *begin,
676 const void *end
677)
678{
679 uintptr_t size;
680 uint32_t rbar;
681
684 size = (uintptr_t) end - (uintptr_t) begin;
685
686 if ( (uintptr_t) end > (uintptr_t) begin ) {
687 rbar = (uintptr_t) begin | region | ARMV7M_MPU_RBAR_VALID;
688 rasr |= _ARMV7M_MPU_Get_region_size(size);
689 } else {
690 rbar = ARMV7M_MPU_RBAR_VALID | region;
691 rasr = 0;
692 }
693
694 mpu->rbar = rbar;
695 mpu->rasr = rasr;
696}
697
698static inline void _ARMV7M_MPU_Disable_region(
699 volatile ARMV7M_MPU *mpu,
700 uint32_t region
701)
702{
703 mpu->rbar = ARMV7M_MPU_RBAR_VALID | region;
704 mpu->rasr = 0;
705}
706
707static inline void _ARMV7M_MPU_Setup(
708 uint32_t ctrl,
709 const ARMV7M_MPU_Region_config *cfg,
710 size_t cfg_count
711)
712{
713 volatile ARMV7M_MPU *mpu;
714 volatile ARMV7M_SCB *scb;
715 uint32_t region_count;
716 uint32_t region;
717
718 mpu = _ARMV7M_MPU;
719 scb = _ARMV7M_SCB;
720
721 mpu->ctrl = 0;
722
723 _ARM_Data_synchronization_barrier();
724 _ARM_Instruction_synchronization_barrier();
725
726 region_count = ARMV7M_MPU_TYPE_DREGION_GET(mpu->type);
727
728 _Assert(cfg_count <= region_count);
729
730 for (region = 0; region < cfg_count; ++region) {
731 _ARMV7M_MPU_Set_region(
732 mpu,
733 region,
734 cfg[region].rasr,
735 cfg[region].begin,
736 cfg[region].end
737 );
738 }
739
740 for (region = cfg_count; region < region_count; ++region) {
741 _ARMV7M_MPU_Disable_region(mpu, region);
742 }
743
744 mpu->ctrl = ctrl;
745 scb->shcsr |= ARMV7M_SCB_SHCSR_MEMFAULTENA;
746
747 _ARM_Data_synchronization_barrier();
748 _ARM_Instruction_synchronization_barrier();
749}
750
751#endif /* ASM */
752
753#endif /* ARM_MULTILIB_ARCH_V7M */
754
755#ifdef __cplusplus
756}
757#endif /* __cplusplus */
758
759#endif /* RTEMS_SCORE_ARMV7M_H */
This header file provides the interfaces of the Assert Handler.
#define RTEMS_OBFUSCATE_VARIABLE(_var)
Obfuscates the variable so that the compiler cannot perform optimizations based on the variable value...
Definition: basedefs.h:690
#define _Assert(_e)
Assertion similar to assert() controlled via RTEMS_DEBUG instead of NDEBUG and static analysis runs.
Definition: assert.h:96
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
unsigned size
Definition: tte.h:1