RTEMS 6.1-rc1
arm-gic-tm27.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
11/*
12 * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36#ifndef _RTEMS_TMTEST27
37#error "This is an RTEMS internal file you must not include directly."
38#endif
39
40#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
41#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
42
43#include <bsp.h>
44#include <bsp/irq.h>
45
46#include <rtems/score/assert.h>
47
48#define MUST_WAIT_FOR_INTERRUPT 1
49
50#ifndef ARM_GIC_TM27_IRQ_LOW
51#define ARM_GIC_TM27_IRQ_LOW ARM_GIC_IRQ_SGI_12
52#endif
53
54#ifndef ARM_GIC_TM27_IRQ_HIGH
55#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13
56#endif
57
58#define ARM_GIC_TM27_PRIO_LOW 0x80
59
60#define ARM_GIC_TM27_PRIO_HIGH 0x00
61
62static inline void Install_tm27_vector( rtems_interrupt_handler handler )
63{
64 static rtems_interrupt_entry entry_low;
65 static rtems_interrupt_entry entry_high;
67
68 rtems_interrupt_entry_initialize(
69 &entry_low,
70 handler,
71 NULL,
72 "tm27 low"
73 );
75 ARM_GIC_TM27_IRQ_LOW,
77 &entry_low
78 );
80
81 sc = arm_gic_irq_set_priority(
82 ARM_GIC_TM27_IRQ_LOW,
83 ARM_GIC_TM27_PRIO_LOW
84 );
86
87 rtems_interrupt_entry_initialize(
88 &entry_high,
89 handler,
90 NULL,
91 "tm27 high"
92 );
94 ARM_GIC_TM27_IRQ_HIGH,
96 &entry_high
97 );
99
100 sc = arm_gic_irq_set_priority(
101 ARM_GIC_TM27_IRQ_HIGH,
102 ARM_GIC_TM27_PRIO_HIGH
103 );
105}
106
107static inline void Cause_tm27_intr(void)
108{
110
111 sc = arm_gic_irq_generate_software_irq(
112 ARM_GIC_TM27_IRQ_LOW,
113 1U << _SMP_Get_current_processor()
114 );
116}
117
118static inline void Clear_tm27_intr(void)
119{
120 /* Nothing to do */
121}
122
123static inline void Lower_tm27_intr(void)
124{
126
127 sc = arm_gic_irq_generate_software_irq(
128 ARM_GIC_TM27_IRQ_HIGH,
129 1U << _SMP_Get_current_processor()
130 );
132}
133
134#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */
This header file provides the interfaces of the Assert Handler.
rtems_status_code rtems_interrupt_entry_install(rtems_vector_number vector, rtems_option options, rtems_interrupt_entry *entry)
Installs the interrupt entry at the interrupt vector.
Definition: irq-generic.c:264
#define RTEMS_INTERRUPT_UNIQUE
This interrupt handler install option ensures that the interrupt handler is unique.
Definition: intr.h:907
void(* rtems_interrupt_handler)(void *)
Interrupt handler routines shall have this type.
Definition: intr.h:965
rtems_status_code
This enumeration provides status codes for directives of the Classic API.
Definition: status.h:85
@ RTEMS_SUCCESSFUL
This status code indicates successful completion of a requested operation.
Definition: status.h:90
#define _Assert_Unused_variable_equals(_var, _val)
Assert if unused return value is equal.
Definition: assert.h:108
#define NULL
Requests a GPIO pin group configuration.
Definition: xil_types.h:54
This structure represents an interrupt entry.
Definition: intr.h:1005