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#define | A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0) |
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#define | A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1) |
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#define | A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2) |
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#define | A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3) |
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#define | A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4) |
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#define | A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5) |
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#define | A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6) |
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#define | A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1) |
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#define | A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1) |
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#define | A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) |
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#define | A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7) |
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#define | A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) |
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#define | A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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#define | A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15) |
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#define | A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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#define | A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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#define | A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) |
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#define | A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ |
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#define | A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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#define | A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) |
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#define | A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ |
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#define | A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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#define | A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) |
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#define | A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ |
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#define | A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) |
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#define | A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) |
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#define | A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ |
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#define | A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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#define | A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0) |
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#define | A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) |
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#define | A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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#define | A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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#define | A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3) |
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#define | A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2) |
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#define | A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1) |
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#define | A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0) |
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#define | A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0) |
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#define | A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) |
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#define | A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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#define | A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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#define | A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2) |
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#define | A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1) |
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#define | A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0) |
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#define | A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0) |
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This header file provides the interfaces of the Cortex-A9 MPCore Support.