RTEMS 6.1-rc1
alt_qspi_private.h
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7/******************************************************************************
8 *
9 * Copyright 2013 Altera Corporation. All Rights Reserved.
10 *
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12 * modification, are permitted provided that the following conditions are met:
13 *
14 * 1. Redistributions of source code must retain the above copyright notice,
15 * this list of conditions and the following disclaimer.
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36
41#ifndef __ALT_QSPI_PRIVATE_H__
42#define __ALT_QSPI_PRIVATE_H__
43
44#include "socal/socal.h"
45
46//
47// This section provisions support for various flash devices.
48//
49
50#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1
51
53
54#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00
55#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B
56#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000
57#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B
58#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000
59#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB
60#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000
61#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB
62
63#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
64#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000
65#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB
66#endif
67
69
70// Default delay timing (in ns) for N25Q.
71// These values are from the N25Q handbook. The timing correctness is difficult
72// to test because the test setup does not feature mutliple chips.
73#define ALT_QSPI_TSHSL_NS_DEF (50)
74#define ALT_QSPI_TSD2D_NS_DEF (0)
75#define ALT_QSPI_TCHSH_NS_DEF (4)
76#define ALT_QSPI_TSLCH_NS_DEF (4)
77
78/*
79// Default delay timing (in ns)
80#define ALT_QSPI_TSHSL_NS_DEF (200)
81#define ALT_QSPI_TSD2D_NS_DEF (255)
82#define ALT_QSPI_TCHSH_NS_DEF (20)
83#define ALT_QSPI_TSLCH_NS_DEF (20)
84*/
85
86// Flash commands
87#define ALT_QSPI_STIG_OPCODE_READ (0x03)
88#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13)
89#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B)
90#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B)
91#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B)
92#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB)
93#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB)
94#define ALT_QSPI_STIG_OPCODE_PP (0x02)
95#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2)
96#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32)
97#define ALT_QSPI_STIG_OPCODE_RDID (0x9F)
98#define ALT_QSPI_STIG_OPCODE_WREN (0x06)
99#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04)
100#define ALT_QSPI_STIG_OPCODE_RDSR (0x05)
101#define ALT_QSPI_STIG_OPCODE_WRSR (0x01)
102#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20)
103#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8)
104#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7)
105#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4)
106#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60)
107#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8)
108#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5)
109#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05)
110#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01)
111#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7)
112#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9)
113
114// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts.
115#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
116#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66)
117#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99)
118#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70)
119#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50)
120#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A)
121#endif
122
123// Spansion commands
124// #define OPCODE_ECRM (0xFF) // Exit continuous read mode
125
126#define QSPI_READ_CLK_MHZ (50)
127#define QSPI_FASTREAD_CLK_MHZ (100)
128
129// Manufacturer ID
130#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20)
131#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron
132#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF)
133#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion
134#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2)
135#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F)
136
137#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff)
138#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff)
139
140#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1)
141#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1)
142#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1)
143#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1)
144#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1)
145#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1)
146#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1)
147
148#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1)
149
151
152#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff)
153
154ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size);
155
156ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout);
157ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy,
158 uint32_t num_bytes, uint32_t * output,
159 uint32_t timeout);
160ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy,
161 uint32_t num_bytes, const uint32_t * input,
162 uint32_t timeout);
163ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy,
164 uint32_t address,
165 uint32_t timeout);
166
167ALT_STATUS_CODE alt_qspi_device_wren(void);
168ALT_STATUS_CODE alt_qspi_device_wrdis(void);
169ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid);
170ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param);
171ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank);
172
173#endif // __ALT_PRIVATE_QSPI_H__
ALT_STATUS_CODE
int32_t ALT_STATUS_CODE
Definition: hwlib.h:60
size
unsigned size
Definition: tte.h:1
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