37#ifndef _RTEMS_SCORE_AARCH32_SYSTEM_REGISTERS_H
38#define _RTEMS_SCORE_AARCH32_SYSTEM_REGISTERS_H
65static inline uint32_t _AArch32_Read_actlr(
void )
70 "mrc p15, 0, %0, c1, c0, 1" :
"=&r" ( value ) : :
"memory"
76static inline void _AArch32_Write_actlr( uint32_t value )
79 "mcr p15, 0, %0, c1, c0, 1" : :
"r" ( value ) :
"memory"
85static inline uint32_t _AArch32_Read_actlr2(
void )
90 "mrc p15, 0, %0, c1, c0, 3" :
"=&r" ( value ) : :
"memory"
96static inline void _AArch32_Write_actlr2( uint32_t value )
99 "mcr p15, 0, %0, c1, c0, 3" : :
"r" ( value ) :
"memory"
105static inline uint32_t _AArch32_Read_adfsr(
void )
110 "mrc p15, 0, %0, c5, c1, 0" :
"=&r" ( value ) : :
"memory"
116static inline void _AArch32_Write_adfsr( uint32_t value )
119 "mcr p15, 0, %0, c5, c1, 0" : :
"r" ( value ) :
"memory"
125static inline uint32_t _AArch32_Read_aidr(
void )
130 "mrc p15, 1, %0, c0, c0, 7" :
"=&r" ( value ) : :
"memory"
138static inline uint32_t _AArch32_Read_aifsr(
void )
143 "mrc p15, 0, %0, c5, c1, 1" :
"=&r" ( value ) : :
"memory"
149static inline void _AArch32_Write_aifsr( uint32_t value )
152 "mcr p15, 0, %0, c5, c1, 1" : :
"r" ( value ) :
"memory"
158static inline uint32_t _AArch32_Read_amair0(
void )
163 "mrc p15, 0, %0, c10, c3, 0" :
"=&r" ( value ) : :
"memory"
169static inline void _AArch32_Write_amair0( uint32_t value )
172 "mcr p15, 0, %0, c10, c3, 0" : :
"r" ( value ) :
"memory"
178static inline uint32_t _AArch32_Read_amair1(
void )
183 "mrc p15, 0, %0, c10, c3, 1" :
"=&r" ( value ) : :
"memory"
189static inline void _AArch32_Write_amair1( uint32_t value )
192 "mcr p15, 0, %0, c10, c3, 1" : :
"r" ( value ) :
"memory"
198#define AARCH32_APSR_GE( _val ) ( ( _val ) << 16 )
199#define AARCH32_APSR_GE_SHIFT 16
200#define AARCH32_APSR_GE_MASK 0xf0000U
201#define AARCH32_APSR_GE_GET( _reg ) \
202 ( ( ( _reg ) >> 16 ) & 0xfU )
204#define AARCH32_APSR_Q 0x8000000U
206#define AARCH32_APSR_V 0x10000000U
208#define AARCH32_APSR_C 0x20000000U
210#define AARCH32_APSR_Z 0x40000000U
212#define AARCH32_APSR_N 0x80000000U
216static inline void _AArch32_Write_ats12nsopr( uint32_t value )
219 "mcr p15, 0, %0, c7, c8, 4" : :
"r" ( value ) :
"memory"
225static inline void _AArch32_Write_ats12nsopw( uint32_t value )
228 "mcr p15, 0, %0, c7, c8, 5" : :
"r" ( value ) :
"memory"
234static inline void _AArch32_Write_ats12nsour( uint32_t value )
237 "mcr p15, 0, %0, c7, c8, 6" : :
"r" ( value ) :
"memory"
243static inline void _AArch32_Write_ats12nsouw( uint32_t value )
246 "mcr p15, 0, %0, c7, c8, 7" : :
"r" ( value ) :
"memory"
252static inline void _AArch32_Write_ats1cpr( uint32_t value )
255 "mcr p15, 0, %0, c7, c8, 0" : :
"r" ( value ) :
"memory"
261static inline void _AArch32_Write_ats1cprp( uint32_t value )
264 "mcr p15, 0, %0, c7, c9, 0" : :
"r" ( value ) :
"memory"
270static inline void _AArch32_Write_ats1cpw( uint32_t value )
273 "mcr p15, 0, %0, c7, c8, 1" : :
"r" ( value ) :
"memory"
279static inline void _AArch32_Write_ats1cpwp( uint32_t value )
282 "mcr p15, 0, %0, c7, c9, 1" : :
"r" ( value ) :
"memory"
288static inline void _AArch32_Write_ats1cur( uint32_t value )
291 "mcr p15, 0, %0, c7, c8, 2" : :
"r" ( value ) :
"memory"
297static inline void _AArch32_Write_ats1cuw( uint32_t value )
300 "mcr p15, 0, %0, c7, c8, 3" : :
"r" ( value ) :
"memory"
306static inline void _AArch32_Write_ats1hr( uint32_t value )
309 "mcr p15, 4, %0, c7, c8, 0" : :
"r" ( value ) :
"memory"
315static inline void _AArch32_Write_ats1hw( uint32_t value )
318 "mcr p15, 4, %0, c7, c8, 1" : :
"r" ( value ) :
"memory"
324static inline void _AArch32_Write_bpiall( uint32_t value )
327 "mcr p15, 0, %0, c7, c5, 6" : :
"r" ( value ) :
"memory"
333static inline void _AArch32_Write_bpiallis( uint32_t value )
336 "mcr p15, 0, %0, c7, c1, 6" : :
"r" ( value ) :
"memory"
342static inline void _AArch32_Write_bpimva( uint32_t value )
345 "mcr p15, 0, %0, c7, c5, 7" : :
"r" ( value ) :
"memory"
351#define AARCH32_CCSIDR_LINESIZE( _val ) ( ( _val ) << 0 )
352#define AARCH32_CCSIDR_LINESIZE_SHIFT 0
353#define AARCH32_CCSIDR_LINESIZE_MASK 0x7U
354#define AARCH32_CCSIDR_LINESIZE_GET( _reg ) \
355 ( ( ( _reg ) >> 0 ) & 0x7U )
357#define AARCH32_CCSIDR_ASSOCIATIVITY_0( _val ) ( ( _val ) << 3 )
358#define AARCH32_CCSIDR_ASSOCIATIVITY_SHIFT_0 3
359#define AARCH32_CCSIDR_ASSOCIATIVITY_MASK_0 0x1ff8U
360#define AARCH32_CCSIDR_ASSOCIATIVITY_GET_0( _reg ) \
361 ( ( ( _reg ) >> 3 ) & 0x3ffU )
363#define AARCH32_CCSIDR_ASSOCIATIVITY_1( _val ) ( ( _val ) << 3 )
364#define AARCH32_CCSIDR_ASSOCIATIVITY_SHIFT_1 3
365#define AARCH32_CCSIDR_ASSOCIATIVITY_MASK_1 0xfffff8U
366#define AARCH32_CCSIDR_ASSOCIATIVITY_GET_1( _reg ) \
367 ( ( ( _reg ) >> 3 ) & 0x1fffffU )
369#define AARCH32_CCSIDR_NUMSETS( _val ) ( ( _val ) << 13 )
370#define AARCH32_CCSIDR_NUMSETS_SHIFT 13
371#define AARCH32_CCSIDR_NUMSETS_MASK 0xfffe000U
372#define AARCH32_CCSIDR_NUMSETS_GET( _reg ) \
373 ( ( ( _reg ) >> 13 ) & 0x7fffU )
375static inline uint32_t _AArch32_Read_ccsidr(
void )
380 "mrc p15, 1, %0, c0, c0, 0" :
"=&r" ( value ) : :
"memory"
388#define AARCH32_CCSIDR2_NUMSETS( _val ) ( ( _val ) << 0 )
389#define AARCH32_CCSIDR2_NUMSETS_SHIFT 0
390#define AARCH32_CCSIDR2_NUMSETS_MASK 0xffffffU
391#define AARCH32_CCSIDR2_NUMSETS_GET( _reg ) \
392 ( ( ( _reg ) >> 0 ) & 0xffffffU )
394static inline uint32_t _AArch32_Read_ccsidr2(
void )
399 "mrc p15, 1, %0, c0, c0, 2" :
"=&r" ( value ) : :
"memory"
407#define AARCH32_CFPRCTX_ASID( _val ) ( ( _val ) << 0 )
408#define AARCH32_CFPRCTX_ASID_SHIFT 0
409#define AARCH32_CFPRCTX_ASID_MASK 0xffU
410#define AARCH32_CFPRCTX_ASID_GET( _reg ) \
411 ( ( ( _reg ) >> 0 ) & 0xffU )
413#define AARCH32_CFPRCTX_GASID 0x100U
415#define AARCH32_CFPRCTX_VMID( _val ) ( ( _val ) << 16 )
416#define AARCH32_CFPRCTX_VMID_SHIFT 16
417#define AARCH32_CFPRCTX_VMID_MASK 0xff0000U
418#define AARCH32_CFPRCTX_VMID_GET( _reg ) \
419 ( ( ( _reg ) >> 16 ) & 0xffU )
421#define AARCH32_CFPRCTX_EL( _val ) ( ( _val ) << 24 )
422#define AARCH32_CFPRCTX_EL_SHIFT 24
423#define AARCH32_CFPRCTX_EL_MASK 0x3000000U
424#define AARCH32_CFPRCTX_EL_GET( _reg ) \
425 ( ( ( _reg ) >> 24 ) & 0x3U )
427#define AARCH32_CFPRCTX_NS 0x4000000U
429#define AARCH32_CFPRCTX_GVMID 0x8000000U
431static inline void _AArch32_Write_cfprctx( uint32_t value )
434 "mcr p15, 0, %0, c7, c3, 4" : :
"r" ( value ) :
"memory"
440#define AARCH32_CLIDR_LOUIS( _val ) ( ( _val ) << 21 )
441#define AARCH32_CLIDR_LOUIS_SHIFT 21
442#define AARCH32_CLIDR_LOUIS_MASK 0xe00000U
443#define AARCH32_CLIDR_LOUIS_GET( _reg ) \
444 ( ( ( _reg ) >> 21 ) & 0x7U )
446#define AARCH32_CLIDR_LOC( _val ) ( ( _val ) << 24 )
447#define AARCH32_CLIDR_LOC_SHIFT 24
448#define AARCH32_CLIDR_LOC_MASK 0x7000000U
449#define AARCH32_CLIDR_LOC_GET( _reg ) \
450 ( ( ( _reg ) >> 24 ) & 0x7U )
452#define AARCH32_CLIDR_LOUU( _val ) ( ( _val ) << 27 )
453#define AARCH32_CLIDR_LOUU_SHIFT 27
454#define AARCH32_CLIDR_LOUU_MASK 0x38000000U
455#define AARCH32_CLIDR_LOUU_GET( _reg ) \
456 ( ( ( _reg ) >> 27 ) & 0x7U )
458#define AARCH32_CLIDR_ICB( _val ) ( ( _val ) << 30 )
459#define AARCH32_CLIDR_ICB_SHIFT 30
460#define AARCH32_CLIDR_ICB_MASK 0xc0000000U
461#define AARCH32_CLIDR_ICB_GET( _reg ) \
462 ( ( ( _reg ) >> 30 ) & 0x3U )
464static inline uint32_t _AArch32_Read_clidr(
void )
469 "mrc p15, 1, %0, c0, c0, 1" :
"=&r" ( value ) : :
"memory"
477#define AARCH32_CONTEXTIDR_ASID( _val ) ( ( _val ) << 0 )
478#define AARCH32_CONTEXTIDR_ASID_SHIFT 0
479#define AARCH32_CONTEXTIDR_ASID_MASK 0xffU
480#define AARCH32_CONTEXTIDR_ASID_GET( _reg ) \
481 ( ( ( _reg ) >> 0 ) & 0xffU )
483#define AARCH32_CONTEXTIDR_PROCID( _val ) ( ( _val ) << 8 )
484#define AARCH32_CONTEXTIDR_PROCID_SHIFT 8
485#define AARCH32_CONTEXTIDR_PROCID_MASK 0xffffff00U
486#define AARCH32_CONTEXTIDR_PROCID_GET( _reg ) \
487 ( ( ( _reg ) >> 8 ) & 0xffffffU )
489static inline uint32_t _AArch32_Read_contextidr(
void )
494 "mrc p15, 0, %0, c13, c0, 1" :
"=&r" ( value ) : :
"memory"
500static inline void _AArch32_Write_contextidr( uint32_t value )
503 "mcr p15, 0, %0, c13, c0, 1" : :
"r" ( value ) :
"memory"
509static inline void _AArch32_Write_cp15dmb( uint32_t value )
512 "mcr p15, 0, %0, c7, c10, 5" : :
"r" ( value ) :
"memory"
518static inline void _AArch32_Write_cp15dsb( uint32_t value )
521 "mcr p15, 0, %0, c7, c10, 4" : :
"r" ( value ) :
"memory"
527static inline void _AArch32_Write_cp15isb( uint32_t value )
530 "mcr p15, 0, %0, c7, c5, 4" : :
"r" ( value ) :
"memory"
536#define AARCH32_CPACR_CP10( _val ) ( ( _val ) << 20 )
537#define AARCH32_CPACR_CP10_SHIFT 20
538#define AARCH32_CPACR_CP10_MASK 0x300000U
539#define AARCH32_CPACR_CP10_GET( _reg ) \
540 ( ( ( _reg ) >> 20 ) & 0x3U )
542#define AARCH32_CPACR_CP11( _val ) ( ( _val ) << 22 )
543#define AARCH32_CPACR_CP11_SHIFT 22
544#define AARCH32_CPACR_CP11_MASK 0xc00000U
545#define AARCH32_CPACR_CP11_GET( _reg ) \
546 ( ( ( _reg ) >> 22 ) & 0x3U )
548#define AARCH32_CPACR_TRCDIS 0x10000000U
550#define AARCH32_CPACR_ASEDIS 0x80000000U
552static inline uint32_t _AArch32_Read_cpacr(
void )
557 "mrc p15, 0, %0, c1, c0, 2" :
"=&r" ( value ) : :
"memory"
563static inline void _AArch32_Write_cpacr( uint32_t value )
566 "mcr p15, 0, %0, c1, c0, 2" : :
"r" ( value ) :
"memory"
572#define AARCH32_CPSR_M( _val ) ( ( _val ) << 0 )
573#define AARCH32_CPSR_M_SHIFT 0
574#define AARCH32_CPSR_M_MASK 0xfU
575#define AARCH32_CPSR_M_GET( _reg ) \
576 ( ( ( _reg ) >> 0 ) & 0xfU )
578#define AARCH32_CPSR_F 0x40U
580#define AARCH32_CPSR_I 0x80U
582#define AARCH32_CPSR_A 0x100U
584#define AARCH32_CPSR_E 0x200U
586#define AARCH32_CPSR_GE( _val ) ( ( _val ) << 16 )
587#define AARCH32_CPSR_GE_SHIFT 16
588#define AARCH32_CPSR_GE_MASK 0xf0000U
589#define AARCH32_CPSR_GE_GET( _reg ) \
590 ( ( ( _reg ) >> 16 ) & 0xfU )
592#define AARCH32_CPSR_DIT 0x200000U
594#define AARCH32_CPSR_PAN 0x400000U
596#define AARCH32_CPSR_SSBS 0x800000U
598#define AARCH32_CPSR_Q 0x8000000U
600#define AARCH32_CPSR_V 0x10000000U
602#define AARCH32_CPSR_C 0x20000000U
604#define AARCH32_CPSR_Z 0x40000000U
606#define AARCH32_CPSR_N 0x80000000U
610#define AARCH32_CPPRCTX_ASID( _val ) ( ( _val ) << 0 )
611#define AARCH32_CPPRCTX_ASID_SHIFT 0
612#define AARCH32_CPPRCTX_ASID_MASK 0xffU
613#define AARCH32_CPPRCTX_ASID_GET( _reg ) \
614 ( ( ( _reg ) >> 0 ) & 0xffU )
616#define AARCH32_CPPRCTX_GASID 0x100U
618#define AARCH32_CPPRCTX_VMID( _val ) ( ( _val ) << 16 )
619#define AARCH32_CPPRCTX_VMID_SHIFT 16
620#define AARCH32_CPPRCTX_VMID_MASK 0xff0000U
621#define AARCH32_CPPRCTX_VMID_GET( _reg ) \
622 ( ( ( _reg ) >> 16 ) & 0xffU )
624#define AARCH32_CPPRCTX_EL( _val ) ( ( _val ) << 24 )
625#define AARCH32_CPPRCTX_EL_SHIFT 24
626#define AARCH32_CPPRCTX_EL_MASK 0x3000000U
627#define AARCH32_CPPRCTX_EL_GET( _reg ) \
628 ( ( ( _reg ) >> 24 ) & 0x3U )
630#define AARCH32_CPPRCTX_NS 0x4000000U
632#define AARCH32_CPPRCTX_GVMID 0x8000000U
634static inline void _AArch32_Write_cpprctx( uint32_t value )
637 "mcr p15, 0, %0, c7, c3, 7" : :
"r" ( value ) :
"memory"
643#define AARCH32_CSSELR_IND 0x1U
645#define AARCH32_CSSELR_LEVEL( _val ) ( ( _val ) << 1 )
646#define AARCH32_CSSELR_LEVEL_SHIFT 1
647#define AARCH32_CSSELR_LEVEL_MASK 0xeU
648#define AARCH32_CSSELR_LEVEL_GET( _reg ) \
649 ( ( ( _reg ) >> 1 ) & 0x7U )
651static inline uint32_t _AArch32_Read_csselr(
void )
656 "mrc p15, 2, %0, c0, c0, 0" :
"=&r" ( value ) : :
"memory"
662static inline void _AArch32_Write_csselr( uint32_t value )
665 "mcr p15, 2, %0, c0, c0, 0" : :
"r" ( value ) :
"memory"
671#define AARCH32_CTR_IMINLINE( _val ) ( ( _val ) << 0 )
672#define AARCH32_CTR_IMINLINE_SHIFT 0
673#define AARCH32_CTR_IMINLINE_MASK 0xfU
674#define AARCH32_CTR_IMINLINE_GET( _reg ) \
675 ( ( ( _reg ) >> 0 ) & 0xfU )
677#define AARCH32_CTR_L1IP( _val ) ( ( _val ) << 14 )
678#define AARCH32_CTR_L1IP_SHIFT 14
679#define AARCH32_CTR_L1IP_MASK 0xc000U
680#define AARCH32_CTR_L1IP_GET( _reg ) \
681 ( ( ( _reg ) >> 14 ) & 0x3U )
683#define AARCH32_CTR_DMINLINE( _val ) ( ( _val ) << 16 )
684#define AARCH32_CTR_DMINLINE_SHIFT 16
685#define AARCH32_CTR_DMINLINE_MASK 0xf0000U
686#define AARCH32_CTR_DMINLINE_GET( _reg ) \
687 ( ( ( _reg ) >> 16 ) & 0xfU )
689#define AARCH32_CTR_ERG( _val ) ( ( _val ) << 20 )
690#define AARCH32_CTR_ERG_SHIFT 20
691#define AARCH32_CTR_ERG_MASK 0xf00000U
692#define AARCH32_CTR_ERG_GET( _reg ) \
693 ( ( ( _reg ) >> 20 ) & 0xfU )
695#define AARCH32_CTR_CWG( _val ) ( ( _val ) << 24 )
696#define AARCH32_CTR_CWG_SHIFT 24
697#define AARCH32_CTR_CWG_MASK 0xf000000U
698#define AARCH32_CTR_CWG_GET( _reg ) \
699 ( ( ( _reg ) >> 24 ) & 0xfU )
701#define AARCH32_CTR_IDC 0x10000000U
703#define AARCH32_CTR_DIC 0x20000000U
705static inline uint32_t _AArch32_Read_ctr(
void )
710 "mrc p15, 0, %0, c0, c0, 1" :
"=&r" ( value ) : :
"memory"
718static inline uint32_t _AArch32_Read_dacr(
void )
723 "mrc p15, 0, %0, c3, c0, 0" :
"=&r" ( value ) : :
"memory"
729static inline void _AArch32_Write_dacr( uint32_t value )
732 "mcr p15, 0, %0, c3, c0, 0" : :
"r" ( value ) :
"memory"
738static inline void _AArch32_Write_dccimvac( uint32_t value )
741 "mcr p15, 0, %0, c7, c14, 1" : :
"r" ( value ) :
"memory"
747#define AARCH32_DCCISW_LEVEL( _val ) ( ( _val ) << 1 )
748#define AARCH32_DCCISW_LEVEL_SHIFT 1
749#define AARCH32_DCCISW_LEVEL_MASK 0xeU
750#define AARCH32_DCCISW_LEVEL_GET( _reg ) \
751 ( ( ( _reg ) >> 1 ) & 0x7U )
753#define AARCH32_DCCISW_SETWAY( _val ) ( ( _val ) << 4 )
754#define AARCH32_DCCISW_SETWAY_SHIFT 4
755#define AARCH32_DCCISW_SETWAY_MASK 0xfffffff0U
756#define AARCH32_DCCISW_SETWAY_GET( _reg ) \
757 ( ( ( _reg ) >> 4 ) & 0xfffffffU )
759static inline void _AArch32_Write_dccisw( uint32_t value )
762 "mcr p15, 0, %0, c7, c14, 2" : :
"r" ( value ) :
"memory"
768static inline void _AArch32_Write_dccmvac( uint32_t value )
771 "mcr p15, 0, %0, c7, c10, 1" : :
"r" ( value ) :
"memory"
777static inline void _AArch32_Write_dccmvau( uint32_t value )
780 "mcr p15, 0, %0, c7, c11, 1" : :
"r" ( value ) :
"memory"
786#define AARCH32_DCCSW_LEVEL( _val ) ( ( _val ) << 1 )
787#define AARCH32_DCCSW_LEVEL_SHIFT 1
788#define AARCH32_DCCSW_LEVEL_MASK 0xeU
789#define AARCH32_DCCSW_LEVEL_GET( _reg ) \
790 ( ( ( _reg ) >> 1 ) & 0x7U )
792#define AARCH32_DCCSW_SETWAY( _val ) ( ( _val ) << 4 )
793#define AARCH32_DCCSW_SETWAY_SHIFT 4
794#define AARCH32_DCCSW_SETWAY_MASK 0xfffffff0U
795#define AARCH32_DCCSW_SETWAY_GET( _reg ) \
796 ( ( ( _reg ) >> 4 ) & 0xfffffffU )
798static inline void _AArch32_Write_dccsw( uint32_t value )
801 "mcr p15, 0, %0, c7, c10, 2" : :
"r" ( value ) :
"memory"
807static inline void _AArch32_Write_dcimvac( uint32_t value )
810 "mcr p15, 0, %0, c7, c6, 1" : :
"r" ( value ) :
"memory"
816#define AARCH32_DCISW_LEVEL( _val ) ( ( _val ) << 1 )
817#define AARCH32_DCISW_LEVEL_SHIFT 1
818#define AARCH32_DCISW_LEVEL_MASK 0xeU
819#define AARCH32_DCISW_LEVEL_GET( _reg ) \
820 ( ( ( _reg ) >> 1 ) & 0x7U )
822#define AARCH32_DCISW_SETWAY( _val ) ( ( _val ) << 4 )
823#define AARCH32_DCISW_SETWAY_SHIFT 4
824#define AARCH32_DCISW_SETWAY_MASK 0xfffffff0U
825#define AARCH32_DCISW_SETWAY_GET( _reg ) \
826 ( ( ( _reg ) >> 4 ) & 0xfffffffU )
828static inline void _AArch32_Write_dcisw( uint32_t value )
831 "mcr p15, 0, %0, c7, c6, 2" : :
"r" ( value ) :
"memory"
837static inline uint32_t _AArch32_Read_dfar(
void )
842 "mrc p15, 0, %0, c6, c0, 0" :
"=&r" ( value ) : :
"memory"
848static inline void _AArch32_Write_dfar( uint32_t value )
851 "mcr p15, 0, %0, c6, c0, 0" : :
"r" ( value ) :
"memory"
857#define AARCH32_DFSR_FS_3_0( _val ) ( ( _val ) << 0 )
858#define AARCH32_DFSR_FS_3_0_SHIFT 0
859#define AARCH32_DFSR_FS_3_0_MASK 0xfU
860#define AARCH32_DFSR_FS_3_0_GET( _reg ) \
861 ( ( ( _reg ) >> 0 ) & 0xfU )
863#define AARCH32_DFSR_STATUS( _val ) ( ( _val ) << 0 )
864#define AARCH32_DFSR_STATUS_SHIFT 0
865#define AARCH32_DFSR_STATUS_MASK 0x3fU
866#define AARCH32_DFSR_STATUS_GET( _reg ) \
867 ( ( ( _reg ) >> 0 ) & 0x3fU )
869#define AARCH32_DFSR_DOMAIN( _val ) ( ( _val ) << 4 )
870#define AARCH32_DFSR_DOMAIN_SHIFT 4
871#define AARCH32_DFSR_DOMAIN_MASK 0xf0U
872#define AARCH32_DFSR_DOMAIN_GET( _reg ) \
873 ( ( ( _reg ) >> 4 ) & 0xfU )
875#define AARCH32_DFSR_LPAE 0x200U
877#define AARCH32_DFSR_FS_4 0x400U
879#define AARCH32_DFSR_WNR 0x800U
881#define AARCH32_DFSR_EXT 0x1000U
883#define AARCH32_DFSR_CM 0x2000U
885#define AARCH32_DFSR_AET( _val ) ( ( _val ) << 14 )
886#define AARCH32_DFSR_AET_SHIFT 14
887#define AARCH32_DFSR_AET_MASK 0xc000U
888#define AARCH32_DFSR_AET_GET( _reg ) \
889 ( ( ( _reg ) >> 14 ) & 0x3U )
891#define AARCH32_DFSR_FNV 0x10000U
893static inline uint32_t _AArch32_Read_dfsr(
void )
898 "mrc p15, 0, %0, c5, c0, 0" :
"=&r" ( value ) : :
"memory"
904static inline void _AArch32_Write_dfsr( uint32_t value )
907 "mcr p15, 0, %0, c5, c0, 0" : :
"r" ( value ) :
"memory"
913static inline void _AArch32_Write_dtlbiall( uint32_t value )
916 "mcr p15, 0, %0, c8, c6, 0" : :
"r" ( value ) :
"memory"
922#define AARCH32_DTLBIASID_ASID( _val ) ( ( _val ) << 0 )
923#define AARCH32_DTLBIASID_ASID_SHIFT 0
924#define AARCH32_DTLBIASID_ASID_MASK 0xffU
925#define AARCH32_DTLBIASID_ASID_GET( _reg ) \
926 ( ( ( _reg ) >> 0 ) & 0xffU )
928static inline void _AArch32_Write_dtlbiasid( uint32_t value )
931 "mcr p15, 0, %0, c8, c6, 2" : :
"r" ( value ) :
"memory"
937#define AARCH32_DTLBIMVA_ASID( _val ) ( ( _val ) << 0 )
938#define AARCH32_DTLBIMVA_ASID_SHIFT 0
939#define AARCH32_DTLBIMVA_ASID_MASK 0xffU
940#define AARCH32_DTLBIMVA_ASID_GET( _reg ) \
941 ( ( ( _reg ) >> 0 ) & 0xffU )
943#define AARCH32_DTLBIMVA_VA( _val ) ( ( _val ) << 12 )
944#define AARCH32_DTLBIMVA_VA_SHIFT 12
945#define AARCH32_DTLBIMVA_VA_MASK 0xfffff000U
946#define AARCH32_DTLBIMVA_VA_GET( _reg ) \
947 ( ( ( _reg ) >> 12 ) & 0xfffffU )
949static inline void _AArch32_Write_dtlbimva( uint32_t value )
952 "mcr p15, 0, %0, c8, c6, 1" : :
"r" ( value ) :
"memory"
958#define AARCH32_DVPRCTX_ASID( _val ) ( ( _val ) << 0 )
959#define AARCH32_DVPRCTX_ASID_SHIFT 0
960#define AARCH32_DVPRCTX_ASID_MASK 0xffU
961#define AARCH32_DVPRCTX_ASID_GET( _reg ) \
962 ( ( ( _reg ) >> 0 ) & 0xffU )
964#define AARCH32_DVPRCTX_GASID 0x100U
966#define AARCH32_DVPRCTX_VMID( _val ) ( ( _val ) << 16 )
967#define AARCH32_DVPRCTX_VMID_SHIFT 16
968#define AARCH32_DVPRCTX_VMID_MASK 0xff0000U
969#define AARCH32_DVPRCTX_VMID_GET( _reg ) \
970 ( ( ( _reg ) >> 16 ) & 0xffU )
972#define AARCH32_DVPRCTX_EL( _val ) ( ( _val ) << 24 )
973#define AARCH32_DVPRCTX_EL_SHIFT 24
974#define AARCH32_DVPRCTX_EL_MASK 0x3000000U
975#define AARCH32_DVPRCTX_EL_GET( _reg ) \
976 ( ( ( _reg ) >> 24 ) & 0x3U )
978#define AARCH32_DVPRCTX_NS 0x4000000U
980#define AARCH32_DVPRCTX_GVMID 0x8000000U
982static inline void _AArch32_Write_dvprctx( uint32_t value )
985 "mcr p15, 0, %0, c7, c3, 5" : :
"r" ( value ) :
"memory"
991static inline uint32_t _AArch32_Read_fcseidr(
void )
996 "mrc p15, 0, %0, c13, c0, 0" :
"=&r" ( value ) : :
"memory"
1002static inline void _AArch32_Write_fcseidr( uint32_t value )
1005 "mcr p15, 0, %0, c13, c0, 0" : :
"r" ( value ) :
"memory"
1011#define AARCH32_FPEXC_IOF 0x1U
1013#define AARCH32_FPEXC_DZF 0x2U
1015#define AARCH32_FPEXC_OFF 0x4U
1017#define AARCH32_FPEXC_UFF 0x8U
1019#define AARCH32_FPEXC_IXF 0x10U
1021#define AARCH32_FPEXC_IDF 0x80U
1023#define AARCH32_FPEXC_VECITR( _val ) ( ( _val ) << 8 )
1024#define AARCH32_FPEXC_VECITR_SHIFT 8
1025#define AARCH32_FPEXC_VECITR_MASK 0x700U
1026#define AARCH32_FPEXC_VECITR_GET( _reg ) \
1027 ( ( ( _reg ) >> 8 ) & 0x7U )
1029#define AARCH32_FPEXC_TFV 0x4000000U
1031#define AARCH32_FPEXC_VV 0x8000000U
1033#define AARCH32_FPEXC_FP2V 0x10000000U
1035#define AARCH32_FPEXC_DEX 0x20000000U
1037#define AARCH32_FPEXC_EN 0x40000000U
1039#define AARCH32_FPEXC_EX 0x80000000U
1043#define AARCH32_FPSCR_IOC 0x1U
1045#define AARCH32_FPSCR_DZC 0x2U
1047#define AARCH32_FPSCR_OFC 0x4U
1049#define AARCH32_FPSCR_UFC 0x8U
1051#define AARCH32_FPSCR_IXC 0x10U
1053#define AARCH32_FPSCR_IDC 0x80U
1055#define AARCH32_FPSCR_IOE 0x100U
1057#define AARCH32_FPSCR_DZE 0x200U
1059#define AARCH32_FPSCR_OFE 0x400U
1061#define AARCH32_FPSCR_UFE 0x800U
1063#define AARCH32_FPSCR_IXE 0x1000U
1065#define AARCH32_FPSCR_IDE 0x8000U
1067#define AARCH32_FPSCR_LEN( _val ) ( ( _val ) << 16 )
1068#define AARCH32_FPSCR_LEN_SHIFT 16
1069#define AARCH32_FPSCR_LEN_MASK 0x70000U
1070#define AARCH32_FPSCR_LEN_GET( _reg ) \
1071 ( ( ( _reg ) >> 16 ) & 0x7U )
1073#define AARCH32_FPSCR_FZ16 0x80000U
1075#define AARCH32_FPSCR_STRIDE( _val ) ( ( _val ) << 20 )
1076#define AARCH32_FPSCR_STRIDE_SHIFT 20
1077#define AARCH32_FPSCR_STRIDE_MASK 0x300000U
1078#define AARCH32_FPSCR_STRIDE_GET( _reg ) \
1079 ( ( ( _reg ) >> 20 ) & 0x3U )
1081#define AARCH32_FPSCR_RMODE( _val ) ( ( _val ) << 22 )
1082#define AARCH32_FPSCR_RMODE_SHIFT 22
1083#define AARCH32_FPSCR_RMODE_MASK 0xc00000U
1084#define AARCH32_FPSCR_RMODE_GET( _reg ) \
1085 ( ( ( _reg ) >> 22 ) & 0x3U )
1087#define AARCH32_FPSCR_FZ 0x1000000U
1089#define AARCH32_FPSCR_DN 0x2000000U
1091#define AARCH32_FPSCR_AHP 0x4000000U
1093#define AARCH32_FPSCR_QC 0x8000000U
1095#define AARCH32_FPSCR_V 0x10000000U
1097#define AARCH32_FPSCR_C 0x20000000U
1099#define AARCH32_FPSCR_Z 0x40000000U
1101#define AARCH32_FPSCR_N 0x80000000U
1105#define AARCH32_FPSID_REVISION( _val ) ( ( _val ) << 0 )
1106#define AARCH32_FPSID_REVISION_SHIFT 0
1107#define AARCH32_FPSID_REVISION_MASK 0xfU
1108#define AARCH32_FPSID_REVISION_GET( _reg ) \
1109 ( ( ( _reg ) >> 0 ) & 0xfU )
1111#define AARCH32_FPSID_VARIANT( _val ) ( ( _val ) << 4 )
1112#define AARCH32_FPSID_VARIANT_SHIFT 4
1113#define AARCH32_FPSID_VARIANT_MASK 0xf0U
1114#define AARCH32_FPSID_VARIANT_GET( _reg ) \
1115 ( ( ( _reg ) >> 4 ) & 0xfU )
1117#define AARCH32_FPSID_PARTNUM( _val ) ( ( _val ) << 8 )
1118#define AARCH32_FPSID_PARTNUM_SHIFT 8
1119#define AARCH32_FPSID_PARTNUM_MASK 0xff00U
1120#define AARCH32_FPSID_PARTNUM_GET( _reg ) \
1121 ( ( ( _reg ) >> 8 ) & 0xffU )
1123#define AARCH32_FPSID_SUBARCHITECTURE( _val ) ( ( _val ) << 16 )
1124#define AARCH32_FPSID_SUBARCHITECTURE_SHIFT 16
1125#define AARCH32_FPSID_SUBARCHITECTURE_MASK 0x7f0000U
1126#define AARCH32_FPSID_SUBARCHITECTURE_GET( _reg ) \
1127 ( ( ( _reg ) >> 16 ) & 0x7fU )
1129#define AARCH32_FPSID_SW 0x800000U
1131#define AARCH32_FPSID_IMPLEMENTER( _val ) ( ( _val ) << 24 )
1132#define AARCH32_FPSID_IMPLEMENTER_SHIFT 24
1133#define AARCH32_FPSID_IMPLEMENTER_MASK 0xff000000U
1134#define AARCH32_FPSID_IMPLEMENTER_GET( _reg ) \
1135 ( ( ( _reg ) >> 24 ) & 0xffU )
1139static inline uint32_t _AArch32_Read_hacr(
void )
1144 "mrc p15, 4, %0, c1, c1, 7" :
"=&r" ( value ) : :
"memory"
1150static inline void _AArch32_Write_hacr( uint32_t value )
1153 "mcr p15, 4, %0, c1, c1, 7" : :
"r" ( value ) :
"memory"
1159static inline uint32_t _AArch32_Read_hactlr(
void )
1164 "mrc p15, 4, %0, c1, c0, 1" :
"=&r" ( value ) : :
"memory"
1170static inline void _AArch32_Write_hactlr( uint32_t value )
1173 "mcr p15, 4, %0, c1, c0, 1" : :
"r" ( value ) :
"memory"
1179static inline uint32_t _AArch32_Read_hactlr2(
void )
1184 "mrc p15, 4, %0, c1, c0, 3" :
"=&r" ( value ) : :
"memory"
1190static inline void _AArch32_Write_hactlr2( uint32_t value )
1193 "mcr p15, 4, %0, c1, c0, 3" : :
"r" ( value ) :
"memory"
1199static inline uint32_t _AArch32_Read_hadfsr(
void )
1204 "mrc p15, 4, %0, c5, c1, 0" :
"=&r" ( value ) : :
"memory"
1210static inline void _AArch32_Write_hadfsr( uint32_t value )
1213 "mcr p15, 4, %0, c5, c1, 0" : :
"r" ( value ) :
"memory"
1219static inline uint32_t _AArch32_Read_haifsr(
void )
1224 "mrc p15, 4, %0, c5, c1, 1" :
"=&r" ( value ) : :
"memory"
1230static inline void _AArch32_Write_haifsr( uint32_t value )
1233 "mcr p15, 4, %0, c5, c1, 1" : :
"r" ( value ) :
"memory"
1239static inline uint32_t _AArch32_Read_hamair0(
void )
1244 "mrc p15, 4, %0, c10, c3, 0" :
"=&r" ( value ) : :
"memory"
1250static inline void _AArch32_Write_hamair0( uint32_t value )
1253 "mcr p15, 4, %0, c10, c3, 0" : :
"r" ( value ) :
"memory"
1259static inline uint32_t _AArch32_Read_hamair1(
void )
1264 "mrc p15, 4, %0, c10, c3, 1" :
"=&r" ( value ) : :
"memory"
1270static inline void _AArch32_Write_hamair1( uint32_t value )
1273 "mcr p15, 4, %0, c10, c3, 1" : :
"r" ( value ) :
"memory"
1279#define AARCH32_HCPTR_TCP10 0x400U
1281#define AARCH32_HCPTR_TCP11 0x800U
1283#define AARCH32_HCPTR_TASE 0x8000U
1285#define AARCH32_HCPTR_TTA 0x100000U
1287#define AARCH32_HCPTR_TAM 0x40000000U
1289#define AARCH32_HCPTR_TCPAC 0x80000000U
1291static inline uint32_t _AArch32_Read_hcptr(
void )
1296 "mrc p15, 4, %0, c1, c1, 2" :
"=&r" ( value ) : :
"memory"
1302static inline void _AArch32_Write_hcptr( uint32_t value )
1305 "mcr p15, 4, %0, c1, c1, 2" : :
"r" ( value ) :
"memory"
1311#define AARCH32_HCR_VM 0x1U
1313#define AARCH32_HCR_SWIO 0x2U
1315#define AARCH32_HCR_PTW 0x4U
1317#define AARCH32_HCR_FMO 0x8U
1319#define AARCH32_HCR_IMO 0x10U
1321#define AARCH32_HCR_AMO 0x20U
1323#define AARCH32_HCR_VF 0x40U
1325#define AARCH32_HCR_VI 0x80U
1327#define AARCH32_HCR_VA 0x100U
1329#define AARCH32_HCR_FB 0x200U
1331#define AARCH32_HCR_BSU( _val ) ( ( _val ) << 10 )
1332#define AARCH32_HCR_BSU_SHIFT 10
1333#define AARCH32_HCR_BSU_MASK 0xc00U
1334#define AARCH32_HCR_BSU_GET( _reg ) \
1335 ( ( ( _reg ) >> 10 ) & 0x3U )
1337#define AARCH32_HCR_DC 0x1000U
1339#define AARCH32_HCR_TWI 0x2000U
1341#define AARCH32_HCR_TWE 0x4000U
1343#define AARCH32_HCR_TID0 0x8000U
1345#define AARCH32_HCR_TID1 0x10000U
1347#define AARCH32_HCR_TID2 0x20000U
1349#define AARCH32_HCR_TID3 0x40000U
1351#define AARCH32_HCR_TSC 0x80000U
1353#define AARCH32_HCR_TIDCP 0x100000U
1355#define AARCH32_HCR_TAC 0x200000U
1357#define AARCH32_HCR_TSW 0x400000U
1359#define AARCH32_HCR_TPC 0x800000U
1361#define AARCH32_HCR_TPU 0x1000000U
1363#define AARCH32_HCR_TTLB 0x2000000U
1365#define AARCH32_HCR_TVM 0x4000000U
1367#define AARCH32_HCR_TGE 0x8000000U
1369#define AARCH32_HCR_HCD 0x20000000U
1371#define AARCH32_HCR_TRVM 0x40000000U
1373static inline uint32_t _AArch32_Read_hcr(
void )
1378 "mrc p15, 4, %0, c1, c1, 0" :
"=&r" ( value ) : :
"memory"
1384static inline void _AArch32_Write_hcr( uint32_t value )
1387 "mcr p15, 4, %0, c1, c1, 0" : :
"r" ( value ) :
"memory"
1393#define AARCH32_HCR2_CD 0x1U
1395#define AARCH32_HCR2_ID 0x2U
1397#define AARCH32_HCR2_TERR 0x10U
1399#define AARCH32_HCR2_TEA 0x20U
1401#define AARCH32_HCR2_MIOCNCE 0x40U
1403#define AARCH32_HCR2_TID4 0x20000U
1405#define AARCH32_HCR2_TICAB 0x40000U
1407#define AARCH32_HCR2_TOCU 0x100000U
1409#define AARCH32_HCR2_TTLBIS 0x400000U
1411static inline uint32_t _AArch32_Read_hcr2(
void )
1416 "mrc p15, 4, %0, c1, c1, 4" :
"=&r" ( value ) : :
"memory"
1422static inline void _AArch32_Write_hcr2( uint32_t value )
1425 "mcr p15, 4, %0, c1, c1, 4" : :
"r" ( value ) :
"memory"
1431static inline uint32_t _AArch32_Read_hdfar(
void )
1436 "mrc p15, 4, %0, c6, c0, 0" :
"=&r" ( value ) : :
"memory"
1442static inline void _AArch32_Write_hdfar( uint32_t value )
1445 "mcr p15, 4, %0, c6, c0, 0" : :
"r" ( value ) :
"memory"
1451static inline uint32_t _AArch32_Read_hifar(
void )
1456 "mrc p15, 4, %0, c6, c0, 2" :
"=&r" ( value ) : :
"memory"
1462static inline void _AArch32_Write_hifar( uint32_t value )
1465 "mcr p15, 4, %0, c6, c0, 2" : :
"r" ( value ) :
"memory"
1471static inline uint32_t _AArch32_Read_hmair0(
void )
1476 "mrc p15, 4, %0, c10, c2, 0" :
"=&r" ( value ) : :
"memory"
1482static inline void _AArch32_Write_hmair0( uint32_t value )
1485 "mcr p15, 4, %0, c10, c2, 0" : :
"r" ( value ) :
"memory"
1491static inline uint32_t _AArch32_Read_hmair1(
void )
1496 "mrc p15, 4, %0, c10, c2, 1" :
"=&r" ( value ) : :
"memory"
1502static inline void _AArch32_Write_hmair1( uint32_t value )
1505 "mcr p15, 4, %0, c10, c2, 1" : :
"r" ( value ) :
"memory"
1511#define AARCH32_HPFAR_FIPA_39_12( _val ) ( ( _val ) << 4 )
1512#define AARCH32_HPFAR_FIPA_39_12_SHIFT 4
1513#define AARCH32_HPFAR_FIPA_39_12_MASK 0xfffffff0U
1514#define AARCH32_HPFAR_FIPA_39_12_GET( _reg ) \
1515 ( ( ( _reg ) >> 4 ) & 0xfffffffU )
1517static inline uint32_t _AArch32_Read_hpfar(
void )
1522 "mrc p15, 4, %0, c6, c0, 4" :
"=&r" ( value ) : :
"memory"
1528static inline void _AArch32_Write_hpfar( uint32_t value )
1531 "mcr p15, 4, %0, c6, c0, 4" : :
"r" ( value ) :
"memory"
1537#define AARCH32_HRMR_AA64 0x1U
1539#define AARCH32_HRMR_RR 0x2U
1541static inline uint32_t _AArch32_Read_hrmr(
void )
1546 "mrc p15, 4, %0, c12, c0, 2" :
"=&r" ( value ) : :
"memory"
1552static inline void _AArch32_Write_hrmr( uint32_t value )
1555 "mcr p15, 4, %0, c12, c0, 2" : :
"r" ( value ) :
"memory"
1561#define AARCH32_HSCTLR_M 0x1U
1563#define AARCH32_HSCTLR_A 0x2U
1565#define AARCH32_HSCTLR_C 0x4U
1567#define AARCH32_HSCTLR_NTLSMD 0x8U
1569#define AARCH32_HSCTLR_LSMAOE 0x10U
1571#define AARCH32_HSCTLR_CP15BEN 0x20U
1573#define AARCH32_HSCTLR_ITD 0x80U
1575#define AARCH32_HSCTLR_SED 0x100U
1577#define AARCH32_HSCTLR_I 0x1000U
1579#define AARCH32_HSCTLR_BR 0x20000U
1581#define AARCH32_HSCTLR_WXN 0x80000U
1583#define AARCH32_HSCTLR_FI 0x200000U
1585#define AARCH32_HSCTLR_EE 0x2000000U
1587#define AARCH32_HSCTLR_TE 0x40000000U
1589#define AARCH32_HSCTLR_DSSBS 0x80000000U
1591static inline uint32_t _AArch32_Read_hsctlr(
void )
1596 "mrc p15, 4, %0, c1, c0, 0" :
"=&r" ( value ) : :
"memory"
1602static inline void _AArch32_Write_hsctlr( uint32_t value )
1605 "mcr p15, 4, %0, c1, c0, 0" : :
"r" ( value ) :
"memory"
1611#define AARCH32_HSR_DIRECTION 0x1U
1613#define AARCH32_HSR_TI 0x1U
1615#define AARCH32_HSR_COPROC( _val ) ( ( _val ) << 0 )
1616#define AARCH32_HSR_COPROC_SHIFT 0
1617#define AARCH32_HSR_COPROC_MASK 0xfU
1618#define AARCH32_HSR_COPROC_GET( _reg ) \
1619 ( ( ( _reg ) >> 0 ) & 0xfU )
1621#define AARCH32_HSR_DFSC( _val ) ( ( _val ) << 0 )
1622#define AARCH32_HSR_DFSC_SHIFT 0
1623#define AARCH32_HSR_DFSC_MASK 0x3fU
1624#define AARCH32_HSR_DFSC_GET( _reg ) \
1625 ( ( ( _reg ) >> 0 ) & 0x3fU )
1627#define AARCH32_HSR_IFSC( _val ) ( ( _val ) << 0 )
1628#define AARCH32_HSR_IFSC_SHIFT 0
1629#define AARCH32_HSR_IFSC_MASK 0x3fU
1630#define AARCH32_HSR_IFSC_GET( _reg ) \
1631 ( ( ( _reg ) >> 0 ) & 0x3fU )
1633#define AARCH32_HSR_IMM16( _val ) ( ( _val ) << 0 )
1634#define AARCH32_HSR_IMM16_SHIFT 0
1635#define AARCH32_HSR_IMM16_MASK 0xffffU
1636#define AARCH32_HSR_IMM16_GET( _reg ) \
1637 ( ( ( _reg ) >> 0 ) & 0xffffU )
1639#define AARCH32_HSR_ISS( _val ) ( ( _val ) << 0 )
1640#define AARCH32_HSR_ISS_SHIFT 0
1641#define AARCH32_HSR_ISS_MASK 0x1ffffffU
1642#define AARCH32_HSR_ISS_GET( _reg ) \
1643 ( ( ( _reg ) >> 0 ) & 0x1ffffffU )
1645#define AARCH32_HSR_AM( _val ) ( ( _val ) << 1 )
1646#define AARCH32_HSR_AM_SHIFT 1
1647#define AARCH32_HSR_AM_MASK 0xeU
1648#define AARCH32_HSR_AM_GET( _reg ) \
1649 ( ( ( _reg ) >> 1 ) & 0x7U )
1651#define AARCH32_HSR_CRM( _val ) ( ( _val ) << 1 )
1652#define AARCH32_HSR_CRM_SHIFT 1
1653#define AARCH32_HSR_CRM_MASK 0x1eU
1654#define AARCH32_HSR_CRM_GET( _reg ) \
1655 ( ( ( _reg ) >> 1 ) & 0xfU )
1657#define AARCH32_HSR_OFFSET 0x10U
1659#define AARCH32_HSR_TA 0x20U
1661#define AARCH32_HSR_RN( _val ) ( ( _val ) << 5 )
1662#define AARCH32_HSR_RN_SHIFT 5
1663#define AARCH32_HSR_RN_MASK 0x1e0U
1664#define AARCH32_HSR_RN_GET( _reg ) \
1665 ( ( ( _reg ) >> 5 ) & 0xfU )
1667#define AARCH32_HSR_RT( _val ) ( ( _val ) << 5 )
1668#define AARCH32_HSR_RT_SHIFT 5
1669#define AARCH32_HSR_RT_MASK 0x1e0U
1670#define AARCH32_HSR_RT_GET( _reg ) \
1671 ( ( ( _reg ) >> 5 ) & 0xfU )
1673#define AARCH32_HSR_WNR 0x40U
1675#define AARCH32_HSR_S1PTW 0x80U
1677#define AARCH32_HSR_CM 0x100U
1679#define AARCH32_HSR_EA 0x200U
1681#define AARCH32_HSR_FNV 0x400U
1683#define AARCH32_HSR_AET( _val ) ( ( _val ) << 10 )
1684#define AARCH32_HSR_AET_SHIFT 10
1685#define AARCH32_HSR_AET_MASK 0xc00U
1686#define AARCH32_HSR_AET_GET( _reg ) \
1687 ( ( ( _reg ) >> 10 ) & 0x3U )
1689#define AARCH32_HSR_CRN( _val ) ( ( _val ) << 10 )
1690#define AARCH32_HSR_CRN_SHIFT 10
1691#define AARCH32_HSR_CRN_MASK 0x3c00U
1692#define AARCH32_HSR_CRN_GET( _reg ) \
1693 ( ( ( _reg ) >> 10 ) & 0xfU )
1695#define AARCH32_HSR_RT2( _val ) ( ( _val ) << 10 )
1696#define AARCH32_HSR_RT2_SHIFT 10
1697#define AARCH32_HSR_RT2_MASK 0x3c00U
1698#define AARCH32_HSR_RT2_GET( _reg ) \
1699 ( ( ( _reg ) >> 10 ) & 0xfU )
1701#define AARCH32_HSR_IMM8( _val ) ( ( _val ) << 12 )
1702#define AARCH32_HSR_IMM8_SHIFT 12
1703#define AARCH32_HSR_IMM8_MASK 0xff000U
1704#define AARCH32_HSR_IMM8_GET( _reg ) \
1705 ( ( ( _reg ) >> 12 ) & 0xffU )
1707#define AARCH32_HSR_AR 0x4000U
1709#define AARCH32_HSR_OPC1_0( _val ) ( ( _val ) << 14 )
1710#define AARCH32_HSR_OPC1_SHIFT_0 14
1711#define AARCH32_HSR_OPC1_MASK_0 0x1c000U
1712#define AARCH32_HSR_OPC1_GET_0( _reg ) \
1713 ( ( ( _reg ) >> 14 ) & 0x7U )
1715#define AARCH32_HSR_OPC1_1( _val ) ( ( _val ) << 16 )
1716#define AARCH32_HSR_OPC1_SHIFT_1 16
1717#define AARCH32_HSR_OPC1_MASK_1 0xf0000U
1718#define AARCH32_HSR_OPC1_GET_1( _reg ) \
1719 ( ( ( _reg ) >> 16 ) & 0xfU )
1721#define AARCH32_HSR_SRT( _val ) ( ( _val ) << 16 )
1722#define AARCH32_HSR_SRT_SHIFT 16
1723#define AARCH32_HSR_SRT_MASK 0xf0000U
1724#define AARCH32_HSR_SRT_GET( _reg ) \
1725 ( ( ( _reg ) >> 16 ) & 0xfU )
1727#define AARCH32_HSR_OPC2( _val ) ( ( _val ) << 17 )
1728#define AARCH32_HSR_OPC2_SHIFT 17
1729#define AARCH32_HSR_OPC2_MASK 0xe0000U
1730#define AARCH32_HSR_OPC2_GET( _reg ) \
1731 ( ( ( _reg ) >> 17 ) & 0x7U )
1733#define AARCH32_HSR_CCKNOWNPASS 0x80000U
1735#define AARCH32_HSR_COND( _val ) ( ( _val ) << 20 )
1736#define AARCH32_HSR_COND_SHIFT 20
1737#define AARCH32_HSR_COND_MASK 0xf00000U
1738#define AARCH32_HSR_COND_GET( _reg ) \
1739 ( ( ( _reg ) >> 20 ) & 0xfU )
1741#define AARCH32_HSR_SSE 0x200000U
1743#define AARCH32_HSR_SAS( _val ) ( ( _val ) << 22 )
1744#define AARCH32_HSR_SAS_SHIFT 22
1745#define AARCH32_HSR_SAS_MASK 0xc00000U
1746#define AARCH32_HSR_SAS_GET( _reg ) \
1747 ( ( ( _reg ) >> 22 ) & 0x3U )
1749#define AARCH32_HSR_CV 0x1000000U
1751#define AARCH32_HSR_ISV 0x1000000U
1753#define AARCH32_HSR_IL 0x2000000U
1755#define AARCH32_HSR_EC( _val ) ( ( _val ) << 26 )
1756#define AARCH32_HSR_EC_SHIFT 26
1757#define AARCH32_HSR_EC_MASK 0xfc000000U
1758#define AARCH32_HSR_EC_GET( _reg ) \
1759 ( ( ( _reg ) >> 26 ) & 0x3fU )
1761static inline uint32_t _AArch32_Read_hsr(
void )
1766 "mrc p15, 4, %0, c5, c2, 0" :
"=&r" ( value ) : :
"memory"
1772static inline void _AArch32_Write_hsr( uint32_t value )
1775 "mcr p15, 4, %0, c5, c2, 0" : :
"r" ( value ) :
"memory"
1781static inline uint32_t _AArch32_Read_hstr(
void )
1786 "mrc p15, 4, %0, c1, c1, 3" :
"=&r" ( value ) : :
"memory"
1792static inline void _AArch32_Write_hstr( uint32_t value )
1795 "mcr p15, 4, %0, c1, c1, 3" : :
"r" ( value ) :
"memory"
1801#define AARCH32_HTCR_T0SZ( _val ) ( ( _val ) << 0 )
1802#define AARCH32_HTCR_T0SZ_SHIFT 0
1803#define AARCH32_HTCR_T0SZ_MASK 0x7U
1804#define AARCH32_HTCR_T0SZ_GET( _reg ) \
1805 ( ( ( _reg ) >> 0 ) & 0x7U )
1807#define AARCH32_HTCR_IRGN0( _val ) ( ( _val ) << 8 )
1808#define AARCH32_HTCR_IRGN0_SHIFT 8
1809#define AARCH32_HTCR_IRGN0_MASK 0x300U
1810#define AARCH32_HTCR_IRGN0_GET( _reg ) \
1811 ( ( ( _reg ) >> 8 ) & 0x3U )
1813#define AARCH32_HTCR_ORGN0( _val ) ( ( _val ) << 10 )
1814#define AARCH32_HTCR_ORGN0_SHIFT 10
1815#define AARCH32_HTCR_ORGN0_MASK 0xc00U
1816#define AARCH32_HTCR_ORGN0_GET( _reg ) \
1817 ( ( ( _reg ) >> 10 ) & 0x3U )
1819#define AARCH32_HTCR_SH0( _val ) ( ( _val ) << 12 )
1820#define AARCH32_HTCR_SH0_SHIFT 12
1821#define AARCH32_HTCR_SH0_MASK 0x3000U
1822#define AARCH32_HTCR_SH0_GET( _reg ) \
1823 ( ( ( _reg ) >> 12 ) & 0x3U )
1825#define AARCH32_HTCR_HPD 0x1000000U
1827#define AARCH32_HTCR_HWU59 0x2000000U
1829#define AARCH32_HTCR_HWU60 0x4000000U
1831#define AARCH32_HTCR_HWU61 0x8000000U
1833#define AARCH32_HTCR_HWU62 0x10000000U
1835static inline uint32_t _AArch32_Read_htcr(
void )
1840 "mrc p15, 4, %0, c2, c0, 2" :
"=&r" ( value ) : :
"memory"
1846static inline void _AArch32_Write_htcr( uint32_t value )
1849 "mcr p15, 4, %0, c2, c0, 2" : :
"r" ( value ) :
"memory"
1855static inline uint32_t _AArch32_Read_htpidr(
void )
1860 "mrc p15, 4, %0, c13, c0, 2" :
"=&r" ( value ) : :
"memory"
1866static inline void _AArch32_Write_htpidr( uint32_t value )
1869 "mcr p15, 4, %0, c13, c0, 2" : :
"r" ( value ) :
"memory"
1875#define AARCH32_HTTBR_CNP 0x1U
1877#define AARCH32_HTTBR_BADDR( _val ) ( ( _val ) << 1 )
1878#define AARCH32_HTTBR_BADDR_SHIFT 1
1879#define AARCH32_HTTBR_BADDR_MASK 0xfffffffffffeULL
1880#define AARCH32_HTTBR_BADDR_GET( _reg ) \
1881 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
1883static inline uint64_t _AArch32_Read_httbr(
void )
1888 "mrrc p15, 4, %Q0, %R0, c2" :
"=&r" ( value ) : :
"memory"
1894static inline void _AArch32_Write_httbr( uint64_t value )
1897 "mcrr p15, 4, %Q0, %R0, c2" : :
"r" ( value ) :
"memory"
1903static inline uint32_t _AArch32_Read_hvbar(
void )
1908 "mrc p15, 4, %0, c12, c0, 0" :
"=&r" ( value ) : :
"memory"
1914static inline void _AArch32_Write_hvbar( uint32_t value )
1917 "mcr p15, 4, %0, c12, c0, 0" : :
"r" ( value ) :
"memory"
1923static inline void _AArch32_Write_iciallu( uint32_t value )
1926 "mcr p15, 0, %0, c7, c5, 0" : :
"r" ( value ) :
"memory"
1932static inline void _AArch32_Write_icialluis( uint32_t value )
1935 "mcr p15, 0, %0, c7, c1, 0" : :
"r" ( value ) :
"memory"
1941static inline void _AArch32_Write_icimvau( uint32_t value )
1944 "mcr p15, 0, %0, c7, c5, 1" : :
"r" ( value ) :
"memory"
1950static inline uint32_t _AArch32_Read_id_afr0(
void )
1955 "mrc p15, 0, %0, c0, c1, 3" :
"=&r" ( value ) : :
"memory"
1963#define AARCH32_ID_DFR0_COPDBG( _val ) ( ( _val ) << 0 )
1964#define AARCH32_ID_DFR0_COPDBG_SHIFT 0
1965#define AARCH32_ID_DFR0_COPDBG_MASK 0xfU
1966#define AARCH32_ID_DFR0_COPDBG_GET( _reg ) \
1967 ( ( ( _reg ) >> 0 ) & 0xfU )
1969#define AARCH32_ID_DFR0_COPSDBG( _val ) ( ( _val ) << 4 )
1970#define AARCH32_ID_DFR0_COPSDBG_SHIFT 4
1971#define AARCH32_ID_DFR0_COPSDBG_MASK 0xf0U
1972#define AARCH32_ID_DFR0_COPSDBG_GET( _reg ) \
1973 ( ( ( _reg ) >> 4 ) & 0xfU )
1975#define AARCH32_ID_DFR0_MMAPDBG( _val ) ( ( _val ) << 8 )
1976#define AARCH32_ID_DFR0_MMAPDBG_SHIFT 8
1977#define AARCH32_ID_DFR0_MMAPDBG_MASK 0xf00U
1978#define AARCH32_ID_DFR0_MMAPDBG_GET( _reg ) \
1979 ( ( ( _reg ) >> 8 ) & 0xfU )
1981#define AARCH32_ID_DFR0_COPTRC( _val ) ( ( _val ) << 12 )
1982#define AARCH32_ID_DFR0_COPTRC_SHIFT 12
1983#define AARCH32_ID_DFR0_COPTRC_MASK 0xf000U
1984#define AARCH32_ID_DFR0_COPTRC_GET( _reg ) \
1985 ( ( ( _reg ) >> 12 ) & 0xfU )
1987#define AARCH32_ID_DFR0_MMAPTRC( _val ) ( ( _val ) << 16 )
1988#define AARCH32_ID_DFR0_MMAPTRC_SHIFT 16
1989#define AARCH32_ID_DFR0_MMAPTRC_MASK 0xf0000U
1990#define AARCH32_ID_DFR0_MMAPTRC_GET( _reg ) \
1991 ( ( ( _reg ) >> 16 ) & 0xfU )
1993#define AARCH32_ID_DFR0_MPROFDBG( _val ) ( ( _val ) << 20 )
1994#define AARCH32_ID_DFR0_MPROFDBG_SHIFT 20
1995#define AARCH32_ID_DFR0_MPROFDBG_MASK 0xf00000U
1996#define AARCH32_ID_DFR0_MPROFDBG_GET( _reg ) \
1997 ( ( ( _reg ) >> 20 ) & 0xfU )
1999#define AARCH32_ID_DFR0_PERFMON( _val ) ( ( _val ) << 24 )
2000#define AARCH32_ID_DFR0_PERFMON_SHIFT 24
2001#define AARCH32_ID_DFR0_PERFMON_MASK 0xf000000U
2002#define AARCH32_ID_DFR0_PERFMON_GET( _reg ) \
2003 ( ( ( _reg ) >> 24 ) & 0xfU )
2005#define AARCH32_ID_DFR0_TRACEFILT( _val ) ( ( _val ) << 28 )
2006#define AARCH32_ID_DFR0_TRACEFILT_SHIFT 28
2007#define AARCH32_ID_DFR0_TRACEFILT_MASK 0xf0000000U
2008#define AARCH32_ID_DFR0_TRACEFILT_GET( _reg ) \
2009 ( ( ( _reg ) >> 28 ) & 0xfU )
2011static inline uint32_t _AArch32_Read_id_dfr0(
void )
2016 "mrc p15, 0, %0, c0, c1, 2" :
"=&r" ( value ) : :
"memory"
2024#define AARCH32_ID_DFR1_MTPMU( _val ) ( ( _val ) << 0 )
2025#define AARCH32_ID_DFR1_MTPMU_SHIFT 0
2026#define AARCH32_ID_DFR1_MTPMU_MASK 0xfU
2027#define AARCH32_ID_DFR1_MTPMU_GET( _reg ) \
2028 ( ( ( _reg ) >> 0 ) & 0xfU )
2030static inline uint32_t _AArch32_Read_id_dfr1(
void )
2035 "mrc p15, 0, %0, c0, c3, 5" :
"=&r" ( value ) : :
"memory"
2043#define AARCH32_ID_ISAR0_SWAP( _val ) ( ( _val ) << 0 )
2044#define AARCH32_ID_ISAR0_SWAP_SHIFT 0
2045#define AARCH32_ID_ISAR0_SWAP_MASK 0xfU
2046#define AARCH32_ID_ISAR0_SWAP_GET( _reg ) \
2047 ( ( ( _reg ) >> 0 ) & 0xfU )
2049#define AARCH32_ID_ISAR0_BITCOUNT( _val ) ( ( _val ) << 4 )
2050#define AARCH32_ID_ISAR0_BITCOUNT_SHIFT 4
2051#define AARCH32_ID_ISAR0_BITCOUNT_MASK 0xf0U
2052#define AARCH32_ID_ISAR0_BITCOUNT_GET( _reg ) \
2053 ( ( ( _reg ) >> 4 ) & 0xfU )
2055#define AARCH32_ID_ISAR0_BITFIELD( _val ) ( ( _val ) << 8 )
2056#define AARCH32_ID_ISAR0_BITFIELD_SHIFT 8
2057#define AARCH32_ID_ISAR0_BITFIELD_MASK 0xf00U
2058#define AARCH32_ID_ISAR0_BITFIELD_GET( _reg ) \
2059 ( ( ( _reg ) >> 8 ) & 0xfU )
2061#define AARCH32_ID_ISAR0_CMPBRANCH( _val ) ( ( _val ) << 12 )
2062#define AARCH32_ID_ISAR0_CMPBRANCH_SHIFT 12
2063#define AARCH32_ID_ISAR0_CMPBRANCH_MASK 0xf000U
2064#define AARCH32_ID_ISAR0_CMPBRANCH_GET( _reg ) \
2065 ( ( ( _reg ) >> 12 ) & 0xfU )
2067#define AARCH32_ID_ISAR0_COPROC( _val ) ( ( _val ) << 16 )
2068#define AARCH32_ID_ISAR0_COPROC_SHIFT 16
2069#define AARCH32_ID_ISAR0_COPROC_MASK 0xf0000U
2070#define AARCH32_ID_ISAR0_COPROC_GET( _reg ) \
2071 ( ( ( _reg ) >> 16 ) & 0xfU )
2073#define AARCH32_ID_ISAR0_DEBUG( _val ) ( ( _val ) << 20 )
2074#define AARCH32_ID_ISAR0_DEBUG_SHIFT 20
2075#define AARCH32_ID_ISAR0_DEBUG_MASK 0xf00000U
2076#define AARCH32_ID_ISAR0_DEBUG_GET( _reg ) \
2077 ( ( ( _reg ) >> 20 ) & 0xfU )
2079#define AARCH32_ID_ISAR0_DIVIDE( _val ) ( ( _val ) << 24 )
2080#define AARCH32_ID_ISAR0_DIVIDE_SHIFT 24
2081#define AARCH32_ID_ISAR0_DIVIDE_MASK 0xf000000U
2082#define AARCH32_ID_ISAR0_DIVIDE_GET( _reg ) \
2083 ( ( ( _reg ) >> 24 ) & 0xfU )
2085static inline uint32_t _AArch32_Read_id_isar0(
void )
2090 "mrc p15, 0, %0, c0, c2, 0" :
"=&r" ( value ) : :
"memory"
2098#define AARCH32_ID_ISAR1_ENDIAN( _val ) ( ( _val ) << 0 )
2099#define AARCH32_ID_ISAR1_ENDIAN_SHIFT 0
2100#define AARCH32_ID_ISAR1_ENDIAN_MASK 0xfU
2101#define AARCH32_ID_ISAR1_ENDIAN_GET( _reg ) \
2102 ( ( ( _reg ) >> 0 ) & 0xfU )
2104#define AARCH32_ID_ISAR1_EXCEPT( _val ) ( ( _val ) << 4 )
2105#define AARCH32_ID_ISAR1_EXCEPT_SHIFT 4
2106#define AARCH32_ID_ISAR1_EXCEPT_MASK 0xf0U
2107#define AARCH32_ID_ISAR1_EXCEPT_GET( _reg ) \
2108 ( ( ( _reg ) >> 4 ) & 0xfU )
2110#define AARCH32_ID_ISAR1_EXCEPT_AR( _val ) ( ( _val ) << 8 )
2111#define AARCH32_ID_ISAR1_EXCEPT_AR_SHIFT 8
2112#define AARCH32_ID_ISAR1_EXCEPT_AR_MASK 0xf00U
2113#define AARCH32_ID_ISAR1_EXCEPT_AR_GET( _reg ) \
2114 ( ( ( _reg ) >> 8 ) & 0xfU )
2116#define AARCH32_ID_ISAR1_EXTEND( _val ) ( ( _val ) << 12 )
2117#define AARCH32_ID_ISAR1_EXTEND_SHIFT 12
2118#define AARCH32_ID_ISAR1_EXTEND_MASK 0xf000U
2119#define AARCH32_ID_ISAR1_EXTEND_GET( _reg ) \
2120 ( ( ( _reg ) >> 12 ) & 0xfU )
2122#define AARCH32_ID_ISAR1_IFTHEN( _val ) ( ( _val ) << 16 )
2123#define AARCH32_ID_ISAR1_IFTHEN_SHIFT 16
2124#define AARCH32_ID_ISAR1_IFTHEN_MASK 0xf0000U
2125#define AARCH32_ID_ISAR1_IFTHEN_GET( _reg ) \
2126 ( ( ( _reg ) >> 16 ) & 0xfU )
2128#define AARCH32_ID_ISAR1_IMMEDIATE( _val ) ( ( _val ) << 20 )
2129#define AARCH32_ID_ISAR1_IMMEDIATE_SHIFT 20
2130#define AARCH32_ID_ISAR1_IMMEDIATE_MASK 0xf00000U
2131#define AARCH32_ID_ISAR1_IMMEDIATE_GET( _reg ) \
2132 ( ( ( _reg ) >> 20 ) & 0xfU )
2134#define AARCH32_ID_ISAR1_INTERWORK( _val ) ( ( _val ) << 24 )
2135#define AARCH32_ID_ISAR1_INTERWORK_SHIFT 24
2136#define AARCH32_ID_ISAR1_INTERWORK_MASK 0xf000000U
2137#define AARCH32_ID_ISAR1_INTERWORK_GET( _reg ) \
2138 ( ( ( _reg ) >> 24 ) & 0xfU )
2140#define AARCH32_ID_ISAR1_JAZELLE( _val ) ( ( _val ) << 28 )
2141#define AARCH32_ID_ISAR1_JAZELLE_SHIFT 28
2142#define AARCH32_ID_ISAR1_JAZELLE_MASK 0xf0000000U
2143#define AARCH32_ID_ISAR1_JAZELLE_GET( _reg ) \
2144 ( ( ( _reg ) >> 28 ) & 0xfU )
2146static inline uint32_t _AArch32_Read_id_isar1(
void )
2151 "mrc p15, 0, %0, c0, c2, 1" :
"=&r" ( value ) : :
"memory"
2159#define AARCH32_ID_ISAR2_LOADSTORE( _val ) ( ( _val ) << 0 )
2160#define AARCH32_ID_ISAR2_LOADSTORE_SHIFT 0
2161#define AARCH32_ID_ISAR2_LOADSTORE_MASK 0xfU
2162#define AARCH32_ID_ISAR2_LOADSTORE_GET( _reg ) \
2163 ( ( ( _reg ) >> 0 ) & 0xfU )
2165#define AARCH32_ID_ISAR2_MEMHINT( _val ) ( ( _val ) << 4 )
2166#define AARCH32_ID_ISAR2_MEMHINT_SHIFT 4
2167#define AARCH32_ID_ISAR2_MEMHINT_MASK 0xf0U
2168#define AARCH32_ID_ISAR2_MEMHINT_GET( _reg ) \
2169 ( ( ( _reg ) >> 4 ) & 0xfU )
2171#define AARCH32_ID_ISAR2_MULTIACCESSINT( _val ) ( ( _val ) << 8 )
2172#define AARCH32_ID_ISAR2_MULTIACCESSINT_SHIFT 8
2173#define AARCH32_ID_ISAR2_MULTIACCESSINT_MASK 0xf00U
2174#define AARCH32_ID_ISAR2_MULTIACCESSINT_GET( _reg ) \
2175 ( ( ( _reg ) >> 8 ) & 0xfU )
2177#define AARCH32_ID_ISAR2_MULT( _val ) ( ( _val ) << 12 )
2178#define AARCH32_ID_ISAR2_MULT_SHIFT 12
2179#define AARCH32_ID_ISAR2_MULT_MASK 0xf000U
2180#define AARCH32_ID_ISAR2_MULT_GET( _reg ) \
2181 ( ( ( _reg ) >> 12 ) & 0xfU )
2183#define AARCH32_ID_ISAR2_MULTS( _val ) ( ( _val ) << 16 )
2184#define AARCH32_ID_ISAR2_MULTS_SHIFT 16
2185#define AARCH32_ID_ISAR2_MULTS_MASK 0xf0000U
2186#define AARCH32_ID_ISAR2_MULTS_GET( _reg ) \
2187 ( ( ( _reg ) >> 16 ) & 0xfU )
2189#define AARCH32_ID_ISAR2_MULTU( _val ) ( ( _val ) << 20 )
2190#define AARCH32_ID_ISAR2_MULTU_SHIFT 20
2191#define AARCH32_ID_ISAR2_MULTU_MASK 0xf00000U
2192#define AARCH32_ID_ISAR2_MULTU_GET( _reg ) \
2193 ( ( ( _reg ) >> 20 ) & 0xfU )
2195#define AARCH32_ID_ISAR2_PSR_AR( _val ) ( ( _val ) << 24 )
2196#define AARCH32_ID_ISAR2_PSR_AR_SHIFT 24
2197#define AARCH32_ID_ISAR2_PSR_AR_MASK 0xf000000U
2198#define AARCH32_ID_ISAR2_PSR_AR_GET( _reg ) \
2199 ( ( ( _reg ) >> 24 ) & 0xfU )
2201#define AARCH32_ID_ISAR2_REVERSAL( _val ) ( ( _val ) << 28 )
2202#define AARCH32_ID_ISAR2_REVERSAL_SHIFT 28
2203#define AARCH32_ID_ISAR2_REVERSAL_MASK 0xf0000000U
2204#define AARCH32_ID_ISAR2_REVERSAL_GET( _reg ) \
2205 ( ( ( _reg ) >> 28 ) & 0xfU )
2207static inline uint32_t _AArch32_Read_id_isar2(
void )
2212 "mrc p15, 0, %0, c0, c2, 2" :
"=&r" ( value ) : :
"memory"
2220#define AARCH32_ID_ISAR3_SATURATE( _val ) ( ( _val ) << 0 )
2221#define AARCH32_ID_ISAR3_SATURATE_SHIFT 0
2222#define AARCH32_ID_ISAR3_SATURATE_MASK 0xfU
2223#define AARCH32_ID_ISAR3_SATURATE_GET( _reg ) \
2224 ( ( ( _reg ) >> 0 ) & 0xfU )
2226#define AARCH32_ID_ISAR3_SIMD( _val ) ( ( _val ) << 4 )
2227#define AARCH32_ID_ISAR3_SIMD_SHIFT 4
2228#define AARCH32_ID_ISAR3_SIMD_MASK 0xf0U
2229#define AARCH32_ID_ISAR3_SIMD_GET( _reg ) \
2230 ( ( ( _reg ) >> 4 ) & 0xfU )
2232#define AARCH32_ID_ISAR3_SVC( _val ) ( ( _val ) << 8 )
2233#define AARCH32_ID_ISAR3_SVC_SHIFT 8
2234#define AARCH32_ID_ISAR3_SVC_MASK 0xf00U
2235#define AARCH32_ID_ISAR3_SVC_GET( _reg ) \
2236 ( ( ( _reg ) >> 8 ) & 0xfU )
2238#define AARCH32_ID_ISAR3_SYNCHPRIM( _val ) ( ( _val ) << 12 )
2239#define AARCH32_ID_ISAR3_SYNCHPRIM_SHIFT 12
2240#define AARCH32_ID_ISAR3_SYNCHPRIM_MASK 0xf000U
2241#define AARCH32_ID_ISAR3_SYNCHPRIM_GET( _reg ) \
2242 ( ( ( _reg ) >> 12 ) & 0xfU )
2244#define AARCH32_ID_ISAR3_TABBRANCH( _val ) ( ( _val ) << 16 )
2245#define AARCH32_ID_ISAR3_TABBRANCH_SHIFT 16
2246#define AARCH32_ID_ISAR3_TABBRANCH_MASK 0xf0000U
2247#define AARCH32_ID_ISAR3_TABBRANCH_GET( _reg ) \
2248 ( ( ( _reg ) >> 16 ) & 0xfU )
2250#define AARCH32_ID_ISAR3_T32COPY( _val ) ( ( _val ) << 20 )
2251#define AARCH32_ID_ISAR3_T32COPY_SHIFT 20
2252#define AARCH32_ID_ISAR3_T32COPY_MASK 0xf00000U
2253#define AARCH32_ID_ISAR3_T32COPY_GET( _reg ) \
2254 ( ( ( _reg ) >> 20 ) & 0xfU )
2256#define AARCH32_ID_ISAR3_TRUENOP( _val ) ( ( _val ) << 24 )
2257#define AARCH32_ID_ISAR3_TRUENOP_SHIFT 24
2258#define AARCH32_ID_ISAR3_TRUENOP_MASK 0xf000000U
2259#define AARCH32_ID_ISAR3_TRUENOP_GET( _reg ) \
2260 ( ( ( _reg ) >> 24 ) & 0xfU )
2262#define AARCH32_ID_ISAR3_T32EE( _val ) ( ( _val ) << 28 )
2263#define AARCH32_ID_ISAR3_T32EE_SHIFT 28
2264#define AARCH32_ID_ISAR3_T32EE_MASK 0xf0000000U
2265#define AARCH32_ID_ISAR3_T32EE_GET( _reg ) \
2266 ( ( ( _reg ) >> 28 ) & 0xfU )
2268static inline uint32_t _AArch32_Read_id_isar3(
void )
2273 "mrc p15, 0, %0, c0, c2, 3" :
"=&r" ( value ) : :
"memory"
2281#define AARCH32_ID_ISAR4_UNPRIV( _val ) ( ( _val ) << 0 )
2282#define AARCH32_ID_ISAR4_UNPRIV_SHIFT 0
2283#define AARCH32_ID_ISAR4_UNPRIV_MASK 0xfU
2284#define AARCH32_ID_ISAR4_UNPRIV_GET( _reg ) \
2285 ( ( ( _reg ) >> 0 ) & 0xfU )
2287#define AARCH32_ID_ISAR4_WITHSHIFTS( _val ) ( ( _val ) << 4 )
2288#define AARCH32_ID_ISAR4_WITHSHIFTS_SHIFT 4
2289#define AARCH32_ID_ISAR4_WITHSHIFTS_MASK 0xf0U
2290#define AARCH32_ID_ISAR4_WITHSHIFTS_GET( _reg ) \
2291 ( ( ( _reg ) >> 4 ) & 0xfU )
2293#define AARCH32_ID_ISAR4_WRITEBACK( _val ) ( ( _val ) << 8 )
2294#define AARCH32_ID_ISAR4_WRITEBACK_SHIFT 8
2295#define AARCH32_ID_ISAR4_WRITEBACK_MASK 0xf00U
2296#define AARCH32_ID_ISAR4_WRITEBACK_GET( _reg ) \
2297 ( ( ( _reg ) >> 8 ) & 0xfU )
2299#define AARCH32_ID_ISAR4_SMC( _val ) ( ( _val ) << 12 )
2300#define AARCH32_ID_ISAR4_SMC_SHIFT 12
2301#define AARCH32_ID_ISAR4_SMC_MASK 0xf000U
2302#define AARCH32_ID_ISAR4_SMC_GET( _reg ) \
2303 ( ( ( _reg ) >> 12 ) & 0xfU )
2305#define AARCH32_ID_ISAR4_BARRIER( _val ) ( ( _val ) << 16 )
2306#define AARCH32_ID_ISAR4_BARRIER_SHIFT 16
2307#define AARCH32_ID_ISAR4_BARRIER_MASK 0xf0000U
2308#define AARCH32_ID_ISAR4_BARRIER_GET( _reg ) \
2309 ( ( ( _reg ) >> 16 ) & 0xfU )
2311#define AARCH32_ID_ISAR4_SYNCHPRIM_FRAC( _val ) ( ( _val ) << 20 )
2312#define AARCH32_ID_ISAR4_SYNCHPRIM_FRAC_SHIFT 20
2313#define AARCH32_ID_ISAR4_SYNCHPRIM_FRAC_MASK 0xf00000U
2314#define AARCH32_ID_ISAR4_SYNCHPRIM_FRAC_GET( _reg ) \
2315 ( ( ( _reg ) >> 20 ) & 0xfU )
2317#define AARCH32_ID_ISAR4_PSR_M( _val ) ( ( _val ) << 24 )
2318#define AARCH32_ID_ISAR4_PSR_M_SHIFT 24
2319#define AARCH32_ID_ISAR4_PSR_M_MASK 0xf000000U
2320#define AARCH32_ID_ISAR4_PSR_M_GET( _reg ) \
2321 ( ( ( _reg ) >> 24 ) & 0xfU )
2323#define AARCH32_ID_ISAR4_SWP_FRAC( _val ) ( ( _val ) << 28 )
2324#define AARCH32_ID_ISAR4_SWP_FRAC_SHIFT 28
2325#define AARCH32_ID_ISAR4_SWP_FRAC_MASK 0xf0000000U
2326#define AARCH32_ID_ISAR4_SWP_FRAC_GET( _reg ) \
2327 ( ( ( _reg ) >> 28 ) & 0xfU )
2329static inline uint32_t _AArch32_Read_id_isar4(
void )
2334 "mrc p15, 0, %0, c0, c2, 4" :
"=&r" ( value ) : :
"memory"
2342#define AARCH32_ID_ISAR5_SEVL( _val ) ( ( _val ) << 0 )
2343#define AARCH32_ID_ISAR5_SEVL_SHIFT 0
2344#define AARCH32_ID_ISAR5_SEVL_MASK 0xfU
2345#define AARCH32_ID_ISAR5_SEVL_GET( _reg ) \
2346 ( ( ( _reg ) >> 0 ) & 0xfU )
2348#define AARCH32_ID_ISAR5_AES( _val ) ( ( _val ) << 4 )
2349#define AARCH32_ID_ISAR5_AES_SHIFT 4
2350#define AARCH32_ID_ISAR5_AES_MASK 0xf0U
2351#define AARCH32_ID_ISAR5_AES_GET( _reg ) \
2352 ( ( ( _reg ) >> 4 ) & 0xfU )
2354#define AARCH32_ID_ISAR5_SHA1( _val ) ( ( _val ) << 8 )
2355#define AARCH32_ID_ISAR5_SHA1_SHIFT 8
2356#define AARCH32_ID_ISAR5_SHA1_MASK 0xf00U
2357#define AARCH32_ID_ISAR5_SHA1_GET( _reg ) \
2358 ( ( ( _reg ) >> 8 ) & 0xfU )
2360#define AARCH32_ID_ISAR5_SHA2( _val ) ( ( _val ) << 12 )
2361#define AARCH32_ID_ISAR5_SHA2_SHIFT 12
2362#define AARCH32_ID_ISAR5_SHA2_MASK 0xf000U
2363#define AARCH32_ID_ISAR5_SHA2_GET( _reg ) \
2364 ( ( ( _reg ) >> 12 ) & 0xfU )
2366#define AARCH32_ID_ISAR5_CRC32( _val ) ( ( _val ) << 16 )
2367#define AARCH32_ID_ISAR5_CRC32_SHIFT 16
2368#define AARCH32_ID_ISAR5_CRC32_MASK 0xf0000U
2369#define AARCH32_ID_ISAR5_CRC32_GET( _reg ) \
2370 ( ( ( _reg ) >> 16 ) & 0xfU )
2372#define AARCH32_ID_ISAR5_RDM( _val ) ( ( _val ) << 24 )
2373#define AARCH32_ID_ISAR5_RDM_SHIFT 24
2374#define AARCH32_ID_ISAR5_RDM_MASK 0xf000000U
2375#define AARCH32_ID_ISAR5_RDM_GET( _reg ) \
2376 ( ( ( _reg ) >> 24 ) & 0xfU )
2378#define AARCH32_ID_ISAR5_VCMA( _val ) ( ( _val ) << 28 )
2379#define AARCH32_ID_ISAR5_VCMA_SHIFT 28
2380#define AARCH32_ID_ISAR5_VCMA_MASK 0xf0000000U
2381#define AARCH32_ID_ISAR5_VCMA_GET( _reg ) \
2382 ( ( ( _reg ) >> 28 ) & 0xfU )
2384static inline uint32_t _AArch32_Read_id_isar5(
void )
2389 "mrc p15, 0, %0, c0, c2, 5" :
"=&r" ( value ) : :
"memory"
2397#define AARCH32_ID_ISAR6_JSCVT( _val ) ( ( _val ) << 0 )
2398#define AARCH32_ID_ISAR6_JSCVT_SHIFT 0
2399#define AARCH32_ID_ISAR6_JSCVT_MASK 0xfU
2400#define AARCH32_ID_ISAR6_JSCVT_GET( _reg ) \
2401 ( ( ( _reg ) >> 0 ) & 0xfU )
2403#define AARCH32_ID_ISAR6_DP( _val ) ( ( _val ) << 4 )
2404#define AARCH32_ID_ISAR6_DP_SHIFT 4
2405#define AARCH32_ID_ISAR6_DP_MASK 0xf0U
2406#define AARCH32_ID_ISAR6_DP_GET( _reg ) \
2407 ( ( ( _reg ) >> 4 ) & 0xfU )
2409#define AARCH32_ID_ISAR6_FHM( _val ) ( ( _val ) << 8 )
2410#define AARCH32_ID_ISAR6_FHM_SHIFT 8
2411#define AARCH32_ID_ISAR6_FHM_MASK 0xf00U
2412#define AARCH32_ID_ISAR6_FHM_GET( _reg ) \
2413 ( ( ( _reg ) >> 8 ) & 0xfU )
2415#define AARCH32_ID_ISAR6_SB( _val ) ( ( _val ) << 12 )
2416#define AARCH32_ID_ISAR6_SB_SHIFT 12
2417#define AARCH32_ID_ISAR6_SB_MASK 0xf000U
2418#define AARCH32_ID_ISAR6_SB_GET( _reg ) \
2419 ( ( ( _reg ) >> 12 ) & 0xfU )
2421#define AARCH32_ID_ISAR6_SPECRES( _val ) ( ( _val ) << 16 )
2422#define AARCH32_ID_ISAR6_SPECRES_SHIFT 16
2423#define AARCH32_ID_ISAR6_SPECRES_MASK 0xf0000U
2424#define AARCH32_ID_ISAR6_SPECRES_GET( _reg ) \
2425 ( ( ( _reg ) >> 16 ) & 0xfU )
2427#define AARCH32_ID_ISAR6_BF16( _val ) ( ( _val ) << 20 )
2428#define AARCH32_ID_ISAR6_BF16_SHIFT 20
2429#define AARCH32_ID_ISAR6_BF16_MASK 0xf00000U
2430#define AARCH32_ID_ISAR6_BF16_GET( _reg ) \
2431 ( ( ( _reg ) >> 20 ) & 0xfU )
2433#define AARCH32_ID_ISAR6_I8MM( _val ) ( ( _val ) << 24 )
2434#define AARCH32_ID_ISAR6_I8MM_SHIFT 24
2435#define AARCH32_ID_ISAR6_I8MM_MASK 0xf000000U
2436#define AARCH32_ID_ISAR6_I8MM_GET( _reg ) \
2437 ( ( ( _reg ) >> 24 ) & 0xfU )
2439static inline uint32_t _AArch32_Read_id_isar6(
void )
2444 "mrc p15, 0, %0, c0, c2, 7" :
"=&r" ( value ) : :
"memory"
2452#define AARCH32_ID_MMFR0_VMSA( _val ) ( ( _val ) << 0 )
2453#define AARCH32_ID_MMFR0_VMSA_SHIFT 0
2454#define AARCH32_ID_MMFR0_VMSA_MASK 0xfU
2455#define AARCH32_ID_MMFR0_VMSA_GET( _reg ) \
2456 ( ( ( _reg ) >> 0 ) & 0xfU )
2458#define AARCH32_ID_MMFR0_PMSA( _val ) ( ( _val ) << 4 )
2459#define AARCH32_ID_MMFR0_PMSA_SHIFT 4
2460#define AARCH32_ID_MMFR0_PMSA_MASK 0xf0U
2461#define AARCH32_ID_MMFR0_PMSA_GET( _reg ) \
2462 ( ( ( _reg ) >> 4 ) & 0xfU )
2464#define AARCH32_ID_MMFR0_OUTERSHR( _val ) ( ( _val ) << 8 )
2465#define AARCH32_ID_MMFR0_OUTERSHR_SHIFT 8
2466#define AARCH32_ID_MMFR0_OUTERSHR_MASK 0xf00U
2467#define AARCH32_ID_MMFR0_OUTERSHR_GET( _reg ) \
2468 ( ( ( _reg ) >> 8 ) & 0xfU )
2470#define AARCH32_ID_MMFR0_SHARELVL( _val ) ( ( _val ) << 12 )
2471#define AARCH32_ID_MMFR0_SHARELVL_SHIFT 12
2472#define AARCH32_ID_MMFR0_SHARELVL_MASK 0xf000U
2473#define AARCH32_ID_MMFR0_SHARELVL_GET( _reg ) \
2474 ( ( ( _reg ) >> 12 ) & 0xfU )
2476#define AARCH32_ID_MMFR0_TCM( _val ) ( ( _val ) << 16 )
2477#define AARCH32_ID_MMFR0_TCM_SHIFT 16
2478#define AARCH32_ID_MMFR0_TCM_MASK 0xf0000U
2479#define AARCH32_ID_MMFR0_TCM_GET( _reg ) \
2480 ( ( ( _reg ) >> 16 ) & 0xfU )
2482#define AARCH32_ID_MMFR0_AUXREG( _val ) ( ( _val ) << 20 )
2483#define AARCH32_ID_MMFR0_AUXREG_SHIFT 20
2484#define AARCH32_ID_MMFR0_AUXREG_MASK 0xf00000U
2485#define AARCH32_ID_MMFR0_AUXREG_GET( _reg ) \
2486 ( ( ( _reg ) >> 20 ) & 0xfU )
2488#define AARCH32_ID_MMFR0_FCSE( _val ) ( ( _val ) << 24 )
2489#define AARCH32_ID_MMFR0_FCSE_SHIFT 24
2490#define AARCH32_ID_MMFR0_FCSE_MASK 0xf000000U
2491#define AARCH32_ID_MMFR0_FCSE_GET( _reg ) \
2492 ( ( ( _reg ) >> 24 ) & 0xfU )
2494#define AARCH32_ID_MMFR0_INNERSHR( _val ) ( ( _val ) << 28 )
2495#define AARCH32_ID_MMFR0_INNERSHR_SHIFT 28
2496#define AARCH32_ID_MMFR0_INNERSHR_MASK 0xf0000000U
2497#define AARCH32_ID_MMFR0_INNERSHR_GET( _reg ) \
2498 ( ( ( _reg ) >> 28 ) & 0xfU )
2500static inline uint32_t _AArch32_Read_id_mmfr0(
void )
2505 "mrc p15, 0, %0, c0, c1, 4" :
"=&r" ( value ) : :
"memory"
2513#define AARCH32_ID_MMFR1_L1HVDVA( _val ) ( ( _val ) << 0 )
2514#define AARCH32_ID_MMFR1_L1HVDVA_SHIFT 0
2515#define AARCH32_ID_MMFR1_L1HVDVA_MASK 0xfU
2516#define AARCH32_ID_MMFR1_L1HVDVA_GET( _reg ) \
2517 ( ( ( _reg ) >> 0 ) & 0xfU )
2519#define AARCH32_ID_MMFR1_L1UNIVA( _val ) ( ( _val ) << 4 )
2520#define AARCH32_ID_MMFR1_L1UNIVA_SHIFT 4
2521#define AARCH32_ID_MMFR1_L1UNIVA_MASK 0xf0U
2522#define AARCH32_ID_MMFR1_L1UNIVA_GET( _reg ) \
2523 ( ( ( _reg ) >> 4 ) & 0xfU )
2525#define AARCH32_ID_MMFR1_L1HVDSW( _val ) ( ( _val ) << 8 )
2526#define AARCH32_ID_MMFR1_L1HVDSW_SHIFT 8
2527#define AARCH32_ID_MMFR1_L1HVDSW_MASK 0xf00U
2528#define AARCH32_ID_MMFR1_L1HVDSW_GET( _reg ) \
2529 ( ( ( _reg ) >> 8 ) & 0xfU )
2531#define AARCH32_ID_MMFR1_L1UNISW( _val ) ( ( _val ) << 12 )
2532#define AARCH32_ID_MMFR1_L1UNISW_SHIFT 12
2533#define AARCH32_ID_MMFR1_L1UNISW_MASK 0xf000U
2534#define AARCH32_ID_MMFR1_L1UNISW_GET( _reg ) \
2535 ( ( ( _reg ) >> 12 ) & 0xfU )
2537#define AARCH32_ID_MMFR1_L1HVD( _val ) ( ( _val ) << 16 )
2538#define AARCH32_ID_MMFR1_L1HVD_SHIFT 16
2539#define AARCH32_ID_MMFR1_L1HVD_MASK 0xf0000U
2540#define AARCH32_ID_MMFR1_L1HVD_GET( _reg ) \
2541 ( ( ( _reg ) >> 16 ) & 0xfU )
2543#define AARCH32_ID_MMFR1_L1UNI( _val ) ( ( _val ) << 20 )
2544#define AARCH32_ID_MMFR1_L1UNI_SHIFT 20
2545#define AARCH32_ID_MMFR1_L1UNI_MASK 0xf00000U
2546#define AARCH32_ID_MMFR1_L1UNI_GET( _reg ) \
2547 ( ( ( _reg ) >> 20 ) & 0xfU )
2549#define AARCH32_ID_MMFR1_L1TSTCLN( _val ) ( ( _val ) << 24 )
2550#define AARCH32_ID_MMFR1_L1TSTCLN_SHIFT 24
2551#define AARCH32_ID_MMFR1_L1TSTCLN_MASK 0xf000000U
2552#define AARCH32_ID_MMFR1_L1TSTCLN_GET( _reg ) \
2553 ( ( ( _reg ) >> 24 ) & 0xfU )
2555#define AARCH32_ID_MMFR1_BPRED( _val ) ( ( _val ) << 28 )
2556#define AARCH32_ID_MMFR1_BPRED_SHIFT 28
2557#define AARCH32_ID_MMFR1_BPRED_MASK 0xf0000000U
2558#define AARCH32_ID_MMFR1_BPRED_GET( _reg ) \
2559 ( ( ( _reg ) >> 28 ) & 0xfU )
2561static inline uint32_t _AArch32_Read_id_mmfr1(
void )
2566 "mrc p15, 0, %0, c0, c1, 5" :
"=&r" ( value ) : :
"memory"
2574#define AARCH32_ID_MMFR2_L1HVDFG( _val ) ( ( _val ) << 0 )
2575#define AARCH32_ID_MMFR2_L1HVDFG_SHIFT 0
2576#define AARCH32_ID_MMFR2_L1HVDFG_MASK 0xfU
2577#define AARCH32_ID_MMFR2_L1HVDFG_GET( _reg ) \
2578 ( ( ( _reg ) >> 0 ) & 0xfU )
2580#define AARCH32_ID_MMFR2_L1HVDBG( _val ) ( ( _val ) << 4 )
2581#define AARCH32_ID_MMFR2_L1HVDBG_SHIFT 4
2582#define AARCH32_ID_MMFR2_L1HVDBG_MASK 0xf0U
2583#define AARCH32_ID_MMFR2_L1HVDBG_GET( _reg ) \
2584 ( ( ( _reg ) >> 4 ) & 0xfU )
2586#define AARCH32_ID_MMFR2_L1HVDRNG( _val ) ( ( _val ) << 8 )
2587#define AARCH32_ID_MMFR2_L1HVDRNG_SHIFT 8
2588#define AARCH32_ID_MMFR2_L1HVDRNG_MASK 0xf00U
2589#define AARCH32_ID_MMFR2_L1HVDRNG_GET( _reg ) \
2590 ( ( ( _reg ) >> 8 ) & 0xfU )
2592#define AARCH32_ID_MMFR2_HVDTLB( _val ) ( ( _val ) << 12 )
2593#define AARCH32_ID_MMFR2_HVDTLB_SHIFT 12
2594#define AARCH32_ID_MMFR2_HVDTLB_MASK 0xf000U
2595#define AARCH32_ID_MMFR2_HVDTLB_GET( _reg ) \
2596 ( ( ( _reg ) >> 12 ) & 0xfU )
2598#define AARCH32_ID_MMFR2_UNITLB( _val ) ( ( _val ) << 16 )
2599#define AARCH32_ID_MMFR2_UNITLB_SHIFT 16
2600#define AARCH32_ID_MMFR2_UNITLB_MASK 0xf0000U
2601#define AARCH32_ID_MMFR2_UNITLB_GET( _reg ) \
2602 ( ( ( _reg ) >> 16 ) & 0xfU )
2604#define AARCH32_ID_MMFR2_MEMBARR( _val ) ( ( _val ) << 20 )
2605#define AARCH32_ID_MMFR2_MEMBARR_SHIFT 20
2606#define AARCH32_ID_MMFR2_MEMBARR_MASK 0xf00000U
2607#define AARCH32_ID_MMFR2_MEMBARR_GET( _reg ) \
2608 ( ( ( _reg ) >> 20 ) & 0xfU )
2610#define AARCH32_ID_MMFR2_WFISTALL( _val ) ( ( _val ) << 24 )
2611#define AARCH32_ID_MMFR2_WFISTALL_SHIFT 24
2612#define AARCH32_ID_MMFR2_WFISTALL_MASK 0xf000000U
2613#define AARCH32_ID_MMFR2_WFISTALL_GET( _reg ) \
2614 ( ( ( _reg ) >> 24 ) & 0xfU )
2616#define AARCH32_ID_MMFR2_HWACCFLG( _val ) ( ( _val ) << 28 )
2617#define AARCH32_ID_MMFR2_HWACCFLG_SHIFT 28
2618#define AARCH32_ID_MMFR2_HWACCFLG_MASK 0xf0000000U
2619#define AARCH32_ID_MMFR2_HWACCFLG_GET( _reg ) \
2620 ( ( ( _reg ) >> 28 ) & 0xfU )
2622static inline uint32_t _AArch32_Read_id_mmfr2(
void )
2627 "mrc p15, 0, %0, c0, c1, 6" :
"=&r" ( value ) : :
"memory"
2635#define AARCH32_ID_MMFR3_CMAINTVA( _val ) ( ( _val ) << 0 )
2636#define AARCH32_ID_MMFR3_CMAINTVA_SHIFT 0
2637#define AARCH32_ID_MMFR3_CMAINTVA_MASK 0xfU
2638#define AARCH32_ID_MMFR3_CMAINTVA_GET( _reg ) \
2639 ( ( ( _reg ) >> 0 ) & 0xfU )
2641#define AARCH32_ID_MMFR3_CMAINTSW( _val ) ( ( _val ) << 4 )
2642#define AARCH32_ID_MMFR3_CMAINTSW_SHIFT 4
2643#define AARCH32_ID_MMFR3_CMAINTSW_MASK 0xf0U
2644#define AARCH32_ID_MMFR3_CMAINTSW_GET( _reg ) \
2645 ( ( ( _reg ) >> 4 ) & 0xfU )
2647#define AARCH32_ID_MMFR3_BPMAINT( _val ) ( ( _val ) << 8 )
2648#define AARCH32_ID_MMFR3_BPMAINT_SHIFT 8
2649#define AARCH32_ID_MMFR3_BPMAINT_MASK 0xf00U
2650#define AARCH32_ID_MMFR3_BPMAINT_GET( _reg ) \
2651 ( ( ( _reg ) >> 8 ) & 0xfU )
2653#define AARCH32_ID_MMFR3_MAINTBCST( _val ) ( ( _val ) << 12 )
2654#define AARCH32_ID_MMFR3_MAINTBCST_SHIFT 12
2655#define AARCH32_ID_MMFR3_MAINTBCST_MASK 0xf000U
2656#define AARCH32_ID_MMFR3_MAINTBCST_GET( _reg ) \
2657 ( ( ( _reg ) >> 12 ) & 0xfU )
2659#define AARCH32_ID_MMFR3_PAN( _val ) ( ( _val ) << 16 )
2660#define AARCH32_ID_MMFR3_PAN_SHIFT 16
2661#define AARCH32_ID_MMFR3_PAN_MASK 0xf0000U
2662#define AARCH32_ID_MMFR3_PAN_GET( _reg ) \
2663 ( ( ( _reg ) >> 16 ) & 0xfU )
2665#define AARCH32_ID_MMFR3_COHWALK( _val ) ( ( _val ) << 20 )
2666#define AARCH32_ID_MMFR3_COHWALK_SHIFT 20
2667#define AARCH32_ID_MMFR3_COHWALK_MASK 0xf00000U
2668#define AARCH32_ID_MMFR3_COHWALK_GET( _reg ) \
2669 ( ( ( _reg ) >> 20 ) & 0xfU )
2671#define AARCH32_ID_MMFR3_CMEMSZ( _val ) ( ( _val ) << 24 )
2672#define AARCH32_ID_MMFR3_CMEMSZ_SHIFT 24
2673#define AARCH32_ID_MMFR3_CMEMSZ_MASK 0xf000000U
2674#define AARCH32_ID_MMFR3_CMEMSZ_GET( _reg ) \
2675 ( ( ( _reg ) >> 24 ) & 0xfU )
2677#define AARCH32_ID_MMFR3_SUPERSEC( _val ) ( ( _val ) << 28 )
2678#define AARCH32_ID_MMFR3_SUPERSEC_SHIFT 28
2679#define AARCH32_ID_MMFR3_SUPERSEC_MASK 0xf0000000U
2680#define AARCH32_ID_MMFR3_SUPERSEC_GET( _reg ) \
2681 ( ( ( _reg ) >> 28 ) & 0xfU )
2683static inline uint32_t _AArch32_Read_id_mmfr3(
void )
2688 "mrc p15, 0, %0, c0, c1, 7" :
"=&r" ( value ) : :
"memory"
2696#define AARCH32_ID_MMFR4_SPECSEI( _val ) ( ( _val ) << 0 )
2697#define AARCH32_ID_MMFR4_SPECSEI_SHIFT 0
2698#define AARCH32_ID_MMFR4_SPECSEI_MASK 0xfU
2699#define AARCH32_ID_MMFR4_SPECSEI_GET( _reg ) \
2700 ( ( ( _reg ) >> 0 ) & 0xfU )
2702#define AARCH32_ID_MMFR4_AC2( _val ) ( ( _val ) << 4 )
2703#define AARCH32_ID_MMFR4_AC2_SHIFT 4
2704#define AARCH32_ID_MMFR4_AC2_MASK 0xf0U
2705#define AARCH32_ID_MMFR4_AC2_GET( _reg ) \
2706 ( ( ( _reg ) >> 4 ) & 0xfU )
2708#define AARCH32_ID_MMFR4_XNX( _val ) ( ( _val ) << 8 )
2709#define AARCH32_ID_MMFR4_XNX_SHIFT 8
2710#define AARCH32_ID_MMFR4_XNX_MASK 0xf00U
2711#define AARCH32_ID_MMFR4_XNX_GET( _reg ) \
2712 ( ( ( _reg ) >> 8 ) & 0xfU )
2714#define AARCH32_ID_MMFR4_CNP( _val ) ( ( _val ) << 12 )
2715#define AARCH32_ID_MMFR4_CNP_SHIFT 12
2716#define AARCH32_ID_MMFR4_CNP_MASK 0xf000U
2717#define AARCH32_ID_MMFR4_CNP_GET( _reg ) \
2718 ( ( ( _reg ) >> 12 ) & 0xfU )
2720#define AARCH32_ID_MMFR4_HPDS( _val ) ( ( _val ) << 16 )
2721#define AARCH32_ID_MMFR4_HPDS_SHIFT 16
2722#define AARCH32_ID_MMFR4_HPDS_MASK 0xf0000U
2723#define AARCH32_ID_MMFR4_HPDS_GET( _reg ) \
2724 ( ( ( _reg ) >> 16 ) & 0xfU )
2726#define AARCH32_ID_MMFR4_LSM( _val ) ( ( _val ) << 20 )
2727#define AARCH32_ID_MMFR4_LSM_SHIFT 20
2728#define AARCH32_ID_MMFR4_LSM_MASK 0xf00000U
2729#define AARCH32_ID_MMFR4_LSM_GET( _reg ) \
2730 ( ( ( _reg ) >> 20 ) & 0xfU )
2732#define AARCH32_ID_MMFR4_CCIDX( _val ) ( ( _val ) << 24 )
2733#define AARCH32_ID_MMFR4_CCIDX_SHIFT 24
2734#define AARCH32_ID_MMFR4_CCIDX_MASK 0xf000000U
2735#define AARCH32_ID_MMFR4_CCIDX_GET( _reg ) \
2736 ( ( ( _reg ) >> 24 ) & 0xfU )
2738#define AARCH32_ID_MMFR4_EVT( _val ) ( ( _val ) << 28 )
2739#define AARCH32_ID_MMFR4_EVT_SHIFT 28
2740#define AARCH32_ID_MMFR4_EVT_MASK 0xf0000000U
2741#define AARCH32_ID_MMFR4_EVT_GET( _reg ) \
2742 ( ( ( _reg ) >> 28 ) & 0xfU )
2744static inline uint32_t _AArch32_Read_id_mmfr4(
void )
2749 "mrc p15, 0, %0, c0, c2, 6" :
"=&r" ( value ) : :
"memory"
2757#define AARCH32_ID_MMFR5_ETS( _val ) ( ( _val ) << 0 )
2758#define AARCH32_ID_MMFR5_ETS_SHIFT 0
2759#define AARCH32_ID_MMFR5_ETS_MASK 0xfU
2760#define AARCH32_ID_MMFR5_ETS_GET( _reg ) \
2761 ( ( ( _reg ) >> 0 ) & 0xfU )
2763static inline uint32_t _AArch32_Read_id_mmfr5(
void )
2768 "mrc p15, 0, %0, c0, c3, 6" :
"=&r" ( value ) : :
"memory"
2776#define AARCH32_ID_PFR0_STATE0( _val ) ( ( _val ) << 0 )
2777#define AARCH32_ID_PFR0_STATE0_SHIFT 0
2778#define AARCH32_ID_PFR0_STATE0_MASK 0xfU
2779#define AARCH32_ID_PFR0_STATE0_GET( _reg ) \
2780 ( ( ( _reg ) >> 0 ) & 0xfU )
2782#define AARCH32_ID_PFR0_STATE1( _val ) ( ( _val ) << 4 )
2783#define AARCH32_ID_PFR0_STATE1_SHIFT 4
2784#define AARCH32_ID_PFR0_STATE1_MASK 0xf0U
2785#define AARCH32_ID_PFR0_STATE1_GET( _reg ) \
2786 ( ( ( _reg ) >> 4 ) & 0xfU )
2788#define AARCH32_ID_PFR0_STATE2( _val ) ( ( _val ) << 8 )
2789#define AARCH32_ID_PFR0_STATE2_SHIFT 8
2790#define AARCH32_ID_PFR0_STATE2_MASK 0xf00U
2791#define AARCH32_ID_PFR0_STATE2_GET( _reg ) \
2792 ( ( ( _reg ) >> 8 ) & 0xfU )
2794#define AARCH32_ID_PFR0_STATE3( _val ) ( ( _val ) << 12 )
2795#define AARCH32_ID_PFR0_STATE3_SHIFT 12
2796#define AARCH32_ID_PFR0_STATE3_MASK 0xf000U
2797#define AARCH32_ID_PFR0_STATE3_GET( _reg ) \
2798 ( ( ( _reg ) >> 12 ) & 0xfU )
2800#define AARCH32_ID_PFR0_CSV2( _val ) ( ( _val ) << 16 )
2801#define AARCH32_ID_PFR0_CSV2_SHIFT 16
2802#define AARCH32_ID_PFR0_CSV2_MASK 0xf0000U
2803#define AARCH32_ID_PFR0_CSV2_GET( _reg ) \
2804 ( ( ( _reg ) >> 16 ) & 0xfU )
2806#define AARCH32_ID_PFR0_AMU( _val ) ( ( _val ) << 20 )
2807#define AARCH32_ID_PFR0_AMU_SHIFT 20
2808#define AARCH32_ID_PFR0_AMU_MASK 0xf00000U
2809#define AARCH32_ID_PFR0_AMU_GET( _reg ) \
2810 ( ( ( _reg ) >> 20 ) & 0xfU )
2812#define AARCH32_ID_PFR0_DIT( _val ) ( ( _val ) << 24 )
2813#define AARCH32_ID_PFR0_DIT_SHIFT 24
2814#define AARCH32_ID_PFR0_DIT_MASK 0xf000000U
2815#define AARCH32_ID_PFR0_DIT_GET( _reg ) \
2816 ( ( ( _reg ) >> 24 ) & 0xfU )
2818#define AARCH32_ID_PFR0_RAS( _val ) ( ( _val ) << 28 )
2819#define AARCH32_ID_PFR0_RAS_SHIFT 28
2820#define AARCH32_ID_PFR0_RAS_MASK 0xf0000000U
2821#define AARCH32_ID_PFR0_RAS_GET( _reg ) \
2822 ( ( ( _reg ) >> 28 ) & 0xfU )
2824static inline uint32_t _AArch32_Read_id_pfr0(
void )
2829 "mrc p15, 0, %0, c0, c1, 0" :
"=&r" ( value ) : :
"memory"
2837#define AARCH32_ID_PFR1_PROGMOD( _val ) ( ( _val ) << 0 )
2838#define AARCH32_ID_PFR1_PROGMOD_SHIFT 0
2839#define AARCH32_ID_PFR1_PROGMOD_MASK 0xfU
2840#define AARCH32_ID_PFR1_PROGMOD_GET( _reg ) \
2841 ( ( ( _reg ) >> 0 ) & 0xfU )
2843#define AARCH32_ID_PFR1_SECURITY( _val ) ( ( _val ) << 4 )
2844#define AARCH32_ID_PFR1_SECURITY_SHIFT 4
2845#define AARCH32_ID_PFR1_SECURITY_MASK 0xf0U
2846#define AARCH32_ID_PFR1_SECURITY_GET( _reg ) \
2847 ( ( ( _reg ) >> 4 ) & 0xfU )
2849#define AARCH32_ID_PFR1_MPROGMOD( _val ) ( ( _val ) << 8 )
2850#define AARCH32_ID_PFR1_MPROGMOD_SHIFT 8
2851#define AARCH32_ID_PFR1_MPROGMOD_MASK 0xf00U
2852#define AARCH32_ID_PFR1_MPROGMOD_GET( _reg ) \
2853 ( ( ( _reg ) >> 8 ) & 0xfU )
2855#define AARCH32_ID_PFR1_VIRTUALIZATION( _val ) ( ( _val ) << 12 )
2856#define AARCH32_ID_PFR1_VIRTUALIZATION_SHIFT 12
2857#define AARCH32_ID_PFR1_VIRTUALIZATION_MASK 0xf000U
2858#define AARCH32_ID_PFR1_VIRTUALIZATION_GET( _reg ) \
2859 ( ( ( _reg ) >> 12 ) & 0xfU )
2861#define AARCH32_ID_PFR1_GENTIMER( _val ) ( ( _val ) << 16 )
2862#define AARCH32_ID_PFR1_GENTIMER_SHIFT 16
2863#define AARCH32_ID_PFR1_GENTIMER_MASK 0xf0000U
2864#define AARCH32_ID_PFR1_GENTIMER_GET( _reg ) \
2865 ( ( ( _reg ) >> 16 ) & 0xfU )
2867#define AARCH32_ID_PFR1_SEC_FRAC( _val ) ( ( _val ) << 20 )
2868#define AARCH32_ID_PFR1_SEC_FRAC_SHIFT 20
2869#define AARCH32_ID_PFR1_SEC_FRAC_MASK 0xf00000U
2870#define AARCH32_ID_PFR1_SEC_FRAC_GET( _reg ) \
2871 ( ( ( _reg ) >> 20 ) & 0xfU )
2873#define AARCH32_ID_PFR1_VIRT_FRAC( _val ) ( ( _val ) << 24 )
2874#define AARCH32_ID_PFR1_VIRT_FRAC_SHIFT 24
2875#define AARCH32_ID_PFR1_VIRT_FRAC_MASK 0xf000000U
2876#define AARCH32_ID_PFR1_VIRT_FRAC_GET( _reg ) \
2877 ( ( ( _reg ) >> 24 ) & 0xfU )
2879#define AARCH32_ID_PFR1_GIC( _val ) ( ( _val ) << 28 )
2880#define AARCH32_ID_PFR1_GIC_SHIFT 28
2881#define AARCH32_ID_PFR1_GIC_MASK 0xf0000000U
2882#define AARCH32_ID_PFR1_GIC_GET( _reg ) \
2883 ( ( ( _reg ) >> 28 ) & 0xfU )
2885static inline uint32_t _AArch32_Read_id_pfr1(
void )
2890 "mrc p15, 0, %0, c0, c1, 1" :
"=&r" ( value ) : :
"memory"
2898#define AARCH32_ID_PFR2_CSV3( _val ) ( ( _val ) << 0 )
2899#define AARCH32_ID_PFR2_CSV3_SHIFT 0
2900#define AARCH32_ID_PFR2_CSV3_MASK 0xfU
2901#define AARCH32_ID_PFR2_CSV3_GET( _reg ) \
2902 ( ( ( _reg ) >> 0 ) & 0xfU )
2904#define AARCH32_ID_PFR2_SSBS( _val ) ( ( _val ) << 4 )
2905#define AARCH32_ID_PFR2_SSBS_SHIFT 4
2906#define AARCH32_ID_PFR2_SSBS_MASK 0xf0U
2907#define AARCH32_ID_PFR2_SSBS_GET( _reg ) \
2908 ( ( ( _reg ) >> 4 ) & 0xfU )
2910#define AARCH32_ID_PFR2_RAS_FRAC( _val ) ( ( _val ) << 8 )
2911#define AARCH32_ID_PFR2_RAS_FRAC_SHIFT 8
2912#define AARCH32_ID_PFR2_RAS_FRAC_MASK 0xf00U
2913#define AARCH32_ID_PFR2_RAS_FRAC_GET( _reg ) \
2914 ( ( ( _reg ) >> 8 ) & 0xfU )
2916static inline uint32_t _AArch32_Read_id_pfr2(
void )
2921 "mrc p15, 0, %0, c0, c3, 4" :
"=&r" ( value ) : :
"memory"
2929static inline uint32_t _AArch32_Read_ifar(
void )
2934 "mrc p15, 0, %0, c6, c0, 2" :
"=&r" ( value ) : :
"memory"
2940static inline void _AArch32_Write_ifar( uint32_t value )
2943 "mcr p15, 0, %0, c6, c0, 2" : :
"r" ( value ) :
"memory"
2949#define AARCH32_IFSR_FS_3_0( _val ) ( ( _val ) << 0 )
2950#define AARCH32_IFSR_FS_3_0_SHIFT 0
2951#define AARCH32_IFSR_FS_3_0_MASK 0xfU
2952#define AARCH32_IFSR_FS_3_0_GET( _reg ) \
2953 ( ( ( _reg ) >> 0 ) & 0xfU )
2955#define AARCH32_IFSR_STATUS( _val ) ( ( _val ) << 0 )
2956#define AARCH32_IFSR_STATUS_SHIFT 0
2957#define AARCH32_IFSR_STATUS_MASK 0x3fU
2958#define AARCH32_IFSR_STATUS_GET( _reg ) \
2959 ( ( ( _reg ) >> 0 ) & 0x3fU )
2961#define AARCH32_IFSR_LPAE 0x200U
2963#define AARCH32_IFSR_FS_4 0x400U
2965#define AARCH32_IFSR_EXT 0x1000U
2967#define AARCH32_IFSR_FNV 0x10000U
2969static inline uint32_t _AArch32_Read_ifsr(
void )
2974 "mrc p15, 0, %0, c5, c0, 1" :
"=&r" ( value ) : :
"memory"
2980static inline void _AArch32_Write_ifsr( uint32_t value )
2983 "mcr p15, 0, %0, c5, c0, 1" : :
"r" ( value ) :
"memory"
2989#define AARCH32_ISR_F 0x40U
2991#define AARCH32_ISR_I 0x80U
2993#define AARCH32_ISR_A 0x100U
2995static inline uint32_t _AArch32_Read_isr(
void )
3000 "mrc p15, 0, %0, c12, c1, 0" :
"=&r" ( value ) : :
"memory"
3008static inline void _AArch32_Write_itlbiall( uint32_t value )
3011 "mcr p15, 0, %0, c8, c5, 0" : :
"r" ( value ) :
"memory"
3017#define AARCH32_ITLBIASID_ASID( _val ) ( ( _val ) << 0 )
3018#define AARCH32_ITLBIASID_ASID_SHIFT 0
3019#define AARCH32_ITLBIASID_ASID_MASK 0xffU
3020#define AARCH32_ITLBIASID_ASID_GET( _reg ) \
3021 ( ( ( _reg ) >> 0 ) & 0xffU )
3023static inline void _AArch32_Write_itlbiasid( uint32_t value )
3026 "mcr p15, 0, %0, c8, c5, 2" : :
"r" ( value ) :
"memory"
3032#define AARCH32_ITLBIMVA_ASID( _val ) ( ( _val ) << 0 )
3033#define AARCH32_ITLBIMVA_ASID_SHIFT 0
3034#define AARCH32_ITLBIMVA_ASID_MASK 0xffU
3035#define AARCH32_ITLBIMVA_ASID_GET( _reg ) \
3036 ( ( ( _reg ) >> 0 ) & 0xffU )
3038#define AARCH32_ITLBIMVA_VA( _val ) ( ( _val ) << 12 )
3039#define AARCH32_ITLBIMVA_VA_SHIFT 12
3040#define AARCH32_ITLBIMVA_VA_MASK 0xfffff000U
3041#define AARCH32_ITLBIMVA_VA_GET( _reg ) \
3042 ( ( ( _reg ) >> 12 ) & 0xfffffU )
3044static inline void _AArch32_Write_itlbimva( uint32_t value )
3047 "mcr p15, 0, %0, c8, c5, 1" : :
"r" ( value ) :
"memory"
3053static inline uint32_t _AArch32_Read_jidr(
void )
3058 "mrc p14, 7, %0, c0, c0, 0" :
"=&r" ( value ) : :
"memory"
3066static inline uint32_t _AArch32_Read_jmcr(
void )
3071 "mrc p14, 7, %0, c2, c0, 0" :
"=&r" ( value ) : :
"memory"
3077static inline void _AArch32_Write_jmcr( uint32_t value )
3080 "mcr p14, 7, %0, c2, c0, 0" : :
"r" ( value ) :
"memory"
3086static inline uint32_t _AArch32_Read_joscr(
void )
3091 "mrc p14, 7, %0, c1, c0, 0" :
"=&r" ( value ) : :
"memory"
3097static inline void _AArch32_Write_joscr( uint32_t value )
3100 "mcr p14, 7, %0, c1, c0, 0" : :
"r" ( value ) :
"memory"
3106static inline uint32_t _AArch32_Read_mair0(
void )
3111 "mrc p15, 0, %0, c10, c2, 0" :
"=&r" ( value ) : :
"memory"
3117static inline void _AArch32_Write_mair0( uint32_t value )
3120 "mcr p15, 0, %0, c10, c2, 0" : :
"r" ( value ) :
"memory"
3126static inline uint32_t _AArch32_Read_mair1(
void )
3131 "mrc p15, 0, %0, c10, c2, 1" :
"=&r" ( value ) : :
"memory"
3137static inline void _AArch32_Write_mair1( uint32_t value )
3140 "mcr p15, 0, %0, c10, c2, 1" : :
"r" ( value ) :
"memory"
3146#define AARCH32_MIDR_REVISION( _val ) ( ( _val ) << 0 )
3147#define AARCH32_MIDR_REVISION_SHIFT 0
3148#define AARCH32_MIDR_REVISION_MASK 0xfU
3149#define AARCH32_MIDR_REVISION_GET( _reg ) \
3150 ( ( ( _reg ) >> 0 ) & 0xfU )
3152#define AARCH32_MIDR_PARTNUM( _val ) ( ( _val ) << 4 )
3153#define AARCH32_MIDR_PARTNUM_SHIFT 4
3154#define AARCH32_MIDR_PARTNUM_MASK 0xfff0U
3155#define AARCH32_MIDR_PARTNUM_GET( _reg ) \
3156 ( ( ( _reg ) >> 4 ) & 0xfffU )
3158#define AARCH32_MIDR_ARCHITECTURE( _val ) ( ( _val ) << 16 )
3159#define AARCH32_MIDR_ARCHITECTURE_SHIFT 16
3160#define AARCH32_MIDR_ARCHITECTURE_MASK 0xf0000U
3161#define AARCH32_MIDR_ARCHITECTURE_GET( _reg ) \
3162 ( ( ( _reg ) >> 16 ) & 0xfU )
3164#define AARCH32_MIDR_VARIANT( _val ) ( ( _val ) << 20 )
3165#define AARCH32_MIDR_VARIANT_SHIFT 20
3166#define AARCH32_MIDR_VARIANT_MASK 0xf00000U
3167#define AARCH32_MIDR_VARIANT_GET( _reg ) \
3168 ( ( ( _reg ) >> 20 ) & 0xfU )
3170#define AARCH32_MIDR_IMPLEMENTER( _val ) ( ( _val ) << 24 )
3171#define AARCH32_MIDR_IMPLEMENTER_SHIFT 24
3172#define AARCH32_MIDR_IMPLEMENTER_MASK 0xff000000U
3173#define AARCH32_MIDR_IMPLEMENTER_GET( _reg ) \
3174 ( ( ( _reg ) >> 24 ) & 0xffU )
3176static inline uint32_t _AArch32_Read_midr(
void )
3181 "mrc p15, 0, %0, c0, c0, 0" :
"=&r" ( value ) : :
"memory"
3189#define AARCH32_MPIDR_AFF0( _val ) ( ( _val ) << 0 )
3190#define AARCH32_MPIDR_AFF0_SHIFT 0
3191#define AARCH32_MPIDR_AFF0_MASK 0xffU
3192#define AARCH32_MPIDR_AFF0_GET( _reg ) \
3193 ( ( ( _reg ) >> 0 ) & 0xffU )
3195#define AARCH32_MPIDR_AFF1( _val ) ( ( _val ) << 8 )
3196#define AARCH32_MPIDR_AFF1_SHIFT 8
3197#define AARCH32_MPIDR_AFF1_MASK 0xff00U
3198#define AARCH32_MPIDR_AFF1_GET( _reg ) \
3199 ( ( ( _reg ) >> 8 ) & 0xffU )
3201#define AARCH32_MPIDR_AFF2( _val ) ( ( _val ) << 16 )
3202#define AARCH32_MPIDR_AFF2_SHIFT 16
3203#define AARCH32_MPIDR_AFF2_MASK 0xff0000U
3204#define AARCH32_MPIDR_AFF2_GET( _reg ) \
3205 ( ( ( _reg ) >> 16 ) & 0xffU )
3207#define AARCH32_MPIDR_MT 0x1000000U
3209#define AARCH32_MPIDR_U 0x40000000U
3211#define AARCH32_MPIDR_M 0x80000000U
3213static inline uint32_t _AArch32_Read_mpidr(
void )
3218 "mrc p15, 0, %0, c0, c0, 5" :
"=&r" ( value ) : :
"memory"
3226#define AARCH32_MVBAR_RESERVED( _val ) ( ( _val ) << 0 )
3227#define AARCH32_MVBAR_RESERVED_SHIFT 0
3228#define AARCH32_MVBAR_RESERVED_MASK 0x1fU
3229#define AARCH32_MVBAR_RESERVED_GET( _reg ) \
3230 ( ( ( _reg ) >> 0 ) & 0x1fU )
3232static inline uint32_t _AArch32_Read_mvbar(
void )
3237 "mrc p15, 0, %0, c12, c0, 1" :
"=&r" ( value ) : :
"memory"
3243static inline void _AArch32_Write_mvbar( uint32_t value )
3246 "mcr p15, 0, %0, c12, c0, 1" : :
"r" ( value ) :
"memory"
3252#define AARCH32_MVFR0_SIMDREG( _val ) ( ( _val ) << 0 )
3253#define AARCH32_MVFR0_SIMDREG_SHIFT 0
3254#define AARCH32_MVFR0_SIMDREG_MASK 0xfU
3255#define AARCH32_MVFR0_SIMDREG_GET( _reg ) \
3256 ( ( ( _reg ) >> 0 ) & 0xfU )
3258#define AARCH32_MVFR0_FPSP( _val ) ( ( _val ) << 4 )
3259#define AARCH32_MVFR0_FPSP_SHIFT 4
3260#define AARCH32_MVFR0_FPSP_MASK 0xf0U
3261#define AARCH32_MVFR0_FPSP_GET( _reg ) \
3262 ( ( ( _reg ) >> 4 ) & 0xfU )
3264#define AARCH32_MVFR0_FPDP( _val ) ( ( _val ) << 8 )
3265#define AARCH32_MVFR0_FPDP_SHIFT 8
3266#define AARCH32_MVFR0_FPDP_MASK 0xf00U
3267#define AARCH32_MVFR0_FPDP_GET( _reg ) \
3268 ( ( ( _reg ) >> 8 ) & 0xfU )
3270#define AARCH32_MVFR0_FPTRAP( _val ) ( ( _val ) << 12 )
3271#define AARCH32_MVFR0_FPTRAP_SHIFT 12
3272#define AARCH32_MVFR0_FPTRAP_MASK 0xf000U
3273#define AARCH32_MVFR0_FPTRAP_GET( _reg ) \
3274 ( ( ( _reg ) >> 12 ) & 0xfU )
3276#define AARCH32_MVFR0_FPDIVIDE( _val ) ( ( _val ) << 16 )
3277#define AARCH32_MVFR0_FPDIVIDE_SHIFT 16
3278#define AARCH32_MVFR0_FPDIVIDE_MASK 0xf0000U
3279#define AARCH32_MVFR0_FPDIVIDE_GET( _reg ) \
3280 ( ( ( _reg ) >> 16 ) & 0xfU )
3282#define AARCH32_MVFR0_FPSQRT( _val ) ( ( _val ) << 20 )
3283#define AARCH32_MVFR0_FPSQRT_SHIFT 20
3284#define AARCH32_MVFR0_FPSQRT_MASK 0xf00000U
3285#define AARCH32_MVFR0_FPSQRT_GET( _reg ) \
3286 ( ( ( _reg ) >> 20 ) & 0xfU )
3288#define AARCH32_MVFR0_FPSHVEC( _val ) ( ( _val ) << 24 )
3289#define AARCH32_MVFR0_FPSHVEC_SHIFT 24
3290#define AARCH32_MVFR0_FPSHVEC_MASK 0xf000000U
3291#define AARCH32_MVFR0_FPSHVEC_GET( _reg ) \
3292 ( ( ( _reg ) >> 24 ) & 0xfU )
3294#define AARCH32_MVFR0_FPROUND( _val ) ( ( _val ) << 28 )
3295#define AARCH32_MVFR0_FPROUND_SHIFT 28
3296#define AARCH32_MVFR0_FPROUND_MASK 0xf0000000U
3297#define AARCH32_MVFR0_FPROUND_GET( _reg ) \
3298 ( ( ( _reg ) >> 28 ) & 0xfU )
3302#define AARCH32_MVFR1_FPFTZ( _val ) ( ( _val ) << 0 )
3303#define AARCH32_MVFR1_FPFTZ_SHIFT 0
3304#define AARCH32_MVFR1_FPFTZ_MASK 0xfU
3305#define AARCH32_MVFR1_FPFTZ_GET( _reg ) \
3306 ( ( ( _reg ) >> 0 ) & 0xfU )
3308#define AARCH32_MVFR1_FPDNAN( _val ) ( ( _val ) << 4 )
3309#define AARCH32_MVFR1_FPDNAN_SHIFT 4
3310#define AARCH32_MVFR1_FPDNAN_MASK 0xf0U
3311#define AARCH32_MVFR1_FPDNAN_GET( _reg ) \
3312 ( ( ( _reg ) >> 4 ) & 0xfU )
3314#define AARCH32_MVFR1_SIMDLS( _val ) ( ( _val ) << 8 )
3315#define AARCH32_MVFR1_SIMDLS_SHIFT 8
3316#define AARCH32_MVFR1_SIMDLS_MASK 0xf00U
3317#define AARCH32_MVFR1_SIMDLS_GET( _reg ) \
3318 ( ( ( _reg ) >> 8 ) & 0xfU )
3320#define AARCH32_MVFR1_SIMDINT( _val ) ( ( _val ) << 12 )
3321#define AARCH32_MVFR1_SIMDINT_SHIFT 12
3322#define AARCH32_MVFR1_SIMDINT_MASK 0xf000U
3323#define AARCH32_MVFR1_SIMDINT_GET( _reg ) \
3324 ( ( ( _reg ) >> 12 ) & 0xfU )
3326#define AARCH32_MVFR1_SIMDSP( _val ) ( ( _val ) << 16 )
3327#define AARCH32_MVFR1_SIMDSP_SHIFT 16
3328#define AARCH32_MVFR1_SIMDSP_MASK 0xf0000U
3329#define AARCH32_MVFR1_SIMDSP_GET( _reg ) \
3330 ( ( ( _reg ) >> 16 ) & 0xfU )
3332#define AARCH32_MVFR1_SIMDHP( _val ) ( ( _val ) << 20 )
3333#define AARCH32_MVFR1_SIMDHP_SHIFT 20
3334#define AARCH32_MVFR1_SIMDHP_MASK 0xf00000U
3335#define AARCH32_MVFR1_SIMDHP_GET( _reg ) \
3336 ( ( ( _reg ) >> 20 ) & 0xfU )
3338#define AARCH32_MVFR1_FPHP( _val ) ( ( _val ) << 24 )
3339#define AARCH32_MVFR1_FPHP_SHIFT 24
3340#define AARCH32_MVFR1_FPHP_MASK 0xf000000U
3341#define AARCH32_MVFR1_FPHP_GET( _reg ) \
3342 ( ( ( _reg ) >> 24 ) & 0xfU )
3344#define AARCH32_MVFR1_SIMDFMAC( _val ) ( ( _val ) << 28 )
3345#define AARCH32_MVFR1_SIMDFMAC_SHIFT 28
3346#define AARCH32_MVFR1_SIMDFMAC_MASK 0xf0000000U
3347#define AARCH32_MVFR1_SIMDFMAC_GET( _reg ) \
3348 ( ( ( _reg ) >> 28 ) & 0xfU )
3352#define AARCH32_MVFR2_SIMDMISC( _val ) ( ( _val ) << 0 )
3353#define AARCH32_MVFR2_SIMDMISC_SHIFT 0
3354#define AARCH32_MVFR2_SIMDMISC_MASK 0xfU
3355#define AARCH32_MVFR2_SIMDMISC_GET( _reg ) \
3356 ( ( ( _reg ) >> 0 ) & 0xfU )
3358#define AARCH32_MVFR2_FPMISC( _val ) ( ( _val ) << 4 )
3359#define AARCH32_MVFR2_FPMISC_SHIFT 4
3360#define AARCH32_MVFR2_FPMISC_MASK 0xf0U
3361#define AARCH32_MVFR2_FPMISC_GET( _reg ) \
3362 ( ( ( _reg ) >> 4 ) & 0xfU )
3366static inline uint32_t _AArch32_Read_nmrr(
void )
3371 "mrc p15, 0, %0, c10, c2, 1" :
"=&r" ( value ) : :
"memory"
3377static inline void _AArch32_Write_nmrr( uint32_t value )
3380 "mcr p15, 0, %0, c10, c2, 1" : :
"r" ( value ) :
"memory"
3386#define AARCH32_NSACR_CP10 0x400U
3388#define AARCH32_NSACR_CP11 0x800U
3390#define AARCH32_NSACR_NSASEDIS 0x8000U
3392#define AARCH32_NSACR_NSTRCDIS 0x100000U
3394static inline uint32_t _AArch32_Read_nsacr(
void )
3399 "mrc p15, 0, %0, c1, c1, 2" :
"=&r" ( value ) : :
"memory"
3405static inline void _AArch32_Write_nsacr( uint32_t value )
3408 "mcr p15, 0, %0, c1, c1, 2" : :
"r" ( value ) :
"memory"
3414#define AARCH32_PAR_F 0x1U
3416#define AARCH32_PAR_SS 0x2U
3418#define AARCH32_PAR_FS_4_0( _val ) ( ( _val ) << 1 )
3419#define AARCH32_PAR_FS_4_0_SHIFT 1
3420#define AARCH32_PAR_FS_4_0_MASK 0x3eU
3421#define AARCH32_PAR_FS_4_0_GET( _reg ) \
3422 ( ( ( _reg ) >> 1 ) & 0x1fU )
3424#define AARCH32_PAR_FST( _val ) ( ( _val ) << 1 )
3425#define AARCH32_PAR_FST_SHIFT 1
3426#define AARCH32_PAR_FST_MASK 0x7eU
3427#define AARCH32_PAR_FST_GET( _reg ) \
3428 ( ( ( _reg ) >> 1 ) & 0x3fU )
3430#define AARCH32_PAR_OUTER_1_0( _val ) ( ( _val ) << 2 )
3431#define AARCH32_PAR_OUTER_1_0_SHIFT 2
3432#define AARCH32_PAR_OUTER_1_0_MASK 0xcU
3433#define AARCH32_PAR_OUTER_1_0_GET( _reg ) \
3434 ( ( ( _reg ) >> 2 ) & 0x3U )
3436#define AARCH32_PAR_INNER_2_0( _val ) ( ( _val ) << 4 )
3437#define AARCH32_PAR_INNER_2_0_SHIFT 4
3438#define AARCH32_PAR_INNER_2_0_MASK 0x70U
3439#define AARCH32_PAR_INNER_2_0_GET( _reg ) \
3440 ( ( ( _reg ) >> 4 ) & 0x7U )
3442#define AARCH32_PAR_FS_5 0x40U
3444#define AARCH32_PAR_SH_0 0x80U
3446#define AARCH32_PAR_SH_1( _val ) ( ( _val ) << 7 )
3447#define AARCH32_PAR_SH_SHIFT_1 7
3448#define AARCH32_PAR_SH_MASK_1 0x180U
3449#define AARCH32_PAR_SH_GET_1( _reg ) \
3450 ( ( ( _reg ) >> 7 ) & 0x3U )
3452#define AARCH32_PAR_S2WLK 0x100U
3454#define AARCH32_PAR_FSTAGE 0x200U
3456#define AARCH32_PAR_NS 0x200U
3458#define AARCH32_PAR_NOS 0x400U
3460#define AARCH32_PAR_LPAE 0x800U
3462#define AARCH32_PAR_PA_0( _val ) ( ( _val ) << 12 )
3463#define AARCH32_PAR_PA_SHIFT_0 12
3464#define AARCH32_PAR_PA_MASK_0 0xfffff000U
3465#define AARCH32_PAR_PA_GET_0( _reg ) \
3466 ( ( ( _reg ) >> 12 ) & 0xfffffU )
3468#define AARCH32_PAR_PA_1( _val ) ( ( _val ) << 12 )
3469#define AARCH32_PAR_PA_SHIFT_1 12
3470#define AARCH32_PAR_PA_MASK_1 0xfffffff000ULL
3471#define AARCH32_PAR_PA_GET_1( _reg ) \
3472 ( ( ( _reg ) >> 12 ) & 0xfffffffULL )
3474#define AARCH32_PAR_ATTR( _val ) ( ( _val ) << 56 )
3475#define AARCH32_PAR_ATTR_SHIFT 56
3476#define AARCH32_PAR_ATTR_MASK 0xff00000000000000ULL
3477#define AARCH32_PAR_ATTR_GET( _reg ) \
3478 ( ( ( _reg ) >> 56 ) & 0xffULL )
3480static inline uint32_t _AArch32_Read_32_par(
void )
3485 "mrc p15, 0, %0, c7, c4, 0" :
"=&r" ( value ) : :
"memory"
3491static inline void _AArch32_Write_32_par( uint32_t value )
3494 "mcr p15, 0, %0, c7, c4, 0" : :
"r" ( value ) :
"memory"
3500static inline uint64_t _AArch32_Read_64_par(
void )
3505 "mrrc p15, 0, %Q0, %R0, c7" :
"=&r" ( value ) : :
"memory"
3511static inline void _AArch32_Write_64_par( uint64_t value )
3514 "mcrr p15, 0, %Q0, %R0, c7" : :
"r" ( value ) :
"memory"
3520#define AARCH32_PRRR_DS0 0x10000U
3522#define AARCH32_PRRR_DS1 0x20000U
3524#define AARCH32_PRRR_NS0 0x40000U
3526#define AARCH32_PRRR_NS1 0x80000U
3528static inline uint32_t _AArch32_Read_prrr(
void )
3533 "mrc p15, 0, %0, c10, c2, 0" :
"=&r" ( value ) : :
"memory"
3539static inline void _AArch32_Write_prrr( uint32_t value )
3542 "mcr p15, 0, %0, c10, c2, 0" : :
"r" ( value ) :
"memory"
3548static inline uint32_t _AArch32_Read_revidr(
void )
3553 "mrc p15, 0, %0, c0, c0, 6" :
"=&r" ( value ) : :
"memory"
3561#define AARCH32_RMR_AA64 0x1U
3563#define AARCH32_RMR_RR 0x2U
3565static inline uint32_t _AArch32_Read_rmr(
void )
3570 "mrc p15, 0, %0, c12, c0, 2" :
"=&r" ( value ) : :
"memory"
3576static inline void _AArch32_Write_rmr( uint32_t value )
3579 "mcr p15, 0, %0, c12, c0, 2" : :
"r" ( value ) :
"memory"
3585static inline uint32_t _AArch32_Read_rvbar(
void )
3590 "mrc p15, 0, %0, c12, c0, 1" :
"=&r" ( value ) : :
"memory"
3598#define AARCH32_SCR_NS 0x1U
3600#define AARCH32_SCR_IRQ 0x2U
3602#define AARCH32_SCR_FIQ 0x4U
3604#define AARCH32_SCR_EA 0x8U
3606#define AARCH32_SCR_FW 0x10U
3608#define AARCH32_SCR_AW 0x20U
3610#define AARCH32_SCR_NET 0x40U
3612#define AARCH32_SCR_SCD 0x80U
3614#define AARCH32_SCR_HCE 0x100U
3616#define AARCH32_SCR_SIF 0x200U
3618#define AARCH32_SCR_TWI 0x1000U
3620#define AARCH32_SCR_TWE 0x2000U
3622#define AARCH32_SCR_TERR 0x8000U
3624static inline uint32_t _AArch32_Read_scr(
void )
3629 "mrc p15, 0, %0, c1, c1, 0" :
"=&r" ( value ) : :
"memory"
3635static inline void _AArch32_Write_scr( uint32_t value )
3638 "mcr p15, 0, %0, c1, c1, 0" : :
"r" ( value ) :
"memory"
3644#define AARCH32_SCTLR_M 0x1U
3646#define AARCH32_SCTLR_A 0x2U
3648#define AARCH32_SCTLR_C 0x4U
3650#define AARCH32_SCTLR_NTLSMD 0x8U
3652#define AARCH32_SCTLR_LSMAOE 0x10U
3654#define AARCH32_SCTLR_CP15BEN 0x20U
3656#define AARCH32_SCTLR_UNK 0x40U
3658#define AARCH32_SCTLR_ITD 0x80U
3660#define AARCH32_SCTLR_SED 0x100U
3662#define AARCH32_SCTLR_ENRCTX 0x400U
3664#define AARCH32_SCTLR_I 0x1000U
3666#define AARCH32_SCTLR_V 0x2000U
3668#define AARCH32_SCTLR_NTWI 0x10000U
3670#define AARCH32_SCTLR_BR 0x20000U
3672#define AARCH32_SCTLR_NTWE 0x40000U
3674#define AARCH32_SCTLR_WXN 0x80000U
3676#define AARCH32_SCTLR_UWXN 0x100000U
3678#define AARCH32_SCTLR_FI 0x200000U
3680#define AARCH32_SCTLR_SPAN 0x800000U
3682#define AARCH32_SCTLR_EE 0x2000000U
3684#define AARCH32_SCTLR_TRE 0x10000000U
3686#define AARCH32_SCTLR_AFE 0x20000000U
3688#define AARCH32_SCTLR_TE 0x40000000U
3690#define AARCH32_SCTLR_DSSBS 0x80000000U
3692static inline uint32_t _AArch32_Read_sctlr(
void )
3697 "mrc p15, 0, %0, c1, c0, 0" :
"=&r" ( value ) : :
"memory"
3703static inline void _AArch32_Write_sctlr( uint32_t value )
3706 "mcr p15, 0, %0, c1, c0, 0" : :
"r" ( value ) :
"memory"
3712#define AARCH32_SPSR_M_4_0( _val ) ( ( _val ) << 0 )
3713#define AARCH32_SPSR_M_4_0_SHIFT 0
3714#define AARCH32_SPSR_M_4_0_MASK 0x1fU
3715#define AARCH32_SPSR_M_4_0_GET( _reg ) \
3716 ( ( ( _reg ) >> 0 ) & 0x1fU )
3718#define AARCH32_SPSR_T 0x20U
3720#define AARCH32_SPSR_F 0x40U
3722#define AARCH32_SPSR_I 0x80U
3724#define AARCH32_SPSR_A 0x100U
3726#define AARCH32_SPSR_E 0x200U
3728#define AARCH32_SPSR_IT_7_2( _val ) ( ( _val ) << 10 )
3729#define AARCH32_SPSR_IT_7_2_SHIFT 10
3730#define AARCH32_SPSR_IT_7_2_MASK 0xfc00U
3731#define AARCH32_SPSR_IT_7_2_GET( _reg ) \
3732 ( ( ( _reg ) >> 10 ) & 0x3fU )
3734#define AARCH32_SPSR_GE( _val ) ( ( _val ) << 16 )
3735#define AARCH32_SPSR_GE_SHIFT 16
3736#define AARCH32_SPSR_GE_MASK 0xf0000U
3737#define AARCH32_SPSR_GE_GET( _reg ) \
3738 ( ( ( _reg ) >> 16 ) & 0xfU )
3740#define AARCH32_SPSR_IL 0x100000U
3742#define AARCH32_SPSR_DIT 0x200000U
3744#define AARCH32_SPSR_PAN 0x400000U
3746#define AARCH32_SPSR_SSBS 0x800000U
3748#define AARCH32_SPSR_J 0x1000000U
3750#define AARCH32_SPSR_IT_1_0( _val ) ( ( _val ) << 25 )
3751#define AARCH32_SPSR_IT_1_0_SHIFT 25
3752#define AARCH32_SPSR_IT_1_0_MASK 0x6000000U
3753#define AARCH32_SPSR_IT_1_0_GET( _reg ) \
3754 ( ( ( _reg ) >> 25 ) & 0x3U )
3756#define AARCH32_SPSR_Q 0x8000000U
3758#define AARCH32_SPSR_V 0x10000000U
3760#define AARCH32_SPSR_C 0x20000000U
3762#define AARCH32_SPSR_Z 0x40000000U
3764#define AARCH32_SPSR_N 0x80000000U
3768#define AARCH32_SPSR_ABT_M_4_0( _val ) ( ( _val ) << 0 )
3769#define AARCH32_SPSR_ABT_M_4_0_SHIFT 0
3770#define AARCH32_SPSR_ABT_M_4_0_MASK 0x1fU
3771#define AARCH32_SPSR_ABT_M_4_0_GET( _reg ) \
3772 ( ( ( _reg ) >> 0 ) & 0x1fU )
3774#define AARCH32_SPSR_ABT_T 0x20U
3776#define AARCH32_SPSR_ABT_F 0x40U
3778#define AARCH32_SPSR_ABT_I 0x80U
3780#define AARCH32_SPSR_ABT_A 0x100U
3782#define AARCH32_SPSR_ABT_E 0x200U
3784#define AARCH32_SPSR_ABT_IT_7_2( _val ) ( ( _val ) << 10 )
3785#define AARCH32_SPSR_ABT_IT_7_2_SHIFT 10
3786#define AARCH32_SPSR_ABT_IT_7_2_MASK 0xfc00U
3787#define AARCH32_SPSR_ABT_IT_7_2_GET( _reg ) \
3788 ( ( ( _reg ) >> 10 ) & 0x3fU )
3790#define AARCH32_SPSR_ABT_GE( _val ) ( ( _val ) << 16 )
3791#define AARCH32_SPSR_ABT_GE_SHIFT 16
3792#define AARCH32_SPSR_ABT_GE_MASK 0xf0000U
3793#define AARCH32_SPSR_ABT_GE_GET( _reg ) \
3794 ( ( ( _reg ) >> 16 ) & 0xfU )
3796#define AARCH32_SPSR_ABT_IL 0x100000U
3798#define AARCH32_SPSR_ABT_DIT 0x200000U
3800#define AARCH32_SPSR_ABT_PAN 0x400000U
3802#define AARCH32_SPSR_ABT_SSBS 0x800000U
3804#define AARCH32_SPSR_ABT_J 0x1000000U
3806#define AARCH32_SPSR_ABT_IT_1_0( _val ) ( ( _val ) << 25 )
3807#define AARCH32_SPSR_ABT_IT_1_0_SHIFT 25
3808#define AARCH32_SPSR_ABT_IT_1_0_MASK 0x6000000U
3809#define AARCH32_SPSR_ABT_IT_1_0_GET( _reg ) \
3810 ( ( ( _reg ) >> 25 ) & 0x3U )
3812#define AARCH32_SPSR_ABT_Q 0x8000000U
3814#define AARCH32_SPSR_ABT_V 0x10000000U
3816#define AARCH32_SPSR_ABT_C 0x20000000U
3818#define AARCH32_SPSR_ABT_Z 0x40000000U
3820#define AARCH32_SPSR_ABT_N 0x80000000U
3824#define AARCH32_SPSR_FIQ_M_4_0( _val ) ( ( _val ) << 0 )
3825#define AARCH32_SPSR_FIQ_M_4_0_SHIFT 0
3826#define AARCH32_SPSR_FIQ_M_4_0_MASK 0x1fU
3827#define AARCH32_SPSR_FIQ_M_4_0_GET( _reg ) \
3828 ( ( ( _reg ) >> 0 ) & 0x1fU )
3830#define AARCH32_SPSR_FIQ_T 0x20U
3832#define AARCH32_SPSR_FIQ_F 0x40U
3834#define AARCH32_SPSR_FIQ_I 0x80U
3836#define AARCH32_SPSR_FIQ_A 0x100U
3838#define AARCH32_SPSR_FIQ_E 0x200U
3840#define AARCH32_SPSR_FIQ_IT_7_2( _val ) ( ( _val ) << 10 )
3841#define AARCH32_SPSR_FIQ_IT_7_2_SHIFT 10
3842#define AARCH32_SPSR_FIQ_IT_7_2_MASK 0xfc00U
3843#define AARCH32_SPSR_FIQ_IT_7_2_GET( _reg ) \
3844 ( ( ( _reg ) >> 10 ) & 0x3fU )
3846#define AARCH32_SPSR_FIQ_GE( _val ) ( ( _val ) << 16 )
3847#define AARCH32_SPSR_FIQ_GE_SHIFT 16
3848#define AARCH32_SPSR_FIQ_GE_MASK 0xf0000U
3849#define AARCH32_SPSR_FIQ_GE_GET( _reg ) \
3850 ( ( ( _reg ) >> 16 ) & 0xfU )
3852#define AARCH32_SPSR_FIQ_IL 0x100000U
3854#define AARCH32_SPSR_FIQ_DIT 0x200000U
3856#define AARCH32_SPSR_FIQ_PAN 0x400000U
3858#define AARCH32_SPSR_FIQ_SSBS 0x800000U
3860#define AARCH32_SPSR_FIQ_J 0x1000000U
3862#define AARCH32_SPSR_FIQ_IT_1_0( _val ) ( ( _val ) << 25 )
3863#define AARCH32_SPSR_FIQ_IT_1_0_SHIFT 25
3864#define AARCH32_SPSR_FIQ_IT_1_0_MASK 0x6000000U
3865#define AARCH32_SPSR_FIQ_IT_1_0_GET( _reg ) \
3866 ( ( ( _reg ) >> 25 ) & 0x3U )
3868#define AARCH32_SPSR_FIQ_Q 0x8000000U
3870#define AARCH32_SPSR_FIQ_V 0x10000000U
3872#define AARCH32_SPSR_FIQ_C 0x20000000U
3874#define AARCH32_SPSR_FIQ_Z 0x40000000U
3876#define AARCH32_SPSR_FIQ_N 0x80000000U
3880#define AARCH32_SPSR_HYP_M_4_0( _val ) ( ( _val ) << 0 )
3881#define AARCH32_SPSR_HYP_M_4_0_SHIFT 0
3882#define AARCH32_SPSR_HYP_M_4_0_MASK 0x1fU
3883#define AARCH32_SPSR_HYP_M_4_0_GET( _reg ) \
3884 ( ( ( _reg ) >> 0 ) & 0x1fU )
3886#define AARCH32_SPSR_HYP_T 0x20U
3888#define AARCH32_SPSR_HYP_F 0x40U
3890#define AARCH32_SPSR_HYP_I 0x80U
3892#define AARCH32_SPSR_HYP_A 0x100U
3894#define AARCH32_SPSR_HYP_E 0x200U
3896#define AARCH32_SPSR_HYP_IT_7_2( _val ) ( ( _val ) << 10 )
3897#define AARCH32_SPSR_HYP_IT_7_2_SHIFT 10
3898#define AARCH32_SPSR_HYP_IT_7_2_MASK 0xfc00U
3899#define AARCH32_SPSR_HYP_IT_7_2_GET( _reg ) \
3900 ( ( ( _reg ) >> 10 ) & 0x3fU )
3902#define AARCH32_SPSR_HYP_GE( _val ) ( ( _val ) << 16 )
3903#define AARCH32_SPSR_HYP_GE_SHIFT 16
3904#define AARCH32_SPSR_HYP_GE_MASK 0xf0000U
3905#define AARCH32_SPSR_HYP_GE_GET( _reg ) \
3906 ( ( ( _reg ) >> 16 ) & 0xfU )
3908#define AARCH32_SPSR_HYP_IL 0x100000U
3910#define AARCH32_SPSR_HYP_DIT 0x200000U
3912#define AARCH32_SPSR_HYP_PAN 0x400000U
3914#define AARCH32_SPSR_HYP_SSBS 0x800000U
3916#define AARCH32_SPSR_HYP_J 0x1000000U
3918#define AARCH32_SPSR_HYP_IT_1_0( _val ) ( ( _val ) << 25 )
3919#define AARCH32_SPSR_HYP_IT_1_0_SHIFT 25
3920#define AARCH32_SPSR_HYP_IT_1_0_MASK 0x6000000U
3921#define AARCH32_SPSR_HYP_IT_1_0_GET( _reg ) \
3922 ( ( ( _reg ) >> 25 ) & 0x3U )
3924#define AARCH32_SPSR_HYP_Q 0x8000000U
3926#define AARCH32_SPSR_HYP_V 0x10000000U
3928#define AARCH32_SPSR_HYP_C 0x20000000U
3930#define AARCH32_SPSR_HYP_Z 0x40000000U
3932#define AARCH32_SPSR_HYP_N 0x80000000U
3936#define AARCH32_SPSR_IRQ_M_4_0( _val ) ( ( _val ) << 0 )
3937#define AARCH32_SPSR_IRQ_M_4_0_SHIFT 0
3938#define AARCH32_SPSR_IRQ_M_4_0_MASK 0x1fU
3939#define AARCH32_SPSR_IRQ_M_4_0_GET( _reg ) \
3940 ( ( ( _reg ) >> 0 ) & 0x1fU )
3942#define AARCH32_SPSR_IRQ_T 0x20U
3944#define AARCH32_SPSR_IRQ_F 0x40U
3946#define AARCH32_SPSR_IRQ_I 0x80U
3948#define AARCH32_SPSR_IRQ_A 0x100U
3950#define AARCH32_SPSR_IRQ_E 0x200U
3952#define AARCH32_SPSR_IRQ_IT_7_2( _val ) ( ( _val ) << 10 )
3953#define AARCH32_SPSR_IRQ_IT_7_2_SHIFT 10
3954#define AARCH32_SPSR_IRQ_IT_7_2_MASK 0xfc00U
3955#define AARCH32_SPSR_IRQ_IT_7_2_GET( _reg ) \
3956 ( ( ( _reg ) >> 10 ) & 0x3fU )
3958#define AARCH32_SPSR_IRQ_GE( _val ) ( ( _val ) << 16 )
3959#define AARCH32_SPSR_IRQ_GE_SHIFT 16
3960#define AARCH32_SPSR_IRQ_GE_MASK 0xf0000U
3961#define AARCH32_SPSR_IRQ_GE_GET( _reg ) \
3962 ( ( ( _reg ) >> 16 ) & 0xfU )
3964#define AARCH32_SPSR_IRQ_IL 0x100000U
3966#define AARCH32_SPSR_IRQ_DIT 0x200000U
3968#define AARCH32_SPSR_IRQ_PAN 0x400000U
3970#define AARCH32_SPSR_IRQ_SSBS 0x800000U
3972#define AARCH32_SPSR_IRQ_J 0x1000000U
3974#define AARCH32_SPSR_IRQ_IT_1_0( _val ) ( ( _val ) << 25 )
3975#define AARCH32_SPSR_IRQ_IT_1_0_SHIFT 25
3976#define AARCH32_SPSR_IRQ_IT_1_0_MASK 0x6000000U
3977#define AARCH32_SPSR_IRQ_IT_1_0_GET( _reg ) \
3978 ( ( ( _reg ) >> 25 ) & 0x3U )
3980#define AARCH32_SPSR_IRQ_Q 0x8000000U
3982#define AARCH32_SPSR_IRQ_V 0x10000000U
3984#define AARCH32_SPSR_IRQ_C 0x20000000U
3986#define AARCH32_SPSR_IRQ_Z 0x40000000U
3988#define AARCH32_SPSR_IRQ_N 0x80000000U
3992#define AARCH32_SPSR_MON_M_4_0( _val ) ( ( _val ) << 0 )
3993#define AARCH32_SPSR_MON_M_4_0_SHIFT 0
3994#define AARCH32_SPSR_MON_M_4_0_MASK 0x1fU
3995#define AARCH32_SPSR_MON_M_4_0_GET( _reg ) \
3996 ( ( ( _reg ) >> 0 ) & 0x1fU )
3998#define AARCH32_SPSR_MON_T 0x20U
4000#define AARCH32_SPSR_MON_F 0x40U
4002#define AARCH32_SPSR_MON_I 0x80U
4004#define AARCH32_SPSR_MON_A 0x100U
4006#define AARCH32_SPSR_MON_E 0x200U
4008#define AARCH32_SPSR_MON_IT_7_2( _val ) ( ( _val ) << 10 )
4009#define AARCH32_SPSR_MON_IT_7_2_SHIFT 10
4010#define AARCH32_SPSR_MON_IT_7_2_MASK 0xfc00U
4011#define AARCH32_SPSR_MON_IT_7_2_GET( _reg ) \
4012 ( ( ( _reg ) >> 10 ) & 0x3fU )
4014#define AARCH32_SPSR_MON_GE( _val ) ( ( _val ) << 16 )
4015#define AARCH32_SPSR_MON_GE_SHIFT 16
4016#define AARCH32_SPSR_MON_GE_MASK 0xf0000U
4017#define AARCH32_SPSR_MON_GE_GET( _reg ) \
4018 ( ( ( _reg ) >> 16 ) & 0xfU )
4020#define AARCH32_SPSR_MON_IL 0x100000U
4022#define AARCH32_SPSR_MON_DIT 0x200000U
4024#define AARCH32_SPSR_MON_PAN 0x400000U
4026#define AARCH32_SPSR_MON_SSBS 0x800000U
4028#define AARCH32_SPSR_MON_J 0x1000000U
4030#define AARCH32_SPSR_MON_IT_1_0( _val ) ( ( _val ) << 25 )
4031#define AARCH32_SPSR_MON_IT_1_0_SHIFT 25
4032#define AARCH32_SPSR_MON_IT_1_0_MASK 0x6000000U
4033#define AARCH32_SPSR_MON_IT_1_0_GET( _reg ) \
4034 ( ( ( _reg ) >> 25 ) & 0x3U )
4036#define AARCH32_SPSR_MON_Q 0x8000000U
4038#define AARCH32_SPSR_MON_V 0x10000000U
4040#define AARCH32_SPSR_MON_C 0x20000000U
4042#define AARCH32_SPSR_MON_Z 0x40000000U
4044#define AARCH32_SPSR_MON_N 0x80000000U
4048#define AARCH32_SPSR_SVC_M_4_0( _val ) ( ( _val ) << 0 )
4049#define AARCH32_SPSR_SVC_M_4_0_SHIFT 0
4050#define AARCH32_SPSR_SVC_M_4_0_MASK 0x1fU
4051#define AARCH32_SPSR_SVC_M_4_0_GET( _reg ) \
4052 ( ( ( _reg ) >> 0 ) & 0x1fU )
4054#define AARCH32_SPSR_SVC_T 0x20U
4056#define AARCH32_SPSR_SVC_F 0x40U
4058#define AARCH32_SPSR_SVC_I 0x80U
4060#define AARCH32_SPSR_SVC_A 0x100U
4062#define AARCH32_SPSR_SVC_E 0x200U
4064#define AARCH32_SPSR_SVC_IT_7_2( _val ) ( ( _val ) << 10 )
4065#define AARCH32_SPSR_SVC_IT_7_2_SHIFT 10
4066#define AARCH32_SPSR_SVC_IT_7_2_MASK 0xfc00U
4067#define AARCH32_SPSR_SVC_IT_7_2_GET( _reg ) \
4068 ( ( ( _reg ) >> 10 ) & 0x3fU )
4070#define AARCH32_SPSR_SVC_GE( _val ) ( ( _val ) << 16 )
4071#define AARCH32_SPSR_SVC_GE_SHIFT 16
4072#define AARCH32_SPSR_SVC_GE_MASK 0xf0000U
4073#define AARCH32_SPSR_SVC_GE_GET( _reg ) \
4074 ( ( ( _reg ) >> 16 ) & 0xfU )
4076#define AARCH32_SPSR_SVC_IL 0x100000U
4078#define AARCH32_SPSR_SVC_DIT 0x200000U
4080#define AARCH32_SPSR_SVC_PAN 0x400000U
4082#define AARCH32_SPSR_SVC_SSBS 0x800000U
4084#define AARCH32_SPSR_SVC_J 0x1000000U
4086#define AARCH32_SPSR_SVC_IT_1_0( _val ) ( ( _val ) << 25 )
4087#define AARCH32_SPSR_SVC_IT_1_0_SHIFT 25
4088#define AARCH32_SPSR_SVC_IT_1_0_MASK 0x6000000U
4089#define AARCH32_SPSR_SVC_IT_1_0_GET( _reg ) \
4090 ( ( ( _reg ) >> 25 ) & 0x3U )
4092#define AARCH32_SPSR_SVC_Q 0x8000000U
4094#define AARCH32_SPSR_SVC_V 0x10000000U
4096#define AARCH32_SPSR_SVC_C 0x20000000U
4098#define AARCH32_SPSR_SVC_Z 0x40000000U
4100#define AARCH32_SPSR_SVC_N 0x80000000U
4104#define AARCH32_SPSR_UND_M_4_0( _val ) ( ( _val ) << 0 )
4105#define AARCH32_SPSR_UND_M_4_0_SHIFT 0
4106#define AARCH32_SPSR_UND_M_4_0_MASK 0x1fU
4107#define AARCH32_SPSR_UND_M_4_0_GET( _reg ) \
4108 ( ( ( _reg ) >> 0 ) & 0x1fU )
4110#define AARCH32_SPSR_UND_T 0x20U
4112#define AARCH32_SPSR_UND_F 0x40U
4114#define AARCH32_SPSR_UND_I 0x80U
4116#define AARCH32_SPSR_UND_A 0x100U
4118#define AARCH32_SPSR_UND_E 0x200U
4120#define AARCH32_SPSR_UND_IT_7_2( _val ) ( ( _val ) << 10 )
4121#define AARCH32_SPSR_UND_IT_7_2_SHIFT 10
4122#define AARCH32_SPSR_UND_IT_7_2_MASK 0xfc00U
4123#define AARCH32_SPSR_UND_IT_7_2_GET( _reg ) \
4124 ( ( ( _reg ) >> 10 ) & 0x3fU )
4126#define AARCH32_SPSR_UND_GE( _val ) ( ( _val ) << 16 )
4127#define AARCH32_SPSR_UND_GE_SHIFT 16
4128#define AARCH32_SPSR_UND_GE_MASK 0xf0000U
4129#define AARCH32_SPSR_UND_GE_GET( _reg ) \
4130 ( ( ( _reg ) >> 16 ) & 0xfU )
4132#define AARCH32_SPSR_UND_IL 0x100000U
4134#define AARCH32_SPSR_UND_DIT 0x200000U
4136#define AARCH32_SPSR_UND_PAN 0x400000U
4138#define AARCH32_SPSR_UND_SSBS 0x800000U
4140#define AARCH32_SPSR_UND_J 0x1000000U
4142#define AARCH32_SPSR_UND_IT_1_0( _val ) ( ( _val ) << 25 )
4143#define AARCH32_SPSR_UND_IT_1_0_SHIFT 25
4144#define AARCH32_SPSR_UND_IT_1_0_MASK 0x6000000U
4145#define AARCH32_SPSR_UND_IT_1_0_GET( _reg ) \
4146 ( ( ( _reg ) >> 25 ) & 0x3U )
4148#define AARCH32_SPSR_UND_Q 0x8000000U
4150#define AARCH32_SPSR_UND_V 0x10000000U
4152#define AARCH32_SPSR_UND_C 0x20000000U
4154#define AARCH32_SPSR_UND_Z 0x40000000U
4156#define AARCH32_SPSR_UND_N 0x80000000U
4160static inline uint32_t _AArch32_Read_tcmtr(
void )
4165 "mrc p15, 0, %0, c0, c0, 2" :
"=&r" ( value ) : :
"memory"
4173static inline void _AArch32_Write_tlbiall( uint32_t value )
4176 "mcr p15, 0, %0, c8, c7, 0" : :
"r" ( value ) :
"memory"
4182static inline void _AArch32_Write_tlbiallh( uint32_t value )
4185 "mcr p15, 4, %0, c8, c7, 0" : :
"r" ( value ) :
"memory"
4191static inline void _AArch32_Write_tlbiallhis( uint32_t value )
4194 "mcr p15, 4, %0, c8, c3, 0" : :
"r" ( value ) :
"memory"
4200static inline void _AArch32_Write_tlbiallis( uint32_t value )
4203 "mcr p15, 0, %0, c8, c3, 0" : :
"r" ( value ) :
"memory"
4209static inline void _AArch32_Write_tlbiallnsnh( uint32_t value )
4212 "mcr p15, 4, %0, c8, c7, 4" : :
"r" ( value ) :
"memory"
4218static inline void _AArch32_Write_tlbiallnsnhis( uint32_t value )
4221 "mcr p15, 4, %0, c8, c3, 4" : :
"r" ( value ) :
"memory"
4227#define AARCH32_TLBIASID_ASID( _val ) ( ( _val ) << 0 )
4228#define AARCH32_TLBIASID_ASID_SHIFT 0
4229#define AARCH32_TLBIASID_ASID_MASK 0xffU
4230#define AARCH32_TLBIASID_ASID_GET( _reg ) \
4231 ( ( ( _reg ) >> 0 ) & 0xffU )
4233static inline void _AArch32_Write_tlbiasid( uint32_t value )
4236 "mcr p15, 0, %0, c8, c7, 2" : :
"r" ( value ) :
"memory"
4242#define AARCH32_TLBIASIDIS_ASID( _val ) ( ( _val ) << 0 )
4243#define AARCH32_TLBIASIDIS_ASID_SHIFT 0
4244#define AARCH32_TLBIASIDIS_ASID_MASK 0xffU
4245#define AARCH32_TLBIASIDIS_ASID_GET( _reg ) \
4246 ( ( ( _reg ) >> 0 ) & 0xffU )
4248static inline void _AArch32_Write_tlbiasidis( uint32_t value )
4251 "mcr p15, 0, %0, c8, c3, 2" : :
"r" ( value ) :
"memory"
4257#define AARCH32_TLBIIPAS2_IPA_39_12( _val ) ( ( _val ) << 0 )
4258#define AARCH32_TLBIIPAS2_IPA_39_12_SHIFT 0
4259#define AARCH32_TLBIIPAS2_IPA_39_12_MASK 0xfffffffU
4260#define AARCH32_TLBIIPAS2_IPA_39_12_GET( _reg ) \
4261 ( ( ( _reg ) >> 0 ) & 0xfffffffU )
4263static inline void _AArch32_Write_tlbiipas2( uint32_t value )
4266 "mcr p15, 4, %0, c8, c4, 1" : :
"r" ( value ) :
"memory"
4272#define AARCH32_TLBIIPAS2IS_IPA_39_12( _val ) ( ( _val ) << 0 )
4273#define AARCH32_TLBIIPAS2IS_IPA_39_12_SHIFT 0
4274#define AARCH32_TLBIIPAS2IS_IPA_39_12_MASK 0xfffffffU
4275#define AARCH32_TLBIIPAS2IS_IPA_39_12_GET( _reg ) \
4276 ( ( ( _reg ) >> 0 ) & 0xfffffffU )
4278static inline void _AArch32_Write_tlbiipas2is( uint32_t value )
4281 "mcr p15, 4, %0, c8, c0, 1" : :
"r" ( value ) :
"memory"
4287#define AARCH32_TLBIIPAS2L_IPA_39_12( _val ) ( ( _val ) << 0 )
4288#define AARCH32_TLBIIPAS2L_IPA_39_12_SHIFT 0
4289#define AARCH32_TLBIIPAS2L_IPA_39_12_MASK 0xfffffffU
4290#define AARCH32_TLBIIPAS2L_IPA_39_12_GET( _reg ) \
4291 ( ( ( _reg ) >> 0 ) & 0xfffffffU )
4293static inline void _AArch32_Write_tlbiipas2l( uint32_t value )
4296 "mcr p15, 4, %0, c8, c4, 5" : :
"r" ( value ) :
"memory"
4302#define AARCH32_TLBIIPAS2LIS_IPA_39_12( _val ) ( ( _val ) << 0 )
4303#define AARCH32_TLBIIPAS2LIS_IPA_39_12_SHIFT 0
4304#define AARCH32_TLBIIPAS2LIS_IPA_39_12_MASK 0xfffffffU
4305#define AARCH32_TLBIIPAS2LIS_IPA_39_12_GET( _reg ) \
4306 ( ( ( _reg ) >> 0 ) & 0xfffffffU )
4308static inline void _AArch32_Write_tlbiipas2lis( uint32_t value )
4311 "mcr p15, 4, %0, c8, c0, 5" : :
"r" ( value ) :
"memory"
4317#define AARCH32_TLBIMVA_ASID( _val ) ( ( _val ) << 0 )
4318#define AARCH32_TLBIMVA_ASID_SHIFT 0
4319#define AARCH32_TLBIMVA_ASID_MASK 0xffU
4320#define AARCH32_TLBIMVA_ASID_GET( _reg ) \
4321 ( ( ( _reg ) >> 0 ) & 0xffU )
4323#define AARCH32_TLBIMVA_VA( _val ) ( ( _val ) << 12 )
4324#define AARCH32_TLBIMVA_VA_SHIFT 12
4325#define AARCH32_TLBIMVA_VA_MASK 0xfffff000U
4326#define AARCH32_TLBIMVA_VA_GET( _reg ) \
4327 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4329static inline void _AArch32_Write_tlbimva( uint32_t value )
4332 "mcr p15, 0, %0, c8, c7, 1" : :
"r" ( value ) :
"memory"
4338#define AARCH32_TLBIMVAA_VA( _val ) ( ( _val ) << 12 )
4339#define AARCH32_TLBIMVAA_VA_SHIFT 12
4340#define AARCH32_TLBIMVAA_VA_MASK 0xfffff000U
4341#define AARCH32_TLBIMVAA_VA_GET( _reg ) \
4342 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4344static inline void _AArch32_Write_tlbimvaa( uint32_t value )
4347 "mcr p15, 0, %0, c8, c7, 3" : :
"r" ( value ) :
"memory"
4353#define AARCH32_TLBIMVAAIS_VA( _val ) ( ( _val ) << 12 )
4354#define AARCH32_TLBIMVAAIS_VA_SHIFT 12
4355#define AARCH32_TLBIMVAAIS_VA_MASK 0xfffff000U
4356#define AARCH32_TLBIMVAAIS_VA_GET( _reg ) \
4357 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4359static inline void _AArch32_Write_tlbimvaais( uint32_t value )
4362 "mcr p15, 0, %0, c8, c3, 3" : :
"r" ( value ) :
"memory"
4368#define AARCH32_TLBIMVAAL_VA( _val ) ( ( _val ) << 12 )
4369#define AARCH32_TLBIMVAAL_VA_SHIFT 12
4370#define AARCH32_TLBIMVAAL_VA_MASK 0xfffff000U
4371#define AARCH32_TLBIMVAAL_VA_GET( _reg ) \
4372 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4374static inline void _AArch32_Write_tlbimvaal( uint32_t value )
4377 "mcr p15, 0, %0, c8, c7, 7" : :
"r" ( value ) :
"memory"
4383#define AARCH32_TLBIMVAALIS_VA( _val ) ( ( _val ) << 12 )
4384#define AARCH32_TLBIMVAALIS_VA_SHIFT 12
4385#define AARCH32_TLBIMVAALIS_VA_MASK 0xfffff000U
4386#define AARCH32_TLBIMVAALIS_VA_GET( _reg ) \
4387 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4389static inline void _AArch32_Write_tlbimvaalis( uint32_t value )
4392 "mcr p15, 0, %0, c8, c3, 7" : :
"r" ( value ) :
"memory"
4398#define AARCH32_TLBIMVAH_VA( _val ) ( ( _val ) << 12 )
4399#define AARCH32_TLBIMVAH_VA_SHIFT 12
4400#define AARCH32_TLBIMVAH_VA_MASK 0xfffff000U
4401#define AARCH32_TLBIMVAH_VA_GET( _reg ) \
4402 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4404static inline void _AArch32_Write_tlbimvah( uint32_t value )
4407 "mcr p15, 4, %0, c8, c7, 1" : :
"r" ( value ) :
"memory"
4413#define AARCH32_TLBIMVAHIS_VA( _val ) ( ( _val ) << 12 )
4414#define AARCH32_TLBIMVAHIS_VA_SHIFT 12
4415#define AARCH32_TLBIMVAHIS_VA_MASK 0xfffff000U
4416#define AARCH32_TLBIMVAHIS_VA_GET( _reg ) \
4417 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4419static inline void _AArch32_Write_tlbimvahis( uint32_t value )
4422 "mcr p15, 4, %0, c8, c3, 1" : :
"r" ( value ) :
"memory"
4428#define AARCH32_TLBIMVAIS_ASID( _val ) ( ( _val ) << 0 )
4429#define AARCH32_TLBIMVAIS_ASID_SHIFT 0
4430#define AARCH32_TLBIMVAIS_ASID_MASK 0xffU
4431#define AARCH32_TLBIMVAIS_ASID_GET( _reg ) \
4432 ( ( ( _reg ) >> 0 ) & 0xffU )
4434#define AARCH32_TLBIMVAIS_VA( _val ) ( ( _val ) << 12 )
4435#define AARCH32_TLBIMVAIS_VA_SHIFT 12
4436#define AARCH32_TLBIMVAIS_VA_MASK 0xfffff000U
4437#define AARCH32_TLBIMVAIS_VA_GET( _reg ) \
4438 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4440static inline void _AArch32_Write_tlbimvais( uint32_t value )
4443 "mcr p15, 0, %0, c8, c3, 1" : :
"r" ( value ) :
"memory"
4449#define AARCH32_TLBIMVAL_ASID( _val ) ( ( _val ) << 0 )
4450#define AARCH32_TLBIMVAL_ASID_SHIFT 0
4451#define AARCH32_TLBIMVAL_ASID_MASK 0xffU
4452#define AARCH32_TLBIMVAL_ASID_GET( _reg ) \
4453 ( ( ( _reg ) >> 0 ) & 0xffU )
4455#define AARCH32_TLBIMVAL_VA( _val ) ( ( _val ) << 12 )
4456#define AARCH32_TLBIMVAL_VA_SHIFT 12
4457#define AARCH32_TLBIMVAL_VA_MASK 0xfffff000U
4458#define AARCH32_TLBIMVAL_VA_GET( _reg ) \
4459 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4461static inline void _AArch32_Write_tlbimval( uint32_t value )
4464 "mcr p15, 0, %0, c8, c7, 5" : :
"r" ( value ) :
"memory"
4470#define AARCH32_TLBIMVALH_VA( _val ) ( ( _val ) << 12 )
4471#define AARCH32_TLBIMVALH_VA_SHIFT 12
4472#define AARCH32_TLBIMVALH_VA_MASK 0xfffff000U
4473#define AARCH32_TLBIMVALH_VA_GET( _reg ) \
4474 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4476static inline void _AArch32_Write_tlbimvalh( uint32_t value )
4479 "mcr p15, 4, %0, c8, c7, 5" : :
"r" ( value ) :
"memory"
4485#define AARCH32_TLBIMVALHIS_VA( _val ) ( ( _val ) << 12 )
4486#define AARCH32_TLBIMVALHIS_VA_SHIFT 12
4487#define AARCH32_TLBIMVALHIS_VA_MASK 0xfffff000U
4488#define AARCH32_TLBIMVALHIS_VA_GET( _reg ) \
4489 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4491static inline void _AArch32_Write_tlbimvalhis( uint32_t value )
4494 "mcr p15, 4, %0, c8, c3, 5" : :
"r" ( value ) :
"memory"
4500#define AARCH32_TLBIMVALIS_ASID( _val ) ( ( _val ) << 0 )
4501#define AARCH32_TLBIMVALIS_ASID_SHIFT 0
4502#define AARCH32_TLBIMVALIS_ASID_MASK 0xffU
4503#define AARCH32_TLBIMVALIS_ASID_GET( _reg ) \
4504 ( ( ( _reg ) >> 0 ) & 0xffU )
4506#define AARCH32_TLBIMVALIS_VA( _val ) ( ( _val ) << 12 )
4507#define AARCH32_TLBIMVALIS_VA_SHIFT 12
4508#define AARCH32_TLBIMVALIS_VA_MASK 0xfffff000U
4509#define AARCH32_TLBIMVALIS_VA_GET( _reg ) \
4510 ( ( ( _reg ) >> 12 ) & 0xfffffU )
4512static inline void _AArch32_Write_tlbimvalis( uint32_t value )
4515 "mcr p15, 0, %0, c8, c3, 5" : :
"r" ( value ) :
"memory"
4521#define AARCH32_TLBTR_NU 0x1U
4523static inline uint32_t _AArch32_Read_tlbtr(
void )
4528 "mrc p15, 0, %0, c0, c0, 3" :
"=&r" ( value ) : :
"memory"
4536static inline uint32_t _AArch32_Read_tpidrprw(
void )
4541 "mrc p15, 0, %0, c13, c0, 4" :
"=&r" ( value ) : :
"memory"
4547static inline void _AArch32_Write_tpidrprw( uint32_t value )
4550 "mcr p15, 0, %0, c13, c0, 4" : :
"r" ( value ) :
"memory"
4556static inline uint32_t _AArch32_Read_tpidruro(
void )
4561 "mrc p15, 0, %0, c13, c0, 3" :
"=&r" ( value ) : :
"memory"
4567static inline void _AArch32_Write_tpidruro( uint32_t value )
4570 "mcr p15, 0, %0, c13, c0, 3" : :
"r" ( value ) :
"memory"
4576static inline uint32_t _AArch32_Read_tpidrurw(
void )
4581 "mrc p15, 0, %0, c13, c0, 2" :
"=&r" ( value ) : :
"memory"
4587static inline void _AArch32_Write_tpidrurw( uint32_t value )
4590 "mcr p15, 0, %0, c13, c0, 2" : :
"r" ( value ) :
"memory"
4596#define AARCH32_TTBCR_N( _val ) ( ( _val ) << 0 )
4597#define AARCH32_TTBCR_N_SHIFT 0
4598#define AARCH32_TTBCR_N_MASK 0x7U
4599#define AARCH32_TTBCR_N_GET( _reg ) \
4600 ( ( ( _reg ) >> 0 ) & 0x7U )
4602#define AARCH32_TTBCR_T0SZ( _val ) ( ( _val ) << 0 )
4603#define AARCH32_TTBCR_T0SZ_SHIFT 0
4604#define AARCH32_TTBCR_T0SZ_MASK 0x7U
4605#define AARCH32_TTBCR_T0SZ_GET( _reg ) \
4606 ( ( ( _reg ) >> 0 ) & 0x7U )
4608#define AARCH32_TTBCR_PD0 0x10U
4610#define AARCH32_TTBCR_PD1 0x20U
4612#define AARCH32_TTBCR_T2E 0x40U
4614#define AARCH32_TTBCR_EPD0 0x80U
4616#define AARCH32_TTBCR_IRGN0( _val ) ( ( _val ) << 8 )
4617#define AARCH32_TTBCR_IRGN0_SHIFT 8
4618#define AARCH32_TTBCR_IRGN0_MASK 0x300U
4619#define AARCH32_TTBCR_IRGN0_GET( _reg ) \
4620 ( ( ( _reg ) >> 8 ) & 0x3U )
4622#define AARCH32_TTBCR_ORGN0( _val ) ( ( _val ) << 10 )
4623#define AARCH32_TTBCR_ORGN0_SHIFT 10
4624#define AARCH32_TTBCR_ORGN0_MASK 0xc00U
4625#define AARCH32_TTBCR_ORGN0_GET( _reg ) \
4626 ( ( ( _reg ) >> 10 ) & 0x3U )
4628#define AARCH32_TTBCR_SH0( _val ) ( ( _val ) << 12 )
4629#define AARCH32_TTBCR_SH0_SHIFT 12
4630#define AARCH32_TTBCR_SH0_MASK 0x3000U
4631#define AARCH32_TTBCR_SH0_GET( _reg ) \
4632 ( ( ( _reg ) >> 12 ) & 0x3U )
4634#define AARCH32_TTBCR_T1SZ( _val ) ( ( _val ) << 16 )
4635#define AARCH32_TTBCR_T1SZ_SHIFT 16
4636#define AARCH32_TTBCR_T1SZ_MASK 0x70000U
4637#define AARCH32_TTBCR_T1SZ_GET( _reg ) \
4638 ( ( ( _reg ) >> 16 ) & 0x7U )
4640#define AARCH32_TTBCR_A1 0x400000U
4642#define AARCH32_TTBCR_EPD1 0x800000U
4644#define AARCH32_TTBCR_IRGN1( _val ) ( ( _val ) << 24 )
4645#define AARCH32_TTBCR_IRGN1_SHIFT 24
4646#define AARCH32_TTBCR_IRGN1_MASK 0x3000000U
4647#define AARCH32_TTBCR_IRGN1_GET( _reg ) \
4648 ( ( ( _reg ) >> 24 ) & 0x3U )
4650#define AARCH32_TTBCR_ORGN1( _val ) ( ( _val ) << 26 )
4651#define AARCH32_TTBCR_ORGN1_SHIFT 26
4652#define AARCH32_TTBCR_ORGN1_MASK 0xc000000U
4653#define AARCH32_TTBCR_ORGN1_GET( _reg ) \
4654 ( ( ( _reg ) >> 26 ) & 0x3U )
4656#define AARCH32_TTBCR_SH1( _val ) ( ( _val ) << 28 )
4657#define AARCH32_TTBCR_SH1_SHIFT 28
4658#define AARCH32_TTBCR_SH1_MASK 0x30000000U
4659#define AARCH32_TTBCR_SH1_GET( _reg ) \
4660 ( ( ( _reg ) >> 28 ) & 0x3U )
4662#define AARCH32_TTBCR_EAE 0x80000000U
4664static inline uint32_t _AArch32_Read_ttbcr(
void )
4669 "mrc p15, 0, %0, c2, c0, 2" :
"=&r" ( value ) : :
"memory"
4675static inline void _AArch32_Write_ttbcr( uint32_t value )
4678 "mcr p15, 0, %0, c2, c0, 2" : :
"r" ( value ) :
"memory"
4684#define AARCH32_TTBCR2_HPD0 0x200U
4686#define AARCH32_TTBCR2_HPD1 0x400U
4688#define AARCH32_TTBCR2_HWU059 0x800U
4690#define AARCH32_TTBCR2_HWU060 0x1000U
4692#define AARCH32_TTBCR2_HWU061 0x2000U
4694#define AARCH32_TTBCR2_HWU062 0x4000U
4696#define AARCH32_TTBCR2_HWU159 0x8000U
4698#define AARCH32_TTBCR2_HWU160 0x10000U
4700#define AARCH32_TTBCR2_HWU161 0x20000U
4702#define AARCH32_TTBCR2_HWU162 0x40000U
4704static inline uint32_t _AArch32_Read_ttbcr2(
void )
4709 "mrc p15, 0, %0, c2, c0, 3" :
"=&r" ( value ) : :
"memory"
4715static inline void _AArch32_Write_ttbcr2( uint32_t value )
4718 "mcr p15, 0, %0, c2, c0, 3" : :
"r" ( value ) :
"memory"
4724#define AARCH32_TTBR0_CNP 0x1U
4726#define AARCH32_TTBR0_IRGN_1 0x1U
4728#define AARCH32_TTBR0_S 0x2U
4730#define AARCH32_TTBR0_BADDR( _val ) ( ( _val ) << 1 )
4731#define AARCH32_TTBR0_BADDR_SHIFT 1
4732#define AARCH32_TTBR0_BADDR_MASK 0xfffffffffffeULL
4733#define AARCH32_TTBR0_BADDR_GET( _reg ) \
4734 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
4736#define AARCH32_TTBR0_IMP 0x4U
4738#define AARCH32_TTBR0_RGN( _val ) ( ( _val ) << 3 )
4739#define AARCH32_TTBR0_RGN_SHIFT 3
4740#define AARCH32_TTBR0_RGN_MASK 0x18U
4741#define AARCH32_TTBR0_RGN_GET( _reg ) \
4742 ( ( ( _reg ) >> 3 ) & 0x3U )
4744#define AARCH32_TTBR0_NOS 0x20U
4746#define AARCH32_TTBR0_IRGN_0 0x40U
4748#define AARCH32_TTBR0_TTB0( _val ) ( ( _val ) << 7 )
4749#define AARCH32_TTBR0_TTB0_SHIFT 7
4750#define AARCH32_TTBR0_TTB0_MASK 0xffffff80U
4751#define AARCH32_TTBR0_TTB0_GET( _reg ) \
4752 ( ( ( _reg ) >> 7 ) & 0x1ffffffU )
4754#define AARCH32_TTBR0_ASID( _val ) ( ( _val ) << 48 )
4755#define AARCH32_TTBR0_ASID_SHIFT 48
4756#define AARCH32_TTBR0_ASID_MASK 0xff000000000000ULL
4757#define AARCH32_TTBR0_ASID_GET( _reg ) \
4758 ( ( ( _reg ) >> 48 ) & 0xffULL )
4760static inline uint32_t _AArch32_Read_32_ttbr0(
void )
4765 "mrc p15, 0, %0, c2, c0, 0" :
"=&r" ( value ) : :
"memory"
4771static inline void _AArch32_Write_32_ttbr0( uint32_t value )
4774 "mcr p15, 0, %0, c2, c0, 0" : :
"r" ( value ) :
"memory"
4780static inline uint64_t _AArch32_Read_64_ttbr0(
void )
4785 "mrrc p15, 0, %Q0, %R0, c2" :
"=&r" ( value ) : :
"memory"
4791static inline void _AArch32_Write_64_ttbr0( uint64_t value )
4794 "mcrr p15, 0, %Q0, %R0, c2" : :
"r" ( value ) :
"memory"
4800#define AARCH32_TTBR1_CNP 0x1U
4802#define AARCH32_TTBR1_IRGN_0 0x1U
4804#define AARCH32_TTBR1_S 0x2U
4806#define AARCH32_TTBR1_BADDR( _val ) ( ( _val ) << 1 )
4807#define AARCH32_TTBR1_BADDR_SHIFT 1
4808#define AARCH32_TTBR1_BADDR_MASK 0xfffffffffffeULL
4809#define AARCH32_TTBR1_BADDR_GET( _reg ) \
4810 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
4812#define AARCH32_TTBR1_IMP 0x4U
4814#define AARCH32_TTBR1_RGN( _val ) ( ( _val ) << 3 )
4815#define AARCH32_TTBR1_RGN_SHIFT 3
4816#define AARCH32_TTBR1_RGN_MASK 0x18U
4817#define AARCH32_TTBR1_RGN_GET( _reg ) \
4818 ( ( ( _reg ) >> 3 ) & 0x3U )
4820#define AARCH32_TTBR1_NOS 0x20U
4822#define AARCH32_TTBR1_IRGN_1 0x40U
4824#define AARCH32_TTBR1_TTB1( _val ) ( ( _val ) << 7 )
4825#define AARCH32_TTBR1_TTB1_SHIFT 7
4826#define AARCH32_TTBR1_TTB1_MASK 0xffffff80U
4827#define AARCH32_TTBR1_TTB1_GET( _reg ) \
4828 ( ( ( _reg ) >> 7 ) & 0x1ffffffU )
4830#define AARCH32_TTBR1_ASID( _val ) ( ( _val ) << 48 )
4831#define AARCH32_TTBR1_ASID_SHIFT 48
4832#define AARCH32_TTBR1_ASID_MASK 0xff000000000000ULL
4833#define AARCH32_TTBR1_ASID_GET( _reg ) \
4834 ( ( ( _reg ) >> 48 ) & 0xffULL )
4836static inline uint32_t _AArch32_Read_32_ttbr1(
void )
4841 "mrc p15, 0, %0, c2, c0, 1" :
"=&r" ( value ) : :
"memory"
4847static inline void _AArch32_Write_32_ttbr1( uint32_t value )
4850 "mcr p15, 0, %0, c2, c0, 1" : :
"r" ( value ) :
"memory"
4856static inline uint64_t _AArch32_Read_64_ttbr1(
void )
4861 "mrrc p15, 1, %Q0, %R0, c2" :
"=&r" ( value ) : :
"memory"
4867static inline void _AArch32_Write_64_ttbr1( uint64_t value )
4870 "mcrr p15, 1, %Q0, %R0, c2" : :
"r" ( value ) :
"memory"
4876static inline uint32_t _AArch32_Read_vbar(
void )
4881 "mrc p15, 0, %0, c12, c0, 0" :
"=&r" ( value ) : :
"memory"
4887static inline void _AArch32_Write_vbar( uint32_t value )
4890 "mcr p15, 0, %0, c12, c0, 0" : :
"r" ( value ) :
"memory"
4896#define AARCH32_VMPIDR_AFF0( _val ) ( ( _val ) << 0 )
4897#define AARCH32_VMPIDR_AFF0_SHIFT 0
4898#define AARCH32_VMPIDR_AFF0_MASK 0xffU
4899#define AARCH32_VMPIDR_AFF0_GET( _reg ) \
4900 ( ( ( _reg ) >> 0 ) & 0xffU )
4902#define AARCH32_VMPIDR_AFF1( _val ) ( ( _val ) << 8 )
4903#define AARCH32_VMPIDR_AFF1_SHIFT 8
4904#define AARCH32_VMPIDR_AFF1_MASK 0xff00U
4905#define AARCH32_VMPIDR_AFF1_GET( _reg ) \
4906 ( ( ( _reg ) >> 8 ) & 0xffU )
4908#define AARCH32_VMPIDR_AFF2( _val ) ( ( _val ) << 16 )
4909#define AARCH32_VMPIDR_AFF2_SHIFT 16
4910#define AARCH32_VMPIDR_AFF2_MASK 0xff0000U
4911#define AARCH32_VMPIDR_AFF2_GET( _reg ) \
4912 ( ( ( _reg ) >> 16 ) & 0xffU )
4914#define AARCH32_VMPIDR_MT 0x1000000U
4916#define AARCH32_VMPIDR_U 0x40000000U
4918#define AARCH32_VMPIDR_M 0x80000000U
4920static inline uint32_t _AArch32_Read_vmpidr(
void )
4925 "mrc p15, 4, %0, c0, c0, 5" :
"=&r" ( value ) : :
"memory"
4931static inline void _AArch32_Write_vmpidr( uint32_t value )
4934 "mcr p15, 4, %0, c0, c0, 5" : :
"r" ( value ) :
"memory"
4940#define AARCH32_VPIDR_REVISION( _val ) ( ( _val ) << 0 )
4941#define AARCH32_VPIDR_REVISION_SHIFT 0
4942#define AARCH32_VPIDR_REVISION_MASK 0xfU
4943#define AARCH32_VPIDR_REVISION_GET( _reg ) \
4944 ( ( ( _reg ) >> 0 ) & 0xfU )
4946#define AARCH32_VPIDR_PARTNUM( _val ) ( ( _val ) << 4 )
4947#define AARCH32_VPIDR_PARTNUM_SHIFT 4
4948#define AARCH32_VPIDR_PARTNUM_MASK 0xfff0U
4949#define AARCH32_VPIDR_PARTNUM_GET( _reg ) \
4950 ( ( ( _reg ) >> 4 ) & 0xfffU )
4952#define AARCH32_VPIDR_ARCHITECTURE( _val ) ( ( _val ) << 16 )
4953#define AARCH32_VPIDR_ARCHITECTURE_SHIFT 16
4954#define AARCH32_VPIDR_ARCHITECTURE_MASK 0xf0000U
4955#define AARCH32_VPIDR_ARCHITECTURE_GET( _reg ) \
4956 ( ( ( _reg ) >> 16 ) & 0xfU )
4958#define AARCH32_VPIDR_VARIANT( _val ) ( ( _val ) << 20 )
4959#define AARCH32_VPIDR_VARIANT_SHIFT 20
4960#define AARCH32_VPIDR_VARIANT_MASK 0xf00000U
4961#define AARCH32_VPIDR_VARIANT_GET( _reg ) \
4962 ( ( ( _reg ) >> 20 ) & 0xfU )
4964#define AARCH32_VPIDR_IMPLEMENTER( _val ) ( ( _val ) << 24 )
4965#define AARCH32_VPIDR_IMPLEMENTER_SHIFT 24
4966#define AARCH32_VPIDR_IMPLEMENTER_MASK 0xff000000U
4967#define AARCH32_VPIDR_IMPLEMENTER_GET( _reg ) \
4968 ( ( ( _reg ) >> 24 ) & 0xffU )
4970static inline uint32_t _AArch32_Read_vpidr(
void )
4975 "mrc p15, 4, %0, c0, c0, 0" :
"=&r" ( value ) : :
"memory"
4981static inline void _AArch32_Write_vpidr( uint32_t value )
4984 "mcr p15, 4, %0, c0, c0, 0" : :
"r" ( value ) :
"memory"
4990#define AARCH32_VTCR_T0SZ( _val ) ( ( _val ) << 0 )
4991#define AARCH32_VTCR_T0SZ_SHIFT 0
4992#define AARCH32_VTCR_T0SZ_MASK 0xfU
4993#define AARCH32_VTCR_T0SZ_GET( _reg ) \
4994 ( ( ( _reg ) >> 0 ) & 0xfU )
4996#define AARCH32_VTCR_S 0x10U
4998#define AARCH32_VTCR_SL0( _val ) ( ( _val ) << 6 )
4999#define AARCH32_VTCR_SL0_SHIFT 6
5000#define AARCH32_VTCR_SL0_MASK 0xc0U
5001#define AARCH32_VTCR_SL0_GET( _reg ) \
5002 ( ( ( _reg ) >> 6 ) & 0x3U )
5004#define AARCH32_VTCR_IRGN0( _val ) ( ( _val ) << 8 )
5005#define AARCH32_VTCR_IRGN0_SHIFT 8
5006#define AARCH32_VTCR_IRGN0_MASK 0x300U
5007#define AARCH32_VTCR_IRGN0_GET( _reg ) \
5008 ( ( ( _reg ) >> 8 ) & 0x3U )
5010#define AARCH32_VTCR_ORGN0( _val ) ( ( _val ) << 10 )
5011#define AARCH32_VTCR_ORGN0_SHIFT 10
5012#define AARCH32_VTCR_ORGN0_MASK 0xc00U
5013#define AARCH32_VTCR_ORGN0_GET( _reg ) \
5014 ( ( ( _reg ) >> 10 ) & 0x3U )
5016#define AARCH32_VTCR_SH0( _val ) ( ( _val ) << 12 )
5017#define AARCH32_VTCR_SH0_SHIFT 12
5018#define AARCH32_VTCR_SH0_MASK 0x3000U
5019#define AARCH32_VTCR_SH0_GET( _reg ) \
5020 ( ( ( _reg ) >> 12 ) & 0x3U )
5022#define AARCH32_VTCR_HWU59 0x2000000U
5024#define AARCH32_VTCR_HWU60 0x4000000U
5026#define AARCH32_VTCR_HWU61 0x8000000U
5028#define AARCH32_VTCR_HWU62 0x10000000U
5030static inline uint32_t _AArch32_Read_vtcr(
void )
5035 "mrc p15, 4, %0, c2, c1, 2" :
"=&r" ( value ) : :
"memory"
5041static inline void _AArch32_Write_vtcr( uint32_t value )
5044 "mcr p15, 4, %0, c2, c1, 2" : :
"r" ( value ) :
"memory"
5050#define AARCH32_VTTBR_CNP 0x1U
5052#define AARCH32_VTTBR_BADDR( _val ) ( ( _val ) << 1 )
5053#define AARCH32_VTTBR_BADDR_SHIFT 1
5054#define AARCH32_VTTBR_BADDR_MASK 0xfffffffffffeULL
5055#define AARCH32_VTTBR_BADDR_GET( _reg ) \
5056 ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )
5058#define AARCH32_VTTBR_VMID( _val ) ( ( _val ) << 48 )
5059#define AARCH32_VTTBR_VMID_SHIFT 48
5060#define AARCH32_VTTBR_VMID_MASK 0xff000000000000ULL
5061#define AARCH32_VTTBR_VMID_GET( _reg ) \
5062 ( ( ( _reg ) >> 48 ) & 0xffULL )
5064static inline uint64_t _AArch32_Read_vttbr(
void )
5069 "mrrc p15, 6, %Q0, %R0, c2" :
"=&r" ( value ) : :
"memory"
5075static inline void _AArch32_Write_vttbr( uint64_t value )
5078 "mcrr p15, 6, %Q0, %R0, c2" : :
"r" ( value ) :
"memory"
5084#define AARCH32_DBGAUTHSTATUS_NSID( _val ) ( ( _val ) << 0 )
5085#define AARCH32_DBGAUTHSTATUS_NSID_SHIFT 0
5086#define AARCH32_DBGAUTHSTATUS_NSID_MASK 0x3U
5087#define AARCH32_DBGAUTHSTATUS_NSID_GET( _reg ) \
5088 ( ( ( _reg ) >> 0 ) & 0x3U )
5090#define AARCH32_DBGAUTHSTATUS_NSNID( _val ) ( ( _val ) << 2 )
5091#define AARCH32_DBGAUTHSTATUS_NSNID_SHIFT 2
5092#define AARCH32_DBGAUTHSTATUS_NSNID_MASK 0xcU
5093#define AARCH32_DBGAUTHSTATUS_NSNID_GET( _reg ) \
5094 ( ( ( _reg ) >> 2 ) & 0x3U )
5096#define AARCH32_DBGAUTHSTATUS_SID( _val ) ( ( _val ) << 4 )
5097#define AARCH32_DBGAUTHSTATUS_SID_SHIFT 4
5098#define AARCH32_DBGAUTHSTATUS_SID_MASK 0x30U
5099#define AARCH32_DBGAUTHSTATUS_SID_GET( _reg ) \
5100 ( ( ( _reg ) >> 4 ) & 0x3U )
5102#define AARCH32_DBGAUTHSTATUS_SNID( _val ) ( ( _val ) << 6 )
5103#define AARCH32_DBGAUTHSTATUS_SNID_SHIFT 6
5104#define AARCH32_DBGAUTHSTATUS_SNID_MASK 0xc0U
5105#define AARCH32_DBGAUTHSTATUS_SNID_GET( _reg ) \
5106 ( ( ( _reg ) >> 6 ) & 0x3U )
5108static inline uint32_t _AArch32_Read_dbgauthstatus(
void )
5113 "mrc p14, 0, %0, c7, c14, 6" :
"=&r" ( value ) : :
"memory"
5121#define AARCH32_DBGBCR_E 0x1U
5123#define AARCH32_DBGBCR_PMC( _val ) ( ( _val ) << 1 )
5124#define AARCH32_DBGBCR_PMC_SHIFT 1
5125#define AARCH32_DBGBCR_PMC_MASK 0x6U
5126#define AARCH32_DBGBCR_PMC_GET( _reg ) \
5127 ( ( ( _reg ) >> 1 ) & 0x3U )
5129#define AARCH32_DBGBCR_BAS( _val ) ( ( _val ) << 5 )
5130#define AARCH32_DBGBCR_BAS_SHIFT 5
5131#define AARCH32_DBGBCR_BAS_MASK 0x1e0U
5132#define AARCH32_DBGBCR_BAS_GET( _reg ) \
5133 ( ( ( _reg ) >> 5 ) & 0xfU )
5135#define AARCH32_DBGBCR_HMC 0x2000U
5137#define AARCH32_DBGBCR_SSC( _val ) ( ( _val ) << 14 )
5138#define AARCH32_DBGBCR_SSC_SHIFT 14
5139#define AARCH32_DBGBCR_SSC_MASK 0xc000U
5140#define AARCH32_DBGBCR_SSC_GET( _reg ) \
5141 ( ( ( _reg ) >> 14 ) & 0x3U )
5143#define AARCH32_DBGBCR_LBN( _val ) ( ( _val ) << 16 )
5144#define AARCH32_DBGBCR_LBN_SHIFT 16
5145#define AARCH32_DBGBCR_LBN_MASK 0xf0000U
5146#define AARCH32_DBGBCR_LBN_GET( _reg ) \
5147 ( ( ( _reg ) >> 16 ) & 0xfU )
5149#define AARCH32_DBGBCR_BT( _val ) ( ( _val ) << 20 )
5150#define AARCH32_DBGBCR_BT_SHIFT 20
5151#define AARCH32_DBGBCR_BT_MASK 0xf00000U
5152#define AARCH32_DBGBCR_BT_GET( _reg ) \
5153 ( ( ( _reg ) >> 20 ) & 0xfU )
5157static inline uint32_t _AArch32_Read_dbgbcr_0(
void )
5162 "mrc p14, 0, %0, c0, c0, 5" :
"=&r" ( value ) : :
"memory"
5168static inline void _AArch32_Write_dbgbcr_0( uint32_t value )
5171 "mcr p14, 0, %0, c0, c0, 5" : :
"r" ( value ) :
"memory"
5177static inline uint32_t _AArch32_Read_dbgbcr_1(
void )
5182 "mrc p14, 0, %0, c0, c1, 5" :
"=&r" ( value ) : :
"memory"
5188static inline void _AArch32_Write_dbgbcr_1( uint32_t value )
5191 "mcr p14, 0, %0, c0, c1, 5" : :
"r" ( value ) :
"memory"
5197static inline uint32_t _AArch32_Read_dbgbcr_2(
void )
5202 "mrc p14, 0, %0, c0, c2, 5" :
"=&r" ( value ) : :
"memory"
5208static inline void _AArch32_Write_dbgbcr_2( uint32_t value )
5211 "mcr p14, 0, %0, c0, c2, 5" : :
"r" ( value ) :
"memory"
5217static inline uint32_t _AArch32_Read_dbgbcr_3(
void )
5222 "mrc p14, 0, %0, c0, c3, 5" :
"=&r" ( value ) : :
"memory"
5228static inline void _AArch32_Write_dbgbcr_3( uint32_t value )
5231 "mcr p14, 0, %0, c0, c3, 5" : :
"r" ( value ) :
"memory"
5237static inline uint32_t _AArch32_Read_dbgbcr_4(
void )
5242 "mrc p14, 0, %0, c0, c4, 5" :
"=&r" ( value ) : :
"memory"
5248static inline void _AArch32_Write_dbgbcr_4( uint32_t value )
5251 "mcr p14, 0, %0, c0, c4, 5" : :
"r" ( value ) :
"memory"
5257static inline uint32_t _AArch32_Read_dbgbcr_5(
void )
5262 "mrc p14, 0, %0, c0, c5, 5" :
"=&r" ( value ) : :
"memory"
5268static inline void _AArch32_Write_dbgbcr_5( uint32_t value )
5271 "mcr p14, 0, %0, c0, c5, 5" : :
"r" ( value ) :
"memory"
5277static inline uint32_t _AArch32_Read_dbgbcr_6(
void )
5282 "mrc p14, 0, %0, c0, c6, 5" :
"=&r" ( value ) : :
"memory"
5288static inline void _AArch32_Write_dbgbcr_6( uint32_t value )
5291 "mcr p14, 0, %0, c0, c6, 5" : :
"r" ( value ) :
"memory"
5297static inline uint32_t _AArch32_Read_dbgbcr_7(
void )
5302 "mrc p14, 0, %0, c0, c7, 5" :
"=&r" ( value ) : :
"memory"
5308static inline void _AArch32_Write_dbgbcr_7( uint32_t value )
5311 "mcr p14, 0, %0, c0, c7, 5" : :
"r" ( value ) :
"memory"
5317static inline uint32_t _AArch32_Read_dbgbcr_8(
void )
5322 "mrc p14, 0, %0, c0, c8, 5" :
"=&r" ( value ) : :
"memory"
5328static inline void _AArch32_Write_dbgbcr_8( uint32_t value )
5331 "mcr p14, 0, %0, c0, c8, 5" : :
"r" ( value ) :
"memory"
5337static inline uint32_t _AArch32_Read_dbgbcr_9(
void )
5342 "mrc p14, 0, %0, c0, c9, 5" :
"=&r" ( value ) : :
"memory"
5348static inline void _AArch32_Write_dbgbcr_9( uint32_t value )
5351 "mcr p14, 0, %0, c0, c9, 5" : :
"r" ( value ) :
"memory"
5357static inline uint32_t _AArch32_Read_dbgbcr_10(
void )
5362 "mrc p14, 0, %0, c0, c10, 5" :
"=&r" ( value ) : :
"memory"
5368static inline void _AArch32_Write_dbgbcr_10( uint32_t value )
5371 "mcr p14, 0, %0, c0, c10, 5" : :
"r" ( value ) :
"memory"
5377static inline uint32_t _AArch32_Read_dbgbcr_11(
void )
5382 "mrc p14, 0, %0, c0, c11, 5" :
"=&r" ( value ) : :
"memory"
5388static inline void _AArch32_Write_dbgbcr_11( uint32_t value )
5391 "mcr p14, 0, %0, c0, c11, 5" : :
"r" ( value ) :
"memory"
5397static inline uint32_t _AArch32_Read_dbgbcr_12(
void )
5402 "mrc p14, 0, %0, c0, c12, 5" :
"=&r" ( value ) : :
"memory"
5408static inline void _AArch32_Write_dbgbcr_12( uint32_t value )
5411 "mcr p14, 0, %0, c0, c12, 5" : :
"r" ( value ) :
"memory"
5417static inline uint32_t _AArch32_Read_dbgbcr_13(
void )
5422 "mrc p14, 0, %0, c0, c13, 5" :
"=&r" ( value ) : :
"memory"
5428static inline void _AArch32_Write_dbgbcr_13( uint32_t value )
5431 "mcr p14, 0, %0, c0, c13, 5" : :
"r" ( value ) :
"memory"
5437static inline uint32_t _AArch32_Read_dbgbcr_14(
void )
5442 "mrc p14, 0, %0, c0, c14, 5" :
"=&r" ( value ) : :
"memory"
5448static inline void _AArch32_Write_dbgbcr_14( uint32_t value )
5451 "mcr p14, 0, %0, c0, c14, 5" : :
"r" ( value ) :
"memory"
5457static inline uint32_t _AArch32_Read_dbgbcr_15(
void )
5462 "mrc p14, 0, %0, c0, c15, 5" :
"=&r" ( value ) : :
"memory"
5468static inline void _AArch32_Write_dbgbcr_15( uint32_t value )
5471 "mcr p14, 0, %0, c0, c15, 5" : :
"r" ( value ) :
"memory"
5477#define AARCH32_DBGBVR_CONTEXTID( _val ) ( ( _val ) << 0 )
5478#define AARCH32_DBGBVR_CONTEXTID_SHIFT 0
5479#define AARCH32_DBGBVR_CONTEXTID_MASK 0xffffffffU
5480#define AARCH32_DBGBVR_CONTEXTID_GET( _reg ) \
5481 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
5483#define AARCH32_DBGBVR_VA_31_2( _val ) ( ( _val ) << 2 )
5484#define AARCH32_DBGBVR_VA_31_2_SHIFT 2
5485#define AARCH32_DBGBVR_VA_31_2_MASK 0xfffffffcU
5486#define AARCH32_DBGBVR_VA_31_2_GET( _reg ) \
5487 ( ( ( _reg ) >> 2 ) & 0x3fffffffU )
5491static inline uint32_t _AArch32_Read_dbgbvr_0(
void )
5496 "mrc p14, 0, %0, c0, c0, 4" :
"=&r" ( value ) : :
"memory"
5502static inline void _AArch32_Write_dbgbvr_0( uint32_t value )
5505 "mcr p14, 0, %0, c0, c0, 4" : :
"r" ( value ) :
"memory"
5511static inline uint32_t _AArch32_Read_dbgbvr_1(
void )
5516 "mrc p14, 0, %0, c0, c1, 4" :
"=&r" ( value ) : :
"memory"
5522static inline void _AArch32_Write_dbgbvr_1( uint32_t value )
5525 "mcr p14, 0, %0, c0, c1, 4" : :
"r" ( value ) :
"memory"
5531static inline uint32_t _AArch32_Read_dbgbvr_2(
void )
5536 "mrc p14, 0, %0, c0, c2, 4" :
"=&r" ( value ) : :
"memory"
5542static inline void _AArch32_Write_dbgbvr_2( uint32_t value )
5545 "mcr p14, 0, %0, c0, c2, 4" : :
"r" ( value ) :
"memory"
5551static inline uint32_t _AArch32_Read_dbgbvr_3(
void )
5556 "mrc p14, 0, %0, c0, c3, 4" :
"=&r" ( value ) : :
"memory"
5562static inline void _AArch32_Write_dbgbvr_3( uint32_t value )
5565 "mcr p14, 0, %0, c0, c3, 4" : :
"r" ( value ) :
"memory"
5571static inline uint32_t _AArch32_Read_dbgbvr_4(
void )
5576 "mrc p14, 0, %0, c0, c4, 4" :
"=&r" ( value ) : :
"memory"
5582static inline void _AArch32_Write_dbgbvr_4( uint32_t value )
5585 "mcr p14, 0, %0, c0, c4, 4" : :
"r" ( value ) :
"memory"
5591static inline uint32_t _AArch32_Read_dbgbvr_5(
void )
5596 "mrc p14, 0, %0, c0, c5, 4" :
"=&r" ( value ) : :
"memory"
5602static inline void _AArch32_Write_dbgbvr_5( uint32_t value )
5605 "mcr p14, 0, %0, c0, c5, 4" : :
"r" ( value ) :
"memory"
5611static inline uint32_t _AArch32_Read_dbgbvr_6(
void )
5616 "mrc p14, 0, %0, c0, c6, 4" :
"=&r" ( value ) : :
"memory"
5622static inline void _AArch32_Write_dbgbvr_6( uint32_t value )
5625 "mcr p14, 0, %0, c0, c6, 4" : :
"r" ( value ) :
"memory"
5631static inline uint32_t _AArch32_Read_dbgbvr_7(
void )
5636 "mrc p14, 0, %0, c0, c7, 4" :
"=&r" ( value ) : :
"memory"
5642static inline void _AArch32_Write_dbgbvr_7( uint32_t value )
5645 "mcr p14, 0, %0, c0, c7, 4" : :
"r" ( value ) :
"memory"
5651static inline uint32_t _AArch32_Read_dbgbvr_8(
void )
5656 "mrc p14, 0, %0, c0, c8, 4" :
"=&r" ( value ) : :
"memory"
5662static inline void _AArch32_Write_dbgbvr_8( uint32_t value )
5665 "mcr p14, 0, %0, c0, c8, 4" : :
"r" ( value ) :
"memory"
5671static inline uint32_t _AArch32_Read_dbgbvr_9(
void )
5676 "mrc p14, 0, %0, c0, c9, 4" :
"=&r" ( value ) : :
"memory"
5682static inline void _AArch32_Write_dbgbvr_9( uint32_t value )
5685 "mcr p14, 0, %0, c0, c9, 4" : :
"r" ( value ) :
"memory"
5691static inline uint32_t _AArch32_Read_dbgbvr_10(
void )
5696 "mrc p14, 0, %0, c0, c10, 4" :
"=&r" ( value ) : :
"memory"
5702static inline void _AArch32_Write_dbgbvr_10( uint32_t value )
5705 "mcr p14, 0, %0, c0, c10, 4" : :
"r" ( value ) :
"memory"
5711static inline uint32_t _AArch32_Read_dbgbvr_11(
void )
5716 "mrc p14, 0, %0, c0, c11, 4" :
"=&r" ( value ) : :
"memory"
5722static inline void _AArch32_Write_dbgbvr_11( uint32_t value )
5725 "mcr p14, 0, %0, c0, c11, 4" : :
"r" ( value ) :
"memory"
5731static inline uint32_t _AArch32_Read_dbgbvr_12(
void )
5736 "mrc p14, 0, %0, c0, c12, 4" :
"=&r" ( value ) : :
"memory"
5742static inline void _AArch32_Write_dbgbvr_12( uint32_t value )
5745 "mcr p14, 0, %0, c0, c12, 4" : :
"r" ( value ) :
"memory"
5751static inline uint32_t _AArch32_Read_dbgbvr_13(
void )
5756 "mrc p14, 0, %0, c0, c13, 4" :
"=&r" ( value ) : :
"memory"
5762static inline void _AArch32_Write_dbgbvr_13( uint32_t value )
5765 "mcr p14, 0, %0, c0, c13, 4" : :
"r" ( value ) :
"memory"
5771static inline uint32_t _AArch32_Read_dbgbvr_14(
void )
5776 "mrc p14, 0, %0, c0, c14, 4" :
"=&r" ( value ) : :
"memory"
5782static inline void _AArch32_Write_dbgbvr_14( uint32_t value )
5785 "mcr p14, 0, %0, c0, c14, 4" : :
"r" ( value ) :
"memory"
5791static inline uint32_t _AArch32_Read_dbgbvr_15(
void )
5796 "mrc p14, 0, %0, c0, c15, 4" :
"=&r" ( value ) : :
"memory"
5802static inline void _AArch32_Write_dbgbvr_15( uint32_t value )
5805 "mcr p14, 0, %0, c0, c15, 4" : :
"r" ( value ) :
"memory"
5811#define AARCH32_DBGBXVR_VMID_7_0( _val ) ( ( _val ) << 0 )
5812#define AARCH32_DBGBXVR_VMID_7_0_SHIFT 0
5813#define AARCH32_DBGBXVR_VMID_7_0_MASK 0xffU
5814#define AARCH32_DBGBXVR_VMID_7_0_GET( _reg ) \
5815 ( ( ( _reg ) >> 0 ) & 0xffU )
5817#define AARCH32_DBGBXVR_CONTEXTID2( _val ) ( ( _val ) << 0 )
5818#define AARCH32_DBGBXVR_CONTEXTID2_SHIFT 0
5819#define AARCH32_DBGBXVR_CONTEXTID2_MASK 0xffffffffU
5820#define AARCH32_DBGBXVR_CONTEXTID2_GET( _reg ) \
5821 ( ( ( _reg ) >> 0 ) & 0xffffffffU )
5823#define AARCH32_DBGBXVR_VMID_15_8( _val ) ( ( _val ) << 8 )
5824#define AARCH32_DBGBXVR_VMID_15_8_SHIFT 8
5825#define AARCH32_DBGBXVR_VMID_15_8_MASK 0xff00U
5826#define AARCH32_DBGBXVR_VMID_15_8_GET( _reg ) \
5827 ( ( ( _reg ) >> 8 ) & 0xffU )
5831static inline uint32_t _AArch32_Read_dbgbxvr_0(
void )
5836 "mrc p14, 0, %0, c1, c0, 1" :
"=&r" ( value ) : :
"memory"
5842static inline void _AArch32_Write_dbgbxvr_0( uint32_t value )
5845 "mcr p14, 0, %0, c1, c0, 1" : :
"r" ( value ) :
"memory"
5851static inline uint32_t _AArch32_Read_dbgbxvr_1(
void )
5856 "mrc p14, 0, %0, c1, c1, 1" :
"=&r" ( value ) : :
"memory"
5862static inline void _AArch32_Write_dbgbxvr_1( uint32_t value )
5865 "mcr p14, 0, %0, c1, c1, 1" : :
"r" ( value ) :
"memory"
5871static inline uint32_t _AArch32_Read_dbgbxvr_2(
void )
5876 "mrc p14, 0, %0, c1, c2, 1" :
"=&r" ( value ) : :
"memory"
5882static inline void _AArch32_Write_dbgbxvr_2( uint32_t value )
5885 "mcr p14, 0, %0, c1, c2, 1" : :
"r" ( value ) :
"memory"
5891static inline uint32_t _AArch32_Read_dbgbxvr_3(
void )
5896 "mrc p14, 0, %0, c1, c3, 1" :
"=&r" ( value ) : :
"memory"
5902static inline void _AArch32_Write_dbgbxvr_3( uint32_t value )
5905 "mcr p14, 0, %0, c1, c3, 1" : :
"r" ( value ) :
"memory"
5911static inline uint32_t _AArch32_Read_dbgbxvr_4(
void )
5916 "mrc p14, 0, %0, c1, c4, 1" :
"=&r" ( value ) : :
"memory"
5922static inline void _AArch32_Write_dbgbxvr_4( uint32_t value )
5925 "mcr p14, 0, %0, c1, c4, 1" : :
"r" ( value ) :
"memory"
5931static inline uint32_t _AArch32_Read_dbgbxvr_5(
void )
5936 "mrc p14, 0, %0, c1, c5, 1" :
"=&r" ( value ) : :
"memory"
5942static inline void _AArch32_Write_dbgbxvr_5( uint32_t value )
5945 "mcr p14, 0, %0, c1, c5, 1" : :
"r" ( value ) :
"memory"
5951static inline uint32_t _AArch32_Read_dbgbxvr_6(
void )
5956 "mrc p14, 0, %0, c1, c6, 1" :
"=&r" ( value ) : :
"memory"
5962static inline void _AArch32_Write_dbgbxvr_6( uint32_t value )
5965 "mcr p14, 0, %0, c1, c6, 1" : :
"r" ( value ) :
"memory"
5971static inline uint32_t _AArch32_Read_dbgbxvr_7(
void )
5976 "mrc p14, 0, %0, c1, c7, 1" :
"=&r" ( value ) : :
"memory"
5982static inline void _AArch32_Write_dbgbxvr_7( uint32_t value )
5985 "mcr p14, 0, %0, c1, c7, 1" : :
"r" ( value ) :
"memory"
5991static inline uint32_t _AArch32_Read_dbgbxvr_8(
void )
5996 "mrc p14, 0, %0, c1, c8, 1" :
"=&r" ( value ) : :
"memory"
6002static inline void _AArch32_Write_dbgbxvr_8( uint32_t value )
6005 "mcr p14, 0, %0, c1, c8, 1" : :
"r" ( value ) :
"memory"
6011static inline uint32_t _AArch32_Read_dbgbxvr_9(
void )
6016 "mrc p14, 0, %0, c1, c9, 1" :
"=&r" ( value ) : :
"memory"
6022static inline void _AArch32_Write_dbgbxvr_9( uint32_t value )
6025 "mcr p14, 0, %0, c1, c9, 1" : :
"r" ( value ) :
"memory"
6031static inline uint32_t _AArch32_Read_dbgbxvr_10(
void )
6036 "mrc p14, 0, %0, c1, c10, 1" :
"=&r" ( value ) : :
"memory"
6042static inline void _AArch32_Write_dbgbxvr_10( uint32_t value )
6045 "mcr p14, 0, %0, c1, c10, 1" : :
"r" ( value ) :
"memory"
6051static inline uint32_t _AArch32_Read_dbgbxvr_11(
void )
6056 "mrc p14, 0, %0, c1, c11, 1" :
"=&r" ( value ) : :
"memory"
6062static inline void _AArch32_Write_dbgbxvr_11( uint32_t value )
6065 "mcr p14, 0, %0, c1, c11, 1" : :
"r" ( value ) :
"memory"
6071static inline uint32_t _AArch32_Read_dbgbxvr_12(
void )
6076 "mrc p14, 0, %0, c1, c12, 1" :
"=&r" ( value ) : :
"memory"
6082static inline void _AArch32_Write_dbgbxvr_12( uint32_t value )
6085 "mcr p14, 0, %0, c1, c12, 1" : :
"r" ( value ) :
"memory"
6091static inline uint32_t _AArch32_Read_dbgbxvr_13(
void )
6096 "mrc p14, 0, %0, c1, c13, 1" :
"=&r" ( value ) : :
"memory"
6102static inline void _AArch32_Write_dbgbxvr_13( uint32_t value )
6105 "mcr p14, 0, %0, c1, c13, 1" : :
"r" ( value ) :
"memory"
6111static inline uint32_t _AArch32_Read_dbgbxvr_14(
void )
6116 "mrc p14, 0, %0, c1, c14, 1" :
"=&r" ( value ) : :
"memory"
6122static inline void _AArch32_Write_dbgbxvr_14( uint32_t value )
6125 "mcr p14, 0, %0, c1, c14, 1" : :
"r" ( value ) :
"memory"
6131static inline uint32_t _AArch32_Read_dbgbxvr_15(
void )
6136 "mrc p14, 0, %0, c1, c15, 1" :
"=&r" ( value ) : :
"memory"
6142static inline void _AArch32_Write_dbgbxvr_15( uint32_t value )
6145 "mcr p14, 0, %0, c1, c15, 1" : :
"r" ( value ) :
"memory"
6151#define AARCH32_DBGCLAIMCLR_CLAIM( _val ) ( ( _val ) << 0 )
6152#define AARCH32_DBGCLAIMCLR_CLAIM_SHIFT 0
6153#define AARCH32_DBGCLAIMCLR_CLAIM_MASK 0xffU
6154#define AARCH32_DBGCLAIMCLR_CLAIM_GET( _reg ) \
6155 ( ( ( _reg ) >> 0 ) & 0xffU )
6157static inline uint32_t _AArch32_Read_dbgclaimclr(
void )
6162 "mrc p14, 0, %0, c7, c9, 6" :
"=&r" ( value ) : :
"memory"
6168static inline void _AArch32_Write_dbgclaimclr( uint32_t value )
6171 "mcr p14, 0, %0, c7, c9, 6" : :
"r" ( value ) :
"memory"
6177#define AARCH32_DBGCLAIMSET_CLAIM( _val ) ( ( _val ) << 0 )
6178#define AARCH32_DBGCLAIMSET_CLAIM_SHIFT 0
6179#define AARCH32_DBGCLAIMSET_CLAIM_MASK 0xffU
6180#define AARCH32_DBGCLAIMSET_CLAIM_GET( _reg ) \
6181 ( ( ( _reg ) >> 0 ) & 0xffU )
6183static inline uint32_t _AArch32_Read_dbgclaimset(
void )
6188 "mrc p14, 0, %0, c7, c8, 6" :
"=&r" ( value ) : :
"memory"
6194static inline void _AArch32_Write_dbgclaimset( uint32_t value )
6197 "mcr p14, 0, %0, c7, c8, 6" : :
"r" ( value ) :
"memory"
6203#define AARCH32_DBGDCCINT_TX 0x20000000U
6205#define AARCH32_DBGDCCINT_RX 0x40000000U
6207static inline uint32_t _AArch32_Read_dbgdccint(
void )
6212 "mrc p14, 0, %0, c0, c2, 0" :
"=&r" ( value ) : :
"memory"
6218static inline void _AArch32_Write_dbgdccint( uint32_t value )
6221 "mcr p14, 0, %0, c0, c2, 0" : :
"r" ( value ) :
"memory"
6227#define AARCH32_DBGDEVID_PCSAMPLE( _val ) ( ( _val ) << 0 )
6228#define AARCH32_DBGDEVID_PCSAMPLE_SHIFT 0
6229#define AARCH32_DBGDEVID_PCSAMPLE_MASK 0xfU
6230#define AARCH32_DBGDEVID_PCSAMPLE_GET( _reg ) \
6231 ( ( ( _reg ) >> 0 ) & 0xfU )
6233#define AARCH32_DBGDEVID_WPADDRMASK( _val ) ( ( _val ) << 4 )
6234#define AARCH32_DBGDEVID_WPADDRMASK_SHIFT 4
6235#define AARCH32_DBGDEVID_WPADDRMASK_MASK 0xf0U
6236#define AARCH32_DBGDEVID_WPADDRMASK_GET( _reg ) \
6237 ( ( ( _reg ) >> 4 ) & 0xfU )
6239#define AARCH32_DBGDEVID_BPADDRMASK( _val ) ( ( _val ) << 8 )
6240#define AARCH32_DBGDEVID_BPADDRMASK_SHIFT 8
6241#define AARCH32_DBGDEVID_BPADDRMASK_MASK 0xf00U
6242#define AARCH32_DBGDEVID_BPADDRMASK_GET( _reg ) \
6243 ( ( ( _reg ) >> 8 ) & 0xfU )
6245#define AARCH32_DBGDEVID_VECTORCATCH( _val ) ( ( _val ) << 12 )
6246#define AARCH32_DBGDEVID_VECTORCATCH_SHIFT 12
6247#define AARCH32_DBGDEVID_VECTORCATCH_MASK 0xf000U
6248#define AARCH32_DBGDEVID_VECTORCATCH_GET( _reg ) \
6249 ( ( ( _reg ) >> 12 ) & 0xfU )
6251#define AARCH32_DBGDEVID_VIRTEXTNS( _val ) ( ( _val ) << 16 )
6252#define AARCH32_DBGDEVID_VIRTEXTNS_SHIFT 16
6253#define AARCH32_DBGDEVID_VIRTEXTNS_MASK 0xf0000U
6254#define AARCH32_DBGDEVID_VIRTEXTNS_GET( _reg ) \
6255 ( ( ( _reg ) >> 16 ) & 0xfU )
6257#define AARCH32_DBGDEVID_DOUBLELOCK( _val ) ( ( _val ) << 20 )
6258#define AARCH32_DBGDEVID_DOUBLELOCK_SHIFT 20
6259#define AARCH32_DBGDEVID_DOUBLELOCK_MASK 0xf00000U
6260#define AARCH32_DBGDEVID_DOUBLELOCK_GET( _reg ) \
6261 ( ( ( _reg ) >> 20 ) & 0xfU )
6263#define AARCH32_DBGDEVID_AUXREGS( _val ) ( ( _val ) << 24 )
6264#define AARCH32_DBGDEVID_AUXREGS_SHIFT 24
6265#define AARCH32_DBGDEVID_AUXREGS_MASK 0xf000000U
6266#define AARCH32_DBGDEVID_AUXREGS_GET( _reg ) \
6267 ( ( ( _reg ) >> 24 ) & 0xfU )
6269#define AARCH32_DBGDEVID_CIDMASK( _val ) ( ( _val ) << 28 )
6270#define AARCH32_DBGDEVID_CIDMASK_SHIFT 28
6271#define AARCH32_DBGDEVID_CIDMASK_MASK 0xf0000000U
6272#define AARCH32_DBGDEVID_CIDMASK_GET( _reg ) \
6273 ( ( ( _reg ) >> 28 ) & 0xfU )
6275static inline uint32_t _AArch32_Read_dbgdevid(
void )
6280 "mrc p14, 0, %0, c7, c2, 7" :
"=&r" ( value ) : :
"memory"
6288#define AARCH32_DBGDEVID1_PCSROFFSET( _val ) ( ( _val ) << 0 )
6289#define AARCH32_DBGDEVID1_PCSROFFSET_SHIFT 0
6290#define AARCH32_DBGDEVID1_PCSROFFSET_MASK 0xfU
6291#define AARCH32_DBGDEVID1_PCSROFFSET_GET( _reg ) \
6292 ( ( ( _reg ) >> 0 ) & 0xfU )
6294static inline uint32_t _AArch32_Read_dbgdevid1(
void )
6299 "mrc p14, 0, %0, c7, c1, 7" :
"=&r" ( value ) : :
"memory"
6307static inline uint32_t _AArch32_Read_dbgdevid2(
void )
6312 "mrc p14, 0, %0, c7, c0, 7" :
"=&r" ( value ) : :
"memory"
6320#define AARCH32_DBGDIDR_SE_IMP 0x1000U
6322#define AARCH32_DBGDIDR_NSUHD_IMP 0x4000U
6324#define AARCH32_DBGDIDR_VERSION( _val ) ( ( _val ) << 16 )
6325#define AARCH32_DBGDIDR_VERSION_SHIFT 16
6326#define AARCH32_DBGDIDR_VERSION_MASK 0xf0000U
6327#define AARCH32_DBGDIDR_VERSION_GET( _reg ) \
6328 ( ( ( _reg ) >> 16 ) & 0xfU )
6330#define AARCH32_DBGDIDR_CTX_CMPS( _val ) ( ( _val ) << 20 )
6331#define AARCH32_DBGDIDR_CTX_CMPS_SHIFT 20
6332#define AARCH32_DBGDIDR_CTX_CMPS_MASK 0xf00000U
6333#define AARCH32_DBGDIDR_CTX_CMPS_GET( _reg ) \
6334 ( ( ( _reg ) >> 20 ) & 0xfU )
6336#define AARCH32_DBGDIDR_BRPS( _val ) ( ( _val ) << 24 )
6337#define AARCH32_DBGDIDR_BRPS_SHIFT 24
6338#define AARCH32_DBGDIDR_BRPS_MASK 0xf000000U
6339#define AARCH32_DBGDIDR_BRPS_GET( _reg ) \
6340 ( ( ( _reg ) >> 24 ) & 0xfU )
6342#define AARCH32_DBGDIDR_WRPS( _val ) ( ( _val ) << 28 )
6343#define AARCH32_DBGDIDR_WRPS_SHIFT 28
6344#define AARCH32_DBGDIDR_WRPS_MASK 0xf0000000U
6345#define AARCH32_DBGDIDR_WRPS_GET( _reg ) \
6346 ( ( ( _reg ) >> 28 ) & 0xfU )
6348static inline uint32_t _AArch32_Read_dbgdidr(
void )
6353 "mrc p14, 0, %0, c0, c0, 0" :
"=&r" ( value ) : :
"memory"
6361#define AARCH32_DBGDRAR_VALID( _val ) ( ( _val ) << 0 )
6362#define AARCH32_DBGDRAR_VALID_SHIFT 0
6363#define AARCH32_DBGDRAR_VALID_MASK 0x3U
6364#define AARCH32_DBGDRAR_VALID_GET( _reg ) \
6365 ( ( ( _reg ) >> 0 ) & 0x3U )
6367#define AARCH32_DBGDRAR_ROMADDR_47_12( _val ) ( ( _val ) << 12 )
6368#define AARCH32_DBGDRAR_ROMADDR_47_12_SHIFT 12
6369#define AARCH32_DBGDRAR_ROMADDR_47_12_MASK 0xfffffffff000ULL
6370#define AARCH32_DBGDRAR_ROMADDR_47_12_GET( _reg ) \
6371 ( ( ( _reg ) >> 12 ) & 0xfffffffffULL )
6373static inline uint32_t _AArch32_Read_32_dbgdrar(
void )
6378 "mrc p14, 0, %0, c1, c0, 0" :
"=&r" ( value ) : :
"memory"
6386static inline uint64_t _AArch32_Read_64_dbgdrar(
void )
6391 "mrrc p14, 0, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
6399static inline uint32_t _AArch32_Read_32_dbgdsar(
void )
6404 "mrc p14, 0, %0, c2, c0, 0" :
"=&r" ( value ) : :
"memory"
6412static inline uint64_t _AArch32_Read_64_dbgdsar(
void )
6417 "mrrc p14, 0, %Q0, %R0, c2" :
"=&r" ( value ) : :
"memory"
6425#define AARCH32_DBGDSCREXT_MOE( _val ) ( ( _val ) << 2 )
6426#define AARCH32_DBGDSCREXT_MOE_SHIFT 2
6427#define AARCH32_DBGDSCREXT_MOE_MASK 0x3cU
6428#define AARCH32_DBGDSCREXT_MOE_GET( _reg ) \
6429 ( ( ( _reg ) >> 2 ) & 0xfU )
6431#define AARCH32_DBGDSCREXT_ERR 0x40U
6433#define AARCH32_DBGDSCREXT_UDCCDIS 0x1000U
6435#define AARCH32_DBGDSCREXT_HDE 0x4000U
6437#define AARCH32_DBGDSCREXT_MDBGEN 0x8000U
6439#define AARCH32_DBGDSCREXT_SPIDDIS 0x10000U
6441#define AARCH32_DBGDSCREXT_SPNIDDIS 0x20000U
6443#define AARCH32_DBGDSCREXT_NS 0x40000U
6445#define AARCH32_DBGDSCREXT_SC2 0x80000U
6447#define AARCH32_DBGDSCREXT_TDA 0x200000U
6449#define AARCH32_DBGDSCREXT_INTDIS( _val ) ( ( _val ) << 22 )
6450#define AARCH32_DBGDSCREXT_INTDIS_SHIFT 22
6451#define AARCH32_DBGDSCREXT_INTDIS_MASK 0xc00000U
6452#define AARCH32_DBGDSCREXT_INTDIS_GET( _reg ) \
6453 ( ( ( _reg ) >> 22 ) & 0x3U )
6455#define AARCH32_DBGDSCREXT_TXU 0x4000000U
6457#define AARCH32_DBGDSCREXT_RXO 0x8000000U
6459#define AARCH32_DBGDSCREXT_TXFULL 0x20000000U
6461#define AARCH32_DBGDSCREXT_RXFULL 0x40000000U
6463#define AARCH32_DBGDSCREXT_TFO 0x80000000U
6465static inline uint32_t _AArch32_Read_dbgdscrext(
void )
6470 "mrc p14, 0, %0, c0, c2, 2" :
"=&r" ( value ) : :
"memory"
6476static inline void _AArch32_Write_dbgdscrext( uint32_t value )
6479 "mcr p14, 0, %0, c0, c2, 2" : :
"r" ( value ) :
"memory"
6485#define AARCH32_DBGDSCRINT_MOE( _val ) ( ( _val ) << 2 )
6486#define AARCH32_DBGDSCRINT_MOE_SHIFT 2
6487#define AARCH32_DBGDSCRINT_MOE_MASK 0x3cU
6488#define AARCH32_DBGDSCRINT_MOE_GET( _reg ) \
6489 ( ( ( _reg ) >> 2 ) & 0xfU )
6491#define AARCH32_DBGDSCRINT_UDCCDIS 0x1000U
6493#define AARCH32_DBGDSCRINT_MDBGEN 0x8000U
6495#define AARCH32_DBGDSCRINT_SPIDDIS 0x10000U
6497#define AARCH32_DBGDSCRINT_SPNIDDIS 0x20000U
6499#define AARCH32_DBGDSCRINT_NS 0x40000U
6501#define AARCH32_DBGDSCRINT_TXFULL 0x20000000U
6503#define AARCH32_DBGDSCRINT_RXFULL 0x40000000U
6505static inline uint32_t _AArch32_Read_dbgdscrint(
void )
6510 "mrc p14, 0, %0, c0, c1, 0" :
"=&r" ( value ) : :
"memory"
6518static inline uint32_t _AArch32_Read_dbgdtrrxext(
void )
6523 "mrc p14, 0, %0, c0, c0, 2" :
"=&r" ( value ) : :
"memory"
6529static inline void _AArch32_Write_dbgdtrrxext( uint32_t value )
6532 "mcr p14, 0, %0, c0, c0, 2" : :
"r" ( value ) :
"memory"
6538static inline uint32_t _AArch32_Read_dbgdtrrxint(
void )
6543 "mrc p14, 0, %0, c0, c5, 0" :
"=&r" ( value ) : :
"memory"
6551static inline uint32_t _AArch32_Read_dbgdtrtxext(
void )
6556 "mrc p14, 0, %0, c0, c3, 2" :
"=&r" ( value ) : :
"memory"
6562static inline void _AArch32_Write_dbgdtrtxext( uint32_t value )
6565 "mcr p14, 0, %0, c0, c3, 2" : :
"r" ( value ) :
"memory"
6571static inline void _AArch32_Write_dbgdtrtxint( uint32_t value )
6574 "mcr p14, 0, %0, c0, c5, 0" : :
"r" ( value ) :
"memory"
6580#define AARCH32_DBGOSDLR_DLK 0x1U
6582static inline uint32_t _AArch32_Read_dbgosdlr(
void )
6587 "mrc p14, 0, %0, c1, c3, 4" :
"=&r" ( value ) : :
"memory"
6593static inline void _AArch32_Write_dbgosdlr( uint32_t value )
6596 "mcr p14, 0, %0, c1, c3, 4" : :
"r" ( value ) :
"memory"
6602static inline uint32_t _AArch32_Read_dbgoseccr(
void )
6607 "mrc p14, 0, %0, c0, c6, 2" :
"=&r" ( value ) : :
"memory"
6613static inline void _AArch32_Write_dbgoseccr( uint32_t value )
6616 "mcr p14, 0, %0, c0, c6, 2" : :
"r" ( value ) :
"memory"
6622static inline void _AArch32_Write_dbgoslar( uint32_t value )
6625 "mcr p14, 0, %0, c1, c0, 4" : :
"r" ( value ) :
"memory"
6631#define AARCH32_DBGOSLSR_OSLM_0 0x1U
6633#define AARCH32_DBGOSLSR_OSLK 0x2U
6635#define AARCH32_DBGOSLSR_NTT 0x4U
6637#define AARCH32_DBGOSLSR_OSLM_1 0x8U
6639static inline uint32_t _AArch32_Read_dbgoslsr(
void )
6644 "mrc p14, 0, %0, c1, c1, 4" :
"=&r" ( value ) : :
"memory"
6652#define AARCH32_DBGPRCR_CORENPDRQ 0x1U
6654static inline uint32_t _AArch32_Read_dbgprcr(
void )
6659 "mrc p14, 0, %0, c1, c4, 4" :
"=&r" ( value ) : :
"memory"
6665static inline void _AArch32_Write_dbgprcr( uint32_t value )
6668 "mcr p14, 0, %0, c1, c4, 4" : :
"r" ( value ) :
"memory"
6674#define AARCH32_DBGVCR_SU 0x2U
6676#define AARCH32_DBGVCR_U 0x2U
6678#define AARCH32_DBGVCR_S 0x4U
6680#define AARCH32_DBGVCR_SS 0x4U
6682#define AARCH32_DBGVCR_P 0x8U
6684#define AARCH32_DBGVCR_SP 0x8U
6686#define AARCH32_DBGVCR_D 0x10U
6688#define AARCH32_DBGVCR_SD 0x10U
6690#define AARCH32_DBGVCR_I 0x40U
6692#define AARCH32_DBGVCR_SI 0x40U
6694#define AARCH32_DBGVCR_F 0x80U
6696#define AARCH32_DBGVCR_SF 0x80U
6698#define AARCH32_DBGVCR_MS 0x400U
6700#define AARCH32_DBGVCR_MP 0x800U
6702#define AARCH32_DBGVCR_MD 0x1000U
6704#define AARCH32_DBGVCR_MI 0x4000U
6706#define AARCH32_DBGVCR_MF 0x8000U
6708#define AARCH32_DBGVCR_NSU 0x2000000U
6710#define AARCH32_DBGVCR_NSS 0x4000000U
6712#define AARCH32_DBGVCR_NSP 0x8000000U
6714#define AARCH32_DBGVCR_NSD 0x10000000U
6716#define AARCH32_DBGVCR_NSI 0x40000000U
6718#define AARCH32_DBGVCR_NSF 0x80000000U
6720static inline uint32_t _AArch32_Read_dbgvcr(
void )
6725 "mrc p14, 0, %0, c0, c7, 0" :
"=&r" ( value ) : :
"memory"
6731static inline void _AArch32_Write_dbgvcr( uint32_t value )
6734 "mcr p14, 0, %0, c0, c7, 0" : :
"r" ( value ) :
"memory"
6740#define AARCH32_DBGWCR_E 0x1U
6742#define AARCH32_DBGWCR_PAC( _val ) ( ( _val ) << 1 )
6743#define AARCH32_DBGWCR_PAC_SHIFT 1
6744#define AARCH32_DBGWCR_PAC_MASK 0x6U
6745#define AARCH32_DBGWCR_PAC_GET( _reg ) \
6746 ( ( ( _reg ) >> 1 ) & 0x3U )
6748#define AARCH32_DBGWCR_LSC( _val ) ( ( _val ) << 3 )
6749#define AARCH32_DBGWCR_LSC_SHIFT 3
6750#define AARCH32_DBGWCR_LSC_MASK 0x18U
6751#define AARCH32_DBGWCR_LSC_GET( _reg ) \
6752 ( ( ( _reg ) >> 3 ) & 0x3U )
6754#define AARCH32_DBGWCR_BAS( _val ) ( ( _val ) << 5 )
6755#define AARCH32_DBGWCR_BAS_SHIFT 5
6756#define AARCH32_DBGWCR_BAS_MASK 0x1fe0U
6757#define AARCH32_DBGWCR_BAS_GET( _reg ) \
6758 ( ( ( _reg ) >> 5 ) & 0xffU )
6760#define AARCH32_DBGWCR_HMC 0x2000U
6762#define AARCH32_DBGWCR_SSC( _val ) ( ( _val ) << 14 )
6763#define AARCH32_DBGWCR_SSC_SHIFT 14
6764#define AARCH32_DBGWCR_SSC_MASK 0xc000U
6765#define AARCH32_DBGWCR_SSC_GET( _reg ) \
6766 ( ( ( _reg ) >> 14 ) & 0x3U )
6768#define AARCH32_DBGWCR_LBN( _val ) ( ( _val ) << 16 )
6769#define AARCH32_DBGWCR_LBN_SHIFT 16
6770#define AARCH32_DBGWCR_LBN_MASK 0xf0000U
6771#define AARCH32_DBGWCR_LBN_GET( _reg ) \
6772 ( ( ( _reg ) >> 16 ) & 0xfU )
6774#define AARCH32_DBGWCR_WT 0x100000U
6776#define AARCH32_DBGWCR_MASK( _val ) ( ( _val ) << 24 )
6777#define AARCH32_DBGWCR_MASK_SHIFT 24
6778#define AARCH32_DBGWCR_MASK_MASK 0x1f000000U
6779#define AARCH32_DBGWCR_MASK_GET( _reg ) \
6780 ( ( ( _reg ) >> 24 ) & 0x1fU )
6784static inline uint32_t _AArch32_Read_dbgwcr_0(
void )
6789 "mrc p14, 0, %0, c0, c0, 7" :
"=&r" ( value ) : :
"memory"
6795static inline void _AArch32_Write_dbgwcr_0( uint32_t value )
6798 "mcr p14, 0, %0, c0, c0, 7" : :
"r" ( value ) :
"memory"
6804static inline uint32_t _AArch32_Read_dbgwcr_1(
void )
6809 "mrc p14, 0, %0, c0, c1, 7" :
"=&r" ( value ) : :
"memory"
6815static inline void _AArch32_Write_dbgwcr_1( uint32_t value )
6818 "mcr p14, 0, %0, c0, c1, 7" : :
"r" ( value ) :
"memory"
6824static inline uint32_t _AArch32_Read_dbgwcr_2(
void )
6829 "mrc p14, 0, %0, c0, c2, 7" :
"=&r" ( value ) : :
"memory"
6835static inline void _AArch32_Write_dbgwcr_2( uint32_t value )
6838 "mcr p14, 0, %0, c0, c2, 7" : :
"r" ( value ) :
"memory"
6844static inline uint32_t _AArch32_Read_dbgwcr_3(
void )
6849 "mrc p14, 0, %0, c0, c3, 7" :
"=&r" ( value ) : :
"memory"
6855static inline void _AArch32_Write_dbgwcr_3( uint32_t value )
6858 "mcr p14, 0, %0, c0, c3, 7" : :
"r" ( value ) :
"memory"
6864static inline uint32_t _AArch32_Read_dbgwcr_4(
void )
6869 "mrc p14, 0, %0, c0, c4, 7" :
"=&r" ( value ) : :
"memory"
6875static inline void _AArch32_Write_dbgwcr_4( uint32_t value )
6878 "mcr p14, 0, %0, c0, c4, 7" : :
"r" ( value ) :
"memory"
6884static inline uint32_t _AArch32_Read_dbgwcr_5(
void )
6889 "mrc p14, 0, %0, c0, c5, 7" :
"=&r" ( value ) : :
"memory"
6895static inline void _AArch32_Write_dbgwcr_5( uint32_t value )
6898 "mcr p14, 0, %0, c0, c5, 7" : :
"r" ( value ) :
"memory"
6904static inline uint32_t _AArch32_Read_dbgwcr_6(
void )
6909 "mrc p14, 0, %0, c0, c6, 7" :
"=&r" ( value ) : :
"memory"
6915static inline void _AArch32_Write_dbgwcr_6( uint32_t value )
6918 "mcr p14, 0, %0, c0, c6, 7" : :
"r" ( value ) :
"memory"
6924static inline uint32_t _AArch32_Read_dbgwcr_7(
void )
6929 "mrc p14, 0, %0, c0, c7, 7" :
"=&r" ( value ) : :
"memory"
6935static inline void _AArch32_Write_dbgwcr_7( uint32_t value )
6938 "mcr p14, 0, %0, c0, c7, 7" : :
"r" ( value ) :
"memory"
6944static inline uint32_t _AArch32_Read_dbgwcr_8(
void )
6949 "mrc p14, 0, %0, c0, c8, 7" :
"=&r" ( value ) : :
"memory"
6955static inline void _AArch32_Write_dbgwcr_8( uint32_t value )
6958 "mcr p14, 0, %0, c0, c8, 7" : :
"r" ( value ) :
"memory"
6964static inline uint32_t _AArch32_Read_dbgwcr_9(
void )
6969 "mrc p14, 0, %0, c0, c9, 7" :
"=&r" ( value ) : :
"memory"
6975static inline void _AArch32_Write_dbgwcr_9( uint32_t value )
6978 "mcr p14, 0, %0, c0, c9, 7" : :
"r" ( value ) :
"memory"
6984static inline uint32_t _AArch32_Read_dbgwcr_10(
void )
6989 "mrc p14, 0, %0, c0, c10, 7" :
"=&r" ( value ) : :
"memory"
6995static inline void _AArch32_Write_dbgwcr_10( uint32_t value )
6998 "mcr p14, 0, %0, c0, c10, 7" : :
"r" ( value ) :
"memory"
7004static inline uint32_t _AArch32_Read_dbgwcr_11(
void )
7009 "mrc p14, 0, %0, c0, c11, 7" :
"=&r" ( value ) : :
"memory"
7015static inline void _AArch32_Write_dbgwcr_11( uint32_t value )
7018 "mcr p14, 0, %0, c0, c11, 7" : :
"r" ( value ) :
"memory"
7024static inline uint32_t _AArch32_Read_dbgwcr_12(
void )
7029 "mrc p14, 0, %0, c0, c12, 7" :
"=&r" ( value ) : :
"memory"
7035static inline void _AArch32_Write_dbgwcr_12( uint32_t value )
7038 "mcr p14, 0, %0, c0, c12, 7" : :
"r" ( value ) :
"memory"
7044static inline uint32_t _AArch32_Read_dbgwcr_13(
void )
7049 "mrc p14, 0, %0, c0, c13, 7" :
"=&r" ( value ) : :
"memory"
7055static inline void _AArch32_Write_dbgwcr_13( uint32_t value )
7058 "mcr p14, 0, %0, c0, c13, 7" : :
"r" ( value ) :
"memory"
7064static inline uint32_t _AArch32_Read_dbgwcr_14(
void )
7069 "mrc p14, 0, %0, c0, c14, 7" :
"=&r" ( value ) : :
"memory"
7075static inline void _AArch32_Write_dbgwcr_14( uint32_t value )
7078 "mcr p14, 0, %0, c0, c14, 7" : :
"r" ( value ) :
"memory"
7084static inline uint32_t _AArch32_Read_dbgwcr_15(
void )
7089 "mrc p14, 0, %0, c0, c15, 7" :
"=&r" ( value ) : :
"memory"
7095static inline void _AArch32_Write_dbgwcr_15( uint32_t value )
7098 "mcr p14, 0, %0, c0, c15, 7" : :
"r" ( value ) :
"memory"
7104static inline uint32_t _AArch32_Read_dbgwfar(
void )
7109 "mrc p14, 0, %0, c0, c6, 0" :
"=&r" ( value ) : :
"memory"
7115static inline void _AArch32_Write_dbgwfar( uint32_t value )
7118 "mcr p14, 0, %0, c0, c6, 0" : :
"r" ( value ) :
"memory"
7124#define AARCH32_DBGWVR_VA( _val ) ( ( _val ) << 2 )
7125#define AARCH32_DBGWVR_VA_SHIFT 2
7126#define AARCH32_DBGWVR_VA_MASK 0xfffffffcU
7127#define AARCH32_DBGWVR_VA_GET( _reg ) \
7128 ( ( ( _reg ) >> 2 ) & 0x3fffffffU )
7132static inline uint32_t _AArch32_Read_dbgwvr_0(
void )
7137 "mrc p14, 0, %0, c0, c0, 6" :
"=&r" ( value ) : :
"memory"
7143static inline void _AArch32_Write_dbgwvr_0( uint32_t value )
7146 "mcr p14, 0, %0, c0, c0, 6" : :
"r" ( value ) :
"memory"
7152static inline uint32_t _AArch32_Read_dbgwvr_1(
void )
7157 "mrc p14, 0, %0, c0, c1, 6" :
"=&r" ( value ) : :
"memory"
7163static inline void _AArch32_Write_dbgwvr_1( uint32_t value )
7166 "mcr p14, 0, %0, c0, c1, 6" : :
"r" ( value ) :
"memory"
7172static inline uint32_t _AArch32_Read_dbgwvr_2(
void )
7177 "mrc p14, 0, %0, c0, c2, 6" :
"=&r" ( value ) : :
"memory"
7183static inline void _AArch32_Write_dbgwvr_2( uint32_t value )
7186 "mcr p14, 0, %0, c0, c2, 6" : :
"r" ( value ) :
"memory"
7192static inline uint32_t _AArch32_Read_dbgwvr_3(
void )
7197 "mrc p14, 0, %0, c0, c3, 6" :
"=&r" ( value ) : :
"memory"
7203static inline void _AArch32_Write_dbgwvr_3( uint32_t value )
7206 "mcr p14, 0, %0, c0, c3, 6" : :
"r" ( value ) :
"memory"
7212static inline uint32_t _AArch32_Read_dbgwvr_4(
void )
7217 "mrc p14, 0, %0, c0, c4, 6" :
"=&r" ( value ) : :
"memory"
7223static inline void _AArch32_Write_dbgwvr_4( uint32_t value )
7226 "mcr p14, 0, %0, c0, c4, 6" : :
"r" ( value ) :
"memory"
7232static inline uint32_t _AArch32_Read_dbgwvr_5(
void )
7237 "mrc p14, 0, %0, c0, c5, 6" :
"=&r" ( value ) : :
"memory"
7243static inline void _AArch32_Write_dbgwvr_5( uint32_t value )
7246 "mcr p14, 0, %0, c0, c5, 6" : :
"r" ( value ) :
"memory"
7252static inline uint32_t _AArch32_Read_dbgwvr_6(
void )
7257 "mrc p14, 0, %0, c0, c6, 6" :
"=&r" ( value ) : :
"memory"
7263static inline void _AArch32_Write_dbgwvr_6( uint32_t value )
7266 "mcr p14, 0, %0, c0, c6, 6" : :
"r" ( value ) :
"memory"
7272static inline uint32_t _AArch32_Read_dbgwvr_7(
void )
7277 "mrc p14, 0, %0, c0, c7, 6" :
"=&r" ( value ) : :
"memory"
7283static inline void _AArch32_Write_dbgwvr_7( uint32_t value )
7286 "mcr p14, 0, %0, c0, c7, 6" : :
"r" ( value ) :
"memory"
7292static inline uint32_t _AArch32_Read_dbgwvr_8(
void )
7297 "mrc p14, 0, %0, c0, c8, 6" :
"=&r" ( value ) : :
"memory"
7303static inline void _AArch32_Write_dbgwvr_8( uint32_t value )
7306 "mcr p14, 0, %0, c0, c8, 6" : :
"r" ( value ) :
"memory"
7312static inline uint32_t _AArch32_Read_dbgwvr_9(
void )
7317 "mrc p14, 0, %0, c0, c9, 6" :
"=&r" ( value ) : :
"memory"
7323static inline void _AArch32_Write_dbgwvr_9( uint32_t value )
7326 "mcr p14, 0, %0, c0, c9, 6" : :
"r" ( value ) :
"memory"
7332static inline uint32_t _AArch32_Read_dbgwvr_10(
void )
7337 "mrc p14, 0, %0, c0, c10, 6" :
"=&r" ( value ) : :
"memory"
7343static inline void _AArch32_Write_dbgwvr_10( uint32_t value )
7346 "mcr p14, 0, %0, c0, c10, 6" : :
"r" ( value ) :
"memory"
7352static inline uint32_t _AArch32_Read_dbgwvr_11(
void )
7357 "mrc p14, 0, %0, c0, c11, 6" :
"=&r" ( value ) : :
"memory"
7363static inline void _AArch32_Write_dbgwvr_11( uint32_t value )
7366 "mcr p14, 0, %0, c0, c11, 6" : :
"r" ( value ) :
"memory"
7372static inline uint32_t _AArch32_Read_dbgwvr_12(
void )
7377 "mrc p14, 0, %0, c0, c12, 6" :
"=&r" ( value ) : :
"memory"
7383static inline void _AArch32_Write_dbgwvr_12( uint32_t value )
7386 "mcr p14, 0, %0, c0, c12, 6" : :
"r" ( value ) :
"memory"
7392static inline uint32_t _AArch32_Read_dbgwvr_13(
void )
7397 "mrc p14, 0, %0, c0, c13, 6" :
"=&r" ( value ) : :
"memory"
7403static inline void _AArch32_Write_dbgwvr_13( uint32_t value )
7406 "mcr p14, 0, %0, c0, c13, 6" : :
"r" ( value ) :
"memory"
7412static inline uint32_t _AArch32_Read_dbgwvr_14(
void )
7417 "mrc p14, 0, %0, c0, c14, 6" :
"=&r" ( value ) : :
"memory"
7423static inline void _AArch32_Write_dbgwvr_14( uint32_t value )
7426 "mcr p14, 0, %0, c0, c14, 6" : :
"r" ( value ) :
"memory"
7432static inline uint32_t _AArch32_Read_dbgwvr_15(
void )
7437 "mrc p14, 0, %0, c0, c15, 6" :
"=&r" ( value ) : :
"memory"
7443static inline void _AArch32_Write_dbgwvr_15( uint32_t value )
7446 "mcr p14, 0, %0, c0, c15, 6" : :
"r" ( value ) :
"memory"
7452static inline uint32_t _AArch32_Read_dlr(
void )
7457 "mrc p15, 3, %0, c4, c5, 1" :
"=&r" ( value ) : :
"memory"
7463static inline void _AArch32_Write_dlr( uint32_t value )
7466 "mcr p15, 3, %0, c4, c5, 1" : :
"r" ( value ) :
"memory"
7472#define AARCH32_DSPSR_M_4_0( _val ) ( ( _val ) << 0 )
7473#define AARCH32_DSPSR_M_4_0_SHIFT 0
7474#define AARCH32_DSPSR_M_4_0_MASK 0x1fU
7475#define AARCH32_DSPSR_M_4_0_GET( _reg ) \
7476 ( ( ( _reg ) >> 0 ) & 0x1fU )
7478#define AARCH32_DSPSR_T 0x20U
7480#define AARCH32_DSPSR_F 0x40U
7482#define AARCH32_DSPSR_I 0x80U
7484#define AARCH32_DSPSR_A 0x100U
7486#define AARCH32_DSPSR_E 0x200U
7488#define AARCH32_DSPSR_IT_7_2( _val ) ( ( _val ) << 10 )
7489#define AARCH32_DSPSR_IT_7_2_SHIFT 10
7490#define AARCH32_DSPSR_IT_7_2_MASK 0xfc00U
7491#define AARCH32_DSPSR_IT_7_2_GET( _reg ) \
7492 ( ( ( _reg ) >> 10 ) & 0x3fU )
7494#define AARCH32_DSPSR_GE( _val ) ( ( _val ) << 16 )
7495#define AARCH32_DSPSR_GE_SHIFT 16
7496#define AARCH32_DSPSR_GE_MASK 0xf0000U
7497#define AARCH32_DSPSR_GE_GET( _reg ) \
7498 ( ( ( _reg ) >> 16 ) & 0xfU )
7500#define AARCH32_DSPSR_IL 0x100000U
7502#define AARCH32_DSPSR_SS 0x200000U
7504#define AARCH32_DSPSR_PAN 0x400000U
7506#define AARCH32_DSPSR_SSBS 0x800000U
7508#define AARCH32_DSPSR_DIT 0x1000000U
7510#define AARCH32_DSPSR_IT_1_0( _val ) ( ( _val ) << 25 )
7511#define AARCH32_DSPSR_IT_1_0_SHIFT 25
7512#define AARCH32_DSPSR_IT_1_0_MASK 0x6000000U
7513#define AARCH32_DSPSR_IT_1_0_GET( _reg ) \
7514 ( ( ( _reg ) >> 25 ) & 0x3U )
7516#define AARCH32_DSPSR_Q 0x8000000U
7518#define AARCH32_DSPSR_V 0x10000000U
7520#define AARCH32_DSPSR_C 0x20000000U
7522#define AARCH32_DSPSR_Z 0x40000000U
7524#define AARCH32_DSPSR_N 0x80000000U
7526static inline uint32_t _AArch32_Read_dspsr(
void )
7531 "mrc p15, 3, %0, c4, c5, 0" :
"=&r" ( value ) : :
"memory"
7537static inline void _AArch32_Write_dspsr( uint32_t value )
7540 "mcr p15, 3, %0, c4, c5, 0" : :
"r" ( value ) :
"memory"
7546#define AARCH32_HDCR_HPMN( _val ) ( ( _val ) << 0 )
7547#define AARCH32_HDCR_HPMN_SHIFT 0
7548#define AARCH32_HDCR_HPMN_MASK 0x1fU
7549#define AARCH32_HDCR_HPMN_GET( _reg ) \
7550 ( ( ( _reg ) >> 0 ) & 0x1fU )
7552#define AARCH32_HDCR_TPMCR 0x20U
7554#define AARCH32_HDCR_TPM 0x40U
7556#define AARCH32_HDCR_HPME 0x80U
7558#define AARCH32_HDCR_TDE 0x100U
7560#define AARCH32_HDCR_TDA 0x200U
7562#define AARCH32_HDCR_TDOSA 0x400U
7564#define AARCH32_HDCR_TDRA 0x800U
7566#define AARCH32_HDCR_HPMD 0x20000U
7568#define AARCH32_HDCR_TTRF 0x80000U
7570#define AARCH32_HDCR_HCCD 0x800000U
7572#define AARCH32_HDCR_HLP 0x4000000U
7574#define AARCH32_HDCR_TDCC 0x8000000U
7576#define AARCH32_HDCR_MTPME 0x10000000U
7578static inline uint32_t _AArch32_Read_hdcr(
void )
7583 "mrc p15, 4, %0, c1, c1, 1" :
"=&r" ( value ) : :
"memory"
7589static inline void _AArch32_Write_hdcr( uint32_t value )
7592 "mcr p15, 4, %0, c1, c1, 1" : :
"r" ( value ) :
"memory"
7598#define AARCH32_HTRFCR_E0HTRE 0x1U
7600#define AARCH32_HTRFCR_E2TRE 0x2U
7602#define AARCH32_HTRFCR_CX 0x8U
7604#define AARCH32_HTRFCR_TS( _val ) ( ( _val ) << 5 )
7605#define AARCH32_HTRFCR_TS_SHIFT 5
7606#define AARCH32_HTRFCR_TS_MASK 0x60U
7607#define AARCH32_HTRFCR_TS_GET( _reg ) \
7608 ( ( ( _reg ) >> 5 ) & 0x3U )
7610static inline uint32_t _AArch32_Read_htrfcr(
void )
7615 "mrc p15, 4, %0, c1, c2, 1" :
"=&r" ( value ) : :
"memory"
7621static inline void _AArch32_Write_htrfcr( uint32_t value )
7624 "mcr p15, 4, %0, c1, c2, 1" : :
"r" ( value ) :
"memory"
7630#define AARCH32_PMMIR_SLOTS( _val ) ( ( _val ) << 0 )
7631#define AARCH32_PMMIR_SLOTS_SHIFT 0
7632#define AARCH32_PMMIR_SLOTS_MASK 0xffU
7633#define AARCH32_PMMIR_SLOTS_GET( _reg ) \
7634 ( ( ( _reg ) >> 0 ) & 0xffU )
7636static inline uint32_t _AArch32_Read_pmmir(
void )
7641 "mrc p15, 0, %0, c9, c14, 6" :
"=&r" ( value ) : :
"memory"
7649#define AARCH32_SDCR_SPD( _val ) ( ( _val ) << 14 )
7650#define AARCH32_SDCR_SPD_SHIFT 14
7651#define AARCH32_SDCR_SPD_MASK 0xc000U
7652#define AARCH32_SDCR_SPD_GET( _reg ) \
7653 ( ( ( _reg ) >> 14 ) & 0x3U )
7655#define AARCH32_SDCR_SPME 0x20000U
7657#define AARCH32_SDCR_STE 0x40000U
7659#define AARCH32_SDCR_TTRF 0x80000U
7661#define AARCH32_SDCR_EDAD 0x100000U
7663#define AARCH32_SDCR_EPMAD 0x200000U
7665#define AARCH32_SDCR_SCCD 0x800000U
7667#define AARCH32_SDCR_TDCC 0x8000000U
7669#define AARCH32_SDCR_MTPME 0x10000000U
7671static inline uint32_t _AArch32_Read_sdcr(
void )
7676 "mrc p15, 0, %0, c1, c3, 1" :
"=&r" ( value ) : :
"memory"
7682static inline void _AArch32_Write_sdcr( uint32_t value )
7685 "mcr p15, 0, %0, c1, c3, 1" : :
"r" ( value ) :
"memory"
7691#define AARCH32_SDER_SUIDEN 0x1U
7693#define AARCH32_SDER_SUNIDEN 0x2U
7695static inline uint32_t _AArch32_Read_sder(
void )
7700 "mrc p15, 0, %0, c1, c1, 1" :
"=&r" ( value ) : :
"memory"
7706static inline void _AArch32_Write_sder( uint32_t value )
7709 "mcr p15, 0, %0, c1, c1, 1" : :
"r" ( value ) :
"memory"
7715#define AARCH32_TRFCR_E0TRE 0x1U
7717#define AARCH32_TRFCR_E1TRE 0x2U
7719#define AARCH32_TRFCR_TS( _val ) ( ( _val ) << 5 )
7720#define AARCH32_TRFCR_TS_SHIFT 5
7721#define AARCH32_TRFCR_TS_MASK 0x60U
7722#define AARCH32_TRFCR_TS_GET( _reg ) \
7723 ( ( ( _reg ) >> 5 ) & 0x3U )
7725static inline uint32_t _AArch32_Read_trfcr(
void )
7730 "mrc p15, 0, %0, c1, c2, 1" :
"=&r" ( value ) : :
"memory"
7736static inline void _AArch32_Write_trfcr( uint32_t value )
7739 "mcr p15, 0, %0, c1, c2, 1" : :
"r" ( value ) :
"memory"
7745#define AARCH32_PMCCFILTR_NSH 0x8000000U
7747#define AARCH32_PMCCFILTR_NSU 0x10000000U
7749#define AARCH32_PMCCFILTR_NSK 0x20000000U
7751#define AARCH32_PMCCFILTR_U 0x40000000U
7753#define AARCH32_PMCCFILTR_P 0x80000000U
7755static inline uint32_t _AArch32_Read_pmccfiltr(
void )
7760 "mrc p15, 0, %0, c14, c15, 7" :
"=&r" ( value ) : :
"memory"
7766static inline void _AArch32_Write_pmccfiltr( uint32_t value )
7769 "mcr p15, 0, %0, c14, c15, 7" : :
"r" ( value ) :
"memory"
7775#define AARCH32_PMCCNTR_CCNT( _val ) ( ( _val ) << 0 )
7776#define AARCH32_PMCCNTR_CCNT_SHIFT 0
7777#define AARCH32_PMCCNTR_CCNT_MASK 0xffffffffffffffffULL
7778#define AARCH32_PMCCNTR_CCNT_GET( _reg ) \
7779 ( ( ( _reg ) >> 0 ) & 0xffffffffffffffffULL )
7781static inline uint32_t _AArch32_Read_32_pmccntr(
void )
7786 "mrc p15, 0, %0, c9, c13, 0" :
"=&r" ( value ) : :
"memory"
7792static inline void _AArch32_Write_32_pmccntr( uint32_t value )
7795 "mcr p15, 0, %0, c9, c13, 0" : :
"r" ( value ) :
"memory"
7801static inline uint64_t _AArch32_Read_64_pmccntr(
void )
7806 "mrrc p15, 0, %Q0, %R0, c9" :
"=&r" ( value ) : :
"memory"
7812static inline void _AArch32_Write_64_pmccntr( uint64_t value )
7815 "mcrr p15, 0, %Q0, %R0, c9" : :
"r" ( value ) :
"memory"
7821static inline uint32_t _AArch32_Read_pmceid0(
void )
7826 "mrc p15, 0, %0, c9, c12, 6" :
"=&r" ( value ) : :
"memory"
7834static inline uint32_t _AArch32_Read_pmceid1(
void )
7839 "mrc p15, 0, %0, c9, c12, 7" :
"=&r" ( value ) : :
"memory"
7847static inline uint32_t _AArch32_Read_pmceid2(
void )
7852 "mrc p15, 0, %0, c9, c14, 4" :
"=&r" ( value ) : :
"memory"
7860static inline uint32_t _AArch32_Read_pmceid3(
void )
7865 "mrc p15, 0, %0, c9, c14, 5" :
"=&r" ( value ) : :
"memory"
7873#define AARCH32_PMCNTENCLR_C 0x80000000U
7875static inline uint32_t _AArch32_Read_pmcntenclr(
void )
7880 "mrc p15, 0, %0, c9, c12, 2" :
"=&r" ( value ) : :
"memory"
7886static inline void _AArch32_Write_pmcntenclr( uint32_t value )
7889 "mcr p15, 0, %0, c9, c12, 2" : :
"r" ( value ) :
"memory"
7895#define AARCH32_PMCNTENSET_C 0x80000000U
7897static inline uint32_t _AArch32_Read_pmcntenset(
void )
7902 "mrc p15, 0, %0, c9, c12, 1" :
"=&r" ( value ) : :
"memory"
7908static inline void _AArch32_Write_pmcntenset( uint32_t value )
7911 "mcr p15, 0, %0, c9, c12, 1" : :
"r" ( value ) :
"memory"
7917#define AARCH32_PMCR_E 0x1U
7919#define AARCH32_PMCR_P 0x2U
7921#define AARCH32_PMCR_C 0x4U
7923#define AARCH32_PMCR_D 0x8U
7925#define AARCH32_PMCR_X 0x10U
7927#define AARCH32_PMCR_DP 0x20U
7929#define AARCH32_PMCR_LC 0x40U
7931#define AARCH32_PMCR_LP 0x80U
7933#define AARCH32_PMCR_N( _val ) ( ( _val ) << 11 )
7934#define AARCH32_PMCR_N_SHIFT 11
7935#define AARCH32_PMCR_N_MASK 0xf800U
7936#define AARCH32_PMCR_N_GET( _reg ) \
7937 ( ( ( _reg ) >> 11 ) & 0x1fU )
7939#define AARCH32_PMCR_IDCODE( _val ) ( ( _val ) << 16 )
7940#define AARCH32_PMCR_IDCODE_SHIFT 16
7941#define AARCH32_PMCR_IDCODE_MASK 0xff0000U
7942#define AARCH32_PMCR_IDCODE_GET( _reg ) \
7943 ( ( ( _reg ) >> 16 ) & 0xffU )
7945#define AARCH32_PMCR_IMP( _val ) ( ( _val ) << 24 )
7946#define AARCH32_PMCR_IMP_SHIFT 24
7947#define AARCH32_PMCR_IMP_MASK 0xff000000U
7948#define AARCH32_PMCR_IMP_GET( _reg ) \
7949 ( ( ( _reg ) >> 24 ) & 0xffU )
7951static inline uint32_t _AArch32_Read_pmcr(
void )
7956 "mrc p15, 0, %0, c9, c12, 0" :
"=&r" ( value ) : :
"memory"
7962static inline void _AArch32_Write_pmcr( uint32_t value )
7965 "mcr p15, 0, %0, c9, c12, 0" : :
"r" ( value ) :
"memory"
7971static inline uint32_t _AArch32_Read_pmevcntr_0(
void )
7976 "mrc p15, 0, %0, c14, c8, 0" :
"=&r" ( value ) : :
"memory"
7982static inline void _AArch32_Write_pmevcntr_0( uint32_t value )
7985 "mcr p15, 0, %0, c14, c8, 0" : :
"r" ( value ) :
"memory"
7991static inline uint32_t _AArch32_Read_pmevcntr_1(
void )
7996 "mrc p15, 0, %0, c14, c8, 1" :
"=&r" ( value ) : :
"memory"
8002static inline void _AArch32_Write_pmevcntr_1( uint32_t value )
8005 "mcr p15, 0, %0, c14, c8, 1" : :
"r" ( value ) :
"memory"
8011static inline uint32_t _AArch32_Read_pmevcntr_2(
void )
8016 "mrc p15, 0, %0, c14, c8, 2" :
"=&r" ( value ) : :
"memory"
8022static inline void _AArch32_Write_pmevcntr_2( uint32_t value )
8025 "mcr p15, 0, %0, c14, c8, 2" : :
"r" ( value ) :
"memory"
8031static inline uint32_t _AArch32_Read_pmevcntr_3(
void )
8036 "mrc p15, 0, %0, c14, c8, 3" :
"=&r" ( value ) : :
"memory"
8042static inline void _AArch32_Write_pmevcntr_3( uint32_t value )
8045 "mcr p15, 0, %0, c14, c8, 3" : :
"r" ( value ) :
"memory"
8051static inline uint32_t _AArch32_Read_pmevcntr_4(
void )
8056 "mrc p15, 0, %0, c14, c8, 4" :
"=&r" ( value ) : :
"memory"
8062static inline void _AArch32_Write_pmevcntr_4( uint32_t value )
8065 "mcr p15, 0, %0, c14, c8, 4" : :
"r" ( value ) :
"memory"
8071static inline uint32_t _AArch32_Read_pmevcntr_5(
void )
8076 "mrc p15, 0, %0, c14, c8, 5" :
"=&r" ( value ) : :
"memory"
8082static inline void _AArch32_Write_pmevcntr_5( uint32_t value )
8085 "mcr p15, 0, %0, c14, c8, 5" : :
"r" ( value ) :
"memory"
8091static inline uint32_t _AArch32_Read_pmevcntr_6(
void )
8096 "mrc p15, 0, %0, c14, c8, 6" :
"=&r" ( value ) : :
"memory"
8102static inline void _AArch32_Write_pmevcntr_6( uint32_t value )
8105 "mcr p15, 0, %0, c14, c8, 6" : :
"r" ( value ) :
"memory"
8111static inline uint32_t _AArch32_Read_pmevcntr_7(
void )
8116 "mrc p15, 0, %0, c14, c8, 7" :
"=&r" ( value ) : :
"memory"
8122static inline void _AArch32_Write_pmevcntr_7( uint32_t value )
8125 "mcr p15, 0, %0, c14, c8, 7" : :
"r" ( value ) :
"memory"
8131static inline uint32_t _AArch32_Read_pmevcntr_8(
void )
8136 "mrc p15, 0, %0, c14, c9, 0" :
"=&r" ( value ) : :
"memory"
8142static inline void _AArch32_Write_pmevcntr_8( uint32_t value )
8145 "mcr p15, 0, %0, c14, c9, 0" : :
"r" ( value ) :
"memory"
8151static inline uint32_t _AArch32_Read_pmevcntr_9(
void )
8156 "mrc p15, 0, %0, c14, c9, 1" :
"=&r" ( value ) : :
"memory"
8162static inline void _AArch32_Write_pmevcntr_9( uint32_t value )
8165 "mcr p15, 0, %0, c14, c9, 1" : :
"r" ( value ) :
"memory"
8171static inline uint32_t _AArch32_Read_pmevcntr_10(
void )
8176 "mrc p15, 0, %0, c14, c9, 2" :
"=&r" ( value ) : :
"memory"
8182static inline void _AArch32_Write_pmevcntr_10( uint32_t value )
8185 "mcr p15, 0, %0, c14, c9, 2" : :
"r" ( value ) :
"memory"
8191static inline uint32_t _AArch32_Read_pmevcntr_11(
void )
8196 "mrc p15, 0, %0, c14, c9, 3" :
"=&r" ( value ) : :
"memory"
8202static inline void _AArch32_Write_pmevcntr_11( uint32_t value )
8205 "mcr p15, 0, %0, c14, c9, 3" : :
"r" ( value ) :
"memory"
8211static inline uint32_t _AArch32_Read_pmevcntr_12(
void )
8216 "mrc p15, 0, %0, c14, c9, 4" :
"=&r" ( value ) : :
"memory"
8222static inline void _AArch32_Write_pmevcntr_12( uint32_t value )
8225 "mcr p15, 0, %0, c14, c9, 4" : :
"r" ( value ) :
"memory"
8231static inline uint32_t _AArch32_Read_pmevcntr_13(
void )
8236 "mrc p15, 0, %0, c14, c9, 5" :
"=&r" ( value ) : :
"memory"
8242static inline void _AArch32_Write_pmevcntr_13( uint32_t value )
8245 "mcr p15, 0, %0, c14, c9, 5" : :
"r" ( value ) :
"memory"
8251static inline uint32_t _AArch32_Read_pmevcntr_14(
void )
8256 "mrc p15, 0, %0, c14, c9, 6" :
"=&r" ( value ) : :
"memory"
8262static inline void _AArch32_Write_pmevcntr_14( uint32_t value )
8265 "mcr p15, 0, %0, c14, c9, 6" : :
"r" ( value ) :
"memory"
8271static inline uint32_t _AArch32_Read_pmevcntr_15(
void )
8276 "mrc p15, 0, %0, c14, c9, 7" :
"=&r" ( value ) : :
"memory"
8282static inline void _AArch32_Write_pmevcntr_15( uint32_t value )
8285 "mcr p15, 0, %0, c14, c9, 7" : :
"r" ( value ) :
"memory"
8291static inline uint32_t _AArch32_Read_pmevcntr_16(
void )
8296 "mrc p15, 0, %0, c14, c10, 0" :
"=&r" ( value ) : :
"memory"
8302static inline void _AArch32_Write_pmevcntr_16( uint32_t value )
8305 "mcr p15, 0, %0, c14, c10, 0" : :
"r" ( value ) :
"memory"
8311static inline uint32_t _AArch32_Read_pmevcntr_17(
void )
8316 "mrc p15, 0, %0, c14, c10, 1" :
"=&r" ( value ) : :
"memory"
8322static inline void _AArch32_Write_pmevcntr_17( uint32_t value )
8325 "mcr p15, 0, %0, c14, c10, 1" : :
"r" ( value ) :
"memory"
8331static inline uint32_t _AArch32_Read_pmevcntr_18(
void )
8336 "mrc p15, 0, %0, c14, c10, 2" :
"=&r" ( value ) : :
"memory"
8342static inline void _AArch32_Write_pmevcntr_18( uint32_t value )
8345 "mcr p15, 0, %0, c14, c10, 2" : :
"r" ( value ) :
"memory"
8351static inline uint32_t _AArch32_Read_pmevcntr_19(
void )
8356 "mrc p15, 0, %0, c14, c10, 3" :
"=&r" ( value ) : :
"memory"
8362static inline void _AArch32_Write_pmevcntr_19( uint32_t value )
8365 "mcr p15, 0, %0, c14, c10, 3" : :
"r" ( value ) :
"memory"
8371static inline uint32_t _AArch32_Read_pmevcntr_20(
void )
8376 "mrc p15, 0, %0, c14, c10, 4" :
"=&r" ( value ) : :
"memory"
8382static inline void _AArch32_Write_pmevcntr_20( uint32_t value )
8385 "mcr p15, 0, %0, c14, c10, 4" : :
"r" ( value ) :
"memory"
8391static inline uint32_t _AArch32_Read_pmevcntr_21(
void )
8396 "mrc p15, 0, %0, c14, c10, 5" :
"=&r" ( value ) : :
"memory"
8402static inline void _AArch32_Write_pmevcntr_21( uint32_t value )
8405 "mcr p15, 0, %0, c14, c10, 5" : :
"r" ( value ) :
"memory"
8411static inline uint32_t _AArch32_Read_pmevcntr_22(
void )
8416 "mrc p15, 0, %0, c14, c10, 6" :
"=&r" ( value ) : :
"memory"
8422static inline void _AArch32_Write_pmevcntr_22( uint32_t value )
8425 "mcr p15, 0, %0, c14, c10, 6" : :
"r" ( value ) :
"memory"
8431static inline uint32_t _AArch32_Read_pmevcntr_23(
void )
8436 "mrc p15, 0, %0, c14, c10, 7" :
"=&r" ( value ) : :
"memory"
8442static inline void _AArch32_Write_pmevcntr_23( uint32_t value )
8445 "mcr p15, 0, %0, c14, c10, 7" : :
"r" ( value ) :
"memory"
8451static inline uint32_t _AArch32_Read_pmevcntr_24(
void )
8456 "mrc p15, 0, %0, c14, c11, 0" :
"=&r" ( value ) : :
"memory"
8462static inline void _AArch32_Write_pmevcntr_24( uint32_t value )
8465 "mcr p15, 0, %0, c14, c11, 0" : :
"r" ( value ) :
"memory"
8471static inline uint32_t _AArch32_Read_pmevcntr_25(
void )
8476 "mrc p15, 0, %0, c14, c11, 1" :
"=&r" ( value ) : :
"memory"
8482static inline void _AArch32_Write_pmevcntr_25( uint32_t value )
8485 "mcr p15, 0, %0, c14, c11, 1" : :
"r" ( value ) :
"memory"
8491static inline uint32_t _AArch32_Read_pmevcntr_26(
void )
8496 "mrc p15, 0, %0, c14, c11, 2" :
"=&r" ( value ) : :
"memory"
8502static inline void _AArch32_Write_pmevcntr_26( uint32_t value )
8505 "mcr p15, 0, %0, c14, c11, 2" : :
"r" ( value ) :
"memory"
8511static inline uint32_t _AArch32_Read_pmevcntr_27(
void )
8516 "mrc p15, 0, %0, c14, c11, 3" :
"=&r" ( value ) : :
"memory"
8522static inline void _AArch32_Write_pmevcntr_27( uint32_t value )
8525 "mcr p15, 0, %0, c14, c11, 3" : :
"r" ( value ) :
"memory"
8531static inline uint32_t _AArch32_Read_pmevcntr_28(
void )
8536 "mrc p15, 0, %0, c14, c11, 4" :
"=&r" ( value ) : :
"memory"
8542static inline void _AArch32_Write_pmevcntr_28( uint32_t value )
8545 "mcr p15, 0, %0, c14, c11, 4" : :
"r" ( value ) :
"memory"
8551static inline uint32_t _AArch32_Read_pmevcntr_29(
void )
8556 "mrc p15, 0, %0, c14, c11, 5" :
"=&r" ( value ) : :
"memory"
8562static inline void _AArch32_Write_pmevcntr_29( uint32_t value )
8565 "mcr p15, 0, %0, c14, c11, 5" : :
"r" ( value ) :
"memory"
8571static inline uint32_t _AArch32_Read_pmevcntr_30(
void )
8576 "mrc p15, 0, %0, c14, c11, 6" :
"=&r" ( value ) : :
"memory"
8582static inline void _AArch32_Write_pmevcntr_30( uint32_t value )
8585 "mcr p15, 0, %0, c14, c11, 6" : :
"r" ( value ) :
"memory"
8591#define AARCH32_PMEVTYPER_EVTCOUNT_9_0( _val ) ( ( _val ) << 0 )
8592#define AARCH32_PMEVTYPER_EVTCOUNT_9_0_SHIFT 0
8593#define AARCH32_PMEVTYPER_EVTCOUNT_9_0_MASK 0x3ffU
8594#define AARCH32_PMEVTYPER_EVTCOUNT_9_0_GET( _reg ) \
8595 ( ( ( _reg ) >> 0 ) & 0x3ffU )
8597#define AARCH32_PMEVTYPER_EVTCOUNT_15_10( _val ) ( ( _val ) << 10 )
8598#define AARCH32_PMEVTYPER_EVTCOUNT_15_10_SHIFT 10
8599#define AARCH32_PMEVTYPER_EVTCOUNT_15_10_MASK 0xfc00U
8600#define AARCH32_PMEVTYPER_EVTCOUNT_15_10_GET( _reg ) \
8601 ( ( ( _reg ) >> 10 ) & 0x3fU )
8603#define AARCH32_PMEVTYPER_MT 0x2000000U
8605#define AARCH32_PMEVTYPER_NSH 0x8000000U
8607#define AARCH32_PMEVTYPER_NSU 0x10000000U
8609#define AARCH32_PMEVTYPER_NSK 0x20000000U
8611#define AARCH32_PMEVTYPER_U 0x40000000U
8613#define AARCH32_PMEVTYPER_P 0x80000000U
8617static inline uint32_t _AArch32_Read_pmevtyper_0(
void )
8622 "mrc p15, 0, %0, c14, c12, 0" :
"=&r" ( value ) : :
"memory"
8628static inline void _AArch32_Write_pmevtyper_0( uint32_t value )
8631 "mcr p15, 0, %0, c14, c12, 0" : :
"r" ( value ) :
"memory"
8637static inline uint32_t _AArch32_Read_pmevtyper_1(
void )
8642 "mrc p15, 0, %0, c14, c12, 1" :
"=&r" ( value ) : :
"memory"
8648static inline void _AArch32_Write_pmevtyper_1( uint32_t value )
8651 "mcr p15, 0, %0, c14, c12, 1" : :
"r" ( value ) :
"memory"
8657static inline uint32_t _AArch32_Read_pmevtyper_2(
void )
8662 "mrc p15, 0, %0, c14, c12, 2" :
"=&r" ( value ) : :
"memory"
8668static inline void _AArch32_Write_pmevtyper_2( uint32_t value )
8671 "mcr p15, 0, %0, c14, c12, 2" : :
"r" ( value ) :
"memory"
8677static inline uint32_t _AArch32_Read_pmevtyper_3(
void )
8682 "mrc p15, 0, %0, c14, c12, 3" :
"=&r" ( value ) : :
"memory"
8688static inline void _AArch32_Write_pmevtyper_3( uint32_t value )
8691 "mcr p15, 0, %0, c14, c12, 3" : :
"r" ( value ) :
"memory"
8697static inline uint32_t _AArch32_Read_pmevtyper_4(
void )
8702 "mrc p15, 0, %0, c14, c12, 4" :
"=&r" ( value ) : :
"memory"
8708static inline void _AArch32_Write_pmevtyper_4( uint32_t value )
8711 "mcr p15, 0, %0, c14, c12, 4" : :
"r" ( value ) :
"memory"
8717static inline uint32_t _AArch32_Read_pmevtyper_5(
void )
8722 "mrc p15, 0, %0, c14, c12, 5" :
"=&r" ( value ) : :
"memory"
8728static inline void _AArch32_Write_pmevtyper_5( uint32_t value )
8731 "mcr p15, 0, %0, c14, c12, 5" : :
"r" ( value ) :
"memory"
8737static inline uint32_t _AArch32_Read_pmevtyper_6(
void )
8742 "mrc p15, 0, %0, c14, c12, 6" :
"=&r" ( value ) : :
"memory"
8748static inline void _AArch32_Write_pmevtyper_6( uint32_t value )
8751 "mcr p15, 0, %0, c14, c12, 6" : :
"r" ( value ) :
"memory"
8757static inline uint32_t _AArch32_Read_pmevtyper_7(
void )
8762 "mrc p15, 0, %0, c14, c12, 7" :
"=&r" ( value ) : :
"memory"
8768static inline void _AArch32_Write_pmevtyper_7( uint32_t value )
8771 "mcr p15, 0, %0, c14, c12, 7" : :
"r" ( value ) :
"memory"
8777static inline uint32_t _AArch32_Read_pmevtyper_8(
void )
8782 "mrc p15, 0, %0, c14, c13, 0" :
"=&r" ( value ) : :
"memory"
8788static inline void _AArch32_Write_pmevtyper_8( uint32_t value )
8791 "mcr p15, 0, %0, c14, c13, 0" : :
"r" ( value ) :
"memory"
8797static inline uint32_t _AArch32_Read_pmevtyper_9(
void )
8802 "mrc p15, 0, %0, c14, c13, 1" :
"=&r" ( value ) : :
"memory"
8808static inline void _AArch32_Write_pmevtyper_9( uint32_t value )
8811 "mcr p15, 0, %0, c14, c13, 1" : :
"r" ( value ) :
"memory"
8817static inline uint32_t _AArch32_Read_pmevtyper_10(
void )
8822 "mrc p15, 0, %0, c14, c13, 2" :
"=&r" ( value ) : :
"memory"
8828static inline void _AArch32_Write_pmevtyper_10( uint32_t value )
8831 "mcr p15, 0, %0, c14, c13, 2" : :
"r" ( value ) :
"memory"
8837static inline uint32_t _AArch32_Read_pmevtyper_11(
void )
8842 "mrc p15, 0, %0, c14, c13, 3" :
"=&r" ( value ) : :
"memory"
8848static inline void _AArch32_Write_pmevtyper_11( uint32_t value )
8851 "mcr p15, 0, %0, c14, c13, 3" : :
"r" ( value ) :
"memory"
8857static inline uint32_t _AArch32_Read_pmevtyper_12(
void )
8862 "mrc p15, 0, %0, c14, c13, 4" :
"=&r" ( value ) : :
"memory"
8868static inline void _AArch32_Write_pmevtyper_12( uint32_t value )
8871 "mcr p15, 0, %0, c14, c13, 4" : :
"r" ( value ) :
"memory"
8877static inline uint32_t _AArch32_Read_pmevtyper_13(
void )
8882 "mrc p15, 0, %0, c14, c13, 5" :
"=&r" ( value ) : :
"memory"
8888static inline void _AArch32_Write_pmevtyper_13( uint32_t value )
8891 "mcr p15, 0, %0, c14, c13, 5" : :
"r" ( value ) :
"memory"
8897static inline uint32_t _AArch32_Read_pmevtyper_14(
void )
8902 "mrc p15, 0, %0, c14, c13, 6" :
"=&r" ( value ) : :
"memory"
8908static inline void _AArch32_Write_pmevtyper_14( uint32_t value )
8911 "mcr p15, 0, %0, c14, c13, 6" : :
"r" ( value ) :
"memory"
8917static inline uint32_t _AArch32_Read_pmevtyper_15(
void )
8922 "mrc p15, 0, %0, c14, c13, 7" :
"=&r" ( value ) : :
"memory"
8928static inline void _AArch32_Write_pmevtyper_15( uint32_t value )
8931 "mcr p15, 0, %0, c14, c13, 7" : :
"r" ( value ) :
"memory"
8937static inline uint32_t _AArch32_Read_pmevtyper_16(
void )
8942 "mrc p15, 0, %0, c14, c14, 0" :
"=&r" ( value ) : :
"memory"
8948static inline void _AArch32_Write_pmevtyper_16( uint32_t value )
8951 "mcr p15, 0, %0, c14, c14, 0" : :
"r" ( value ) :
"memory"
8957static inline uint32_t _AArch32_Read_pmevtyper_17(
void )
8962 "mrc p15, 0, %0, c14, c14, 1" :
"=&r" ( value ) : :
"memory"
8968static inline void _AArch32_Write_pmevtyper_17( uint32_t value )
8971 "mcr p15, 0, %0, c14, c14, 1" : :
"r" ( value ) :
"memory"
8977static inline uint32_t _AArch32_Read_pmevtyper_18(
void )
8982 "mrc p15, 0, %0, c14, c14, 2" :
"=&r" ( value ) : :
"memory"
8988static inline void _AArch32_Write_pmevtyper_18( uint32_t value )
8991 "mcr p15, 0, %0, c14, c14, 2" : :
"r" ( value ) :
"memory"
8997static inline uint32_t _AArch32_Read_pmevtyper_19(
void )
9002 "mrc p15, 0, %0, c14, c14, 3" :
"=&r" ( value ) : :
"memory"
9008static inline void _AArch32_Write_pmevtyper_19( uint32_t value )
9011 "mcr p15, 0, %0, c14, c14, 3" : :
"r" ( value ) :
"memory"
9017static inline uint32_t _AArch32_Read_pmevtyper_20(
void )
9022 "mrc p15, 0, %0, c14, c14, 4" :
"=&r" ( value ) : :
"memory"
9028static inline void _AArch32_Write_pmevtyper_20( uint32_t value )
9031 "mcr p15, 0, %0, c14, c14, 4" : :
"r" ( value ) :
"memory"
9037static inline uint32_t _AArch32_Read_pmevtyper_21(
void )
9042 "mrc p15, 0, %0, c14, c14, 5" :
"=&r" ( value ) : :
"memory"
9048static inline void _AArch32_Write_pmevtyper_21( uint32_t value )
9051 "mcr p15, 0, %0, c14, c14, 5" : :
"r" ( value ) :
"memory"
9057static inline uint32_t _AArch32_Read_pmevtyper_22(
void )
9062 "mrc p15, 0, %0, c14, c14, 6" :
"=&r" ( value ) : :
"memory"
9068static inline void _AArch32_Write_pmevtyper_22( uint32_t value )
9071 "mcr p15, 0, %0, c14, c14, 6" : :
"r" ( value ) :
"memory"
9077static inline uint32_t _AArch32_Read_pmevtyper_23(
void )
9082 "mrc p15, 0, %0, c14, c14, 7" :
"=&r" ( value ) : :
"memory"
9088static inline void _AArch32_Write_pmevtyper_23( uint32_t value )
9091 "mcr p15, 0, %0, c14, c14, 7" : :
"r" ( value ) :
"memory"
9097static inline uint32_t _AArch32_Read_pmevtyper_24(
void )
9102 "mrc p15, 0, %0, c14, c15, 0" :
"=&r" ( value ) : :
"memory"
9108static inline void _AArch32_Write_pmevtyper_24( uint32_t value )
9111 "mcr p15, 0, %0, c14, c15, 0" : :
"r" ( value ) :
"memory"
9117static inline uint32_t _AArch32_Read_pmevtyper_25(
void )
9122 "mrc p15, 0, %0, c14, c15, 1" :
"=&r" ( value ) : :
"memory"
9128static inline void _AArch32_Write_pmevtyper_25( uint32_t value )
9131 "mcr p15, 0, %0, c14, c15, 1" : :
"r" ( value ) :
"memory"
9137static inline uint32_t _AArch32_Read_pmevtyper_26(
void )
9142 "mrc p15, 0, %0, c14, c15, 2" :
"=&r" ( value ) : :
"memory"
9148static inline void _AArch32_Write_pmevtyper_26( uint32_t value )
9151 "mcr p15, 0, %0, c14, c15, 2" : :
"r" ( value ) :
"memory"
9157static inline uint32_t _AArch32_Read_pmevtyper_27(
void )
9162 "mrc p15, 0, %0, c14, c15, 3" :
"=&r" ( value ) : :
"memory"
9168static inline void _AArch32_Write_pmevtyper_27( uint32_t value )
9171 "mcr p15, 0, %0, c14, c15, 3" : :
"r" ( value ) :
"memory"
9177static inline uint32_t _AArch32_Read_pmevtyper_28(
void )
9182 "mrc p15, 0, %0, c14, c15, 4" :
"=&r" ( value ) : :
"memory"
9188static inline void _AArch32_Write_pmevtyper_28( uint32_t value )
9191 "mcr p15, 0, %0, c14, c15, 4" : :
"r" ( value ) :
"memory"
9197static inline uint32_t _AArch32_Read_pmevtyper_29(
void )
9202 "mrc p15, 0, %0, c14, c15, 5" :
"=&r" ( value ) : :
"memory"
9208static inline void _AArch32_Write_pmevtyper_29( uint32_t value )
9211 "mcr p15, 0, %0, c14, c15, 5" : :
"r" ( value ) :
"memory"
9217static inline uint32_t _AArch32_Read_pmevtyper_30(
void )
9222 "mrc p15, 0, %0, c14, c15, 6" :
"=&r" ( value ) : :
"memory"
9228static inline void _AArch32_Write_pmevtyper_30( uint32_t value )
9231 "mcr p15, 0, %0, c14, c15, 6" : :
"r" ( value ) :
"memory"
9237#define AARCH32_PMINTENCLR_C 0x80000000U
9239static inline uint32_t _AArch32_Read_pmintenclr(
void )
9244 "mrc p15, 0, %0, c9, c14, 2" :
"=&r" ( value ) : :
"memory"
9250static inline void _AArch32_Write_pmintenclr( uint32_t value )
9253 "mcr p15, 0, %0, c9, c14, 2" : :
"r" ( value ) :
"memory"
9259#define AARCH32_PMINTENSET_C 0x80000000U
9261static inline uint32_t _AArch32_Read_pmintenset(
void )
9266 "mrc p15, 0, %0, c9, c14, 1" :
"=&r" ( value ) : :
"memory"
9272static inline void _AArch32_Write_pmintenset( uint32_t value )
9275 "mcr p15, 0, %0, c9, c14, 1" : :
"r" ( value ) :
"memory"
9281#define AARCH32_PMOVSR_C 0x80000000U
9283static inline uint32_t _AArch32_Read_pmovsr(
void )
9288 "mrc p15, 0, %0, c9, c12, 3" :
"=&r" ( value ) : :
"memory"
9294static inline void _AArch32_Write_pmovsr( uint32_t value )
9297 "mcr p15, 0, %0, c9, c12, 3" : :
"r" ( value ) :
"memory"
9303#define AARCH32_PMOVSSET_C 0x80000000U
9305static inline uint32_t _AArch32_Read_pmovsset(
void )
9310 "mrc p15, 0, %0, c9, c14, 3" :
"=&r" ( value ) : :
"memory"
9316static inline void _AArch32_Write_pmovsset( uint32_t value )
9319 "mcr p15, 0, %0, c9, c14, 3" : :
"r" ( value ) :
"memory"
9325#define AARCH32_PMSELR_SEL( _val ) ( ( _val ) << 0 )
9326#define AARCH32_PMSELR_SEL_SHIFT 0
9327#define AARCH32_PMSELR_SEL_MASK 0x1fU
9328#define AARCH32_PMSELR_SEL_GET( _reg ) \
9329 ( ( ( _reg ) >> 0 ) & 0x1fU )
9331static inline uint32_t _AArch32_Read_pmselr(
void )
9336 "mrc p15, 0, %0, c9, c12, 5" :
"=&r" ( value ) : :
"memory"
9342static inline void _AArch32_Write_pmselr( uint32_t value )
9345 "mcr p15, 0, %0, c9, c12, 5" : :
"r" ( value ) :
"memory"
9351static inline void _AArch32_Write_pmswinc( uint32_t value )
9354 "mcr p15, 0, %0, c9, c12, 4" : :
"r" ( value ) :
"memory"
9360#define AARCH32_PMUSERENR_EN 0x1U
9362#define AARCH32_PMUSERENR_SW 0x2U
9364#define AARCH32_PMUSERENR_CR 0x4U
9366#define AARCH32_PMUSERENR_ER 0x8U
9368static inline uint32_t _AArch32_Read_pmuserenr(
void )
9373 "mrc p15, 0, %0, c9, c14, 0" :
"=&r" ( value ) : :
"memory"
9379static inline void _AArch32_Write_pmuserenr( uint32_t value )
9382 "mcr p15, 0, %0, c9, c14, 0" : :
"r" ( value ) :
"memory"
9388static inline uint32_t _AArch32_Read_pmxevcntr(
void )
9393 "mrc p15, 0, %0, c9, c13, 2" :
"=&r" ( value ) : :
"memory"
9399static inline void _AArch32_Write_pmxevcntr( uint32_t value )
9402 "mcr p15, 0, %0, c9, c13, 2" : :
"r" ( value ) :
"memory"
9408static inline uint32_t _AArch32_Read_pmxevtyper(
void )
9413 "mrc p15, 0, %0, c9, c13, 1" :
"=&r" ( value ) : :
"memory"
9419static inline void _AArch32_Write_pmxevtyper( uint32_t value )
9422 "mcr p15, 0, %0, c9, c13, 1" : :
"r" ( value ) :
"memory"
9428#define AARCH32_AMCFGR_N( _val ) ( ( _val ) << 0 )
9429#define AARCH32_AMCFGR_N_SHIFT 0
9430#define AARCH32_AMCFGR_N_MASK 0xffU
9431#define AARCH32_AMCFGR_N_GET( _reg ) \
9432 ( ( ( _reg ) >> 0 ) & 0xffU )
9434#define AARCH32_AMCFGR_SIZE( _val ) ( ( _val ) << 8 )
9435#define AARCH32_AMCFGR_SIZE_SHIFT 8
9436#define AARCH32_AMCFGR_SIZE_MASK 0x3f00U
9437#define AARCH32_AMCFGR_SIZE_GET( _reg ) \
9438 ( ( ( _reg ) >> 8 ) & 0x3fU )
9440#define AARCH32_AMCFGR_HDBG 0x1000000U
9442#define AARCH32_AMCFGR_NCG( _val ) ( ( _val ) << 28 )
9443#define AARCH32_AMCFGR_NCG_SHIFT 28
9444#define AARCH32_AMCFGR_NCG_MASK 0xf0000000U
9445#define AARCH32_AMCFGR_NCG_GET( _reg ) \
9446 ( ( ( _reg ) >> 28 ) & 0xfU )
9448static inline uint32_t _AArch32_Read_amcfgr(
void )
9453 "mrc p15, 0, %0, c13, c2, 1" :
"=&r" ( value ) : :
"memory"
9461#define AARCH32_AMCGCR_CG0NC( _val ) ( ( _val ) << 0 )
9462#define AARCH32_AMCGCR_CG0NC_SHIFT 0
9463#define AARCH32_AMCGCR_CG0NC_MASK 0xffU
9464#define AARCH32_AMCGCR_CG0NC_GET( _reg ) \
9465 ( ( ( _reg ) >> 0 ) & 0xffU )
9467#define AARCH32_AMCGCR_CG1NC( _val ) ( ( _val ) << 8 )
9468#define AARCH32_AMCGCR_CG1NC_SHIFT 8
9469#define AARCH32_AMCGCR_CG1NC_MASK 0xff00U
9470#define AARCH32_AMCGCR_CG1NC_GET( _reg ) \
9471 ( ( ( _reg ) >> 8 ) & 0xffU )
9473static inline uint32_t _AArch32_Read_amcgcr(
void )
9478 "mrc p15, 0, %0, c13, c2, 2" :
"=&r" ( value ) : :
"memory"
9486static inline uint32_t _AArch32_Read_amcntenclr0(
void )
9491 "mrc p15, 0, %0, c13, c2, 4" :
"=&r" ( value ) : :
"memory"
9497static inline void _AArch32_Write_amcntenclr0( uint32_t value )
9500 "mcr p15, 0, %0, c13, c2, 4" : :
"r" ( value ) :
"memory"
9506static inline uint32_t _AArch32_Read_amcntenclr1(
void )
9511 "mrc p15, 0, %0, c13, c3, 0" :
"=&r" ( value ) : :
"memory"
9517static inline void _AArch32_Write_amcntenclr1( uint32_t value )
9520 "mcr p15, 0, %0, c13, c3, 0" : :
"r" ( value ) :
"memory"
9526static inline uint32_t _AArch32_Read_amcntenset0(
void )
9531 "mrc p15, 0, %0, c13, c2, 5" :
"=&r" ( value ) : :
"memory"
9537static inline void _AArch32_Write_amcntenset0( uint32_t value )
9540 "mcr p15, 0, %0, c13, c2, 5" : :
"r" ( value ) :
"memory"
9546static inline uint32_t _AArch32_Read_amcntenset1(
void )
9551 "mrc p15, 0, %0, c13, c3, 1" :
"=&r" ( value ) : :
"memory"
9557static inline void _AArch32_Write_amcntenset1( uint32_t value )
9560 "mcr p15, 0, %0, c13, c3, 1" : :
"r" ( value ) :
"memory"
9566#define AARCH32_AMCR_HDBG 0x400U
9568#define AARCH32_AMCR_CG1RZ 0x20000U
9570static inline uint32_t _AArch32_Read_amcr(
void )
9575 "mrc p15, 0, %0, c13, c2, 0" :
"=&r" ( value ) : :
"memory"
9581static inline void _AArch32_Write_amcr( uint32_t value )
9584 "mcr p15, 0, %0, c13, c2, 0" : :
"r" ( value ) :
"memory"
9590#define AARCH32_AMEVCNTR0_ACNT( _val ) ( ( _val ) << 0 )
9591#define AARCH32_AMEVCNTR0_ACNT_SHIFT 0
9592#define AARCH32_AMEVCNTR0_ACNT_MASK 0xffffffffffffffffULL
9593#define AARCH32_AMEVCNTR0_ACNT_GET( _reg ) \
9594 ( ( ( _reg ) >> 0 ) & 0xffffffffffffffffULL )
9598static inline uint64_t _AArch32_Read_amevcntr0_0(
void )
9603 "mrrc p15, 0, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9609static inline void _AArch32_Write_amevcntr0_0( uint64_t value )
9612 "mcrr p15, 0, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9618static inline uint64_t _AArch32_Read_amevcntr0_1(
void )
9623 "mrrc p15, 1, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9629static inline void _AArch32_Write_amevcntr0_1( uint64_t value )
9632 "mcrr p15, 1, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9638static inline uint64_t _AArch32_Read_amevcntr0_2(
void )
9643 "mrrc p15, 2, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9649static inline void _AArch32_Write_amevcntr0_2( uint64_t value )
9652 "mcrr p15, 2, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9658static inline uint64_t _AArch32_Read_amevcntr0_3(
void )
9663 "mrrc p15, 3, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9669static inline void _AArch32_Write_amevcntr0_3( uint64_t value )
9672 "mcrr p15, 3, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9678static inline uint64_t _AArch32_Read_amevcntr0_4(
void )
9683 "mrrc p15, 4, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9689static inline void _AArch32_Write_amevcntr0_4( uint64_t value )
9692 "mcrr p15, 4, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9698static inline uint64_t _AArch32_Read_amevcntr0_5(
void )
9703 "mrrc p15, 5, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9709static inline void _AArch32_Write_amevcntr0_5( uint64_t value )
9712 "mcrr p15, 5, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9718static inline uint64_t _AArch32_Read_amevcntr0_6(
void )
9723 "mrrc p15, 6, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9729static inline void _AArch32_Write_amevcntr0_6( uint64_t value )
9732 "mcrr p15, 6, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9738static inline uint64_t _AArch32_Read_amevcntr0_7(
void )
9743 "mrrc p15, 7, %Q0, %R0, c0" :
"=&r" ( value ) : :
"memory"
9749static inline void _AArch32_Write_amevcntr0_7( uint64_t value )
9752 "mcrr p15, 7, %Q0, %R0, c0" : :
"r" ( value ) :
"memory"
9758static inline uint64_t _AArch32_Read_amevcntr0_8(
void )
9763 "mrrc p15, 0, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9769static inline void _AArch32_Write_amevcntr0_8( uint64_t value )
9772 "mcrr p15, 0, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9778static inline uint64_t _AArch32_Read_amevcntr0_9(
void )
9783 "mrrc p15, 1, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9789static inline void _AArch32_Write_amevcntr0_9( uint64_t value )
9792 "mcrr p15, 1, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9798static inline uint64_t _AArch32_Read_amevcntr0_10(
void )
9803 "mrrc p15, 2, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9809static inline void _AArch32_Write_amevcntr0_10( uint64_t value )
9812 "mcrr p15, 2, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9818static inline uint64_t _AArch32_Read_amevcntr0_11(
void )
9823 "mrrc p15, 3, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9829static inline void _AArch32_Write_amevcntr0_11( uint64_t value )
9832 "mcrr p15, 3, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9838static inline uint64_t _AArch32_Read_amevcntr0_12(
void )
9843 "mrrc p15, 4, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9849static inline void _AArch32_Write_amevcntr0_12( uint64_t value )
9852 "mcrr p15, 4, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9858static inline uint64_t _AArch32_Read_amevcntr0_13(
void )
9863 "mrrc p15, 5, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9869static inline void _AArch32_Write_amevcntr0_13( uint64_t value )
9872 "mcrr p15, 5, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9878static inline uint64_t _AArch32_Read_amevcntr0_14(
void )
9883 "mrrc p15, 6, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9889static inline void _AArch32_Write_amevcntr0_14( uint64_t value )
9892 "mcrr p15, 6, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9898static inline uint64_t _AArch32_Read_amevcntr0_15(
void )
9903 "mrrc p15, 7, %Q0, %R0, c1" :
"=&r" ( value ) : :
"memory"
9909static inline void _AArch32_Write_amevcntr0_15( uint64_t value )
9912 "mcrr p15, 7, %Q0, %R0, c1" : :
"r" ( value ) :
"memory"
9918#define AARCH32_AMEVCNTR1_ACNT( _val ) ( ( _val ) << 0 )
9919#define AARCH32_AMEVCNTR1_ACNT_SHIFT 0
9920#define AARCH32_AMEVCNTR1_ACNT_MASK 0xffffffffffffffffULL
9921#define AARCH32_AMEVCNTR1_ACNT_GET( _reg ) \
9922 ( ( ( _reg ) >> 0 ) & 0xffffffffffffffffULL )
9926static inline uint64_t _AArch32_Read_amevcntr1_0(
void )
9931 "mrrc p15, 0, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
9937static inline void _AArch32_Write_amevcntr1_0( uint64_t value )
9940 "mcrr p15, 0, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
9946static inline uint64_t _AArch32_Read_amevcntr1_1(
void )
9951 "mrrc p15, 1, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
9957static inline void _AArch32_Write_amevcntr1_1( uint64_t value )
9960 "mcrr p15, 1, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
9966static inline uint64_t _AArch32_Read_amevcntr1_2(
void )
9971 "mrrc p15, 2, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
9977static inline void _AArch32_Write_amevcntr1_2( uint64_t value )
9980 "mcrr p15, 2, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
9986static inline uint64_t _AArch32_Read_amevcntr1_3(
void )
9991 "mrrc p15, 3, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
9997static inline void _AArch32_Write_amevcntr1_3( uint64_t value )
10000 "mcrr p15, 3, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
10006static inline uint64_t _AArch32_Read_amevcntr1_4(
void )
10011 "mrrc p15, 4, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
10017static inline void _AArch32_Write_amevcntr1_4( uint64_t value )
10020 "mcrr p15, 4, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
10026static inline uint64_t _AArch32_Read_amevcntr1_5(
void )
10031 "mrrc p15, 5, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
10037static inline void _AArch32_Write_amevcntr1_5( uint64_t value )
10040 "mcrr p15, 5, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
10046static inline uint64_t _AArch32_Read_amevcntr1_6(
void )
10051 "mrrc p15, 6, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
10057static inline void _AArch32_Write_amevcntr1_6( uint64_t value )
10060 "mcrr p15, 6, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
10066static inline uint64_t _AArch32_Read_amevcntr1_7(
void )
10071 "mrrc p15, 7, %Q0, %R0, c4" :
"=&r" ( value ) : :
"memory"
10077static inline void _AArch32_Write_amevcntr1_7( uint64_t value )
10080 "mcrr p15, 7, %Q0, %R0, c4" : :
"r" ( value ) :
"memory"
10086static inline uint64_t _AArch32_Read_amevcntr1_8(
void )
10091 "mrrc p15, 0, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10097static inline void _AArch32_Write_amevcntr1_8( uint64_t value )
10100 "mcrr p15, 0, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10106static inline uint64_t _AArch32_Read_amevcntr1_9(
void )
10111 "mrrc p15, 1, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10117static inline void _AArch32_Write_amevcntr1_9( uint64_t value )
10120 "mcrr p15, 1, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10126static inline uint64_t _AArch32_Read_amevcntr1_10(
void )
10131 "mrrc p15, 2, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10137static inline void _AArch32_Write_amevcntr1_10( uint64_t value )
10140 "mcrr p15, 2, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10146static inline uint64_t _AArch32_Read_amevcntr1_11(
void )
10151 "mrrc p15, 3, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10157static inline void _AArch32_Write_amevcntr1_11( uint64_t value )
10160 "mcrr p15, 3, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10166static inline uint64_t _AArch32_Read_amevcntr1_12(
void )
10171 "mrrc p15, 4, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10177static inline void _AArch32_Write_amevcntr1_12( uint64_t value )
10180 "mcrr p15, 4, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10186static inline uint64_t _AArch32_Read_amevcntr1_13(
void )
10191 "mrrc p15, 5, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10197static inline void _AArch32_Write_amevcntr1_13( uint64_t value )
10200 "mcrr p15, 5, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10206static inline uint64_t _AArch32_Read_amevcntr1_14(
void )
10211 "mrrc p15, 6, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10217static inline void _AArch32_Write_amevcntr1_14( uint64_t value )
10220 "mcrr p15, 6, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10226static inline uint64_t _AArch32_Read_amevcntr1_15(
void )
10231 "mrrc p15, 7, %Q0, %R0, c5" :
"=&r" ( value ) : :
"memory"
10237static inline void _AArch32_Write_amevcntr1_15( uint64_t value )
10240 "mcrr p15, 7, %Q0, %R0, c5" : :
"r" ( value ) :
"memory"
10246#define AARCH32_AMEVTYPER0_EVTCOUNT( _val ) ( ( _val ) << 0 )
10247#define AARCH32_AMEVTYPER0_EVTCOUNT_SHIFT 0
10248#define AARCH32_AMEVTYPER0_EVTCOUNT_MASK 0xffffU
10249#define AARCH32_AMEVTYPER0_EVTCOUNT_GET( _reg ) \
10250 ( ( ( _reg ) >> 0 ) & 0xffffU )
10254static inline uint32_t _AArch32_Read_amevtyper0_0(
void )
10259 "mrc p15, 0, %0, c13, c6, 0" :
"=&r" ( value ) : :
"memory"
10267static inline uint32_t _AArch32_Read_amevtyper0_1(
void )
10272 "mrc p15, 0, %0, c13, c6, 1" :
"=&r" ( value ) : :
"memory"
10280static inline uint32_t _AArch32_Read_amevtyper0_2(
void )
10285 "mrc p15, 0, %0, c13, c6, 2" :
"=&r" ( value ) : :
"memory"
10293static inline uint32_t _AArch32_Read_amevtyper0_3(
void )
10298 "mrc p15, 0, %0, c13, c6, 3" :
"=&r" ( value ) : :
"memory"
10306static inline uint32_t _AArch32_Read_amevtyper0_4(
void )
10311 "mrc p15, 0, %0, c13, c6, 4" :
"=&r" ( value ) : :
"memory"
10319static inline uint32_t _AArch32_Read_amevtyper0_5(
void )
10324 "mrc p15, 0, %0, c13, c6, 5" :
"=&r" ( value ) : :
"memory"
10332static inline uint32_t _AArch32_Read_amevtyper0_6(
void )
10337 "mrc p15, 0, %0, c13, c6, 6" :
"=&r" ( value ) : :
"memory"
10345static inline uint32_t _AArch32_Read_amevtyper0_7(
void )
10350 "mrc p15, 0, %0, c13, c6, 7" :
"=&r" ( value ) : :
"memory"
10358static inline uint32_t _AArch32_Read_amevtyper0_8(
void )
10363 "mrc p15, 0, %0, c13, c7, 0" :
"=&r" ( value ) : :
"memory"
10371static inline uint32_t _AArch32_Read_amevtyper0_9(
void )
10376 "mrc p15, 0, %0, c13, c7, 1" :
"=&r" ( value ) : :
"memory"
10384static inline uint32_t _AArch32_Read_amevtyper0_10(
void )
10389 "mrc p15, 0, %0, c13, c7, 2" :
"=&r" ( value ) : :
"memory"
10397static inline uint32_t _AArch32_Read_amevtyper0_11(
void )
10402 "mrc p15, 0, %0, c13, c7, 3" :
"=&r" ( value ) : :
"memory"
10410static inline uint32_t _AArch32_Read_amevtyper0_12(
void )
10415 "mrc p15, 0, %0, c13, c7, 4" :
"=&r" ( value ) : :
"memory"
10423static inline uint32_t _AArch32_Read_amevtyper0_13(
void )
10428 "mrc p15, 0, %0, c13, c7, 5" :
"=&r" ( value ) : :
"memory"
10436static inline uint32_t _AArch32_Read_amevtyper0_14(
void )
10441 "mrc p15, 0, %0, c13, c7, 6" :
"=&r" ( value ) : :
"memory"
10449static inline uint32_t _AArch32_Read_amevtyper0_15(
void )
10454 "mrc p15, 0, %0, c13, c7, 7" :
"=&r" ( value ) : :
"memory"
10462#define AARCH32_AMEVTYPER1_EVTCOUNT( _val ) ( ( _val ) << 0 )
10463#define AARCH32_AMEVTYPER1_EVTCOUNT_SHIFT 0
10464#define AARCH32_AMEVTYPER1_EVTCOUNT_MASK 0xffffU
10465#define AARCH32_AMEVTYPER1_EVTCOUNT_GET( _reg ) \
10466 ( ( ( _reg ) >> 0 ) & 0xffffU )
10470static inline uint32_t _AArch32_Read_amevtyper1_0(
void )
10475 "mrc p15, 0, %0, c13, c14, 0" :
"=&r" ( value ) : :
"memory"
10481static inline void _AArch32_Write_amevtyper1_0( uint32_t value )
10484 "mcr p15, 0, %0, c13, c14, 0" : :
"r" ( value ) :
"memory"
10490static inline uint32_t _AArch32_Read_amevtyper1_1(
void )
10495 "mrc p15, 0, %0, c13, c14, 1" :
"=&r" ( value ) : :
"memory"
10501static inline void _AArch32_Write_amevtyper1_1( uint32_t value )
10504 "mcr p15, 0, %0, c13, c14, 1" : :
"r" ( value ) :
"memory"
10510static inline uint32_t _AArch32_Read_amevtyper1_2(
void )
10515 "mrc p15, 0, %0, c13, c14, 2" :
"=&r" ( value ) : :
"memory"
10521static inline void _AArch32_Write_amevtyper1_2( uint32_t value )
10524 "mcr p15, 0, %0, c13, c14, 2" : :
"r" ( value ) :
"memory"
10530static inline uint32_t _AArch32_Read_amevtyper1_3(
void )
10535 "mrc p15, 0, %0, c13, c14, 3" :
"=&r" ( value ) : :
"memory"
10541static inline void _AArch32_Write_amevtyper1_3( uint32_t value )
10544 "mcr p15, 0, %0, c13, c14, 3" : :
"r" ( value ) :
"memory"
10550static inline uint32_t _AArch32_Read_amevtyper1_4(
void )
10555 "mrc p15, 0, %0, c13, c14, 4" :
"=&r" ( value ) : :
"memory"
10561static inline void _AArch32_Write_amevtyper1_4( uint32_t value )
10564 "mcr p15, 0, %0, c13, c14, 4" : :
"r" ( value ) :
"memory"
10570static inline uint32_t _AArch32_Read_amevtyper1_5(
void )
10575 "mrc p15, 0, %0, c13, c14, 5" :
"=&r" ( value ) : :
"memory"
10581static inline void _AArch32_Write_amevtyper1_5( uint32_t value )
10584 "mcr p15, 0, %0, c13, c14, 5" : :
"r" ( value ) :
"memory"
10590static inline uint32_t _AArch32_Read_amevtyper1_6(
void )
10595 "mrc p15, 0, %0, c13, c14, 6" :
"=&r" ( value ) : :
"memory"
10601static inline void _AArch32_Write_amevtyper1_6( uint32_t value )
10604 "mcr p15, 0, %0, c13, c14, 6" : :
"r" ( value ) :
"memory"
10610static inline uint32_t _AArch32_Read_amevtyper1_7(
void )
10615 "mrc p15, 0, %0, c13, c14, 7" :
"=&r" ( value ) : :
"memory"
10621static inline void _AArch32_Write_amevtyper1_7( uint32_t value )
10624 "mcr p15, 0, %0, c13, c14, 7" : :
"r" ( value ) :
"memory"
10630static inline uint32_t _AArch32_Read_amevtyper1_8(
void )
10635 "mrc p15, 0, %0, c13, c15, 0" :
"=&r" ( value ) : :
"memory"
10641static inline void _AArch32_Write_amevtyper1_8( uint32_t value )
10644 "mcr p15, 0, %0, c13, c15, 0" : :
"r" ( value ) :
"memory"
10650static inline uint32_t _AArch32_Read_amevtyper1_9(
void )
10655 "mrc p15, 0, %0, c13, c15, 1" :
"=&r" ( value ) : :
"memory"
10661static inline void _AArch32_Write_amevtyper1_9( uint32_t value )
10664 "mcr p15, 0, %0, c13, c15, 1" : :
"r" ( value ) :
"memory"
10670static inline uint32_t _AArch32_Read_amevtyper1_10(
void )
10675 "mrc p15, 0, %0, c13, c15, 2" :
"=&r" ( value ) : :
"memory"
10681static inline void _AArch32_Write_amevtyper1_10( uint32_t value )
10684 "mcr p15, 0, %0, c13, c15, 2" : :
"r" ( value ) :
"memory"
10690static inline uint32_t _AArch32_Read_amevtyper1_11(
void )
10695 "mrc p15, 0, %0, c13, c15, 3" :
"=&r" ( value ) : :
"memory"
10701static inline void _AArch32_Write_amevtyper1_11( uint32_t value )
10704 "mcr p15, 0, %0, c13, c15, 3" : :
"r" ( value ) :
"memory"
10710static inline uint32_t _AArch32_Read_amevtyper1_12(
void )
10715 "mrc p15, 0, %0, c13, c15, 4" :
"=&r" ( value ) : :
"memory"
10721static inline void _AArch32_Write_amevtyper1_12( uint32_t value )
10724 "mcr p15, 0, %0, c13, c15, 4" : :
"r" ( value ) :
"memory"
10730static inline uint32_t _AArch32_Read_amevtyper1_13(
void )
10735 "mrc p15, 0, %0, c13, c15, 5" :
"=&r" ( value ) : :
"memory"
10741static inline void _AArch32_Write_amevtyper1_13( uint32_t value )
10744 "mcr p15, 0, %0, c13, c15, 5" : :
"r" ( value ) :
"memory"
10750static inline uint32_t _AArch32_Read_amevtyper1_14(
void )
10755 "mrc p15, 0, %0, c13, c15, 6" :
"=&r" ( value ) : :
"memory"
10761static inline void _AArch32_Write_amevtyper1_14( uint32_t value )
10764 "mcr p15, 0, %0, c13, c15, 6" : :
"r" ( value ) :
"memory"
10770static inline uint32_t _AArch32_Read_amevtyper1_15(
void )
10775 "mrc p15, 0, %0, c13, c15, 7" :
"=&r" ( value ) : :
"memory"
10781static inline void _AArch32_Write_amevtyper1_15( uint32_t value )
10784 "mcr p15, 0, %0, c13, c15, 7" : :
"r" ( value ) :
"memory"
10790#define AARCH32_AMUSERENR_EN 0x1U
10792static inline uint32_t _AArch32_Read_amuserenr(
void )
10797 "mrc p15, 0, %0, c13, c2, 3" :
"=&r" ( value ) : :
"memory"
10803static inline void _AArch32_Write_amuserenr( uint32_t value )
10806 "mcr p15, 0, %0, c13, c2, 3" : :
"r" ( value ) :
"memory"
10812#define AARCH32_DISR_FS_3_0( _val ) ( ( _val ) << 0 )
10813#define AARCH32_DISR_FS_3_0_SHIFT 0
10814#define AARCH32_DISR_FS_3_0_MASK 0xfU
10815#define AARCH32_DISR_FS_3_0_GET( _reg ) \
10816 ( ( ( _reg ) >> 0 ) & 0xfU )
10818#define AARCH32_DISR_DFSC( _val ) ( ( _val ) << 0 )
10819#define AARCH32_DISR_DFSC_SHIFT 0
10820#define AARCH32_DISR_DFSC_MASK 0x3fU
10821#define AARCH32_DISR_DFSC_GET( _reg ) \
10822 ( ( ( _reg ) >> 0 ) & 0x3fU )
10824#define AARCH32_DISR_STATUS( _val ) ( ( _val ) << 0 )
10825#define AARCH32_DISR_STATUS_SHIFT 0
10826#define AARCH32_DISR_STATUS_MASK 0x3fU
10827#define AARCH32_DISR_STATUS_GET( _reg ) \
10828 ( ( ( _reg ) >> 0 ) & 0x3fU )
10830#define AARCH32_DISR_EA 0x200U
10832#define AARCH32_DISR_LPAE 0x200U
10834#define AARCH32_DISR_FS_4 0x400U
10836#define AARCH32_DISR_AET_0( _val ) ( ( _val ) << 10 )
10837#define AARCH32_DISR_AET_SHIFT_0 10
10838#define AARCH32_DISR_AET_MASK_0 0xc00U
10839#define AARCH32_DISR_AET_GET_0( _reg ) \
10840 ( ( ( _reg ) >> 10 ) & 0x3U )
10842#define AARCH32_DISR_EXT 0x1000U
10844#define AARCH32_DISR_AET_1( _val ) ( ( _val ) << 14 )
10845#define AARCH32_DISR_AET_SHIFT_1 14
10846#define AARCH32_DISR_AET_MASK_1 0xc000U
10847#define AARCH32_DISR_AET_GET_1( _reg ) \
10848 ( ( ( _reg ) >> 14 ) & 0x3U )
10850#define AARCH32_DISR_A 0x80000000U
10852static inline uint32_t _AArch32_Read_disr(
void )
10857 "mrc p15, 0, %0, c12, c1, 1" :
"=&r" ( value ) : :
"memory"
10863static inline void _AArch32_Write_disr( uint32_t value )
10866 "mcr p15, 0, %0, c12, c1, 1" : :
"r" ( value ) :
"memory"
10872#define AARCH32_ERRIDR_NUM( _val ) ( ( _val ) << 0 )
10873#define AARCH32_ERRIDR_NUM_SHIFT 0
10874#define AARCH32_ERRIDR_NUM_MASK 0xffffU
10875#define AARCH32_ERRIDR_NUM_GET( _reg ) \
10876 ( ( ( _reg ) >> 0 ) & 0xffffU )
10878static inline uint32_t _AArch32_Read_erridr(
void )
10883 "mrc p15, 0, %0, c5, c3, 0" :
"=&r" ( value ) : :
"memory"
10891#define AARCH32_ERRSELR_SEL( _val ) ( ( _val ) << 0 )
10892#define AARCH32_ERRSELR_SEL_SHIFT 0
10893#define AARCH32_ERRSELR_SEL_MASK 0xffffU
10894#define AARCH32_ERRSELR_SEL_GET( _reg ) \
10895 ( ( ( _reg ) >> 0 ) & 0xffffU )
10897static inline uint32_t _AArch32_Read_errselr(
void )
10902 "mrc p15, 0, %0, c5, c3, 1" :
"=&r" ( value ) : :
"memory"
10908static inline void _AArch32_Write_errselr( uint32_t value )
10911 "mcr p15, 0, %0, c5, c3, 1" : :
"r" ( value ) :
"memory"
10917static inline uint32_t _AArch32_Read_erxaddr(
void )
10922 "mrc p15, 0, %0, c5, c4, 3" :
"=&r" ( value ) : :
"memory"
10928static inline void _AArch32_Write_erxaddr( uint32_t value )
10931 "mcr p15, 0, %0, c5, c4, 3" : :
"r" ( value ) :
"memory"
10937static inline uint32_t _AArch32_Read_erxaddr2(
void )
10942 "mrc p15, 0, %0, c5, c4, 7" :
"=&r" ( value ) : :
"memory"
10948static inline void _AArch32_Write_erxaddr2( uint32_t value )
10951 "mcr p15, 0, %0, c5, c4, 7" : :
"r" ( value ) :
"memory"
10957static inline uint32_t _AArch32_Read_erxctlr(
void )
10962 "mrc p15, 0, %0, c5, c4, 1" :
"=&r" ( value ) : :
"memory"
10968static inline void _AArch32_Write_erxctlr( uint32_t value )
10971 "mcr p15, 0, %0, c5, c4, 1" : :
"r" ( value ) :
"memory"
10977static inline uint32_t _AArch32_Read_erxctlr2(
void )
10982 "mrc p15, 0, %0, c5, c4, 5" :
"=&r" ( value ) : :
"memory"
10988static inline void _AArch32_Write_erxctlr2( uint32_t value )
10991 "mcr p15, 0, %0, c5, c4, 5" : :
"r" ( value ) :
"memory"
10997static inline uint32_t _AArch32_Read_erxfr(
void )
11002 "mrc p15, 0, %0, c5, c4, 0" :
"=&r" ( value ) : :
"memory"
11010static inline uint32_t _AArch32_Read_erxfr2(
void )
11015 "mrc p15, 0, %0, c5, c4, 4" :
"=&r" ( value ) : :
"memory"
11023static inline uint32_t _AArch32_Read_erxmisc0(
void )
11028 "mrc p15, 0, %0, c5, c5, 0" :
"=&r" ( value ) : :
"memory"
11034static inline void _AArch32_Write_erxmisc0( uint32_t value )
11037 "mcr p15, 0, %0, c5, c5, 0" : :
"r" ( value ) :
"memory"
11043static inline uint32_t _AArch32_Read_erxmisc1(
void )
11048 "mrc p15, 0, %0, c5, c5, 1" :
"=&r" ( value ) : :
"memory"
11054static inline void _AArch32_Write_erxmisc1( uint32_t value )
11057 "mcr p15, 0, %0, c5, c5, 1" : :
"r" ( value ) :
"memory"
11063static inline uint32_t _AArch32_Read_erxmisc2(
void )
11068 "mrc p15, 0, %0, c5, c5, 4" :
"=&r" ( value ) : :
"memory"
11074static inline void _AArch32_Write_erxmisc2( uint32_t value )
11077 "mcr p15, 0, %0, c5, c5, 4" : :
"r" ( value ) :
"memory"
11083static inline uint32_t _AArch32_Read_erxmisc3(
void )
11088 "mrc p15, 0, %0, c5, c5, 5" :
"=&r" ( value ) : :
"memory"
11094static inline void _AArch32_Write_erxmisc3( uint32_t value )
11097 "mcr p15, 0, %0, c5, c5, 5" : :
"r" ( value ) :
"memory"
11103static inline uint32_t _AArch32_Read_erxmisc4(
void )
11108 "mrc p15, 0, %0, c5, c5, 2" :
"=&r" ( value ) : :
"memory"
11114static inline void _AArch32_Write_erxmisc4( uint32_t value )
11117 "mcr p15, 0, %0, c5, c5, 2" : :
"r" ( value ) :
"memory"
11123static inline uint32_t _AArch32_Read_erxmisc5(
void )
11128 "mrc p15, 0, %0, c5, c5, 3" :
"=&r" ( value ) : :
"memory"
11134static inline void _AArch32_Write_erxmisc5( uint32_t value )
11137 "mcr p15, 0, %0, c5, c5, 3" : :
"r" ( value ) :
"memory"
11143static inline uint32_t _AArch32_Read_erxmisc6(
void )
11148 "mrc p15, 0, %0, c5, c5, 6" :
"=&r" ( value ) : :
"memory"
11154static inline void _AArch32_Write_erxmisc6( uint32_t value )
11157 "mcr p15, 0, %0, c5, c5, 6" : :
"r" ( value ) :
"memory"
11163static inline uint32_t _AArch32_Read_erxmisc7(
void )
11168 "mrc p15, 0, %0, c5, c5, 7" :
"=&r" ( value ) : :
"memory"
11174static inline void _AArch32_Write_erxmisc7( uint32_t value )
11177 "mcr p15, 0, %0, c5, c5, 7" : :
"r" ( value ) :
"memory"
11183static inline uint32_t _AArch32_Read_erxstatus(
void )
11188 "mrc p15, 0, %0, c5, c4, 2" :
"=&r" ( value ) : :
"memory"
11194static inline void _AArch32_Write_erxstatus( uint32_t value )
11197 "mcr p15, 0, %0, c5, c4, 2" : :
"r" ( value ) :
"memory"
11203#define AARCH32_VDFSR_EXT 0x1000U
11205#define AARCH32_VDFSR_AET( _val ) ( ( _val ) << 14 )
11206#define AARCH32_VDFSR_AET_SHIFT 14
11207#define AARCH32_VDFSR_AET_MASK 0xc000U
11208#define AARCH32_VDFSR_AET_GET( _reg ) \
11209 ( ( ( _reg ) >> 14 ) & 0x3U )
11211static inline uint32_t _AArch32_Read_vdfsr(
void )
11216 "mrc p15, 4, %0, c5, c2, 3" :
"=&r" ( value ) : :
"memory"
11222static inline void _AArch32_Write_vdfsr( uint32_t value )
11225 "mcr p15, 4, %0, c5, c2, 3" : :
"r" ( value ) :
"memory"
11231#define AARCH32_VDISR_FS_3_0( _val ) ( ( _val ) << 0 )
11232#define AARCH32_VDISR_FS_3_0_SHIFT 0
11233#define AARCH32_VDISR_FS_3_0_MASK 0xfU
11234#define AARCH32_VDISR_FS_3_0_GET( _reg ) \
11235 ( ( ( _reg ) >> 0 ) & 0xfU )
11237#define AARCH32_VDISR_STATUS( _val ) ( ( _val ) << 0 )
11238#define AARCH32_VDISR_STATUS_SHIFT 0
11239#define AARCH32_VDISR_STATUS_MASK 0x3fU
11240#define AARCH32_VDISR_STATUS_GET( _reg ) \
11241 ( ( ( _reg ) >> 0 ) & 0x3fU )
11243#define AARCH32_VDISR_LPAE 0x200U
11245#define AARCH32_VDISR_FS_4 0x400U
11247#define AARCH32_VDISR_EXT 0x1000U
11249#define AARCH32_VDISR_AET( _val ) ( ( _val ) << 14 )
11250#define AARCH32_VDISR_AET_SHIFT 14
11251#define AARCH32_VDISR_AET_MASK 0xc000U
11252#define AARCH32_VDISR_AET_GET( _reg ) \
11253 ( ( ( _reg ) >> 14 ) & 0x3U )
11255#define AARCH32_VDISR_A 0x80000000U
11257static inline uint32_t _AArch32_Read_vdisr(
void )
11262 "mrc p15, 4, %0, c12, c1, 1" :
"=&r" ( value ) : :
"memory"
11268static inline void _AArch32_Write_vdisr( uint32_t value )
11271 "mcr p15, 4, %0, c12, c1, 1" : :
"r" ( value ) :
"memory"
11277static inline uint32_t _AArch32_Read_cntfrq(
void )
11282 "mrc p15, 0, %0, c14, c0, 0" :
"=&r" ( value ) : :
"memory"
11288static inline void _AArch32_Write_cntfrq( uint32_t value )
11291 "mcr p15, 0, %0, c14, c0, 0" : :
"r" ( value ) :
"memory"
11297#define AARCH32_CNTHCTL_PL1PCTEN 0x1U
11299#define AARCH32_CNTHCTL_PL1PCEN 0x2U
11301#define AARCH32_CNTHCTL_EVNTEN 0x4U
11303#define AARCH32_CNTHCTL_EVNTDIR 0x8U
11305#define AARCH32_CNTHCTL_EVNTI( _val ) ( ( _val ) << 4 )
11306#define AARCH32_CNTHCTL_EVNTI_SHIFT 4
11307#define AARCH32_CNTHCTL_EVNTI_MASK 0xf0U
11308#define AARCH32_CNTHCTL_EVNTI_GET( _reg ) \
11309 ( ( ( _reg ) >> 4 ) & 0xfU )
11311#define AARCH32_CNTHCTL_EVNTIS 0x20000U
11313static inline uint32_t _AArch32_Read_cnthctl(
void )
11318 "mrc p15, 4, %0, c14, c1, 0" :
"=&r" ( value ) : :
"memory"
11324static inline void _AArch32_Write_cnthctl( uint32_t value )
11327 "mcr p15, 4, %0, c14, c1, 0" : :
"r" ( value ) :
"memory"
11333#define AARCH32_CNTHP_CTL_ENABLE 0x1U
11335#define AARCH32_CNTHP_CTL_IMASK 0x2U
11337#define AARCH32_CNTHP_CTL_ISTATUS 0x4U
11339static inline uint32_t _AArch32_Read_cnthp_ctl(
void )
11344 "mrc p15, 4, %0, c14, c2, 1" :
"=&r" ( value ) : :
"memory"
11350static inline void _AArch32_Write_cnthp_ctl( uint32_t value )
11353 "mcr p15, 4, %0, c14, c2, 1" : :
"r" ( value ) :
"memory"
11359static inline uint64_t _AArch32_Read_cnthp_cval(
void )
11364 "mrrc p15, 6, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11370static inline void _AArch32_Write_cnthp_cval( uint64_t value )
11373 "mcrr p15, 6, %Q0, %R0, c14" : :
"r" ( value ) :
"memory"
11379static inline uint32_t _AArch32_Read_cnthp_tval(
void )
11384 "mrc p15, 4, %0, c14, c2, 0" :
"=&r" ( value ) : :
"memory"
11390static inline void _AArch32_Write_cnthp_tval( uint32_t value )
11393 "mcr p15, 4, %0, c14, c2, 0" : :
"r" ( value ) :
"memory"
11399#define AARCH32_CNTHPS_CTL_ENABLE 0x1U
11401#define AARCH32_CNTHPS_CTL_IMASK 0x2U
11403#define AARCH32_CNTHPS_CTL_ISTATUS 0x4U
11405static inline uint32_t _AArch32_Read_cnthps_ctl(
void )
11410 "mrc p15, 0, %0, c14, c2, 1" :
"=&r" ( value ) : :
"memory"
11416static inline void _AArch32_Write_cnthps_ctl( uint32_t value )
11419 "mcr p15, 0, %0, c14, c2, 1" : :
"r" ( value ) :
"memory"
11425static inline uint64_t _AArch32_Read_cnthps_cval(
void )
11430 "mrrc p15, 2, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11436static inline void _AArch32_Write_cnthps_cval( uint64_t value )
11439 "mcrr p15, 2, %Q0, %R0, c14" : :
"r" ( value ) :
"memory"
11445static inline uint32_t _AArch32_Read_cnthps_tval(
void )
11450 "mrc p15, 0, %0, c14, c2, 0" :
"=&r" ( value ) : :
"memory"
11456static inline void _AArch32_Write_cnthps_tval( uint32_t value )
11459 "mcr p15, 0, %0, c14, c2, 0" : :
"r" ( value ) :
"memory"
11465#define AARCH32_CNTHV_CTL_ENABLE 0x1U
11467#define AARCH32_CNTHV_CTL_IMASK 0x2U
11469#define AARCH32_CNTHV_CTL_ISTATUS 0x4U
11471static inline uint32_t _AArch32_Read_cnthv_ctl(
void )
11476 "mrc p15, 0, %0, c14, c3, 1" :
"=&r" ( value ) : :
"memory"
11482static inline void _AArch32_Write_cnthv_ctl( uint32_t value )
11485 "mcr p15, 0, %0, c14, c3, 1" : :
"r" ( value ) :
"memory"
11491static inline uint64_t _AArch32_Read_cnthv_cval(
void )
11496 "mrrc p15, 3, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11502static inline void _AArch32_Write_cnthv_cval( uint64_t value )
11505 "mcrr p15, 3, %Q0, %R0, c14" : :
"r" ( value ) :
"memory"
11511static inline uint32_t _AArch32_Read_cnthv_tval(
void )
11516 "mrc p15, 0, %0, c14, c3, 0" :
"=&r" ( value ) : :
"memory"
11522static inline void _AArch32_Write_cnthv_tval( uint32_t value )
11525 "mcr p15, 0, %0, c14, c3, 0" : :
"r" ( value ) :
"memory"
11531#define AARCH32_CNTHVS_CTL_ENABLE 0x1U
11533#define AARCH32_CNTHVS_CTL_IMASK 0x2U
11535#define AARCH32_CNTHVS_CTL_ISTATUS 0x4U
11537static inline uint32_t _AArch32_Read_cnthvs_ctl(
void )
11542 "mrc p15, 0, %0, c14, c3, 1" :
"=&r" ( value ) : :
"memory"
11548static inline void _AArch32_Write_cnthvs_ctl( uint32_t value )
11551 "mcr p15, 0, %0, c14, c3, 1" : :
"r" ( value ) :
"memory"
11557static inline uint64_t _AArch32_Read_cnthvs_cval(
void )
11562 "mrrc p15, 3, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11568static inline void _AArch32_Write_cnthvs_cval( uint64_t value )
11571 "mcrr p15, 3, %Q0, %R0, c14" : :
"r" ( value ) :
"memory"
11577static inline uint32_t _AArch32_Read_cnthvs_tval(
void )
11582 "mrc p15, 0, %0, c14, c3, 0" :
"=&r" ( value ) : :
"memory"
11588static inline void _AArch32_Write_cnthvs_tval( uint32_t value )
11591 "mcr p15, 0, %0, c14, c3, 0" : :
"r" ( value ) :
"memory"
11597#define AARCH32_CNTKCTL_PL0PCTEN 0x1U
11599#define AARCH32_CNTKCTL_PL0VCTEN 0x2U
11601#define AARCH32_CNTKCTL_EVNTEN 0x4U
11603#define AARCH32_CNTKCTL_EVNTDIR 0x8U
11605#define AARCH32_CNTKCTL_EVNTI( _val ) ( ( _val ) << 4 )
11606#define AARCH32_CNTKCTL_EVNTI_SHIFT 4
11607#define AARCH32_CNTKCTL_EVNTI_MASK 0xf0U
11608#define AARCH32_CNTKCTL_EVNTI_GET( _reg ) \
11609 ( ( ( _reg ) >> 4 ) & 0xfU )
11611#define AARCH32_CNTKCTL_PL0VTEN 0x100U
11613#define AARCH32_CNTKCTL_PL0PTEN 0x200U
11615#define AARCH32_CNTKCTL_EVNTIS 0x20000U
11617static inline uint32_t _AArch32_Read_cntkctl(
void )
11622 "mrc p15, 0, %0, c14, c1, 0" :
"=&r" ( value ) : :
"memory"
11628static inline void _AArch32_Write_cntkctl( uint32_t value )
11631 "mcr p15, 0, %0, c14, c1, 0" : :
"r" ( value ) :
"memory"
11637#define AARCH32_CNTP_CTL_ENABLE 0x1U
11639#define AARCH32_CNTP_CTL_IMASK 0x2U
11641#define AARCH32_CNTP_CTL_ISTATUS 0x4U
11643static inline uint32_t _AArch32_Read_cntp_ctl(
void )
11648 "mrc p15, 0, %0, c14, c2, 1" :
"=&r" ( value ) : :
"memory"
11654static inline void _AArch32_Write_cntp_ctl( uint32_t value )
11657 "mcr p15, 0, %0, c14, c2, 1" : :
"r" ( value ) :
"memory"
11663static inline uint64_t _AArch32_Read_cntp_cval(
void )
11668 "mrrc p15, 2, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11674static inline void _AArch32_Write_cntp_cval( uint64_t value )
11677 "mcrr p15, 2, %Q0, %R0, c14" : :
"r" ( value ) :
"memory"
11683static inline uint32_t _AArch32_Read_cntp_tval(
void )
11688 "mrc p15, 0, %0, c14, c2, 0" :
"=&r" ( value ) : :
"memory"
11694static inline void _AArch32_Write_cntp_tval( uint32_t value )
11697 "mcr p15, 0, %0, c14, c2, 0" : :
"r" ( value ) :
"memory"
11703static inline uint64_t _AArch32_Read_cntpct(
void )
11708 "mrrc p15, 0, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11716static inline uint64_t _AArch32_Read_cntpctss(
void )
11721 "mrrc p15, 8, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11729#define AARCH32_CNTV_CTL_ENABLE 0x1U
11731#define AARCH32_CNTV_CTL_IMASK 0x2U
11733#define AARCH32_CNTV_CTL_ISTATUS 0x4U
11735static inline uint32_t _AArch32_Read_cntv_ctl(
void )
11740 "mrc p15, 0, %0, c14, c3, 1" :
"=&r" ( value ) : :
"memory"
11746static inline void _AArch32_Write_cntv_ctl( uint32_t value )
11749 "mcr p15, 0, %0, c14, c3, 1" : :
"r" ( value ) :
"memory"
11755static inline uint64_t _AArch32_Read_cntv_cval(
void )
11760 "mrrc p15, 3, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11766static inline void _AArch32_Write_cntv_cval( uint64_t value )
11769 "mcrr p15, 3, %Q0, %R0, c14" : :
"r" ( value ) :
"memory"
11775static inline uint32_t _AArch32_Read_cntv_tval(
void )
11780 "mrc p15, 0, %0, c14, c3, 0" :
"=&r" ( value ) : :
"memory"
11786static inline void _AArch32_Write_cntv_tval( uint32_t value )
11789 "mcr p15, 0, %0, c14, c3, 0" : :
"r" ( value ) :
"memory"
11795static inline uint64_t _AArch32_Read_cntvct(
void )
11800 "mrrc p15, 1, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11808static inline uint64_t _AArch32_Read_cntvctss(
void )
11813 "mrrc p15, 9, %Q0, %R0, c14" :
"=&r" ( value ) : :
"memory"
11821#define AARCH32_HMPUIR_REGION( _val ) ( ( _val ) << 0 )
11822#define AARCH32_HMPUIR_REGION_SHIFT 0
11823#define AARCH32_HMPUIR_REGION_MASK 0xffU
11824#define AARCH32_HMPUIR_REGION_GET( _reg ) \
11825 ( ( ( _reg ) >> 0 ) & 0xffU )
11827static inline uint32_t _AArch32_Read_hmpuir(
void )
11832 "mrc p15, 4, %0, c0, c0, 4" :
"=&r" ( value ) : :
"memory"
11838static inline void _AArch32_Write_hmpuir( uint32_t value )
11841 "mcr p15, 4, %0, c0, c0, 4" : :
"r" ( value ) :
"memory"
11847#define AARCH32_HPRBAR_XN 0x1U
11849#define AARCH32_HPRBAR_AP_2_1( _val ) ( ( _val ) << 1 )
11850#define AARCH32_HPRBAR_AP_2_1_SHIFT 1
11851#define AARCH32_HPRBAR_AP_2_1_MASK 0x6U
11852#define AARCH32_HPRBAR_AP_2_1_GET( _reg ) \
11853 ( ( ( _reg ) >> 1 ) & 0x3U )
11855#define AARCH32_HPRBAR_SH_1_0( _val ) ( ( _val ) << 3 )
11856#define AARCH32_HPRBAR_SH_1_0_SHIFT 3
11857#define AARCH32_HPRBAR_SH_1_0_MASK 0x18U
11858#define AARCH32_HPRBAR_SH_1_0_GET( _reg ) \
11859 ( ( ( _reg ) >> 3 ) & 0x3U )
11861#define AARCH32_HPRBAR_BASE( _val ) ( ( _val ) << 6 )
11862#define AARCH32_HPRBAR_BASE_SHIFT 6
11863#define AARCH32_HPRBAR_BASE_MASK 0xffffffc0U
11864#define AARCH32_HPRBAR_BASE_GET( _reg ) \
11865 ( ( ( _reg ) >> 6 ) & 0x3ffffffU )
11867static inline uint32_t _AArch32_Read_hprbar(
void )
11872 "mrc p15, 4, %0, c6, c3, 0" :
"=&r" ( value ) : :
"memory"
11878static inline void _AArch32_Write_hprbar( uint32_t value )
11881 "mcr p15, 4, %0, c6, c3, 0" : :
"r" ( value ) :
"memory"
11887static inline uint32_t _AArch32_Read_hprbar_0(
void )
11892 "mrc p15, 4, %0, c6, c8, 0" :
"=&r" ( value ) : :
"memory"
11898static inline void _AArch32_Write_hprbar_0( uint32_t value )
11901 "mcr p15, 4, %0, c6, c8, 0" : :
"r" ( value ) :
"memory"
11907static inline uint32_t _AArch32_Read_hprbar_1(
void )
11912 "mrc p15, 4, %0, c6, c8, 4" :
"=&r" ( value ) : :
"memory"
11918static inline void _AArch32_Write_hprbar_1( uint32_t value )
11921 "mcr p15, 4, %0, c6, c8, 4" : :
"r" ( value ) :
"memory"
11927static inline uint32_t _AArch32_Read_hprbar_2(
void )
11932 "mrc p15, 4, %0, c6, c9, 0" :
"=&r" ( value ) : :
"memory"
11938static inline void _AArch32_Write_hprbar_2( uint32_t value )
11941 "mcr p15, 4, %0, c6, c9, 0" : :
"r" ( value ) :
"memory"
11947static inline uint32_t _AArch32_Read_hprbar_3(
void )
11952 "mrc p15, 4, %0, c6, c9, 4" :
"=&r" ( value ) : :
"memory"
11958static inline void _AArch32_Write_hprbar_3( uint32_t value )
11961 "mcr p15, 4, %0, c6, c9, 4" : :
"r" ( value ) :
"memory"
11967static inline uint32_t _AArch32_Read_hprbar_4(
void )
11972 "mrc p15, 4, %0, c6, c10, 0" :
"=&r" ( value ) : :
"memory"
11978static inline void _AArch32_Write_hprbar_4( uint32_t value )
11981 "mcr p15, 4, %0, c6, c10, 0" : :
"r" ( value ) :
"memory"
11987static inline uint32_t _AArch32_Read_hprbar_5(
void )
11992 "mrc p15, 4, %0, c6, c10, 4" :
"=&r" ( value ) : :
"memory"
11998static inline void _AArch32_Write_hprbar_5( uint32_t value )
12001 "mcr p15, 4, %0, c6, c10, 4" : :
"r" ( value ) :
"memory"
12007static inline uint32_t _AArch32_Read_hprbar_6(
void )
12012 "mrc p15, 4, %0, c6, c11, 0" :
"=&r" ( value ) : :
"memory"
12018static inline void _AArch32_Write_hprbar_6( uint32_t value )
12021 "mcr p15, 4, %0, c6, c11, 0" : :
"r" ( value ) :
"memory"
12027static inline uint32_t _AArch32_Read_hprbar_7(
void )
12032 "mrc p15, 4, %0, c6, c11, 4" :
"=&r" ( value ) : :
"memory"
12038static inline void _AArch32_Write_hprbar_7( uint32_t value )
12041 "mcr p15, 4, %0, c6, c11, 4" : :
"r" ( value ) :
"memory"
12047static inline uint32_t _AArch32_Read_hprbar_8(
void )
12052 "mrc p15, 4, %0, c6, c12, 0" :
"=&r" ( value ) : :
"memory"
12058static inline void _AArch32_Write_hprbar_8( uint32_t value )
12061 "mcr p15, 4, %0, c6, c12, 0" : :
"r" ( value ) :
"memory"
12067static inline uint32_t _AArch32_Read_hprbar_9(
void )
12072 "mrc p15, 4, %0, c6, c12, 4" :
"=&r" ( value ) : :
"memory"
12078static inline void _AArch32_Write_hprbar_9( uint32_t value )
12081 "mcr p15, 4, %0, c6, c12, 4" : :
"r" ( value ) :
"memory"
12087static inline uint32_t _AArch32_Read_hprbar_10(
void )
12092 "mrc p15, 4, %0, c6, c13, 0" :
"=&r" ( value ) : :
"memory"
12098static inline void _AArch32_Write_hprbar_10( uint32_t value )
12101 "mcr p15, 4, %0, c6, c13, 0" : :
"r" ( value ) :
"memory"
12107static inline uint32_t _AArch32_Read_hprbar_11(
void )
12112 "mrc p15, 4, %0, c6, c13, 4" :
"=&r" ( value ) : :
"memory"
12118static inline void _AArch32_Write_hprbar_11( uint32_t value )
12121 "mcr p15, 4, %0, c6, c13, 4" : :
"r" ( value ) :
"memory"
12127static inline uint32_t _AArch32_Read_hprbar_12(
void )
12132 "mrc p15, 4, %0, c6, c14, 0" :
"=&r" ( value ) : :
"memory"
12138static inline void _AArch32_Write_hprbar_12( uint32_t value )
12141 "mcr p15, 4, %0, c6, c14, 0" : :
"r" ( value ) :
"memory"
12147static inline uint32_t _AArch32_Read_hprbar_13(
void )
12152 "mrc p15, 4, %0, c6, c14, 4" :
"=&r" ( value ) : :
"memory"
12158static inline void _AArch32_Write_hprbar_13( uint32_t value )
12161 "mcr p15, 4, %0, c6, c14, 4" : :
"r" ( value ) :
"memory"
12167static inline uint32_t _AArch32_Read_hprbar_14(
void )
12172 "mrc p15, 4, %0, c6, c15, 0" :
"=&r" ( value ) : :
"memory"
12178static inline void _AArch32_Write_hprbar_14( uint32_t value )
12181 "mcr p15, 4, %0, c6, c15, 0" : :
"r" ( value ) :
"memory"
12187static inline uint32_t _AArch32_Read_hprbar_15(
void )
12192 "mrc p15, 4, %0, c6, c15, 4" :
"=&r" ( value ) : :
"memory"
12198static inline void _AArch32_Write_hprbar_15( uint32_t value )
12201 "mcr p15, 4, %0, c6, c15, 4" : :
"r" ( value ) :
"memory"
12207static inline uint32_t _AArch32_Read_hprbar_16(
void )
12212 "mrc p15, 5, %0, c6, c8, 0" :
"=&r" ( value ) : :
"memory"
12218static inline void _AArch32_Write_hprbar_16( uint32_t value )
12221 "mcr p15, 5, %0, c6, c8, 0" : :
"r" ( value ) :
"memory"
12227static inline uint32_t _AArch32_Read_hprbar_17(
void )
12232 "mrc p15, 5, %0, c6, c8, 4" :
"=&r" ( value ) : :
"memory"
12238static inline void _AArch32_Write_hprbar_17( uint32_t value )
12241 "mcr p15, 5, %0, c6, c8, 4" : :
"r" ( value ) :
"memory"
12247static inline uint32_t _AArch32_Read_hprbar_18(
void )
12252 "mrc p15, 5, %0, c6, c9, 0" :
"=&r" ( value ) : :
"memory"
12258static inline void _AArch32_Write_hprbar_18( uint32_t value )
12261 "mcr p15, 5, %0, c6, c9, 0" : :
"r" ( value ) :
"memory"
12267static inline uint32_t _AArch32_Read_hprbar_19(
void )
12272 "mrc p15, 5, %0, c6, c9, 4" :
"=&r" ( value ) : :
"memory"
12278static inline void _AArch32_Write_hprbar_19( uint32_t value )
12281 "mcr p15, 5, %0, c6, c9, 4" : :
"r" ( value ) :
"memory"
12287static inline uint32_t _AArch32_Read_hprbar_20(
void )
12292 "mrc p15, 5, %0, c6, c10, 0" :
"=&r" ( value ) : :
"memory"
12298static inline void _AArch32_Write_hprbar_20( uint32_t value )
12301 "mcr p15, 5, %0, c6, c10, 0" : :
"r" ( value ) :
"memory"
12307static inline uint32_t _AArch32_Read_hprbar_21(
void )
12312 "mrc p15, 5, %0, c6, c10, 4" :
"=&r" ( value ) : :
"memory"
12318static inline void _AArch32_Write_hprbar_21( uint32_t value )
12321 "mcr p15, 5, %0, c6, c10, 4" : :
"r" ( value ) :
"memory"
12327static inline uint32_t _AArch32_Read_hprbar_22(
void )
12332 "mrc p15, 5, %0, c6, c11, 0" :
"=&r" ( value ) : :
"memory"
12338static inline void _AArch32_Write_hprbar_22( uint32_t value )
12341 "mcr p15, 5, %0, c6, c11, 0" : :
"r" ( value ) :
"memory"
12347static inline uint32_t _AArch32_Read_hprbar_23(
void )
12352 "mrc p15, 5, %0, c6, c11, 4" :
"=&r" ( value ) : :
"memory"
12358static inline void _AArch32_Write_hprbar_23( uint32_t value )
12361 "mcr p15, 5, %0, c6, c11, 4" : :
"r" ( value ) :
"memory"
12367static inline uint32_t _AArch32_Read_hprbar_24(
void )
12372 "mrc p15, 5, %0, c6, c12, 0" :
"=&r" ( value ) : :
"memory"
12378static inline void _AArch32_Write_hprbar_24( uint32_t value )
12381 "mcr p15, 5, %0, c6, c12, 0" : :
"r" ( value ) :
"memory"
12387static inline uint32_t _AArch32_Read_hprbar_25(
void )
12392 "mrc p15, 5, %0, c6, c12, 4" :
"=&r" ( value ) : :
"memory"
12398static inline void _AArch32_Write_hprbar_25( uint32_t value )
12401 "mcr p15, 5, %0, c6, c12, 4" : :
"r" ( value ) :
"memory"
12407static inline uint32_t _AArch32_Read_hprbar_26(
void )
12412 "mrc p15, 5, %0, c6, c13, 0" :
"=&r" ( value ) : :
"memory"
12418static inline void _AArch32_Write_hprbar_26( uint32_t value )
12421 "mcr p15, 5, %0, c6, c13, 0" : :
"r" ( value ) :
"memory"
12427static inline uint32_t _AArch32_Read_hprbar_27(
void )
12432 "mrc p15, 5, %0, c6, c13, 4" :
"=&r" ( value ) : :
"memory"
12438static inline void _AArch32_Write_hprbar_27( uint32_t value )
12441 "mcr p15, 5, %0, c6, c13, 4" : :
"r" ( value ) :
"memory"
12447static inline uint32_t _AArch32_Read_hprbar_28(
void )
12452 "mrc p15, 5, %0, c6, c14, 0" :
"=&r" ( value ) : :
"memory"
12458static inline void _AArch32_Write_hprbar_28( uint32_t value )
12461 "mcr p15, 5, %0, c6, c14, 0" : :
"r" ( value ) :
"memory"
12467static inline uint32_t _AArch32_Read_hprbar_29(
void )
12472 "mrc p15, 5, %0, c6, c14, 4" :
"=&r" ( value ) : :
"memory"
12478static inline void _AArch32_Write_hprbar_29( uint32_t value )
12481 "mcr p15, 5, %0, c6, c14, 4" : :
"r" ( value ) :
"memory"
12487static inline uint32_t _AArch32_Read_hprbar_30(
void )
12492 "mrc p15, 5, %0, c6, c15, 0" :
"=&r" ( value ) : :
"memory"
12498static inline void _AArch32_Write_hprbar_30( uint32_t value )
12501 "mcr p15, 5, %0, c6, c15, 0" : :
"r" ( value ) :
"memory"
12507static inline uint32_t _AArch32_Read_hprbar_31(
void )
12512 "mrc p15, 5, %0, c6, c15, 4" :
"=&r" ( value ) : :
"memory"
12518static inline void _AArch32_Write_hprbar_31( uint32_t value )
12521 "mcr p15, 5, %0, c6, c15, 4" : :
"r" ( value ) :
"memory"
12527static inline uint32_t _AArch32_Read_hprenr(
void )
12532 "mrc p15, 4, %0, c6, c1, 1" :
"=&r" ( value ) : :
"memory"
12538static inline void _AArch32_Write_hprenr( uint32_t value )
12541 "mcr p15, 4, %0, c6, c1, 1" : :
"r" ( value ) :
"memory"
12547#define AARCH32_HPRLAR_EN 0x1U
12549#define AARCH32_HPRLAR_ATTRINDX_2_0( _val ) ( ( _val ) << 1 )
12550#define AARCH32_HPRLAR_ATTRINDX_2_0_SHIFT 1
12551#define AARCH32_HPRLAR_ATTRINDX_2_0_MASK 0xeU
12552#define AARCH32_HPRLAR_ATTRINDX_2_0_GET( _reg ) \
12553 ( ( ( _reg ) >> 1 ) & 0x7U )
12555#define AARCH32_HPRLAR_LIMIT( _val ) ( ( _val ) << 6 )
12556#define AARCH32_HPRLAR_LIMIT_SHIFT 6
12557#define AARCH32_HPRLAR_LIMIT_MASK 0xffffffc0U
12558#define AARCH32_HPRLAR_LIMIT_GET( _reg ) \
12559 ( ( ( _reg ) >> 6 ) & 0x3ffffffU )
12561static inline uint32_t _AArch32_Read_hprlar(
void )
12566 "mrc p15, 4, %0, c6, c3, 1" :
"=&r" ( value ) : :
"memory"
12572static inline void _AArch32_Write_hprlar( uint32_t value )
12575 "mcr p15, 4, %0, c6, c3, 1" : :
"r" ( value ) :
"memory"
12581static inline uint32_t _AArch32_Read_hprlar_0(
void )
12586 "mrc p15, 4, %0, c6, c8, 1" :
"=&r" ( value ) : :
"memory"
12592static inline void _AArch32_Write_hprlar_0( uint32_t value )
12595 "mcr p15, 4, %0, c6, c8, 1" : :
"r" ( value ) :
"memory"
12601static inline uint32_t _AArch32_Read_hprlar_1(
void )
12606 "mrc p15, 4, %0, c6, c8, 5" :
"=&r" ( value ) : :
"memory"
12612static inline void _AArch32_Write_hprlar_1( uint32_t value )
12615 "mcr p15, 4, %0, c6, c8, 5" : :
"r" ( value ) :
"memory"
12621static inline uint32_t _AArch32_Read_hprlar_2(
void )
12626 "mrc p15, 4, %0, c6, c9, 1" :
"=&r" ( value ) : :
"memory"
12632static inline void _AArch32_Write_hprlar_2( uint32_t value )
12635 "mcr p15, 4, %0, c6, c9, 1" : :
"r" ( value ) :
"memory"
12641static inline uint32_t _AArch32_Read_hprlar_3(
void )
12646 "mrc p15, 4, %0, c6, c9, 5" :
"=&r" ( value ) : :
"memory"
12652static inline void _AArch32_Write_hprlar_3( uint32_t value )
12655 "mcr p15, 4, %0, c6, c9, 5" : :
"r" ( value ) :
"memory"
12661static inline uint32_t _AArch32_Read_hprlar_4(
void )
12666 "mrc p15, 4, %0, c6, c10, 1" :
"=&r" ( value ) : :
"memory"
12672static inline void _AArch32_Write_hprlar_4( uint32_t value )
12675 "mcr p15, 4, %0, c6, c10, 1" : :
"r" ( value ) :
"memory"
12681static inline uint32_t _AArch32_Read_hprlar_5(
void )
12686 "mrc p15, 4, %0, c6, c10, 5" :
"=&r" ( value ) : :
"memory"
12692static inline void _AArch32_Write_hprlar_5( uint32_t value )
12695 "mcr p15, 4, %0, c6, c10, 5" : :
"r" ( value ) :
"memory"
12701static inline uint32_t _AArch32_Read_hprlar_6(
void )
12706 "mrc p15, 4, %0, c6, c11, 1" :
"=&r" ( value ) : :
"memory"
12712static inline void _AArch32_Write_hprlar_6( uint32_t value )
12715 "mcr p15, 4, %0, c6, c11, 1" : :
"r" ( value ) :
"memory"
12721static inline uint32_t _AArch32_Read_hprlar_7(
void )
12726 "mrc p15, 4, %0, c6, c11, 5" :
"=&r" ( value ) : :
"memory"
12732static inline void _AArch32_Write_hprlar_7( uint32_t value )
12735 "mcr p15, 4, %0, c6, c11, 5" : :
"r" ( value ) :
"memory"
12741static inline uint32_t _AArch32_Read_hprlar_8(
void )
12746 "mrc p15, 4, %0, c6, c12, 1" :
"=&r" ( value ) : :
"memory"
12752static inline void _AArch32_Write_hprlar_8( uint32_t value )
12755 "mcr p15, 4, %0, c6, c12, 1" : :
"r" ( value ) :
"memory"
12761static inline uint32_t _AArch32_Read_hprlar_9(
void )
12766 "mrc p15, 4, %0, c6, c12, 5" :
"=&r" ( value ) : :
"memory"
12772static inline void _AArch32_Write_hprlar_9( uint32_t value )
12775 "mcr p15, 4, %0, c6, c12, 5" : :
"r" ( value ) :
"memory"
12781static inline uint32_t _AArch32_Read_hprlar_10(
void )
12786 "mrc p15, 4, %0, c6, c13, 1" :
"=&r" ( value ) : :
"memory"
12792static inline void _AArch32_Write_hprlar_10( uint32_t value )
12795 "mcr p15, 4, %0, c6, c13, 1" : :
"r" ( value ) :
"memory"
12801static inline uint32_t _AArch32_Read_hprlar_11(
void )
12806 "mrc p15, 4, %0, c6, c13, 5" :
"=&r" ( value ) : :
"memory"
12812static inline void _AArch32_Write_hprlar_11( uint32_t value )
12815 "mcr p15, 4, %0, c6, c13, 5" : :
"r" ( value ) :
"memory"
12821static inline uint32_t _AArch32_Read_hprlar_12(
void )
12826 "mrc p15, 4, %0, c6, c14, 1" :
"=&r" ( value ) : :
"memory"
12832static inline void _AArch32_Write_hprlar_12( uint32_t value )
12835 "mcr p15, 4, %0, c6, c14, 1" : :
"r" ( value ) :
"memory"
12841static inline uint32_t _AArch32_Read_hprlar_13(
void )
12846 "mrc p15, 4, %0, c6, c14, 5" :
"=&r" ( value ) : :
"memory"
12852static inline void _AArch32_Write_hprlar_13( uint32_t value )
12855 "mcr p15, 4, %0, c6, c14, 5" : :
"r" ( value ) :
"memory"
12861static inline uint32_t _AArch32_Read_hprlar_14(
void )
12866 "mrc p15, 4, %0, c6, c15, 1" :
"=&r" ( value ) : :
"memory"
12872static inline void _AArch32_Write_hprlar_14( uint32_t value )
12875 "mcr p15, 4, %0, c6, c15, 1" : :
"r" ( value ) :
"memory"
12881static inline uint32_t _AArch32_Read_hprlar_15(
void )
12886 "mrc p15, 4, %0, c6, c15, 5" :
"=&r" ( value ) : :
"memory"
12892static inline void _AArch32_Write_hprlar_15( uint32_t value )
12895 "mcr p15, 4, %0, c6, c15, 5" : :
"r" ( value ) :
"memory"
12901static inline uint32_t _AArch32_Read_hprlar_16(
void )
12906 "mrc p15, 5, %0, c6, c8, 1" :
"=&r" ( value ) : :
"memory"
12912static inline void _AArch32_Write_hprlar_16( uint32_t value )
12915 "mcr p15, 5, %0, c6, c8, 1" : :
"r" ( value ) :
"memory"
12921static inline uint32_t _AArch32_Read_hprlar_17(
void )
12926 "mrc p15, 5, %0, c6, c8, 5" :
"=&r" ( value ) : :
"memory"
12932static inline void _AArch32_Write_hprlar_17( uint32_t value )
12935 "mcr p15, 5, %0, c6, c8, 5" : :
"r" ( value ) :
"memory"
12941static inline uint32_t _AArch32_Read_hprlar_18(
void )
12946 "mrc p15, 5, %0, c6, c9, 1" :
"=&r" ( value ) : :
"memory"
12952static inline void _AArch32_Write_hprlar_18( uint32_t value )
12955 "mcr p15, 5, %0, c6, c9, 1" : :
"r" ( value ) :
"memory"
12961static inline uint32_t _AArch32_Read_hprlar_19(
void )
12966 "mrc p15, 5, %0, c6, c9, 5" :
"=&r" ( value ) : :
"memory"
12972static inline void _AArch32_Write_hprlar_19( uint32_t value )
12975 "mcr p15, 5, %0, c6, c9, 5" : :
"r" ( value ) :
"memory"
12981static inline uint32_t _AArch32_Read_hprlar_20(
void )
12986 "mrc p15, 5, %0, c6, c10, 1" :
"=&r" ( value ) : :
"memory"
12992static inline void _AArch32_Write_hprlar_20( uint32_t value )
12995 "mcr p15, 5, %0, c6, c10, 1" : :
"r" ( value ) :
"memory"
13001static inline uint32_t _AArch32_Read_hprlar_21(
void )
13006 "mrc p15, 5, %0, c6, c10, 5" :
"=&r" ( value ) : :
"memory"
13012static inline void _AArch32_Write_hprlar_21( uint32_t value )
13015 "mcr p15, 5, %0, c6, c10, 5" : :
"r" ( value ) :
"memory"
13021static inline uint32_t _AArch32_Read_hprlar_22(
void )
13026 "mrc p15, 5, %0, c6, c11, 1" :
"=&r" ( value ) : :
"memory"
13032static inline void _AArch32_Write_hprlar_22( uint32_t value )
13035 "mcr p15, 5, %0, c6, c11, 1" : :
"r" ( value ) :
"memory"
13041static inline uint32_t _AArch32_Read_hprlar_23(
void )
13046 "mrc p15, 5, %0, c6, c11, 5" :
"=&r" ( value ) : :
"memory"
13052static inline void _AArch32_Write_hprlar_23( uint32_t value )
13055 "mcr p15, 5, %0, c6, c11, 5" : :
"r" ( value ) :
"memory"
13061static inline uint32_t _AArch32_Read_hprlar_24(
void )
13066 "mrc p15, 5, %0, c6, c12, 1" :
"=&r" ( value ) : :
"memory"
13072static inline void _AArch32_Write_hprlar_24( uint32_t value )
13075 "mcr p15, 5, %0, c6, c12, 1" : :
"r" ( value ) :
"memory"
13081static inline uint32_t _AArch32_Read_hprlar_25(
void )
13086 "mrc p15, 5, %0, c6, c12, 5" :
"=&r" ( value ) : :
"memory"
13092static inline void _AArch32_Write_hprlar_25( uint32_t value )
13095 "mcr p15, 5, %0, c6, c12, 5" : :
"r" ( value ) :
"memory"
13101static inline uint32_t _AArch32_Read_hprlar_26(
void )
13106 "mrc p15, 5, %0, c6, c13, 1" :
"=&r" ( value ) : :
"memory"
13112static inline void _AArch32_Write_hprlar_26( uint32_t value )
13115 "mcr p15, 5, %0, c6, c13, 1" : :
"r" ( value ) :
"memory"
13121static inline uint32_t _AArch32_Read_hprlar_27(
void )
13126 "mrc p15, 5, %0, c6, c13, 5" :
"=&r" ( value ) : :
"memory"
13132static inline void _AArch32_Write_hprlar_27( uint32_t value )
13135 "mcr p15, 5, %0, c6, c13, 5" : :
"r" ( value ) :
"memory"
13141static inline uint32_t _AArch32_Read_hprlar_28(
void )
13146 "mrc p15, 5, %0, c6, c14, 1" :
"=&r" ( value ) : :
"memory"
13152static inline void _AArch32_Write_hprlar_28( uint32_t value )
13155 "mcr p15, 5, %0, c6, c14, 1" : :
"r" ( value ) :
"memory"
13161static inline uint32_t _AArch32_Read_hprlar_29(
void )
13166 "mrc p15, 5, %0, c6, c14, 5" :
"=&r" ( value ) : :
"memory"
13172static inline void _AArch32_Write_hprlar_29( uint32_t value )
13175 "mcr p15, 5, %0, c6, c14, 5" : :
"r" ( value ) :
"memory"
13181static inline uint32_t _AArch32_Read_hprlar_30(
void )
13186 "mrc p15, 5, %0, c6, c15, 1" :
"=&r" ( value ) : :
"memory"
13192static inline void _AArch32_Write_hprlar_30( uint32_t value )
13195 "mcr p15, 5, %0, c6, c15, 1" : :
"r" ( value ) :
"memory"
13201static inline uint32_t _AArch32_Read_hprlar_31(
void )
13206 "mrc p15, 5, %0, c6, c15, 5" :
"=&r" ( value ) : :
"memory"
13212static inline void _AArch32_Write_hprlar_31( uint32_t value )
13215 "mcr p15, 5, %0, c6, c15, 5" : :
"r" ( value ) :
"memory"
13221#define AARCH32_HPRSELR_REGION( _val ) ( ( _val ) << 0 )
13222#define AARCH32_HPRSELR_REGION_SHIFT 0
13223#define AARCH32_HPRSELR_REGION_MASK 0xffU
13224#define AARCH32_HPRSELR_REGION_GET( _reg ) \
13225 ( ( ( _reg ) >> 0 ) & 0xffU )
13227static inline uint32_t _AArch32_Read_hprselr(
void )
13232 "mrc p15, 4, %0, c6, c2, 1" :
"=&r" ( value ) : :
"memory"
13238static inline void _AArch32_Write_hprselr( uint32_t value )
13241 "mcr p15, 4, %0, c6, c2, 1" : :
"r" ( value ) :
"memory"
13247#define AARCH32_MPUIR_REGION( _val ) ( ( _val ) << 8 )
13248#define AARCH32_MPUIR_REGION_SHIFT 8
13249#define AARCH32_MPUIR_REGION_MASK 0xff00U
13250#define AARCH32_MPUIR_REGION_GET( _reg ) \
13251 ( ( ( _reg ) >> 8 ) & 0xffU )
13253static inline uint32_t _AArch32_Read_mpuir(
void )
13258 "mrc p15, 0, %0, c0, c0, 4" :
"=&r" ( value ) : :
"memory"
13264static inline void _AArch32_Write_mpuir( uint32_t value )
13267 "mcr p15, 0, %0, c0, c0, 4" : :
"r" ( value ) :
"memory"
13273#define AARCH32_PRBAR_XN 0x1U
13275#define AARCH32_PRBAR_AP_2_1( _val ) ( ( _val ) << 1 )
13276#define AARCH32_PRBAR_AP_2_1_SHIFT 1
13277#define AARCH32_PRBAR_AP_2_1_MASK 0x6U
13278#define AARCH32_PRBAR_AP_2_1_GET( _reg ) \
13279 ( ( ( _reg ) >> 1 ) & 0x3U )
13281#define AARCH32_PRBAR_SH_1_0( _val ) ( ( _val ) << 3 )
13282#define AARCH32_PRBAR_SH_1_0_SHIFT 3
13283#define AARCH32_PRBAR_SH_1_0_MASK 0x18U
13284#define AARCH32_PRBAR_SH_1_0_GET( _reg ) \
13285 ( ( ( _reg ) >> 3 ) & 0x3U )
13287#define AARCH32_PRBAR_BASE( _val ) ( ( _val ) << 6 )
13288#define AARCH32_PRBAR_BASE_SHIFT 6
13289#define AARCH32_PRBAR_BASE_MASK 0xffffffc0U
13290#define AARCH32_PRBAR_BASE_GET( _reg ) \
13291 ( ( ( _reg ) >> 6 ) & 0x3ffffffU )
13293static inline uint32_t _AArch32_Read_prbar(
void )
13298 "mrc p15, 0, %0, c6, c3, 0" :
"=&r" ( value ) : :
"memory"
13304static inline void _AArch32_Write_prbar( uint32_t value )
13307 "mcr p15, 0, %0, c6, c3, 0" : :
"r" ( value ) :
"memory"
13313static inline uint32_t _AArch32_Read_prbar_0(
void )
13318 "mrc p15, 0, %0, c6, c8, 0" :
"=&r" ( value ) : :
"memory"
13324static inline void _AArch32_Write_prbar_0( uint32_t value )
13327 "mcr p15, 0, %0, c6, c8, 0" : :
"r" ( value ) :
"memory"
13333static inline uint32_t _AArch32_Read_prbar_1(
void )
13338 "mrc p15, 0, %0, c6, c8, 4" :
"=&r" ( value ) : :
"memory"
13344static inline void _AArch32_Write_prbar_1( uint32_t value )
13347 "mcr p15, 0, %0, c6, c8, 4" : :
"r" ( value ) :
"memory"
13353static inline uint32_t _AArch32_Read_prbar_2(
void )
13358 "mrc p15, 0, %0, c6, c9, 0" :
"=&r" ( value ) : :
"memory"
13364static inline void _AArch32_Write_prbar_2( uint32_t value )
13367 "mcr p15, 0, %0, c6, c9, 0" : :
"r" ( value ) :
"memory"
13373static inline uint32_t _AArch32_Read_prbar_3(
void )
13378 "mrc p15, 0, %0, c6, c9, 4" :
"=&r" ( value ) : :
"memory"
13384static inline void _AArch32_Write_prbar_3( uint32_t value )
13387 "mcr p15, 0, %0, c6, c9, 4" : :
"r" ( value ) :
"memory"
13393static inline uint32_t _AArch32_Read_prbar_4(
void )
13398 "mrc p15, 0, %0, c6, c10, 0" :
"=&r" ( value ) : :
"memory"
13404static inline void _AArch32_Write_prbar_4( uint32_t value )
13407 "mcr p15, 0, %0, c6, c10, 0" : :
"r" ( value ) :
"memory"
13413static inline uint32_t _AArch32_Read_prbar_5(
void )
13418 "mrc p15, 0, %0, c6, c10, 4" :
"=&r" ( value ) : :
"memory"
13424static inline void _AArch32_Write_prbar_5( uint32_t value )
13427 "mcr p15, 0, %0, c6, c10, 4" : :
"r" ( value ) :
"memory"
13433static inline uint32_t _AArch32_Read_prbar_6(
void )
13438 "mrc p15, 0, %0, c6, c11, 0" :
"=&r" ( value ) : :
"memory"
13444static inline void _AArch32_Write_prbar_6( uint32_t value )
13447 "mcr p15, 0, %0, c6, c11, 0" : :
"r" ( value ) :
"memory"
13453static inline uint32_t _AArch32_Read_prbar_7(
void )
13458 "mrc p15, 0, %0, c6, c11, 4" :
"=&r" ( value ) : :
"memory"
13464static inline void _AArch32_Write_prbar_7( uint32_t value )
13467 "mcr p15, 0, %0, c6, c11, 4" : :
"r" ( value ) :
"memory"
13473static inline uint32_t _AArch32_Read_prbar_8(
void )
13478 "mrc p15, 0, %0, c6, c12, 0" :
"=&r" ( value ) : :
"memory"
13484static inline void _AArch32_Write_prbar_8( uint32_t value )
13487 "mcr p15, 0, %0, c6, c12, 0" : :
"r" ( value ) :
"memory"
13493static inline uint32_t _AArch32_Read_prbar_9(
void )
13498 "mrc p15, 0, %0, c6, c12, 4" :
"=&r" ( value ) : :
"memory"
13504static inline void _AArch32_Write_prbar_9( uint32_t value )
13507 "mcr p15, 0, %0, c6, c12, 4" : :
"r" ( value ) :
"memory"
13513static inline uint32_t _AArch32_Read_prbar_10(
void )
13518 "mrc p15, 0, %0, c6, c13, 0" :
"=&r" ( value ) : :
"memory"
13524static inline void _AArch32_Write_prbar_10( uint32_t value )
13527 "mcr p15, 0, %0, c6, c13, 0" : :
"r" ( value ) :
"memory"
13533static inline uint32_t _AArch32_Read_prbar_11(
void )
13538 "mrc p15, 0, %0, c6, c13, 4" :
"=&r" ( value ) : :
"memory"
13544static inline void _AArch32_Write_prbar_11( uint32_t value )
13547 "mcr p15, 0, %0, c6, c13, 4" : :
"r" ( value ) :
"memory"
13553static inline uint32_t _AArch32_Read_prbar_12(
void )
13558 "mrc p15, 0, %0, c6, c14, 0" :
"=&r" ( value ) : :
"memory"
13564static inline void _AArch32_Write_prbar_12( uint32_t value )
13567 "mcr p15, 0, %0, c6, c14, 0" : :
"r" ( value ) :
"memory"
13573static inline uint32_t _AArch32_Read_prbar_13(
void )
13578 "mrc p15, 0, %0, c6, c14, 4" :
"=&r" ( value ) : :
"memory"
13584static inline void _AArch32_Write_prbar_13( uint32_t value )
13587 "mcr p15, 0, %0, c6, c14, 4" : :
"r" ( value ) :
"memory"
13593static inline uint32_t _AArch32_Read_prbar_14(
void )
13598 "mrc p15, 0, %0, c6, c15, 0" :
"=&r" ( value ) : :
"memory"
13604static inline void _AArch32_Write_prbar_14( uint32_t value )
13607 "mcr p15, 0, %0, c6, c15, 0" : :
"r" ( value ) :
"memory"
13613static inline uint32_t _AArch32_Read_prbar_15(
void )
13618 "mrc p15, 0, %0, c6, c15, 4" :
"=&r" ( value ) : :
"memory"
13624static inline void _AArch32_Write_prbar_15( uint32_t value )
13627 "mcr p15, 0, %0, c6, c15, 4" : :
"r" ( value ) :
"memory"
13633static inline uint32_t _AArch32_Read_prbar_16(
void )
13638 "mrc p15, 1, %0, c6, c8, 0" :
"=&r" ( value ) : :
"memory"
13644static inline void _AArch32_Write_prbar_16( uint32_t value )
13647 "mcr p15, 1, %0, c6, c8, 0" : :
"r" ( value ) :
"memory"
13653static inline uint32_t _AArch32_Read_prbar_17(
void )
13658 "mrc p15, 1, %0, c6, c8, 4" :
"=&r" ( value ) : :
"memory"
13664static inline void _AArch32_Write_prbar_17( uint32_t value )
13667 "mcr p15, 1, %0, c6, c8, 4" : :
"r" ( value ) :
"memory"
13673static inline uint32_t _AArch32_Read_prbar_18(
void )
13678 "mrc p15, 1, %0, c6, c9, 0" :
"=&r" ( value ) : :
"memory"
13684static inline void _AArch32_Write_prbar_18( uint32_t value )
13687 "mcr p15, 1, %0, c6, c9, 0" : :
"r" ( value ) :
"memory"
13693static inline uint32_t _AArch32_Read_prbar_19(
void )
13698 "mrc p15, 1, %0, c6, c9, 4" :
"=&r" ( value ) : :
"memory"
13704static inline void _AArch32_Write_prbar_19( uint32_t value )
13707 "mcr p15, 1, %0, c6, c9, 4" : :
"r" ( value ) :
"memory"
13713static inline uint32_t _AArch32_Read_prbar_20(
void )
13718 "mrc p15, 1, %0, c6, c10, 0" :
"=&r" ( value ) : :
"memory"
13724static inline void _AArch32_Write_prbar_20( uint32_t value )
13727 "mcr p15, 1, %0, c6, c10, 0" : :
"r" ( value ) :
"memory"
13733static inline uint32_t _AArch32_Read_prbar_21(
void )
13738 "mrc p15, 1, %0, c6, c10, 4" :
"=&r" ( value ) : :
"memory"
13744static inline void _AArch32_Write_prbar_21( uint32_t value )
13747 "mcr p15, 1, %0, c6, c10, 4" : :
"r" ( value ) :
"memory"
13753static inline uint32_t _AArch32_Read_prbar_22(
void )
13758 "mrc p15, 1, %0, c6, c11, 0" :
"=&r" ( value ) : :
"memory"
13764static inline void _AArch32_Write_prbar_22( uint32_t value )
13767 "mcr p15, 1, %0, c6, c11, 0" : :
"r" ( value ) :
"memory"
13773static inline uint32_t _AArch32_Read_prbar_23(
void )
13778 "mrc p15, 1, %0, c6, c11, 4" :
"=&r" ( value ) : :
"memory"
13784static inline void _AArch32_Write_prbar_23( uint32_t value )
13787 "mcr p15, 1, %0, c6, c11, 4" : :
"r" ( value ) :
"memory"
13793static inline uint32_t _AArch32_Read_prbar_24(
void )
13798 "mrc p15, 1, %0, c6, c12, 0" :
"=&r" ( value ) : :
"memory"
13804static inline void _AArch32_Write_prbar_24( uint32_t value )
13807 "mcr p15, 1, %0, c6, c12, 0" : :
"r" ( value ) :
"memory"
13813static inline uint32_t _AArch32_Read_prbar_25(
void )
13818 "mrc p15, 1, %0, c6, c12, 4" :
"=&r" ( value ) : :
"memory"
13824static inline void _AArch32_Write_prbar_25( uint32_t value )
13827 "mcr p15, 1, %0, c6, c12, 4" : :
"r" ( value ) :
"memory"
13833static inline uint32_t _AArch32_Read_prbar_26(
void )
13838 "mrc p15, 1, %0, c6, c13, 0" :
"=&r" ( value ) : :
"memory"
13844static inline void _AArch32_Write_prbar_26( uint32_t value )
13847 "mcr p15, 1, %0, c6, c13, 0" : :
"r" ( value ) :
"memory"
13853static inline uint32_t _AArch32_Read_prbar_27(
void )
13858 "mrc p15, 1, %0, c6, c13, 4" :
"=&r" ( value ) : :
"memory"
13864static inline void _AArch32_Write_prbar_27( uint32_t value )
13867 "mcr p15, 1, %0, c6, c13, 4" : :
"r" ( value ) :
"memory"
13873static inline uint32_t _AArch32_Read_prbar_28(
void )
13878 "mrc p15, 1, %0, c6, c14, 0" :
"=&r" ( value ) : :
"memory"
13884static inline void _AArch32_Write_prbar_28( uint32_t value )
13887 "mcr p15, 1, %0, c6, c14, 0" : :
"r" ( value ) :
"memory"
13893static inline uint32_t _AArch32_Read_prbar_29(
void )
13898 "mrc p15, 1, %0, c6, c14, 4" :
"=&r" ( value ) : :
"memory"
13904static inline void _AArch32_Write_prbar_29( uint32_t value )
13907 "mcr p15, 1, %0, c6, c14, 4" : :
"r" ( value ) :
"memory"
13913static inline uint32_t _AArch32_Read_prbar_30(
void )
13918 "mrc p15, 1, %0, c6, c15, 0" :
"=&r" ( value ) : :
"memory"
13924static inline void _AArch32_Write_prbar_30( uint32_t value )
13927 "mcr p15, 1, %0, c6, c15, 0" : :
"r" ( value ) :
"memory"
13933static inline uint32_t _AArch32_Read_prbar_31(
void )
13938 "mrc p15, 1, %0, c6, c15, 4" :
"=&r" ( value ) : :
"memory"
13944static inline void _AArch32_Write_prbar_31( uint32_t value )
13947 "mcr p15, 1, %0, c6, c15, 4" : :
"r" ( value ) :
"memory"
13953#define AARCH32_PRLAR_EN 0x1U
13955#define AARCH32_PRLAR_ATTRINDX_2_0( _val ) ( ( _val ) << 1 )
13956#define AARCH32_PRLAR_ATTRINDX_2_0_SHIFT 1
13957#define AARCH32_PRLAR_ATTRINDX_2_0_MASK 0xeU
13958#define AARCH32_PRLAR_ATTRINDX_2_0_GET( _reg ) \
13959 ( ( ( _reg ) >> 1 ) & 0x7U )
13961#define AARCH32_PRLAR_LIMIT( _val ) ( ( _val ) << 6 )
13962#define AARCH32_PRLAR_LIMIT_SHIFT 6
13963#define AARCH32_PRLAR_LIMIT_MASK 0xffffffc0U
13964#define AARCH32_PRLAR_LIMIT_GET( _reg ) \
13965 ( ( ( _reg ) >> 6 ) & 0x3ffffffU )
13967static inline uint32_t _AArch32_Read_prlar(
void )
13972 "mrc p15, 0, %0, c6, c3, 1" :
"=&r" ( value ) : :
"memory"
13978static inline void _AArch32_Write_prlar( uint32_t value )
13981 "mcr p15, 0, %0, c6, c3, 1" : :
"r" ( value ) :
"memory"
13987static inline uint32_t _AArch32_Read_prlar_0(
void )
13992 "mrc p15, 0, %0, c6, c8, 1" :
"=&r" ( value ) : :
"memory"
13998static inline void _AArch32_Write_prlar_0( uint32_t value )
14001 "mcr p15, 0, %0, c6, c8, 1" : :
"r" ( value ) :
"memory"
14007static inline uint32_t _AArch32_Read_prlar_1(
void )
14012 "mrc p15, 0, %0, c6, c8, 5" :
"=&r" ( value ) : :
"memory"
14018static inline void _AArch32_Write_prlar_1( uint32_t value )
14021 "mcr p15, 0, %0, c6, c8, 5" : :
"r" ( value ) :
"memory"
14027static inline uint32_t _AArch32_Read_prlar_2(
void )
14032 "mrc p15, 0, %0, c6, c9, 1" :
"=&r" ( value ) : :
"memory"
14038static inline void _AArch32_Write_prlar_2( uint32_t value )
14041 "mcr p15, 0, %0, c6, c9, 1" : :
"r" ( value ) :
"memory"
14047static inline uint32_t _AArch32_Read_prlar_3(
void )
14052 "mrc p15, 0, %0, c6, c9, 5" :
"=&r" ( value ) : :
"memory"
14058static inline void _AArch32_Write_prlar_3( uint32_t value )
14061 "mcr p15, 0, %0, c6, c9, 5" : :
"r" ( value ) :
"memory"
14067static inline uint32_t _AArch32_Read_prlar_4(
void )
14072 "mrc p15, 0, %0, c6, c10, 1" :
"=&r" ( value ) : :
"memory"
14078static inline void _AArch32_Write_prlar_4( uint32_t value )
14081 "mcr p15, 0, %0, c6, c10, 1" : :
"r" ( value ) :
"memory"
14087static inline uint32_t _AArch32_Read_prlar_5(
void )
14092 "mrc p15, 0, %0, c6, c10, 5" :
"=&r" ( value ) : :
"memory"
14098static inline void _AArch32_Write_prlar_5( uint32_t value )
14101 "mcr p15, 0, %0, c6, c10, 5" : :
"r" ( value ) :
"memory"
14107static inline uint32_t _AArch32_Read_prlar_6(
void )
14112 "mrc p15, 0, %0, c6, c11, 1" :
"=&r" ( value ) : :
"memory"
14118static inline void _AArch32_Write_prlar_6( uint32_t value )
14121 "mcr p15, 0, %0, c6, c11, 1" : :
"r" ( value ) :
"memory"
14127static inline uint32_t _AArch32_Read_prlar_7(
void )
14132 "mrc p15, 0, %0, c6, c11, 5" :
"=&r" ( value ) : :
"memory"
14138static inline void _AArch32_Write_prlar_7( uint32_t value )
14141 "mcr p15, 0, %0, c6, c11, 5" : :
"r" ( value ) :
"memory"
14147static inline uint32_t _AArch32_Read_prlar_8(
void )
14152 "mrc p15, 0, %0, c6, c12, 1" :
"=&r" ( value ) : :
"memory"
14158static inline void _AArch32_Write_prlar_8( uint32_t value )
14161 "mcr p15, 0, %0, c6, c12, 1" : :
"r" ( value ) :
"memory"
14167static inline uint32_t _AArch32_Read_prlar_9(
void )
14172 "mrc p15, 0, %0, c6, c12, 5" :
"=&r" ( value ) : :
"memory"
14178static inline void _AArch32_Write_prlar_9( uint32_t value )
14181 "mcr p15, 0, %0, c6, c12, 5" : :
"r" ( value ) :
"memory"
14187static inline uint32_t _AArch32_Read_prlar_10(
void )
14192 "mrc p15, 0, %0, c6, c13, 1" :
"=&r" ( value ) : :
"memory"
14198static inline void _AArch32_Write_prlar_10( uint32_t value )
14201 "mcr p15, 0, %0, c6, c13, 1" : :
"r" ( value ) :
"memory"
14207static inline uint32_t _AArch32_Read_prlar_11(
void )
14212 "mrc p15, 0, %0, c6, c13, 5" :
"=&r" ( value ) : :
"memory"
14218static inline void _AArch32_Write_prlar_11( uint32_t value )
14221 "mcr p15, 0, %0, c6, c13, 5" : :
"r" ( value ) :
"memory"
14227static inline uint32_t _AArch32_Read_prlar_12(
void )
14232 "mrc p15, 0, %0, c6, c14, 1" :
"=&r" ( value ) : :
"memory"
14238static inline void _AArch32_Write_prlar_12( uint32_t value )
14241 "mcr p15, 0, %0, c6, c14, 1" : :
"r" ( value ) :
"memory"
14247static inline uint32_t _AArch32_Read_prlar_13(
void )
14252 "mrc p15, 0, %0, c6, c14, 5" :
"=&r" ( value ) : :
"memory"
14258static inline void _AArch32_Write_prlar_13( uint32_t value )
14261 "mcr p15, 0, %0, c6, c14, 5" : :
"r" ( value ) :
"memory"
14267static inline uint32_t _AArch32_Read_prlar_14(
void )
14272 "mrc p15, 0, %0, c6, c15, 1" :
"=&r" ( value ) : :
"memory"
14278static inline void _AArch32_Write_prlar_14( uint32_t value )
14281 "mcr p15, 0, %0, c6, c15, 1" : :
"r" ( value ) :
"memory"
14287static inline uint32_t _AArch32_Read_prlar_15(
void )
14292 "mrc p15, 0, %0, c6, c15, 5" :
"=&r" ( value ) : :
"memory"
14298static inline void _AArch32_Write_prlar_15( uint32_t value )
14301 "mcr p15, 0, %0, c6, c15, 5" : :
"r" ( value ) :
"memory"
14307static inline uint32_t _AArch32_Read_prlar_16(
void )
14312 "mrc p15, 1, %0, c6, c8, 1" :
"=&r" ( value ) : :
"memory"
14318static inline void _AArch32_Write_prlar_16( uint32_t value )
14321 "mcr p15, 1, %0, c6, c8, 1" : :
"r" ( value ) :
"memory"
14327static inline uint32_t _AArch32_Read_prlar_17(
void )
14332 "mrc p15, 1, %0, c6, c8, 5" :
"=&r" ( value ) : :
"memory"
14338static inline void _AArch32_Write_prlar_17( uint32_t value )
14341 "mcr p15, 1, %0, c6, c8, 5" : :
"r" ( value ) :
"memory"
14347static inline uint32_t _AArch32_Read_prlar_18(
void )
14352 "mrc p15, 1, %0, c6, c9, 1" :
"=&r" ( value ) : :
"memory"
14358static inline void _AArch32_Write_prlar_18( uint32_t value )
14361 "mcr p15, 1, %0, c6, c9, 1" : :
"r" ( value ) :
"memory"
14367static inline uint32_t _AArch32_Read_prlar_19(
void )
14372 "mrc p15, 1, %0, c6, c9, 5" :
"=&r" ( value ) : :
"memory"
14378static inline void _AArch32_Write_prlar_19( uint32_t value )
14381 "mcr p15, 1, %0, c6, c9, 5" : :
"r" ( value ) :
"memory"
14387static inline uint32_t _AArch32_Read_prlar_20(
void )
14392 "mrc p15, 1, %0, c6, c10, 1" :
"=&r" ( value ) : :
"memory"
14398static inline void _AArch32_Write_prlar_20( uint32_t value )
14401 "mcr p15, 1, %0, c6, c10, 1" : :
"r" ( value ) :
"memory"
14407static inline uint32_t _AArch32_Read_prlar_21(
void )
14412 "mrc p15, 1, %0, c6, c10, 5" :
"=&r" ( value ) : :
"memory"
14418static inline void _AArch32_Write_prlar_21( uint32_t value )
14421 "mcr p15, 1, %0, c6, c10, 5" : :
"r" ( value ) :
"memory"
14427static inline uint32_t _AArch32_Read_prlar_22(
void )
14432 "mrc p15, 1, %0, c6, c11, 1" :
"=&r" ( value ) : :
"memory"
14438static inline void _AArch32_Write_prlar_22( uint32_t value )
14441 "mcr p15, 1, %0, c6, c11, 1" : :
"r" ( value ) :
"memory"
14447static inline uint32_t _AArch32_Read_prlar_23(
void )
14452 "mrc p15, 1, %0, c6, c11, 5" :
"=&r" ( value ) : :
"memory"
14458static inline void _AArch32_Write_prlar_23( uint32_t value )
14461 "mcr p15, 1, %0, c6, c11, 5" : :
"r" ( value ) :
"memory"
14467static inline uint32_t _AArch32_Read_prlar_24(
void )
14472 "mrc p15, 1, %0, c6, c12, 1" :
"=&r" ( value ) : :
"memory"
14478static inline void _AArch32_Write_prlar_24( uint32_t value )
14481 "mcr p15, 1, %0, c6, c12, 1" : :
"r" ( value ) :
"memory"
14487static inline uint32_t _AArch32_Read_prlar_25(
void )
14492 "mrc p15, 1, %0, c6, c12, 5" :
"=&r" ( value ) : :
"memory"
14498static inline void _AArch32_Write_prlar_25( uint32_t value )
14501 "mcr p15, 1, %0, c6, c12, 5" : :
"r" ( value ) :
"memory"
14507static inline uint32_t _AArch32_Read_prlar_26(
void )
14512 "mrc p15, 1, %0, c6, c13, 1" :
"=&r" ( value ) : :
"memory"
14518static inline void _AArch32_Write_prlar_26( uint32_t value )
14521 "mcr p15, 1, %0, c6, c13, 1" : :
"r" ( value ) :
"memory"
14527static inline uint32_t _AArch32_Read_prlar_27(
void )
14532 "mrc p15, 1, %0, c6, c13, 5" :
"=&r" ( value ) : :
"memory"
14538static inline void _AArch32_Write_prlar_27( uint32_t value )
14541 "mcr p15, 1, %0, c6, c13, 5" : :
"r" ( value ) :
"memory"
14547static inline uint32_t _AArch32_Read_prlar_28(
void )
14552 "mrc p15, 1, %0, c6, c14, 1" :
"=&r" ( value ) : :
"memory"
14558static inline void _AArch32_Write_prlar_28( uint32_t value )
14561 "mcr p15, 1, %0, c6, c14, 1" : :
"r" ( value ) :
"memory"
14567static inline uint32_t _AArch32_Read_prlar_29(
void )
14572 "mrc p15, 1, %0, c6, c14, 5" :
"=&r" ( value ) : :
"memory"
14578static inline void _AArch32_Write_prlar_29( uint32_t value )
14581 "mcr p15, 1, %0, c6, c14, 5" : :
"r" ( value ) :
"memory"
14587static inline uint32_t _AArch32_Read_prlar_30(
void )
14592 "mrc p15, 1, %0, c6, c15, 1" :
"=&r" ( value ) : :
"memory"
14598static inline void _AArch32_Write_prlar_30( uint32_t value )
14601 "mcr p15, 1, %0, c6, c15, 1" : :
"r" ( value ) :
"memory"
14607static inline uint32_t _AArch32_Read_prlar_31(
void )
14612 "mrc p15, 1, %0, c6, c15, 5" :
"=&r" ( value ) : :
"memory"
14618static inline void _AArch32_Write_prlar_31( uint32_t value )
14621 "mcr p15, 1, %0, c6, c15, 5" : :
"r" ( value ) :
"memory"
14627#define AARCH32_PRSELR_REGION( _val ) ( ( _val ) << 0 )
14628#define AARCH32_PRSELR_REGION_SHIFT 0
14629#define AARCH32_PRSELR_REGION_MASK 0xffU
14630#define AARCH32_PRSELR_REGION_GET( _reg ) \
14631 ( ( ( _reg ) >> 0 ) & 0xffU )
14633static inline uint32_t _AArch32_Read_prselr(
void )
14638 "mrc p15, 0, %0, c6, c2, 1" :
"=&r" ( value ) : :
"memory"
14644static inline void _AArch32_Write_prselr( uint32_t value )
14647 "mcr p15, 0, %0, c6, c2, 1" : :
"r" ( value ) :
"memory"
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.