zynq-uart-regs.h File Reference

This header file provides Zynq UART interfaces. More...

#include <bsp/utility.h>

Go to the source code of this file.

Data Structures
struct	zynq_uart

Macros
#define	ZYNQ_UART_DEFAULT_BAUD   115200
#define	ZYNQ_UART_FIFO_DEPTH   64
#define	ZYNQ_UART_CONTROL_STPBRK   BSP_BIT32(8)
#define	ZYNQ_UART_CONTROL_STTBRK   BSP_BIT32(7)
#define	ZYNQ_UART_CONTROL_RSTTO   BSP_BIT32(6)
#define	ZYNQ_UART_CONTROL_TXDIS   BSP_BIT32(5)
#define	ZYNQ_UART_CONTROL_TXEN   BSP_BIT32(4)
#define	ZYNQ_UART_CONTROL_RXDIS   BSP_BIT32(3)
#define	ZYNQ_UART_CONTROL_RXEN   BSP_BIT32(2)
#define	ZYNQ_UART_CONTROL_TXRES   BSP_BIT32(1)
#define	ZYNQ_UART_CONTROL_RXRES   BSP_BIT32(0)
#define	ZYNQ_UART_MODE_CHMODE(val)
#define	ZYNQ_UART_MODE_CHMODE_GET(reg)
#define	ZYNQ_UART_MODE_CHMODE_SET(reg, val)
#define	ZYNQ_UART_MODE_CHMODE_NORMAL   0x00U
#define	ZYNQ_UART_MODE_CHMODE_AUTO_ECHO   0x01U
#define	ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK   0x02U
#define	ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK   0x03U
#define	ZYNQ_UART_MODE_NBSTOP(val)
#define	ZYNQ_UART_MODE_NBSTOP_GET(reg)
#define	ZYNQ_UART_MODE_NBSTOP_SET(reg, val)
#define	ZYNQ_UART_MODE_NBSTOP_STOP_1   0x00U
#define	ZYNQ_UART_MODE_NBSTOP_STOP_1_5   0x01U
#define	ZYNQ_UART_MODE_NBSTOP_STOP_2   0x02U
#define	ZYNQ_UART_MODE_PAR(val)
#define	ZYNQ_UART_MODE_PAR_GET(reg)
#define	ZYNQ_UART_MODE_PAR_SET(reg, val)
#define	ZYNQ_UART_MODE_PAR_EVEN   0x00U
#define	ZYNQ_UART_MODE_PAR_ODD   0x01U
#define	ZYNQ_UART_MODE_PAR_SPACE   0x02U
#define	ZYNQ_UART_MODE_PAR_MARK   0x03U
#define	ZYNQ_UART_MODE_PAR_MASK   ZYNQ_UART_MODE_PAR(7)
#define	ZYNQ_UART_MODE_PAR_NONE   0x04U
#define	ZYNQ_UART_MODE_CHRL(val)
#define	ZYNQ_UART_MODE_CHRL_GET(reg)
#define	ZYNQ_UART_MODE_CHRL_SET(reg, val)
#define	ZYNQ_UART_MODE_CHRL_8   0x00U
#define	ZYNQ_UART_MODE_CHRL_7   0x02U
#define	ZYNQ_UART_MODE_CHRL_6   0x03U
#define	ZYNQ_UART_MODE_CLKS   BSP_BIT32(0)
#define	ZYNQ_UART_TOVR   BSP_BIT32(12)
#define	ZYNQ_UART_TNFUL   BSP_BIT32(11)
#define	ZYNQ_UART_TTRIG   BSP_BIT32(10)
#define	ZYNQ_UART_DMSI   BSP_BIT32(9)
#define	ZYNQ_UART_TIMEOUT   BSP_BIT32(8)
#define	ZYNQ_UART_PARE   BSP_BIT32(7)
#define	ZYNQ_UART_FRAME   BSP_BIT32(6)
#define	ZYNQ_UART_ROVR   BSP_BIT32(5)
#define	ZYNQ_UART_TFUL   BSP_BIT32(4)
#define	ZYNQ_UART_TEMPTY   BSP_BIT32(3)
#define	ZYNQ_UART_RFUL   BSP_BIT32(2)
#define	ZYNQ_UART_REMPTY   BSP_BIT32(1)
#define	ZYNQ_UART_RTRIG   BSP_BIT32(0)
#define	ZYNQ_UART_BAUD_RATE_GEN_CD(val)
#define	ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg)
#define	ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val)
#define	ZYNQ_UART_RX_TIMEOUT_RTO(val)
#define	ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg)
#define	ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val)
#define	ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val)
#define	ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg)
#define	ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val)
#define	ZYNQ_UART_MODEM_CTRL_FCM   BSP_BIT32(5)
#define	ZYNQ_UART_MODEM_CTRL_RTS   BSP_BIT32(1)
#define	ZYNQ_UART_MODEM_CTRL_DTR   BSP_BIT32(0)
#define	ZYNQ_UART_MODEM_STS_FCMS   BSP_BIT32(8)
#define	ZYNQ_UART_MODEM_STS_DCD   BSP_BIT32(7)
#define	ZYNQ_UART_MODEM_STS_RI   BSP_BIT32(6)
#define	ZYNQ_UART_MODEM_STS_DSR   BSP_BIT32(5)
#define	ZYNQ_UART_MODEM_STS_CTS   BSP_BIT32(4)
#define	ZYNQ_UART_MODEM_STS_DDCD   BSP_BIT32(3)
#define	ZYNQ_UART_MODEM_STS_TERI   BSP_BIT32(2)
#define	ZYNQ_UART_MODEM_STS_DDSR   BSP_BIT32(1)
#define	ZYNQ_UART_MODEM_STS_DCTS   BSP_BIT32(0)
#define	ZYNQ_UART_CHANNEL_STS_TNFUL   BSP_BIT32(14)
#define	ZYNQ_UART_CHANNEL_STS_TTRIG   BSP_BIT32(13)
#define	ZYNQ_UART_CHANNEL_STS_FDELT   BSP_BIT32(12)
#define	ZYNQ_UART_CHANNEL_STS_TACTIVE   BSP_BIT32(11)
#define	ZYNQ_UART_CHANNEL_STS_RACTIVE   BSP_BIT32(10)
#define	ZYNQ_UART_CHANNEL_STS_TFUL   BSP_BIT32(4)
#define	ZYNQ_UART_CHANNEL_STS_TEMPTY   BSP_BIT32(3)
#define	ZYNQ_UART_CHANNEL_STS_RFUL   BSP_BIT32(2)
#define	ZYNQ_UART_CHANNEL_STS_REMPTY   BSP_BIT32(1)
#define	ZYNQ_UART_CHANNEL_STS_RTRIG   BSP_BIT32(0)
#define	ZYNQ_UART_TX_RX_FIFO_FIFO(val)
#define	ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg)
#define	ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val)
#define	ZYNQ_UART_BAUD_RATE_DIV_BDIV(val)
#define	ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg)
#define	ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val)
#define	ZYNQ_UART_FLOW_DELAY_FDEL(val)
#define	ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg)
#define	ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val)
#define	ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val)
#define	ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg)
#define	ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val)

Typedefs
typedef struct zynq_uart	zynq_uart

Functions
void	zynq_uart_initialize (volatile zynq_uart *regs)
int	zynq_uart_read_char_polled (volatile zynq_uart *regs)
void	zynq_uart_write_char_polled (volatile zynq_uart *regs, char c)
void	zynq_uart_reset_tx_flush (volatile zynq_uart *regs)
uint32_t	zynq_uart_input_clock (void)
	Returns the Zynq UART input clock frequency in Hz.
uint32_t	zynq_uart_calculate_baud (uint32_t desired_baud, uint32_t mode_clks, uint32_t *cd_ptr, uint32_t *bdiv_ptr)
	Calculates the clock and baud divisor of the best approximation of the desired baud.

Detailed Description

This header file provides Zynq UART interfaces.

Macro Definition Documentation

ZYNQ_UART_BAUD_RATE_DIV_BDIV

#define ZYNQ_UART_BAUD_RATE_DIV_BDIV

(

val

)

Value:

BSP_FLD32(val, 0, 7)

ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET

#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 7)

ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET

#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 7)

ZYNQ_UART_BAUD_RATE_GEN_CD

#define ZYNQ_UART_BAUD_RATE_GEN_CD

(

val

)

Value:

BSP_FLD32(val, 0, 15)

ZYNQ_UART_BAUD_RATE_GEN_CD_GET

#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 15)

ZYNQ_UART_BAUD_RATE_GEN_CD_SET

#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 15)

ZYNQ_UART_FLOW_DELAY_FDEL

#define ZYNQ_UART_FLOW_DELAY_FDEL

(

val

)

Value:

BSP_FLD32(val, 0, 5)

ZYNQ_UART_FLOW_DELAY_FDEL_GET

#define ZYNQ_UART_FLOW_DELAY_FDEL_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 5)

ZYNQ_UART_FLOW_DELAY_FDEL_SET

#define ZYNQ_UART_FLOW_DELAY_FDEL_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 5)

ZYNQ_UART_MODE_CHMODE

#define ZYNQ_UART_MODE_CHMODE

(

val

)

Value:

BSP_FLD32(val, 8, 9)

ZYNQ_UART_MODE_CHMODE_GET

#define ZYNQ_UART_MODE_CHMODE_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 8, 9)

ZYNQ_UART_MODE_CHMODE_SET

#define ZYNQ_UART_MODE_CHMODE_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 8, 9)

ZYNQ_UART_MODE_CHRL

#define ZYNQ_UART_MODE_CHRL

(

val

)

Value:

BSP_FLD32(val, 1, 2)

ZYNQ_UART_MODE_CHRL_GET

#define ZYNQ_UART_MODE_CHRL_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 1, 2)

ZYNQ_UART_MODE_CHRL_SET

#define ZYNQ_UART_MODE_CHRL_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 1, 2)

ZYNQ_UART_MODE_NBSTOP

#define ZYNQ_UART_MODE_NBSTOP

(

val

)

Value:

BSP_FLD32(val, 6, 7)

ZYNQ_UART_MODE_NBSTOP_GET

#define ZYNQ_UART_MODE_NBSTOP_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 6, 7)

ZYNQ_UART_MODE_NBSTOP_SET

#define ZYNQ_UART_MODE_NBSTOP_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 6, 7)

ZYNQ_UART_MODE_PAR

#define ZYNQ_UART_MODE_PAR

(

val

)

Value:

BSP_FLD32(val, 3, 5)

ZYNQ_UART_MODE_PAR_GET

#define ZYNQ_UART_MODE_PAR_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 3, 5)

ZYNQ_UART_MODE_PAR_SET

#define ZYNQ_UART_MODE_PAR_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 3, 5)

ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG

#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG

(

val

)

Value:

BSP_FLD32(val, 0, 5)

ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET

#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 5)

ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET

#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 5)

ZYNQ_UART_RX_TIMEOUT_RTO

#define ZYNQ_UART_RX_TIMEOUT_RTO

(

val

)

Value:

BSP_FLD32(val, 0, 7)

ZYNQ_UART_RX_TIMEOUT_RTO_GET

#define ZYNQ_UART_RX_TIMEOUT_RTO_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 7)

ZYNQ_UART_RX_TIMEOUT_RTO_SET

#define ZYNQ_UART_RX_TIMEOUT_RTO_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 7)

ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG

#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG

(

val

)

Value:

BSP_FLD32(val, 0, 5)

ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET

#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 5)

ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET

#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 5)

ZYNQ_UART_TX_RX_FIFO_FIFO

#define ZYNQ_UART_TX_RX_FIFO_FIFO

(

val

)

Value:

BSP_FLD32(val, 0, 7)

ZYNQ_UART_TX_RX_FIFO_FIFO_GET

#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET

(

reg

)

Value:

BSP_FLD32GET(reg, 0, 7)

ZYNQ_UART_TX_RX_FIFO_FIFO_SET

#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET	(		reg,
			val )

Value:

BSP_FLD32SET(reg, val, 0, 7)