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bsps
arm
xilinx-zynq
include
dev
devcfg
zynq-devcfg-regs.h
Go to the documentation of this file.
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/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (c) 2016
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Florida. All rights reserved.
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* Copyright (c) 2017
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* NSF Center for High-Performance Reconfigurable Computing (CHREC),
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* University of Pittsburgh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of CHREC.
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*
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* Author: Patrick Gauvin <gauvin@hcs.ufl.edu>
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*/
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#ifndef LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
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#define LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H
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#include <stdint.h>
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#include <
bsp/utility.h
>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
/* __cplusplus */
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/* Zynq-7000 series devcfg address */
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#define ZYNQ_DEVCFG_BASE_ADDR 0xF8007000UL
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/* For use with the PCAP DMA */
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#define ZYNQ_DEVCFG_BITSTREAM_ADDR 0xFFFFFFFFUL
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#define ZYNQ_DEVCFG_INTERRUPT_VECTOR 40
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typedef
struct
{
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uint32_t ctrl;
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#define ZYNQ_DEVCFG_CTRL_FORCE_RST( val ) BSP_FLD32( val, 31, 31 )
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#define ZYNQ_DEVCFG_CTRL_FORCE_RST_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B_GET( reg ) BSP_FLD32GET( reg, 30, 30 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_PROG_B( val ) BSP_FLD32( val, 30, 30 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K_GET( reg ) BSP_FLD32GET( reg, 29, 29 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_POR_CNT_4K( val ) BSP_FLD32( val, 29, 29 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR( val ) BSP_FLD32( val, 27, 27 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR_GET( reg ) BSP_FLD32GET( reg, 27, 27 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR_ICAP ( 0 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_PR_PCAP ( 1 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_MODE( val ) BSP_FLD32( val, 26, 26 )
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#define ZYNQ_DEVCFG_CTRL_PCAP_MODE_GET( reg ) BSP_FLD32GET( reg, 26, 26 )
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#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN( val ) BSP_FLD32( val, 25, 25 )
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#define ZYNQ_DEVCFG_CTRL_QUARTER_PCAP_RATE_EN_GET( reg ) \
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BSP_FLD32GET( reg, 25, 25 )
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#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN( val ) BSP_FLD32( val, 24, 24 )
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#define ZYNQ_DEVCFG_CTRL_MULTIBOOT_EN_GET( reg ) BSP_FLD32GET( reg, 24, 24 )
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#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS( val ) BSP_FLD32( val, 23, 23 )
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#define ZYNQ_DEVCFG_CTRL_JTAG_CHAIN_DIS_GET( reg ) BSP_FLD32GET( reg, 23, 23 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE( val ) BSP_FLD32( val, 12, 12 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_BBRAM ( 0 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_FUSE_EFUSE ( 1 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN( val ) BSP_FLD32( val, 9, 11 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_GET( reg ) BSP_FLD32GET( reg, 9, 11 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_ENABLE ( 0x3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_DISABLE ( 0x0 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_AES_EN_LOCKDOWN ( 0x1 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN( val ) BSP_FLD32( val, 8, 8 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SEU_EN_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SEC_EN_GET( reg ) BSP_FLD32GET( reg, 7, 7 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN( val ) BSP_FLD32( val, 6, 6 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPNIDEN_GET( reg ) BSP_FLD32GET( reg, 6, 6 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN( val ) BSP_FLD32( val, 5, 5 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_SPIDEN_GET( reg ) BSP_FLD32GET( reg, 5, 5 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN( val ) BSP_FLD32( val, 4, 4 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_NIDEN_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN( val ) BSP_FLD32( val, 3, 3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DBGEN_GET( reg ) BSP_FLD32GET( reg, 3, 3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN( val ) BSP_FLD32( val, 0, 2 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_GET( reg ) BSP_FLD32GET( reg, 0, 2 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_ENABLE ( 0x3 )
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#define ZYNQ_DEVCFG_CTRL_PCFG_DAP_EN_BYPASS ( 0x0 )
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#define ZYNQ_DEVCFG_CTRL_RESERVED_BITS ( 0x6000 )
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uint32_t lock;
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uint32_t cfg;
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/* int_sts and int_mask directly overlap, so they share the ZYNQ_DEVCFG_INT_*
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* macros */
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uint32_t int_sts;
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uint32_t int_mask;
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#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT BSP_BIT32( 27 )
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#define ZYNQ_DEVCFG_INT_PSS_CFG_RESET_B_INT_GET( reg ) \
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BSP_FLD32GET( reg, 27, 27 )
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#define ZYNQ_DEVCFG_INT_AXI_WERR_INT_GET( reg ) BSP_FLD32GET( reg, 22, 22 )
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#define ZYNQ_DEVCFG_INT_AXI_RTO_INT_GET( reg ) BSP_FLD32GET( reg, 21, 21 )
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#define ZYNQ_DEVCFG_INT_AXI_RERR_INT_GET( reg ) BSP_FLD32GET( reg, 20, 20 )
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#define ZYNQ_DEVCFG_INT_RX_FIFO_OV_INT_GET( reg ) \
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BSP_FLD32GET( reg, 18, 18 )
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#define ZYNQ_DEVCFG_INT_DMA_CMD_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 15, 15 )
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#define ZYNQ_DEVCFG_INT_DMA_Q_OV_INT_GET( reg ) BSP_FLD32GET( reg, 14, 14 )
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#define ZYNQ_DEVCFG_INT_DMA_DONE_INT BSP_BIT32( 13 )
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#define ZYNQ_DEVCFG_INT_DMA_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 13, 13 )
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#define ZYNQ_DEVCFG_INT_D_P_DONE_INT BSP_BIT32( 12 )
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#define ZYNQ_DEVCFG_INT_D_P_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 12, 12 )
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#define ZYNQ_DEVCFG_INT_P2D_LEN_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 11, 11 )
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#define ZYNQ_DEVCFG_INT_PCFG_HMAC_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 6, 6 )
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#define ZYNQ_DEVCFG_INT_PCFG_SEU_ERR_INT_GET( reg ) \
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BSP_FLD32GET( reg, 5, 5 )
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#define ZYNQ_DEVCFG_INT_PCFG_POR_B_INT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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#define ZYNQ_DEVCFG_INT_PCFG_CFG_RST_INT_GET( reg ) \
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BSP_FLD32GET( reg, 3, 3 )
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#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT BSP_BIT32( 2 )
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#define ZYNQ_DEVCFG_INT_PCFG_DONE_INT_GET( reg ) BSP_FLD32GET( reg, 2, 2 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT BSP_BIT32( 1 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_PE_INT_GET( reg ) \
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BSP_FLD32GET( reg, 1, 1 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT BSP_BIT32( 0 )
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#define ZYNQ_DEVCFG_INT_PCFG_INIT_NE_INT_GET( reg ) \
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BSP_FLD32GET( reg, 0, 0 )
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#define ZYNQ_DEVCFG_INT_ALL ( 0xf8f7f87f )
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uint32_t status;
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#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F( val ) BSP_FLD32( val, 31, 31 )
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#define ZYNQ_DEVCFG_STATUS_DMA_CMD_Q_F_GET( reg ) BSP_FLD32GET( reg, 31, 31 )
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#define ZYNQ_DEVCFG_STATUS_PCFG_INIT_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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uint32_t dma_src_addr;
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#define ZYNQ_DEVCFG_DMA_SRC_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
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uint32_t dma_dst_addr;
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#define ZYNQ_DEVCFG_DMA_DST_ADDR_DMA_DONE_INT_WAIT_PCAP ( 0x1 )
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uint32_t dma_src_len;
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#define ZYNQ_DEVCFG_DMA_SRC_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
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uint32_t dma_dest_len;
/* (sic) */
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#define ZYNQ_DEVCFG_DMA_DEST_LEN_LEN( val ) BSP_FLD32( val, 0, 26 )
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uint32_t reserved0;
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uint32_t multiboot_addr;
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uint32_t reserved1;
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uint32_t unlock;
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uint32_t reserved2[18];
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uint32_t mctrl;
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_GET( reg ) BSP_FLD32GET( reg, 28, 31 )
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_1_0 0x0
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_2_0 0x1
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_0 0x2
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#define ZYNQ_DEVCFG_MCTRL_PS_VERSION_3_1 0x3
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#define ZYNQ_DEVCFG_MCTRL_PCFG_POR_B_GET( reg ) BSP_FLD32GET( reg, 8, 8 )
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#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK_GET( reg ) BSP_FLD32GET( reg, 4, 4 )
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#define ZYNQ_DEVCFG_MCTRL_INT_PCAP_LPBK( val ) BSP_FLD32( val, 4, 4 )
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#define ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS ( 0x800000 )
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#define ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ( 0x3 )
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#define ZYNQ_DEVCFG_MCTRL_SET( reg, val ) ( ( ( reg ) & \
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~ZYNQ_DEVCFG_MCTRL_RESERVED_UNSET_BITS ) | \
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ZYNQ_DEVCFG_MCTRL_RESERVED_SET_BITS | ( val ) )
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uint32_t reserved3[32];
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uint32_t xadcif_cfg;
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uint32_t xadcif_int_sts;
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uint32_t xadcif_int_mask;
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uint32_t xadcif_msts;
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uint32_t xadcif_cmdfifo;
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uint32_t xadcif_rdfifo;
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uint32_t xadcif_mctrl;
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}
zynq_devcfg_regs
;
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#ifdef __cplusplus
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}
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#endif
/* __cplusplus */
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#endif
/* LIBBSP_ARM_XILINX_ZYNQ_DEVCFG_REGS_H */
utility.h
This header file provides utility macros for BSPs.
zynq_devcfg_regs
Definition
zynq-devcfg-regs.h:67
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