RTEMS
6.3
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bsps
include
dev
clock
xttcps_hw.h
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/******************************************************************************
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* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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/*****************************************************************************/
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#ifndef XTTCPS_HW_H
/* prevent circular inclusions */
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#define XTTCPS_HW_H
/* by using protection macros */
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/***************************** Include Files *********************************/
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#ifndef __rtems__
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#include "xil_types.h"
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#include "xil_assert.h"
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#include "xil_io.h"
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#else
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#include <bsp/xil-compat.h>
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#endif
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/************************** Constant Definitions *****************************/
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/*
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* Flag for a9 processor
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*/
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#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
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#define ARMA9
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#endif
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U
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#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U
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#define XTTCPS_MATCH_0_OFFSET 0x00000030U
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#define XTTCPS_MATCH_1_OFFSET 0x0000003CU
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#define XTTCPS_MATCH_2_OFFSET 0x00000048U
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#define XTTCPS_ISR_OFFSET 0x00000054U
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#define XTTCPS_IER_OFFSET 0x00000060U
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/* @} */
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#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U
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#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU
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#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U
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#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U
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#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U
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#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U
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/* @} */
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#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U
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#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U
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#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U
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#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U
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#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U
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#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U
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#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U
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#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U
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/* @} */
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#if defined(ARMA9)
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#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU
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#else
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#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU
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#endif
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/* @} */
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#if defined(ARMA9)
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#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU
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#else
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#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU
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#endif
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/* @} */
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#if defined(ARMA9)
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#define XTTCPS_MATCH_MASK 0x0000FFFFU
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#else
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#define XTTCPS_MATCH_MASK 0xFFFFFFFFU
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#endif
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#define XTTCPS_NUM_MATCH_REG 3U
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/* @} */
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#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U
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#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U
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#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U
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#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U
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#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U
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#define XTTCPS_IXR_ALL_MASK 0x0000001FU
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/* @} */
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/***************** Macros (Inline Functions) Definitions *********************/
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/****************************************************************************/
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#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
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(Xil_In32((BaseAddress) + (u32)(RegOffset)))
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/****************************************************************************/
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#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
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(Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
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/****************************************************************************/
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#define XTtcPs_Match_N_Offset(MatchIndex) \
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((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
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/************************** Function Prototypes ******************************/
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/************************** Variable Definitions *****************************/
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#ifdef __cplusplus
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}
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#endif
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#endif
/* end of protection macro */
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