xttcps_hw.h File Reference

#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"

Go to the source code of this file.

Macros
#define	XTTCPS_HW_H
#define	ARMA9
Register Map
Register offsets from the base address of the device.
#define	XTTCPS_CLK_CNTRL_OFFSET   0x00000000U
#define	XTTCPS_CNT_CNTRL_OFFSET   0x0000000CU
#define	XTTCPS_COUNT_VALUE_OFFSET   0x00000018U
#define	XTTCPS_INTERVAL_VAL_OFFSET   0x00000024U
#define	XTTCPS_MATCH_0_OFFSET   0x00000030U
#define	XTTCPS_MATCH_1_OFFSET   0x0000003CU
#define	XTTCPS_MATCH_2_OFFSET   0x00000048U
#define	XTTCPS_ISR_OFFSET   0x00000054U
#define	XTTCPS_IER_OFFSET   0x00000060U
Clock Control Register
Clock Control Register definitions
#define	XTTCPS_CLK_CNTRL_PS_EN_MASK   0x00000001U
#define	XTTCPS_CLK_CNTRL_PS_VAL_MASK   0x0000001EU
#define	XTTCPS_CLK_CNTRL_PS_VAL_SHIFT   1U
#define	XTTCPS_CLK_CNTRL_PS_DISABLE   16U
#define	XTTCPS_CLK_CNTRL_SRC_MASK   0x00000020U
#define	XTTCPS_CLK_CNTRL_EXT_EDGE_MASK   0x00000040U
Counter Control Register
Counter Control Register definitions
#define	XTTCPS_CNT_CNTRL_DIS_MASK   0x00000001U
#define	XTTCPS_CNT_CNTRL_INT_MASK   0x00000002U
#define	XTTCPS_CNT_CNTRL_DECR_MASK   0x00000004U
#define	XTTCPS_CNT_CNTRL_MATCH_MASK   0x00000008U
#define	XTTCPS_CNT_CNTRL_RST_MASK   0x00000010U
#define	XTTCPS_CNT_CNTRL_EN_WAVE_MASK   0x00000020U
#define	XTTCPS_CNT_CNTRL_POL_WAVE_MASK   0x00000040U
#define	XTTCPS_CNT_CNTRL_RESET_VALUE   0x00000021U
Current Counter Value Register
Current Counter Value Register definitions
#define	XTTCPS_COUNT_VALUE_MASK   0x0000FFFFU
Interval Value Register
Interval Value Register is the maximum value the counter will count up or down to.
#define	XTTCPS_INTERVAL_VAL_MASK   0x0000FFFFU
Match Registers
Definitions for Match registers, each timer counter has three match registers.
#define	XTTCPS_MATCH_MASK   0x0000FFFFU
#define	XTTCPS_NUM_MATCH_REG   3U
Interrupt Registers
Following register bit mask is for all interrupt registers.
#define	XTTCPS_IXR_INTERVAL_MASK   0x00000001U
#define	XTTCPS_IXR_MATCH_0_MASK   0x00000002U
#define	XTTCPS_IXR_MATCH_1_MASK   0x00000004U
#define	XTTCPS_IXR_MATCH_2_MASK   0x00000008U
#define	XTTCPS_IXR_CNT_OVR_MASK   0x00000010U
#define	XTTCPS_IXR_ALL_MASK   0x0000001FU
#define	XTtcPs_ReadReg(BaseAddress, RegOffset)
#define	XTtcPs_WriteReg(BaseAddress, RegOffset, Data)
#define	XTtcPs_Match_N_Offset(MatchIndex)

Detailed Description

This file defines the hardware interface to one of the three timer counters in the Ps block.

MODIFICATION HISTORY:

Ver   Who    Date     Changes


1.00a drg/jz 01/21/10 First release
3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
3.5   srm    10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
                      XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
                      mask 16 bit values for zynq and 32 bit values for
                      zynq ultrascale+mpsoc "