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RTEMS 6.3
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Go to the source code of this file.
Macros | |
| #define | TX3904_TIMER0_BASE 0xFFFFF000 |
| #define | TX3904_TIMER1_BASE 0xFFFFF100 |
| #define | TX3904_TIMER2_BASE 0xFFFFF200 |
| #define | TX3904_TIMER_TCR 0x00 |
| #define | TX3904_TIMER_TISR 0x04 |
| #define | TX3904_TIMER_CPRA 0x08 |
| #define | TX3904_TIMER_CPRB 0x0C |
| #define | TX3904_TIMER_ITMR 0x10 |
| #define | TX3904_TIMER_CCDR 0x20 |
| #define | TX3904_TIMER_PGMR 0x30 |
| #define | TX3904_TIMER_WTMR 0x40 |
| #define | TX3904_TIMER_TRR 0xF0 |
| #define | TX3904_TIMER_READ(_base, _register) |
| #define | TX3904_TIMER_WRITE(_base, _register, _value) |
MIPS Tx3904 specific information
NOTE: This is far from complete. –joel (13 Dec 2000)
| #define TX3904_TIMER_READ | ( | _base, | |
| _register ) |
| #define TX3904_TIMER_WRITE | ( | _base, | |
| _register, | |||
| _value ) |