TMR_Type::[struct].CHANNEL Struct Reference

Data Fields
__IO uint16_t	COMP1
__IO uint16_t	COMP2
__IO uint16_t	CAPT
__IO uint16_t	LOAD
__IO uint16_t	HOLD
__IO uint16_t	CNTR
__IO uint16_t	CTRL
__IO uint16_t	SCTRL
__IO uint16_t	CMPLD1
__IO uint16_t	CMPLD2
__IO uint16_t	CSCTRL
__IO uint16_t	FILT
__IO uint16_t	DMA
uint8_t	RESERVED_0 [4]
__IO uint16_t	ENBL
__IO uint16_t	COMP1
__IO uint16_t	COMP2
__IO uint16_t	CAPT
__IO uint16_t	LOAD
__IO uint16_t	HOLD
__IO uint16_t	CNTR
__IO uint16_t	CTRL
__IO uint16_t	SCTRL
__IO uint16_t	CMPLD1
__IO uint16_t	CMPLD2
__IO uint16_t	CSCTRL
__IO uint16_t	FILT
__IO uint16_t	DMA
uint8_t	RESERVED_0 [4]
__IO uint16_t	ENBL
__IO uint16_t	COMP1
__IO uint16_t	COMP2
__IO uint16_t	CAPT
__IO uint16_t	LOAD
__IO uint16_t	HOLD
__IO uint16_t	CNTR
__IO uint16_t	CTRL
__IO uint16_t	SCTRL
__IO uint16_t	CMPLD1
__IO uint16_t	CMPLD2
__IO uint16_t	CSCTRL
__IO uint16_t	FILT
__IO uint16_t	DMA
uint8_t	RESERVED_0 [4]
__IO uint16_t	ENBL

Field Documentation

CAPT [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

CAPT [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

CAPT [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CAPT

Timer Channel Capture Register, array offset: 0x4, array step: 0x20

CMPLD1 [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

CMPLD1 [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

CMPLD1 [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CMPLD1

Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20

CMPLD2 [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

CMPLD2 [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

CMPLD2 [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CMPLD2

Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20

CNTR [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

CNTR [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

CNTR [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CNTR

Timer Channel Counter Register, array offset: 0xA, array step: 0x20

COMP1 [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

COMP1 [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

COMP1 [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL COMP1

Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20

COMP2 [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

COMP2 [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

COMP2 [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL COMP2

Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20

CSCTRL [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

CSCTRL [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

CSCTRL [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CSCTRL

Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20

CTRL [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

CTRL [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

CTRL [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL CTRL

Timer Channel Control Register, array offset: 0xC, array step: 0x20

DMA [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

DMA [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

DMA [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL DMA

Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20

ENBL [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

ENBL [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

ENBL [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL ENBL

Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances

FILT [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

FILT [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

FILT [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL FILT

Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20

HOLD [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

HOLD [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

HOLD [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL HOLD

Timer Channel Hold Register, array offset: 0x8, array step: 0x20

LOAD [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

LOAD [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

LOAD [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL LOAD

Timer Channel Load Register, array offset: 0x6, array step: 0x20

SCTRL [1/3]

__IO uint16_t TMR_Type::[struct].CHANNEL SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

SCTRL [2/3]

__IO uint16_t TMR_Type::[struct].CHANNEL SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

SCTRL [3/3]

__IO uint16_t TMR_Type::[struct].CHANNEL SCTRL

Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20

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The documentation for this struct was generated from the following files: