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RTEMS 6.3
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RTEMS 6.3
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Secure digital input/output Interface. More...
#include <stm32h723xx.h>
Data Fields | |
| __IO uint32_t | POWER |
| __IO uint32_t | CLKCR |
| __IO uint32_t | ARG |
| __IO uint32_t | CMD |
| __I uint32_t | RESPCMD |
| __I uint32_t | RESP1 |
| __I uint32_t | RESP2 |
| __I uint32_t | RESP3 |
| __I uint32_t | RESP4 |
| __IO uint32_t | DTIMER |
| __IO uint32_t | DLEN |
| __IO uint32_t | DCTRL |
| __I uint32_t | DCOUNT |
| __I uint32_t | STA |
| __IO uint32_t | ICR |
| __IO uint32_t | MASK |
| __IO uint32_t | ACKTIME |
| uint32_t | RESERVED0 [3] |
| __IO uint32_t | IDMACTRL |
| __IO uint32_t | IDMABSIZE |
| __IO uint32_t | IDMABASE0 |
| __IO uint32_t | IDMABASE1 |
| uint32_t | RESERVED1 [8] |
| __IO uint32_t | FIFO |
| uint32_t | RESERVED2 [222] |
| __IO uint32_t | IPVR |
Secure digital input/output Interface.
| __IO uint32_t SDMMC_TypeDef::ACKTIME |
SDMMC Acknowledgement timer register, Address offset: 0x40
| __IO uint32_t SDMMC_TypeDef::ARG |
SDMMC argument register, Address offset: 0x08
| __IO uint32_t SDMMC_TypeDef::CLKCR |
SDMMC clock control register, Address offset: 0x04
| __IO uint32_t SDMMC_TypeDef::CMD |
SDMMC command register, Address offset: 0x0C
| __I uint32_t SDMMC_TypeDef::DCOUNT |
SDMMC data counter register, Address offset: 0x30
| __IO uint32_t SDMMC_TypeDef::DCTRL |
SDMMC data control register, Address offset: 0x2C
| __IO uint32_t SDMMC_TypeDef::DLEN |
SDMMC data length register, Address offset: 0x28
| __IO uint32_t SDMMC_TypeDef::DTIMER |
SDMMC data timer register, Address offset: 0x24
| __IO uint32_t SDMMC_TypeDef::FIFO |
SDMMC data FIFO register, Address offset: 0x80
| __IO uint32_t SDMMC_TypeDef::ICR |
SDMMC interrupt clear register, Address offset: 0x38
| __IO uint32_t SDMMC_TypeDef::IDMABASE0 |
SDMMC DMA buffer 0 base address register, Address offset: 0x58
| __IO uint32_t SDMMC_TypeDef::IDMABASE1 |
SDMMC DMA buffer 1 base address register, Address offset: 0x5C
| __IO uint32_t SDMMC_TypeDef::IDMABSIZE |
SDMMC DMA buffer size register, Address offset: 0x54
| __IO uint32_t SDMMC_TypeDef::IDMACTRL |
SDMMC DMA control register, Address offset: 0x50
| __IO uint32_t SDMMC_TypeDef::IPVR |
SDMMC data FIFO register, Address offset: 0x3FC
| __IO uint32_t SDMMC_TypeDef::MASK |
SDMMC mask register, Address offset: 0x3C
| __IO uint32_t SDMMC_TypeDef::POWER |
SDMMC power control register, Address offset: 0x00
| uint32_t SDMMC_TypeDef::RESERVED0 |
Reserved, 0x44 - 0x4C - 0x4C
| uint32_t SDMMC_TypeDef::RESERVED1 |
Reserved, 0x60-0x7C
| uint32_t SDMMC_TypeDef::RESERVED2 |
Reserved, 0x84-0x3F8
| __I uint32_t SDMMC_TypeDef::RESP1 |
SDMMC response 1 register, Address offset: 0x14
| __I uint32_t SDMMC_TypeDef::RESP2 |
SDMMC response 2 register, Address offset: 0x18
| __I uint32_t SDMMC_TypeDef::RESP3 |
SDMMC response 3 register, Address offset: 0x1C
| __I uint32_t SDMMC_TypeDef::RESP4 |
SDMMC response 4 register, Address offset: 0x20
| __I uint32_t SDMMC_TypeDef::RESPCMD |
SDMMC command response register, Address offset: 0x10
| __I uint32_t SDMMC_TypeDef::STA |
SDMMC status register, Address offset: 0x34
1.18.0