PWM_Type::[struct].SM Struct Reference

Data Fields
__I uint16_t	CNT
__IO uint16_t	INIT
__IO uint16_t	CTRL2
__IO uint16_t	CTRL
uint8_t	RESERVED_0 [2]
__IO uint16_t	VAL0
__IO uint16_t	FRACVAL1
__IO uint16_t	VAL1
__IO uint16_t	FRACVAL2
__IO uint16_t	VAL2
__IO uint16_t	FRACVAL3
__IO uint16_t	VAL3
__IO uint16_t	FRACVAL4
__IO uint16_t	VAL4
__IO uint16_t	FRACVAL5
__IO uint16_t	VAL5
__IO uint16_t	FRCTRL
__IO uint16_t	OCTRL
__IO uint16_t	STS
__IO uint16_t	INTEN
__IO uint16_t	DMAEN
__IO uint16_t	TCTRL
__IO uint16_t	DISMAP [2]
__IO uint16_t	DTCNT0
__IO uint16_t	DTCNT1
__IO uint16_t	CAPTCTRLA
__IO uint16_t	CAPTCOMPA
__IO uint16_t	CAPTCTRLB
__IO uint16_t	CAPTCOMPB
__IO uint16_t	CAPTCTRLX
__IO uint16_t	CAPTCOMPX
__I uint16_t	CVAL0
__I uint16_t	CVAL0CYC
__I uint16_t	CVAL1
__I uint16_t	CVAL1CYC
__I uint16_t	CVAL2
__I uint16_t	CVAL2CYC
__I uint16_t	CVAL3
__I uint16_t	CVAL3CYC
__I uint16_t	CVAL4
__I uint16_t	CVAL4CYC
__I uint16_t	CVAL5
__I uint16_t	CVAL5CYC
uint8_t	RESERVED_1 [8]
__I uint16_t	CNT
__IO uint16_t	INIT
__IO uint16_t	CTRL2
__IO uint16_t	CTRL
uint8_t	RESERVED_0 [2]
__IO uint16_t	VAL0
__IO uint16_t	FRACVAL1
__IO uint16_t	VAL1
__IO uint16_t	FRACVAL2
__IO uint16_t	VAL2
__IO uint16_t	FRACVAL3
__IO uint16_t	VAL3
__IO uint16_t	FRACVAL4
__IO uint16_t	VAL4
__IO uint16_t	FRACVAL5
__IO uint16_t	VAL5
__IO uint16_t	FRCTRL
__IO uint16_t	OCTRL
__IO uint16_t	STS
__IO uint16_t	INTEN
__IO uint16_t	DMAEN
__IO uint16_t	TCTRL
__IO uint16_t	DISMAP [1]
uint8_t	RESERVED_1 [2]
__IO uint16_t	DTCNT0
__IO uint16_t	DTCNT1
__IO uint16_t	CAPTCTRLA
__IO uint16_t	CAPTCOMPA
__IO uint16_t	CAPTCTRLB
__IO uint16_t	CAPTCOMPB
__IO uint16_t	CAPTCTRLX
__IO uint16_t	CAPTCOMPX
__I uint16_t	CVAL0
__I uint16_t	CVAL0CYC
__I uint16_t	CVAL1
__I uint16_t	CVAL1CYC
__I uint16_t	CVAL2
__I uint16_t	CVAL2CYC
__I uint16_t	CVAL3
__I uint16_t	CVAL3CYC
__I uint16_t	CVAL4
__I uint16_t	CVAL4CYC
__I uint16_t	CVAL5
__I uint16_t	CVAL5CYC
uint8_t	RESERVED_2 [8]
__I uint16_t	CNT
__IO uint16_t	INIT
__IO uint16_t	CTRL2
__IO uint16_t	CTRL
uint8_t	RESERVED_0 [2]
__IO uint16_t	VAL0
__IO uint16_t	FRACVAL1
__IO uint16_t	VAL1
__IO uint16_t	FRACVAL2
__IO uint16_t	VAL2
__IO uint16_t	FRACVAL3
__IO uint16_t	VAL3
__IO uint16_t	FRACVAL4
__IO uint16_t	VAL4
__IO uint16_t	FRACVAL5
__IO uint16_t	VAL5
__IO uint16_t	FRCTRL
__IO uint16_t	OCTRL
__IO uint16_t	STS
__IO uint16_t	INTEN
__IO uint16_t	DMAEN
__IO uint16_t	TCTRL
__IO uint16_t	DISMAP [1]
uint8_t	RESERVED_1 [2]
__IO uint16_t	DTCNT0
__IO uint16_t	DTCNT1
__IO uint16_t	CAPTCTRLA
__IO uint16_t	CAPTCOMPA
__IO uint16_t	CAPTCTRLB
__IO uint16_t	CAPTCOMPB
__IO uint16_t	CAPTCTRLX
__IO uint16_t	CAPTCOMPX
__I uint16_t	CVAL0
__I uint16_t	CVAL0CYC
__I uint16_t	CVAL1
__I uint16_t	CVAL1CYC
__I uint16_t	CVAL2
__I uint16_t	CVAL2CYC
__I uint16_t	CVAL3
__I uint16_t	CVAL3CYC
__I uint16_t	CVAL4
__I uint16_t	CVAL4CYC
__I uint16_t	CVAL5
__I uint16_t	CVAL5CYC
uint8_t	RESERVED_2 [8]

Field Documentation

CAPTCOMPA [1/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

CAPTCOMPA [2/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

CAPTCOMPA [3/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPA

Capture Compare A Register, array offset: 0x36, array step: 0x60

CAPTCOMPB [1/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

CAPTCOMPB [2/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

CAPTCOMPB [3/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPB

Capture Compare B Register, array offset: 0x3A, array step: 0x60

CAPTCOMPX [1/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

CAPTCOMPX [2/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

CAPTCOMPX [3/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCOMPX

Capture Compare X Register, array offset: 0x3E, array step: 0x60

CAPTCTRLA [1/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

CAPTCTRLA [2/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

CAPTCTRLA [3/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLA

Capture Control A Register, array offset: 0x34, array step: 0x60

CAPTCTRLB [1/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

CAPTCTRLB [2/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

CAPTCTRLB [3/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLB

Capture Control B Register, array offset: 0x38, array step: 0x60

CAPTCTRLX [1/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

CAPTCTRLX [2/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

CAPTCTRLX [3/3]

__IO uint16_t PWM_Type::[struct].SM CAPTCTRLX

Capture Control X Register, array offset: 0x3C, array step: 0x60

CNT [1/3]

__I uint16_t PWM_Type::[struct].SM CNT

Counter Register, array offset: 0x0, array step: 0x60

CNT [2/3]

__I uint16_t PWM_Type::[struct].SM CNT

Counter Register, array offset: 0x0, array step: 0x60

CNT [3/3]

__I uint16_t PWM_Type::[struct].SM CNT

Counter Register, array offset: 0x0, array step: 0x60

CTRL [1/3]

__IO uint16_t PWM_Type::[struct].SM CTRL

Control Register, array offset: 0x6, array step: 0x60

CTRL [2/3]

__IO uint16_t PWM_Type::[struct].SM CTRL

Control Register, array offset: 0x6, array step: 0x60

CTRL [3/3]

__IO uint16_t PWM_Type::[struct].SM CTRL

Control Register, array offset: 0x6, array step: 0x60

CTRL2 [1/3]

__IO uint16_t PWM_Type::[struct].SM CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

CTRL2 [2/3]

__IO uint16_t PWM_Type::[struct].SM CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

CTRL2 [3/3]

__IO uint16_t PWM_Type::[struct].SM CTRL2

Control 2 Register, array offset: 0x4, array step: 0x60

CVAL0 [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

CVAL0 [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

CVAL0 [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL0

Capture Value 0 Register, array offset: 0x40, array step: 0x60

CVAL0CYC [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

CVAL0CYC [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

CVAL0CYC [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL0CYC

Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60

CVAL1 [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

CVAL1 [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

CVAL1 [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL1

Capture Value 1 Register, array offset: 0x44, array step: 0x60

CVAL1CYC [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

CVAL1CYC [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

CVAL1CYC [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL1CYC

Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60

CVAL2 [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

CVAL2 [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

CVAL2 [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL2

Capture Value 2 Register, array offset: 0x48, array step: 0x60

CVAL2CYC [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

CVAL2CYC [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

CVAL2CYC [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL2CYC

Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60

CVAL3 [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

CVAL3 [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

CVAL3 [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL3

Capture Value 3 Register, array offset: 0x4C, array step: 0x60

CVAL3CYC [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

CVAL3CYC [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

CVAL3CYC [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL3CYC

Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60

CVAL4 [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

CVAL4 [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

CVAL4 [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL4

Capture Value 4 Register, array offset: 0x50, array step: 0x60

CVAL4CYC [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

CVAL4CYC [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

CVAL4CYC [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL4CYC

Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60

CVAL5 [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

CVAL5 [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

CVAL5 [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL5

Capture Value 5 Register, array offset: 0x54, array step: 0x60

CVAL5CYC [1/3]

__I uint16_t PWM_Type::[struct].SM CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

CVAL5CYC [2/3]

__I uint16_t PWM_Type::[struct].SM CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

CVAL5CYC [3/3]

__I uint16_t PWM_Type::[struct].SM CVAL5CYC

Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60

DISMAP [1/3]

__IO uint16_t PWM_Type::[struct].SM[1]

Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2

DISMAP [2/3]

__IO uint16_t PWM_Type::[struct].SM[1]

Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2

DISMAP [3/3]

__IO uint16_t PWM_Type::[struct].SM[2]

Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2

DMAEN [1/3]

__IO uint16_t PWM_Type::[struct].SM DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

DMAEN [2/3]

__IO uint16_t PWM_Type::[struct].SM DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

DMAEN [3/3]

__IO uint16_t PWM_Type::[struct].SM DMAEN

DMA Enable Register, array offset: 0x28, array step: 0x60

DTCNT0 [1/3]

__IO uint16_t PWM_Type::[struct].SM DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

DTCNT0 [2/3]

__IO uint16_t PWM_Type::[struct].SM DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

DTCNT0 [3/3]

__IO uint16_t PWM_Type::[struct].SM DTCNT0

Deadtime Count Register 0, array offset: 0x30, array step: 0x60

DTCNT1 [1/3]

__IO uint16_t PWM_Type::[struct].SM DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

DTCNT1 [2/3]

__IO uint16_t PWM_Type::[struct].SM DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

DTCNT1 [3/3]

__IO uint16_t PWM_Type::[struct].SM DTCNT1

Deadtime Count Register 1, array offset: 0x32, array step: 0x60

FRACVAL1 [1/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

FRACVAL1 [2/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

FRACVAL1 [3/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL1

Fractional Value Register 1, array offset: 0xC, array step: 0x60

FRACVAL2 [1/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

FRACVAL2 [2/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

FRACVAL2 [3/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL2

Fractional Value Register 2, array offset: 0x10, array step: 0x60

FRACVAL3 [1/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

FRACVAL3 [2/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

FRACVAL3 [3/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL3

Fractional Value Register 3, array offset: 0x14, array step: 0x60

FRACVAL4 [1/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

FRACVAL4 [2/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

FRACVAL4 [3/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL4

Fractional Value Register 4, array offset: 0x18, array step: 0x60

FRACVAL5 [1/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

FRACVAL5 [2/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

FRACVAL5 [3/3]

__IO uint16_t PWM_Type::[struct].SM FRACVAL5

Fractional Value Register 5, array offset: 0x1C, array step: 0x60

FRCTRL [1/3]

__IO uint16_t PWM_Type::[struct].SM FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

FRCTRL [2/3]

__IO uint16_t PWM_Type::[struct].SM FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

FRCTRL [3/3]

__IO uint16_t PWM_Type::[struct].SM FRCTRL

Fractional Control Register, array offset: 0x20, array step: 0x60

INIT [1/3]

__IO uint16_t PWM_Type::[struct].SM INIT

Initial Count Register, array offset: 0x2, array step: 0x60

INIT [2/3]

__IO uint16_t PWM_Type::[struct].SM INIT

Initial Count Register, array offset: 0x2, array step: 0x60

INIT [3/3]

__IO uint16_t PWM_Type::[struct].SM INIT

Initial Count Register, array offset: 0x2, array step: 0x60

INTEN [1/3]

__IO uint16_t PWM_Type::[struct].SM INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

INTEN [2/3]

__IO uint16_t PWM_Type::[struct].SM INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

INTEN [3/3]

__IO uint16_t PWM_Type::[struct].SM INTEN

Interrupt Enable Register, array offset: 0x26, array step: 0x60

OCTRL [1/3]

__IO uint16_t PWM_Type::[struct].SM OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

OCTRL [2/3]

__IO uint16_t PWM_Type::[struct].SM OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

OCTRL [3/3]

__IO uint16_t PWM_Type::[struct].SM OCTRL

Output Control Register, array offset: 0x22, array step: 0x60

STS [1/3]

__IO uint16_t PWM_Type::[struct].SM STS

Status Register, array offset: 0x24, array step: 0x60

STS [2/3]

__IO uint16_t PWM_Type::[struct].SM STS

Status Register, array offset: 0x24, array step: 0x60

STS [3/3]

__IO uint16_t PWM_Type::[struct].SM STS

Status Register, array offset: 0x24, array step: 0x60

TCTRL [1/3]

__IO uint16_t PWM_Type::[struct].SM TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

TCTRL [2/3]

__IO uint16_t PWM_Type::[struct].SM TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

TCTRL [3/3]

__IO uint16_t PWM_Type::[struct].SM TCTRL

Output Trigger Control Register, array offset: 0x2A, array step: 0x60

VAL0 [1/3]

__IO uint16_t PWM_Type::[struct].SM VAL0

Value Register 0, array offset: 0xA, array step: 0x60

VAL0 [2/3]

__IO uint16_t PWM_Type::[struct].SM VAL0

Value Register 0, array offset: 0xA, array step: 0x60

VAL0 [3/3]

__IO uint16_t PWM_Type::[struct].SM VAL0

Value Register 0, array offset: 0xA, array step: 0x60

VAL1 [1/3]

__IO uint16_t PWM_Type::[struct].SM VAL1

Value Register 1, array offset: 0xE, array step: 0x60

VAL1 [2/3]

__IO uint16_t PWM_Type::[struct].SM VAL1

Value Register 1, array offset: 0xE, array step: 0x60

VAL1 [3/3]

__IO uint16_t PWM_Type::[struct].SM VAL1

Value Register 1, array offset: 0xE, array step: 0x60

VAL2 [1/3]

__IO uint16_t PWM_Type::[struct].SM VAL2

Value Register 2, array offset: 0x12, array step: 0x60

VAL2 [2/3]

__IO uint16_t PWM_Type::[struct].SM VAL2

Value Register 2, array offset: 0x12, array step: 0x60

VAL2 [3/3]

__IO uint16_t PWM_Type::[struct].SM VAL2

Value Register 2, array offset: 0x12, array step: 0x60

VAL3 [1/3]

__IO uint16_t PWM_Type::[struct].SM VAL3

Value Register 3, array offset: 0x16, array step: 0x60

VAL3 [2/3]

__IO uint16_t PWM_Type::[struct].SM VAL3

Value Register 3, array offset: 0x16, array step: 0x60

VAL3 [3/3]

__IO uint16_t PWM_Type::[struct].SM VAL3

Value Register 3, array offset: 0x16, array step: 0x60

VAL4 [1/3]

__IO uint16_t PWM_Type::[struct].SM VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

VAL4 [2/3]

__IO uint16_t PWM_Type::[struct].SM VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

VAL4 [3/3]

__IO uint16_t PWM_Type::[struct].SM VAL4

Value Register 4, array offset: 0x1A, array step: 0x60

VAL5 [1/3]

__IO uint16_t PWM_Type::[struct].SM VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

VAL5 [2/3]

__IO uint16_t PWM_Type::[struct].SM VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

VAL5 [3/3]

__IO uint16_t PWM_Type::[struct].SM VAL5

Value Register 5, array offset: 0x1E, array step: 0x60

---

The documentation for this struct was generated from the following files: