PIT_Type::[struct].CHANNEL Struct Reference

Data Fields
__IO uint32_t	LDVAL
__I uint32_t	CVAL
__IO uint32_t	TCTRL
__IO uint32_t	TFLG
__IO uint32_t	LDVAL
__I uint32_t	CVAL
__IO uint32_t	TCTRL
__IO uint32_t	TFLG
__IO uint32_t	LDVAL
__I uint32_t	CVAL
__IO uint32_t	TCTRL
__IO uint32_t	TFLG

Field Documentation

CVAL [1/3]

__I uint32_t PIT_Type::[struct].CHANNEL CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

CVAL [2/3]

__I uint32_t PIT_Type::[struct].CHANNEL CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

CVAL [3/3]

__I uint32_t PIT_Type::[struct].CHANNEL CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10

LDVAL [1/3]

__IO uint32_t PIT_Type::[struct].CHANNEL LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

LDVAL [2/3]

__IO uint32_t PIT_Type::[struct].CHANNEL LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

LDVAL [3/3]

__IO uint32_t PIT_Type::[struct].CHANNEL LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10

TCTRL [1/3]

__IO uint32_t PIT_Type::[struct].CHANNEL TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

TCTRL [2/3]

__IO uint32_t PIT_Type::[struct].CHANNEL TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

TCTRL [3/3]

__IO uint32_t PIT_Type::[struct].CHANNEL TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10

TFLG [1/3]

__IO uint32_t PIT_Type::[struct].CHANNEL TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

TFLG [2/3]

__IO uint32_t PIT_Type::[struct].CHANNEL TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

TFLG [3/3]

__IO uint32_t PIT_Type::[struct].CHANNEL TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10

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The documentation for this struct was generated from the following files: