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RTEMS 6.3
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RTEMS 6.3
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DCMI. More...
#include <stm32h723xx.h>
Data Fields | |
| __IO uint32_t | CR |
| __IO uint32_t | SR |
| __IO uint32_t | RISR |
| __IO uint32_t | IER |
| __IO uint32_t | MISR |
| __IO uint32_t | ICR |
| __IO uint32_t | ESCR |
| __IO uint32_t | ESUR |
| __IO uint32_t | CWSTRTR |
| __IO uint32_t | CWSIZER |
| __IO uint32_t | DR |
DCMI.
| __IO uint32_t DCMI_TypeDef::CR |
DCMI control register 1, Address offset: 0x00
| __IO uint32_t DCMI_TypeDef::CWSIZER |
DCMI crop window size, Address offset: 0x24
| __IO uint32_t DCMI_TypeDef::CWSTRTR |
DCMI crop window start, Address offset: 0x20
| __IO uint32_t DCMI_TypeDef::DR |
DCMI data register, Address offset: 0x28
| __IO uint32_t DCMI_TypeDef::ESCR |
DCMI embedded synchronization code register, Address offset: 0x18
| __IO uint32_t DCMI_TypeDef::ESUR |
DCMI embedded synchronization unmask register, Address offset: 0x1C
| __IO uint32_t DCMI_TypeDef::ICR |
DCMI interrupt clear register, Address offset: 0x14
| __IO uint32_t DCMI_TypeDef::IER |
DCMI interrupt enable register, Address offset: 0x0C
| __IO uint32_t DCMI_TypeDef::MISR |
DCMI masked interrupt status register, Address offset: 0x10
| __IO uint32_t DCMI_TypeDef::RISR |
DCMI raw interrupt status register, Address offset: 0x08
| __IO uint32_t DCMI_TypeDef::SR |
DCMI status register, Address offset: 0x04
1.18.0