CAAM_Type::[struct].PX_PG0 Struct Reference

Data Fields
__I uint32_t	PX_SDID_PG0
__IO uint32_t	PX_SMAPR_PG0
__IO uint32_t	PX_SMAG2_PG0
__IO uint32_t	PX_SMAG1_PG0
__I uint32_t	PX_SDID_PG0
__IO uint32_t	PX_SMAPR_PG0
__IO uint32_t	PX_SMAG2_PG0
__IO uint32_t	PX_SMAG1_PG0

Field Documentation

PX_SDID_PG0 [1/2]

__I uint32_t CAAM_Type::[struct].PX_PG0 PX_SDID_PG0

Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10

PX_SDID_PG0 [2/2]

__I uint32_t CAAM_Type::[struct].PX_PG0 PX_SDID_PG0

Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10

PX_SMAG1_PG0 [1/2]

__IO uint32_t CAAM_Type::[struct].PX_PG0 PX_SMAG1_PG0

Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10

PX_SMAG1_PG0 [2/2]

__IO uint32_t CAAM_Type::[struct].PX_PG0 PX_SMAG1_PG0

Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10

PX_SMAG2_PG0 [1/2]

__IO uint32_t CAAM_Type::[struct].PX_PG0 PX_SMAG2_PG0

Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10

PX_SMAG2_PG0 [2/2]

__IO uint32_t CAAM_Type::[struct].PX_PG0 PX_SMAG2_PG0

Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10

PX_SMAPR_PG0 [1/2]

__IO uint32_t CAAM_Type::[struct].PX_PG0 PX_SMAPR_PG0

Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10

PX_SMAPR_PG0 [2/2]

__IO uint32_t CAAM_Type::[struct].PX_PG0 PX_SMAPR_PG0

Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10

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The documentation for this struct was generated from the following files: