RTEMS 6.3
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Data Structures | Data Fields
CAAM_Type::[struct].DC Struct Reference
Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » CAAM Peripheral Access Layer | Mapping Information » Iomuxc_pads » Device Peripheral Access Layer » CAAM Peripheral Access Layer

Data Structures

union  [union].DC.__unnamed0__
union  [union].DC.__unnamed1__
struct  [struct].DC.DDMTHB
struct  [struct].DC.DDGTR
struct  [struct].DC.DDSTR

Data Fields

uint8_t RESERVED_0 [4]
union  
uint8_t RESERVED_1 [4]
__IO uint32_t CC1KSR
__IO uint64_t CC1DSR
uint8_t RESERVED_2 [4]
__IO uint32_t CC1ICVSR
uint8_t RESERVED_3 [20]
__O uint32_t CCCTRL
uint8_t RESERVED_4 [4]
__IO uint32_t CICTL
uint8_t RESERVED_5 [4]
__O uint32_t CCWR
__I uint32_t CCSTA_MS
__I uint32_t CCSTA_LS
uint8_t RESERVED_6 [12]
__IO uint32_t CC1AADSZR
uint8_t RESERVED_7 [4]
__IO uint32_t CC1IVSZR
uint8_t RESERVED_8 [28]
__IO uint32_t CPKASZR
uint8_t RESERVED_9 [4]
__IO uint32_t CPKBSZR
uint8_t RESERVED_10 [4]
__IO uint32_t CPKNSZR
uint8_t RESERVED_11 [4]
__IO uint32_t CPKESZR
uint8_t RESERVED_12 [96]
__IO uint32_t CC1CTXR [16]
uint8_t RESERVED_13 [192]
__IO uint32_t CC1KR [8]
uint8_t RESERVED_14 [484]
__IO uint32_t CC2MR
uint8_t RESERVED_15 [4]
__IO uint32_t CC2KSR
__IO uint64_t CC2DSR
uint8_t RESERVED_16 [4]
__IO uint32_t CC2ICVSZR
uint8_t RESERVED_17 [224]
__IO uint32_t CC2CTXR [18]
uint8_t RESERVED_18 [184]
__IO uint32_t CC2KEYR [32]
uint8_t RESERVED_19 [320]
__I uint32_t CFIFOSTA
uint8_t RESERVED_20 [12]
union  
uint8_t RESERVED_21 [12]
__O uint32_t CIFIFO
uint8_t RESERVED_22 [12]
__I uint64_t COFIFO
uint8_t RESERVED_23 [8]
__IO uint32_t DJQCR_MS
__I uint32_t DJQCR_LS
__I uint64_t DDAR
__I uint32_t DOPSTA_MS
__I uint32_t DOPSTA_LS
uint8_t RESERVED_24 [8]
__I uint32_t DPDIDSR
__I uint32_t DODIDSR
uint8_t RESERVED_25 [24]
struct  DDMTHB [4]
uint8_t RESERVED_26 [32]
struct  DDGTR [1]
uint8_t RESERVED_27 [112]
struct  DDSTR [1]
uint8_t RESERVED_28 [240]
__IO uint32_t DDESB [64]
uint8_t RESERVED_29 [768]
__I uint32_t DDJR
__I uint32_t DDDR
__I uint64_t DDJP
__I uint64_t DSDP
__I uint32_t DDDR_MS
__I uint32_t DDDR_LS
__IO uint32_t SOL
__IO uint32_t VSOL
__IO uint32_t SIL
__IO uint32_t VSIL
__IO uint32_t DPOVRD
__IO uint32_t UVSOL
__IO uint32_t UVSIL
uint8_t RESERVED_0 [4]
union  
uint8_t RESERVED_1 [4]
__IO uint32_t CC1KSR
__IO uint64_t CC1DSR
uint8_t RESERVED_2 [4]
__IO uint32_t CC1ICVSR
uint8_t RESERVED_3 [20]
__O uint32_t CCCTRL
uint8_t RESERVED_4 [4]
__IO uint32_t CICTL
uint8_t RESERVED_5 [4]
__O uint32_t CCWR
__I uint32_t CCSTA_MS
__I uint32_t CCSTA_LS
uint8_t RESERVED_6 [12]
__IO uint32_t CC1AADSZR
uint8_t RESERVED_7 [4]
__IO uint32_t CC1IVSZR
uint8_t RESERVED_8 [28]
__IO uint32_t CPKASZR
uint8_t RESERVED_9 [4]
__IO uint32_t CPKBSZR
uint8_t RESERVED_10 [4]
__IO uint32_t CPKNSZR
uint8_t RESERVED_11 [4]
__IO uint32_t CPKESZR
uint8_t RESERVED_12 [96]
__IO uint32_t CC1CTXR [16]
uint8_t RESERVED_13 [192]
__IO uint32_t CC1KR [8]
uint8_t RESERVED_14 [484]
__IO uint32_t CC2MR
uint8_t RESERVED_15 [4]
__IO uint32_t CC2KSR
__IO uint64_t CC2DSR
uint8_t RESERVED_16 [4]
__IO uint32_t CC2ICVSZR
uint8_t RESERVED_17 [224]
__IO uint32_t CC2CTXR [18]
uint8_t RESERVED_18 [184]
__IO uint32_t CC2KEYR [32]
uint8_t RESERVED_19 [320]
__I uint32_t CFIFOSTA
uint8_t RESERVED_20 [12]
union  
uint8_t RESERVED_21 [12]
__O uint32_t CIFIFO
uint8_t RESERVED_22 [12]
__I uint64_t COFIFO
uint8_t RESERVED_23 [8]
__IO uint32_t DJQCR_MS
__I uint32_t DJQCR_LS
__I uint64_t DDAR
__I uint32_t DOPSTA_MS
__I uint32_t DOPSTA_LS
uint8_t RESERVED_24 [8]
__I uint32_t DPDIDSR
__I uint32_t DODIDSR
uint8_t RESERVED_25 [24]
struct  DDMTHB [4]
uint8_t RESERVED_26 [32]
struct  DDGTR [1]
uint8_t RESERVED_27 [112]
struct  DDSTR [1]
uint8_t RESERVED_28 [240]
__IO uint32_t DDESB [64]
uint8_t RESERVED_29 [768]
__I uint32_t DDJR
__I uint32_t DDDR
__I uint64_t DDJP
__I uint64_t DSDP
__I uint32_t DDDR_MS
__I uint32_t DDDR_LS
__IO uint32_t SOL
__IO uint32_t VSOL
__IO uint32_t SIL
__IO uint32_t VSIL
__IO uint32_t DPOVRD
__IO uint32_t UVSOL
__IO uint32_t UVSIL

Field Documentation

◆ CC1AADSZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC1AADSZR

CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C

◆ CC1AADSZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC1AADSZR

CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C

◆ CC1CTXR [1/2]

__IO uint32_t CAAM_Type::[struct].DC[16]

CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4

◆ CC1CTXR [2/2]

__IO uint32_t CAAM_Type::[struct].DC[16]

CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4

◆ CC1DSR [1/2]

__IO uint64_t CAAM_Type::[struct].DC CC1DSR

CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C

◆ CC1DSR [2/2]

__IO uint64_t CAAM_Type::[struct].DC CC1DSR

CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C

◆ CC1ICVSR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC1ICVSR

CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C

◆ CC1ICVSR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC1ICVSR

CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C

◆ CC1IVSZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC1IVSZR

CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C

◆ CC1IVSZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC1IVSZR

CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C

◆ CC1KR [1/2]

__IO uint32_t CAAM_Type::[struct].DC[8]

CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4

◆ CC1KR [2/2]

__IO uint32_t CAAM_Type::[struct].DC[8]

CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4

◆ CC1KSR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC1KSR

CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C

◆ CC1KSR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC1KSR

CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C

◆ CC2CTXR [1/2]

__IO uint32_t CAAM_Type::[struct].DC[18]

CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4

◆ CC2CTXR [2/2]

__IO uint32_t CAAM_Type::[struct].DC[18]

CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4

◆ CC2DSR [1/2]

__IO uint64_t CAAM_Type::[struct].DC CC2DSR

CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C

◆ CC2DSR [2/2]

__IO uint64_t CAAM_Type::[struct].DC CC2DSR

CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C

◆ CC2ICVSZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC2ICVSZR

CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C

◆ CC2ICVSZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC2ICVSZR

CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C

◆ CC2KEYR [1/2]

__IO uint32_t CAAM_Type::[struct].DC[32]

CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4

◆ CC2KEYR [2/2]

__IO uint32_t CAAM_Type::[struct].DC[32]

CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4

◆ CC2KSR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC2KSR

CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C

◆ CC2KSR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC2KSR

CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C

◆ CC2MR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CC2MR

CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C

◆ CC2MR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CC2MR

CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C

◆ CCCTRL [1/2]

__O uint32_t CAAM_Type::[struct].DC CCCTRL

CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C

◆ CCCTRL [2/2]

__O uint32_t CAAM_Type::[struct].DC CCCTRL

CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C

◆ CCSTA_LS [1/2]

__I uint32_t CAAM_Type::[struct].DC CCSTA_LS

CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C

◆ CCSTA_LS [2/2]

__I uint32_t CAAM_Type::[struct].DC CCSTA_LS

CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C

◆ CCSTA_MS [1/2]

__I uint32_t CAAM_Type::[struct].DC CCSTA_MS

CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C

◆ CCSTA_MS [2/2]

__I uint32_t CAAM_Type::[struct].DC CCSTA_MS

CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C

◆ CCWR [1/2]

__O uint32_t CAAM_Type::[struct].DC CCWR

CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C

◆ CCWR [2/2]

__O uint32_t CAAM_Type::[struct].DC CCWR

CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C

◆ CFIFOSTA [1/2]

__I uint32_t CAAM_Type::[struct].DC CFIFOSTA

CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C

◆ CFIFOSTA [2/2]

__I uint32_t CAAM_Type::[struct].DC CFIFOSTA

CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C

◆ CICTL [1/2]

__IO uint32_t CAAM_Type::[struct].DC CICTL

CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C

◆ CICTL [2/2]

__IO uint32_t CAAM_Type::[struct].DC CICTL

CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C

◆ CIFIFO [1/2]

__O uint32_t CAAM_Type::[struct].DC CIFIFO

CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C

◆ CIFIFO [2/2]

__O uint32_t CAAM_Type::[struct].DC CIFIFO

CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C

◆ COFIFO [1/2]

__I uint64_t CAAM_Type::[struct].DC COFIFO

CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C

◆ COFIFO [2/2]

__I uint64_t CAAM_Type::[struct].DC COFIFO

CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C

◆ CPKASZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CPKASZR

PKHA A Size Register, array offset: 0x80084, array step: 0xE3C

◆ CPKASZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CPKASZR

PKHA A Size Register, array offset: 0x80084, array step: 0xE3C

◆ CPKBSZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CPKBSZR

PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C

◆ CPKBSZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CPKBSZR

PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C

◆ CPKESZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CPKESZR

PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C

◆ CPKESZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CPKESZR

PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C

◆ CPKNSZR [1/2]

__IO uint32_t CAAM_Type::[struct].DC CPKNSZR

PKHA N Size Register, array offset: 0x80094, array step: 0xE3C

◆ CPKNSZR [2/2]

__IO uint32_t CAAM_Type::[struct].DC CPKNSZR

PKHA N Size Register, array offset: 0x80094, array step: 0xE3C

◆ DDAR [1/2]

__I uint64_t CAAM_Type::[struct].DC DDAR

DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C

◆ DDAR [2/2]

__I uint64_t CAAM_Type::[struct].DC DDAR

DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C

◆ DDDR [1/2]

__I uint32_t CAAM_Type::[struct].DC DDDR

DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C

◆ DDDR [2/2]

__I uint32_t CAAM_Type::[struct].DC DDDR

DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C

◆ DDDR_LS [1/2]

__I uint32_t CAAM_Type::[struct].DC DDDR_LS

DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C

◆ DDDR_LS [2/2]

__I uint32_t CAAM_Type::[struct].DC DDDR_LS

DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C

◆ DDDR_MS [1/2]

__I uint32_t CAAM_Type::[struct].DC DDDR_MS

DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C

◆ DDDR_MS [2/2]

__I uint32_t CAAM_Type::[struct].DC DDDR_MS

DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C

◆ DDESB [1/2]

__IO uint32_t CAAM_Type::[struct].DC[64]

DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4

◆ DDESB [2/2]

__IO uint32_t CAAM_Type::[struct].DC[64]

DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4

◆ DDJP [1/2]

__I uint64_t CAAM_Type::[struct].DC DDJP

DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C

◆ DDJP [2/2]

__I uint64_t CAAM_Type::[struct].DC DDJP

DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C

◆ DDJR [1/2]

__I uint32_t CAAM_Type::[struct].DC DDJR

DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C

◆ DDJR [2/2]

__I uint32_t CAAM_Type::[struct].DC DDJR

DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C

◆ DJQCR_LS [1/2]

__I uint32_t CAAM_Type::[struct].DC DJQCR_LS

DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C

◆ DJQCR_LS [2/2]

__I uint32_t CAAM_Type::[struct].DC DJQCR_LS

DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C

◆ DJQCR_MS [1/2]

__IO uint32_t CAAM_Type::[struct].DC DJQCR_MS

DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C

◆ DJQCR_MS [2/2]

__IO uint32_t CAAM_Type::[struct].DC DJQCR_MS

DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C

◆ DODIDSR [1/2]

__I uint32_t CAAM_Type::[struct].DC DODIDSR

DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C

◆ DODIDSR [2/2]

__I uint32_t CAAM_Type::[struct].DC DODIDSR

DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C

◆ DOPSTA_LS [1/2]

__I uint32_t CAAM_Type::[struct].DC DOPSTA_LS

DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C

◆ DOPSTA_LS [2/2]

__I uint32_t CAAM_Type::[struct].DC DOPSTA_LS

DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C

◆ DOPSTA_MS [1/2]

__I uint32_t CAAM_Type::[struct].DC DOPSTA_MS

DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C

◆ DOPSTA_MS [2/2]

__I uint32_t CAAM_Type::[struct].DC DOPSTA_MS

DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C

◆ DPDIDSR [1/2]

__I uint32_t CAAM_Type::[struct].DC DPDIDSR

DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C

◆ DPDIDSR [2/2]

__I uint32_t CAAM_Type::[struct].DC DPDIDSR

DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C

◆ DPOVRD [1/2]

__IO uint32_t CAAM_Type::[struct].DC DPOVRD

Protocol Override Register, array offset: 0x80E30, array step: 0xE3C

◆ DPOVRD [2/2]

__IO uint32_t CAAM_Type::[struct].DC DPOVRD

Protocol Override Register, array offset: 0x80E30, array step: 0xE3C

◆ DSDP [1/2]

__I uint64_t CAAM_Type::[struct].DC DSDP

DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C

◆ DSDP [2/2]

__I uint64_t CAAM_Type::[struct].DC DSDP

DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C

◆ SIL [1/2]

__IO uint32_t CAAM_Type::[struct].DC SIL

Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C

◆ SIL [2/2]

__IO uint32_t CAAM_Type::[struct].DC SIL

Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C

◆ SOL [1/2]

__IO uint32_t CAAM_Type::[struct].DC SOL

Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C

◆ SOL [2/2]

__IO uint32_t CAAM_Type::[struct].DC SOL

Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C

◆ UVSIL [1/2]

__IO uint32_t CAAM_Type::[struct].DC UVSIL

Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C

◆ UVSIL [2/2]

__IO uint32_t CAAM_Type::[struct].DC UVSIL

Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C

◆ UVSOL [1/2]

__IO uint32_t CAAM_Type::[struct].DC UVSOL

Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C

◆ UVSOL [2/2]

__IO uint32_t CAAM_Type::[struct].DC UVSOL

Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C

◆ VSIL [1/2]

__IO uint32_t CAAM_Type::[struct].DC VSIL

Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C

◆ VSIL [2/2]

__IO uint32_t CAAM_Type::[struct].DC VSIL

Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C

◆ VSOL [1/2]

__IO uint32_t CAAM_Type::[struct].DC VSOL

Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C

◆ VSOL [2/2]

__IO uint32_t CAAM_Type::[struct].DC VSOL

Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C

The documentation for this struct was generated from the following files:
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